Put hsync and vsync in phase.

src/vga.pio

@@ -13,6 +13,8 @@ entrypoint_vga_hsync:
     mov isr, osr
     pull
 
+loope:
+    set y, 15
 loop:
     mov x, isr
     set pins, 0
@@ -23,7 +25,10 @@ hsync_pulse:
     set pins, 1
 hsync_idle:
     jmp x-- hsync_idle
-    jmp loop
+    jmp y-- loop
+
+    irq set 0
+    jmp loope
 
 .program vga_vsync
 
@@ -33,13 +38,11 @@ entrypoint_vga_vsync:
     pull
 
 loop:
+    wait irq 0
     mov x, isr
     set pins, 0
 vsync_pulse:
     jmp x-- vsync_pulse
 
-    mov x, osr
     set pins, 1
-vsync_idle:
-    jmp x-- vsync_idle
     jmp loop