273 lines
8.8 KiB
C
273 lines
8.8 KiB
C
#include "vga.h"
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#include <stdio.h>
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#include "hardware/dma.h"
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#include "hardware/pio.h"
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#include "hardware/structs/pio.h"
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#include "hardware/clocks.h"
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#include "hardware/pll.h"
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#include "framebuffer.h"
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#include "vga.pio.h"
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/**
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* @brief Represents a program running on the SM of a PIO.
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*
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*/
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typedef struct PIORun
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{
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PIO pio; //< executing PIO
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uint offset; //< PIO memory offset for program
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uint sm; //< executing SM
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} PIORun;
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/*
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There are 3 SM running: horizontal and vertical sync, and pixels.
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See vga.pio for details.
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*/
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static PIORun vga_hsync, vga_vsync, vga_pixel;
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static bool dma_ready = false; //< current DMA acceleration status
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static int dma_channel; //< DMA channel number, used to refill the vga_pixel FIFO
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static unsigned long int frame_counter = 0; //< current frame
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/**
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* @brief Setup system clocks.
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*
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* Main system clock must run at 126MHz,
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* which is 4 times pixel clock (31.5 MHz).
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* This allows SM to output one pixel every 4 clock cycles,
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* and to do some stuff in the mean time (eg. sending interrupts to sync with the other SM)
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*
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*/
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static void setup_clocks(void)
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{
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// disable resuscitation clock
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clocks_hw->resus.ctrl = 0;
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// before changing PLL, switch sys and ref cleanly away from their aux sources
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hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS);
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while (clocks_hw->clk[clk_sys].selected != 0x1)
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tight_loop_contents();
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hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS);
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while (clocks_hw->clk[clk_ref].selected != 0x1)
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tight_loop_contents();
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// set PLL at 126 MHz, and wait for it to stabilize
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pll_init(pll_sys, 1, 1512 * MHZ, 6, 2);
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// re-configure sys_clk to use PLL
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clock_configure(clk_sys, CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
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CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, 126 * MHZ, 126 * MHZ);
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// re-configure CLK PERI = clk_sys
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clock_configure(clk_peri, 0, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, 126 * MHZ, 126 * MHZ);
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}
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/**
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* @brief Initializes the VGA pixel shift machine.
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*
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* @param pio PIO peripheral to use.
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* @param sm SM to use.
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* @param offset PIO memory offset for program.
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*/
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static void vga_pixel_program_init(PIO pio, uint sm, uint offset)
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{
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// config function is automatically declared by SDK scripts
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// based on the names given to programs in .pio
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pio_sm_config config = vga_pixel_program_get_default_config(offset);
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// destination pins for OUT instructions
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sm_config_set_out_pins(&config, 22, 1);
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sm_config_set_out_shift(&config, true, true, 0);
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pio_gpio_init(pio, 22);
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pio_sm_set_consecutive_pindirs(pio, sm, 22, 1, true);
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sm_config_set_wrap(&config, offset + vga_pixel_wrap_target, offset + vga_pixel_wrap);
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pio_sm_init(pio, sm, offset, &config);
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pio_sm_set_clkdiv_int_frac(pio, sm, 1, 0);
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pio_sm_set_enabled(pio, sm, true);
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}
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/**
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* @brief Initializes the VGA horizontal sync machine.
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*
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* @param pio PIO peripheral to use.
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* @param sm SM to use.
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* @param offset PIO memory offset for program.
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*/
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static void vga_hsync_program_init(PIO pio, uint sm, uint offset)
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{
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pio_sm_config config = vga_hsync_program_get_default_config(offset);
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// destination pins for SET instructions
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sm_config_set_set_pins(&config, 20, 1);
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pio_gpio_init(pio, 20);
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pio_sm_set_consecutive_pindirs(pio, sm, 20, 1, true);
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sm_config_set_wrap(&config, offset + vga_hsync_wrap_target, offset + vga_hsync_wrap);
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pio_sm_init(pio, sm, offset, &config);
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pio_sm_set_clkdiv_int_frac(pio, sm, 1, 0);
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pio->sm->shiftctrl = (1 << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB);
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pio_sm_set_enabled(pio, sm, true);
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}
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/**
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* @brief Initializes the VGA vertical sync machine.
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*
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* @param pio PIO peripheral to use.
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* @param sm SM to use.
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* @param offset PIO memory offset for program.
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*/
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static void vga_vsync_program_init(PIO pio, uint sm, uint offset)
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{
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pio_sm_config config = vga_vsync_program_get_default_config(offset);
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// destination pins for SET instructions
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sm_config_set_set_pins(&config, 21, 1);
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pio_gpio_init(pio, 21);
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pio_sm_set_consecutive_pindirs(pio, sm, 21, 1, true);
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sm_config_set_wrap(&config, offset + vga_vsync_wrap_target, offset + vga_vsync_wrap);
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pio_sm_init(pio, sm, offset, &config);
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pio_sm_set_clkdiv_int_frac(pio, sm, 1, 0);
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pio->sm->shiftctrl = (1 << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB);
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pio_sm_set_enabled(pio, sm, true);
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}
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/**
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* @brief DMA interrupt handler.
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*/
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static void dma_handler(void)
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{
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// acknoweledge DMA
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dma_hw->ints0 = 1 << dma_channel;
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}
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/**
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* @brief Vertical sync interrupt handler.
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*
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*/
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static void new_frame_handler(void)
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{
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if (dma_ready)
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{
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// Explicitly put the first uint32_t word in the FIFO,
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// because, when PIO pulls data for the first time,
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// and its FIFO is empty, the DMA controller takes "a while"
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// to put the first word and keep up with the transfer,
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// making the whole frame a bit offset to the right.
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// Since front porch is very short, even the smallest delay,
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// may disrupt the timing.
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// Also note: despite the "blocking put", when this interrupt
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// is serviced, PIO FIFO is always empty, so in practice
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// this will never block.
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pio_sm_put_blocking(vga_pixel.pio, vga_pixel.sm, 0);
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// Start DMA (but skip the initial word, which has been put manually)
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dma_channel_set_read_addr(dma_channel, &frame[4], true);
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}
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frame_counter++;
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pio_interrupt_clear(pio0_hw, 1);
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}
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void vga_machines_init(void)
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{
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// setup a proper system clock
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setup_clocks();
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// Running programs on PIO
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vga_hsync.pio = vga_vsync.pio = vga_pixel.pio = pio0;
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// Prepare frame interrupt
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// Frame interrupt is asserted on PIO0 interrupt 1 by SM1
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pio_set_irq1_source_enabled(vga_vsync.pio, pis_interrupt1,
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true); // allow SM1 of PIO to fire the interrupt
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irq_set_exclusive_handler(PIO0_IRQ_1, new_frame_handler); // set handler for IRQ1 of PIO
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irq_set_enabled(PIO0_IRQ_1, true); // enable interrupt
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// VGA HSYNC program
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printf("Starting VGA hsync machine... ");
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if (!pio_can_add_program(vga_hsync.pio, &vga_hsync_program))
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panic("cannot add program");
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vga_hsync.offset = pio_add_program(vga_hsync.pio, &vga_hsync_program);
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vga_hsync.sm = pio_claim_unused_sm(vga_hsync.pio, true);
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vga_hsync_program_init(vga_hsync.pio, vga_hsync.sm, vga_hsync.offset);
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// push configuration words to horizontal sync machine FIFO
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// - hsync pulse duration (in pixel), assert time (low)
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// - hsync pulse duration (in pixel), idle time (high), minus back porch
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pio_sm_put_blocking(vga_hsync.pio, vga_hsync.sm, (64 - 2));
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pio_sm_put_blocking(vga_hsync.pio, vga_hsync.sm, (640 + 16 - 1)); // 16 is front porch
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printf("OK\n");
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// VGA VSYNC program
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printf("Starting VGA vsync machine... ");
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if (!pio_can_add_program(vga_vsync.pio, &vga_vsync_program))
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panic("cannot add program");
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vga_vsync.offset = pio_add_program(vga_vsync.pio, &vga_vsync_program);
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vga_vsync.sm = pio_claim_unused_sm(vga_vsync.pio, true);
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vga_vsync_program_init(vga_vsync.pio, vga_vsync.sm, vga_vsync.offset);
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// push configuration words to vertical sync machine FIFO
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// - vsync pulse duration (in lines), assert time (low)
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// - vsync pulse duration (in lines), idle time (high)
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pio_sm_put_blocking(vga_vsync.pio, vga_vsync.sm, 3 - 1);
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pio_sm_put_blocking(vga_vsync.pio, vga_vsync.sm, 500 - 3 - 1);
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printf("OK\n");
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// VGA pixel program
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printf("Starting VGA pixel machine... ");
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if (!pio_can_add_program(vga_pixel.pio, &vga_pixel_program))
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panic("cannot add program");
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vga_pixel.offset = pio_add_program(vga_pixel.pio, &vga_pixel_program);
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vga_pixel.sm = pio_claim_unused_sm(vga_pixel.pio, false);
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vga_pixel_program_init(vga_pixel.pio, vga_pixel.sm, vga_pixel.offset);
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// push configuration word to pixel machine FIFO
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// - number of visible pixels in a line
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pio_sm_put_blocking(vga_pixel.pio, vga_pixel.sm, 640 - 1);
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printf("OK\n");
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printf("Setting up VGA DMA... ");
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dma_channel = dma_claim_unused_channel(true);
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dma_channel_config dma_config = dma_channel_get_default_config(dma_channel);
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channel_config_set_transfer_data_size(&dma_config, DMA_SIZE_32);
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channel_config_set_read_increment(&dma_config, true);
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channel_config_set_write_increment(&dma_config, false);
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// link Data Request signal of PIO SM2 TX FIFO to DMA
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channel_config_set_dreq(&dma_config, DREQ_PIO0_TX2);
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// setup transfer acknowledge interrupt
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dma_channel_set_irq0_enabled(dma_channel, true);
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irq_set_exclusive_handler(DMA_IRQ_0, dma_handler);
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irq_set_enabled(DMA_IRQ_0, true);
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// pull one word less, because first word is manually injected
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// before the first DMA request, in order to avoid any possible delay
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// (see new frame interrupt handler)
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dma_channel_configure(dma_channel, &dma_config, &pio0_hw->txf[2], &frame[0],
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HPIXEL * (VSPULSE + VPIXEL + VBBLANK) / 32 - 1, true);
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dma_ready = true;
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printf("OK\n");
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}
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/**
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* @brief Get current frame counter.
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*
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* @return Current frame counter.
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*/
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unsigned long int vga_get_frame_counter(void)
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{
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return frame_counter;
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} |