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Merge branch 'develop' into contrib/build/cleanup

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This commit is contained in:
Simon Duquennoy 2018-04-05 08:37:55 +02:00 committed by GitHub
commit 005a45009b
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GPG Key ID: 4AEE18F83AFDEB23
44 changed files with 1624 additions and 614 deletions
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3
arch/cpu/cc2538/Makefile.cc2538
View File

@ -15,7 +15,8 @@ CONTIKI_CPU_DIRS = . dev usb usb/common usb/common/cdc-acm
### CPU-dependent source files
CONTIKI_CPU_SOURCEFILES += soc.c clock.c rtimer-arch.c uart.c watchdog.c
CONTIKI_CPU_SOURCEFILES += nvic.c sys-ctrl.c gpio.c ioc.c spi.c adc.c
CONTIKI_CPU_SOURCEFILES += nvic.c sys-ctrl.c gpio.c ioc.c spi-legacy.c adc.c
CONTIKI_CPU_SOURCEFILES += spi-arch.c
CONTIKI_CPU_SOURCEFILES += crypto.c aes.c ecb.c cbc.c ctr.c cbc-mac.c gcm.c
CONTIKI_CPU_SOURCEFILES += ccm.c sha256.c gpio-hal-arch.c
CONTIKI_CPU_SOURCEFILES += cc2538-aes-128.c cc2538-ccm-star.c

2
arch/cpu/cc2538/cc2538-def.h
View File

@ -58,6 +58,8 @@
#define TSCH_CONF_HW_FRAME_FILTERING 0
#endif /* MAC_CONF_WITH_TSCH */
/*---------------------------------------------------------------------------*/
#define SPI_CONF_CONTROLLER_COUNT 2
/*---------------------------------------------------------------------------*/
/* Path to CMSIS header */
#define CMSIS_CONF_HEADER_PATH "cc2538_cm3.h"

1
arch/cpu/cc2538/dev/gpio-hal-arch.h
View File

@ -53,6 +53,7 @@
#include <stdint.h>
/*---------------------------------------------------------------------------*/
#define PIN_TO_PORT(pin) (pin >> 3)
#define PIN_TO_NUM(pin) (pin % 8)
#define PIN_TO_PORT_BASE(pin) GPIO_PORT_TO_BASE(PIN_TO_PORT(pin))
/*---------------------------------------------------------------------------*/
#define gpio_hal_arch_interrupt_enable(p) do { \

8
arch/cpu/cc2538/spi-arch.h → arch/cpu/cc2538/dev/spi-arch-legacy.h
View File

@ -78,8 +78,8 @@
* - SPI1_RX_PORT
* - SPI1_RX_PIN
*/
#ifndef SPI_ARCH_H_
#define SPI_ARCH_H_
#ifndef SPI_ARCH_LEGACY_H_
#define SPI_ARCH_LEGACY_H_
#include "contiki.h"
@ -138,7 +138,7 @@
#define SPI_WAITFOREOTx() SPIX_WAITFOREOTx(SPI_DEFAULT_INSTANCE)
#define SPI_WAITFOREORx() SPIX_WAITFOREORx(SPI_DEFAULT_INSTANCE)
#ifdef SPI_FLUSH
#error You must include spi-arch.h before spi.h for the CC2538
#error You must include spi-arch-legacy.h before spi-legacy.h for the CC2538
#else
#define SPI_FLUSH() SPIX_FLUSH(SPI_DEFAULT_INSTANCE)
#endif
@ -215,7 +215,7 @@ void spix_cs_init(uint8_t port, uint8_t pin);
/** @} */
#endif /* SPI_ARCH_H_ */
#endif /* SPI_ARCH_LEGACY_H_ */
/**
* @}

355
arch/cpu/cc2538/dev/spi-arch.c Normal file
View File

@ -0,0 +1,355 @@
/*
* Copyright (c) 2016-2017, Yanzi Networks.
* Copyright (c) 2018, University of Bristol.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdint.h>
#include "contiki.h"
#include "reg.h"
#include "dev/spi.h"
#include "gpio-hal-arch.h"
#include "sys/cc.h"
#include "ioc.h"
#include "sys-ctrl.h"
#include "ssi.h"
#include "gpio.h"
#include "sys/log.h"
#include "sys/mutex.h"
/*---------------------------------------------------------------------------*/
/* Log configuration */
#define LOG_MODULE "spi-hal-arch"
#define LOG_LEVEL LOG_LEVEL_NONE
/*---------------------------------------------------------------------------*/
/* Default values for the clock rate divider */
#ifdef SPI_ARCH_CONF_SPI0_CPRS_CPSDVSR
#define SPI_ARCH_SPI0_CPRS_CPSDVSR SPI_ARCH_CONF_SPI0_CPRS_CPSDVSR
#else
#define SPI_ARCH_SPI0_CPRS_CPSDVSR 2
#endif
#ifdef SPI_ARCH_CONF_SPI1_CPRS_CPSDVSR
#define SPI_ARCH_SPI1_CPRS_CPSDVSR SPI_ARCH_CONF_SPI1_CPRS_CPSDVSR
#else
#define SPI_ARCH_SPI1_CPRS_CPSDVSR 2
#endif
#if (SPI_ARCH_SPI0_CPRS_CPSDVSR & 1) == 1 || \
SPI_ARCH_SPI0_CPRS_CPSDVSR < 2 || \
SPI_ARCH_SPI0_CPRS_CPSDVSR > 254
#error SPI_ARCH_SPI0_CPRS_CPSDVSR must be an even number between 2 and 254
#endif
#if (SPI_ARCH_SPI1_CPRS_CPSDVSR & 1) == 1 || \
SPI_ARCH_SPI1_CPRS_CPSDVSR < 2 || \
SPI_ARCH_SPI1_CPRS_CPSDVSR > 254
#error SPI_ARCH_SPI1_CPRS_CPSDVSR must be an even number between 2 and 254
#endif
/*---------------------------------------------------------------------------*/
/* CS set and clear macros */
#define SPIX_CS_CLR(port, pin) GPIO_CLR_PIN(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin))
#define SPIX_CS_SET(port, pin) GPIO_SET_PIN(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin))
/*---------------------------------------------------------------------------*/
/*
* Clock source from which the baud clock is determined for the SSI, according
* to SSI_CC.CS.
*/
#define SSI_SYS_CLOCK SYS_CTRL_SYS_CLOCK
/*---------------------------------------------------------------------------*/
typedef struct {
uint32_t base;
uint32_t ioc_ssirxd_ssi;
uint32_t ioc_pxx_sel_ssi_clkout;
uint32_t ioc_pxx_sel_ssi_txd;
uint8_t ssi_cprs_cpsdvsr;
} spi_regs_t;
/*---------------------------------------------------------------------------*/
static const spi_regs_t spi_regs[SSI_INSTANCE_COUNT] = {
{
.base = SSI0_BASE,
.ioc_ssirxd_ssi = IOC_SSIRXD_SSI0,
.ioc_pxx_sel_ssi_clkout = IOC_PXX_SEL_SSI0_CLKOUT,
.ioc_pxx_sel_ssi_txd = IOC_PXX_SEL_SSI0_TXD,
.ssi_cprs_cpsdvsr = SPI_ARCH_SPI0_CPRS_CPSDVSR,
}, {
.base = SSI1_BASE,
.ioc_ssirxd_ssi = IOC_SSIRXD_SSI1,
.ioc_pxx_sel_ssi_clkout = IOC_PXX_SEL_SSI1_CLKOUT,
.ioc_pxx_sel_ssi_txd = IOC_PXX_SEL_SSI1_TXD,
.ssi_cprs_cpsdvsr = SPI_ARCH_SPI1_CPRS_CPSDVSR,
}
};
typedef struct spi_locks_s {
mutex_t lock;
spi_device_t *owner;
} spi_locks_t;
/* One lock per SPI controller */
spi_locks_t board_spi_locks_spi[SPI_CONTROLLER_COUNT] = { { MUTEX_STATUS_UNLOCKED, NULL } };
/*---------------------------------------------------------------------------*/
static void
spix_wait_tx_ready(spi_device_t *dev)
{
/* Infinite loop until SR_TNF - Transmit FIFO Not Full */
while(!(REG(spi_regs[dev->spi_controller].base + SSI_SR) & SSI_SR_TNF));
}
/*---------------------------------------------------------------------------*/
static int
spix_read_buf(spi_device_t *dev)
{
return REG(spi_regs[dev->spi_controller].base + SSI_DR);
}
/*---------------------------------------------------------------------------*/
static void
spix_write_buf(spi_device_t *dev, int data)
{
REG(spi_regs[dev->spi_controller].base + SSI_DR) = data;
}
/*---------------------------------------------------------------------------*/
static void
spix_wait_eotx(spi_device_t *dev)
{
/* wait until not busy */
while(REG(spi_regs[dev->spi_controller].base + SSI_SR) & SSI_SR_BSY);
}
/*---------------------------------------------------------------------------*/
static void
spix_wait_eorx(spi_device_t *dev)
{
/* wait as long as receive is empty */
while(!(REG(spi_regs[dev->spi_controller].base + SSI_SR) & SSI_SR_RNE));
}
/*---------------------------------------------------------------------------*/
bool
spi_arch_has_lock(spi_device_t *dev)
{
if(board_spi_locks_spi[dev->spi_controller].owner == dev) {
return true;
}
return false;
}
/*---------------------------------------------------------------------------*/
bool
spi_arch_is_bus_locked(spi_device_t *dev)
{
if(board_spi_locks_spi[dev->spi_controller].lock == MUTEX_STATUS_LOCKED) {
return true;
}
return false;
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_arch_lock_and_open(spi_device_t *dev)
{
const spi_regs_t *regs;
uint32_t scr;
uint64_t div;
uint32_t cs_port = PIN_TO_PORT(dev->pin_spi_cs);
uint32_t cs_pin = PIN_TO_NUM(dev->pin_spi_cs);
uint32_t clk_port = PIN_TO_PORT(dev->pin_spi_sck);
uint32_t clk_pin = PIN_TO_NUM(dev->pin_spi_sck);
uint32_t miso_port = PIN_TO_PORT(dev->pin_spi_miso);
uint32_t miso_pin = PIN_TO_NUM(dev->pin_spi_miso);
uint32_t mosi_port = PIN_TO_PORT(dev->pin_spi_mosi);
uint32_t mosi_pin = PIN_TO_NUM(dev->pin_spi_mosi);
uint32_t mode = 0;
/* lock the SPI bus */
if(mutex_try_lock(&board_spi_locks_spi[dev->spi_controller].lock) == false) {
return SPI_DEV_STATUS_BUS_LOCKED;
}
board_spi_locks_spi[dev->spi_controller].owner = dev;
/* Set SPI phase */
if(dev->spi_pha != 0) {
mode = mode | SSI_CR0_SPH;
}
/* Set SPI polarity */
if(dev->spi_pol != 0) {
mode = mode | SSI_CR0_SPO;
}
/* CS pin configuration */
GPIO_SOFTWARE_CONTROL(GPIO_PORT_TO_BASE(cs_port),
GPIO_PIN_MASK(cs_pin));
ioc_set_over(cs_port, cs_pin, IOC_OVERRIDE_DIS);
GPIO_SET_OUTPUT(GPIO_PORT_TO_BASE(cs_port), GPIO_PIN_MASK(cs_pin));
GPIO_SET_PIN(GPIO_PORT_TO_BASE(cs_port), GPIO_PIN_MASK(cs_pin));
regs = &spi_regs[dev->spi_controller];
/* SSI Enable */
REG(SYS_CTRL_RCGCSSI) |= (1 << dev->spi_controller);
/* Start by disabling the peripheral before configuring it */
REG(regs->base + SSI_CR1) = 0;
/* Set the system clock as the SSI clock */
REG(regs->base + SSI_CC) = 0;
/* Set the mux correctly to connect the SSI pins to the correct GPIO pins */
ioc_set_sel(clk_port, clk_pin, regs->ioc_pxx_sel_ssi_clkout);
ioc_set_sel(mosi_port, mosi_pin, regs->ioc_pxx_sel_ssi_txd);
REG(regs->ioc_ssirxd_ssi) = dev->pin_spi_miso;
/* Put all the SSI gpios into peripheral mode */
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(clk_port),
GPIO_PIN_MASK(clk_pin));
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(mosi_port),
GPIO_PIN_MASK(mosi_pin));
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(miso_port),
GPIO_PIN_MASK(miso_pin));
/* Disable any pull ups or the like */
ioc_set_over(clk_port, clk_pin, IOC_OVERRIDE_DIS);
ioc_set_over(mosi_port, mosi_pin, IOC_OVERRIDE_DIS);
ioc_set_over(miso_port, miso_pin, IOC_OVERRIDE_DIS);
/* Configure the clock */
REG(regs->base + SSI_CPSR) = regs->ssi_cprs_cpsdvsr;
/* Configure the mode */
REG(regs->base + SSI_CR0) = mode | (0x07);
/* Configure the SSI serial clock rate */
if(!dev->spi_bit_rate) {
scr = 255;
} else {
div = (uint64_t)regs->ssi_cprs_cpsdvsr * dev->spi_bit_rate;
scr = (SSI_SYS_CLOCK + div - 1) / div;
scr = MIN(MAX(scr, 1), 256) - 1;
}
REG(regs->base + SSI_CR0) = (REG(regs->base + SSI_CR0) & ~SSI_CR0_SCR_M) |
scr << SSI_CR0_SCR_S;
/* Enable the SSI */
REG(regs->base + SSI_CR1) |= SSI_CR1_SSE;
return SPI_DEV_STATUS_OK;
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_arch_close_and_unlock(spi_device_t *dev)
{
if(!spi_arch_has_lock(dev)) {
return SPI_DEV_STATUS_BUS_NOT_OWNED;
}
/* Disable SSI */
REG(SYS_CTRL_RCGCSSI) &= ~(1 << dev->spi_controller);
/* Unlock the SPI bus */
board_spi_locks_spi[dev->spi_controller].owner = NULL;
mutex_unlock(&board_spi_locks_spi[dev->spi_controller].lock);
return SPI_DEV_STATUS_OK;
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_arch_select(spi_device_t *dev)
{
if(!spi_arch_has_lock(dev)) {
return SPI_DEV_STATUS_BUS_NOT_OWNED;
}
SPIX_CS_CLR(PIN_TO_PORT(dev->pin_spi_cs), PIN_TO_NUM(dev->pin_spi_cs));
return SPI_DEV_STATUS_OK;
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_arch_deselect(spi_device_t *dev)
{
SPIX_CS_SET(PIN_TO_PORT(dev->pin_spi_cs), PIN_TO_NUM(dev->pin_spi_cs));
return SPI_DEV_STATUS_OK;
}
/*---------------------------------------------------------------------------*/
/* Assumes that checking dev and bus is not NULL before calling this */
spi_status_t
spi_arch_transfer(spi_device_t *dev,
const uint8_t *write_buf, int wlen,
uint8_t *inbuf, int rlen, int ignore_len)
{
int i;
int totlen;
uint8_t c;
if(!spi_arch_has_lock(dev)) {
return SPI_DEV_STATUS_BUS_NOT_OWNED;
}
LOG_DBG("SPI: transfer (r:%d,w:%d) ", rlen, wlen);
if(write_buf == NULL && wlen > 0) {
return SPI_DEV_STATUS_EINVAL;
}
if(inbuf == NULL && rlen > 0) {
return SPI_DEV_STATUS_EINVAL;
}
totlen = MAX(rlen + ignore_len, wlen);
if(totlen == 0) {
/* Nothing to do */
return SPI_DEV_STATUS_OK;
}
LOG_DBG_("%c%c%c: %u ", rlen > 0 ? 'R' : '-', wlen > 0 ? 'W' : '-',
ignore_len > 0 ? 'S' : '-', totlen);
for(i = 0; i < totlen; i++) {
spix_wait_tx_ready(dev);
c = i < wlen ? write_buf[i] : 0;
spix_write_buf(dev, c);
LOG_DBG_("%c%02x->", i < rlen ? ' ' : '#', c);
spix_wait_eotx(dev);
spix_wait_eorx(dev);
c = spix_read_buf(dev);
if(i < rlen) {
inbuf[i] = c;
}
LOG_DBG_("%02x", c);
}
LOG_DBG_("\n");
return SPI_DEV_STATUS_OK;
}
/*---------------------------------------------------------------------------*/

4
arch/cpu/cc2538/dev/spi.c → arch/cpu/cc2538/dev/spi-legacy.c
View File

@ -39,11 +39,11 @@
*/
#include "contiki.h"
#include "reg.h"
#include "spi-arch.h"
#include "dev/spi-arch-legacy.h"
#include "sys/cc.h"
#include "dev/ioc.h"
#include "dev/sys-ctrl.h"
#include "dev/spi.h"
#include "dev/spi-legacy.h"
#include "dev/ssi.h"
#include "dev/gpio.h"
/*---------------------------------------------------------------------------*/

1
arch/cpu/cc26xx-cc13xx/Makefile.cc26xx-cc13xx
View File

@ -36,6 +36,7 @@ CONTIKI_CPU_SOURCEFILES += gpio-interrupt.c gpio-hal-arch.c oscillators.c
CONTIKI_CPU_SOURCEFILES += rf-core.c rf-ble.c ieee-mode.c
CONTIKI_CPU_SOURCEFILES += ble-cc2650.c ble-hal-cc26xx.c ble-addr.c rf-ble-cmd.c
CONTIKI_CPU_SOURCEFILES += random.c soc-trng.c int-master.c
CONTIKI_CPU_SOURCEFILES += spi-arch.c
MODULES += os/lib/dbg-io

2
arch/cpu/cc26xx-cc13xx/cc13xx-cc26xx-def.h
View File

@ -104,5 +104,7 @@
/*---------------------------------------------------------------------------*/
#define GPIO_HAL_CONF_ARCH_SW_TOGGLE 0
/*---------------------------------------------------------------------------*/
#define SPI_CONF_CONTROLLER_COUNT 2
/*---------------------------------------------------------------------------*/
#endif /* CC13XX_CC26XX_DEF_H_ */
/*---------------------------------------------------------------------------*/

237
arch/cpu/cc26xx-cc13xx/dev/spi-arch.c Normal file
View File

@ -0,0 +1,237 @@
/*
* Copyright (c) 2017, University of Bristol - http://www.bristol.ac.uk/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "contiki.h"
#include "ti-lib.h"
#include "dev/spi.h"
#include "sys/mutex.h"
#include <stdint.h>
#include <stdbool.h>
typedef struct spi_locks_s {
mutex_t lock;
spi_device_t *owner;
} spi_locks_t;
/* One lock per SPI controller */
spi_locks_t board_spi_locks_spi[SPI_CONTROLLER_COUNT] = { { MUTEX_STATUS_UNLOCKED, NULL } };
/*---------------------------------------------------------------------------*/
/* Arch-specific properties of each SPI controller */
typedef struct board_spi_controller_s {
uint32_t ssi_base;
uint32_t power_domain;
uint32_t prcm_periph;
uint32_t ssi_clkgr_clk_en;
} board_spi_controller_t;
static const board_spi_controller_t spi_controller[SPI_CONTROLLER_COUNT] = {
{
.ssi_base = SSI0_BASE,
.power_domain = PRCM_DOMAIN_SERIAL,
.prcm_periph = PRCM_PERIPH_SSI0,
.ssi_clkgr_clk_en = PRCM_SSICLKGR_CLK_EN_SSI0
},
{
.ssi_base = SSI1_BASE,
.power_domain = PRCM_DOMAIN_PERIPH,
.prcm_periph = PRCM_PERIPH_SSI1,
.ssi_clkgr_clk_en = PRCM_SSICLKGR_CLK_EN_SSI1
}
};
/*---------------------------------------------------------------------------*/
bool
spi_arch_has_lock(spi_device_t *dev)
{
if(board_spi_locks_spi[dev->spi_controller].owner == dev) {
return true;
}
return false;
}
/*---------------------------------------------------------------------------*/
bool
spi_arch_is_bus_locked(spi_device_t *dev)
{
if(board_spi_locks_spi[dev->spi_controller].lock == MUTEX_STATUS_LOCKED) {
return true;
}
return false;
}
/*---------------------------------------------------------------------------*/
static uint32_t
get_mode(spi_device_t *dev)
{
/* Select the correct SPI mode */
if(dev->spi_pha == 0 && dev->spi_pol == 0) {
return SSI_FRF_MOTO_MODE_0;
} else if(dev->spi_pha != 0 && dev->spi_pol == 0) {
return SSI_FRF_MOTO_MODE_1;
} else if(dev->spi_pha == 0 && dev->spi_pol != 0) {
return SSI_FRF_MOTO_MODE_2;
} else {
return SSI_FRF_MOTO_MODE_3;
}
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_arch_lock_and_open(spi_device_t *dev)
{
uint32_t c;
/* Lock the SPI bus */
if(mutex_try_lock(&board_spi_locks_spi[dev->spi_controller].lock) == false) {
return SPI_DEV_STATUS_BUS_LOCKED;
}
board_spi_locks_spi[dev->spi_controller].owner = dev;
/* CS pin configuration */
ti_lib_ioc_pin_type_gpio_output(dev->pin_spi_cs);
/* First, make sure the SERIAL PD is on */
ti_lib_prcm_power_domain_on(spi_controller[dev->spi_controller].power_domain);
while((ti_lib_prcm_power_domain_status(spi_controller[dev->spi_controller].power_domain)
!= PRCM_DOMAIN_POWER_ON)) ;
/* Enable clock in active mode */
ti_lib_rom_prcm_peripheral_run_enable(spi_controller[dev->spi_controller].prcm_periph);
ti_lib_prcm_load_set();
while(!ti_lib_prcm_load_get()) ;
/* SPI configuration */
ti_lib_ssi_int_disable(spi_controller[dev->spi_controller].ssi_base, SSI_RXOR | SSI_RXFF | SSI_RXTO | SSI_TXFF);
ti_lib_ssi_int_clear(spi_controller[dev->spi_controller].ssi_base, SSI_RXOR | SSI_RXTO);
ti_lib_rom_ssi_config_set_exp_clk(spi_controller[dev->spi_controller].ssi_base, ti_lib_sys_ctrl_clock_get(),
get_mode(dev), SSI_MODE_MASTER, dev->spi_bit_rate, 8);
ti_lib_rom_ioc_pin_type_ssi_master(spi_controller[dev->spi_controller].ssi_base, dev->pin_spi_miso,
dev->pin_spi_mosi, IOID_UNUSED, dev->pin_spi_sck);
ti_lib_ssi_enable(spi_controller[dev->spi_controller].ssi_base);
/* Get rid of residual data from SSI port */
while(ti_lib_ssi_data_get_non_blocking(spi_controller[dev->spi_controller].ssi_base, &c)) ;
return SPI_DEV_STATUS_OK;
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_arch_close_and_unlock(spi_device_t *dev)
{
if(!spi_arch_has_lock(dev)) {
return SPI_DEV_STATUS_BUS_NOT_OWNED;
}
/* Power down SSI */
ti_lib_rom_prcm_peripheral_run_disable(spi_controller[dev->spi_controller].prcm_periph);
ti_lib_prcm_load_set();
while(!ti_lib_prcm_load_get()) ;
/* Restore pins to a low-consumption state */
ti_lib_ioc_pin_type_gpio_input(dev->pin_spi_miso);
ti_lib_ioc_io_port_pull_set(dev->pin_spi_miso, IOC_IOPULL_DOWN);
ti_lib_ioc_pin_type_gpio_input(dev->pin_spi_mosi);
ti_lib_ioc_io_port_pull_set(dev->pin_spi_mosi, IOC_IOPULL_DOWN);
ti_lib_ioc_pin_type_gpio_input(dev->pin_spi_sck);
ti_lib_ioc_io_port_pull_set(dev->pin_spi_sck, IOC_IOPULL_DOWN);
/* Unlock the SPI bus */
board_spi_locks_spi[dev->spi_controller].owner = NULL;
mutex_unlock(&board_spi_locks_spi[dev->spi_controller].lock);
return SPI_DEV_STATUS_OK;
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_arch_transfer(spi_device_t *dev,
const uint8_t *write_buf, int wlen,
uint8_t *inbuf, int rlen, int ignore_len)
{
int i;
int totlen;
uint32_t c;
if(!spi_arch_has_lock(dev)) {
return SPI_DEV_STATUS_BUS_NOT_OWNED;
}
if(ti_lib_prcm_power_domain_status(spi_controller[dev->spi_controller].power_domain)
!= PRCM_DOMAIN_POWER_ON) {
return SPI_DEV_STATUS_CLOSED;
}
/* Then check the 'run mode' clock gate */
if(!(HWREG(PRCM_BASE + PRCM_O_SSICLKGR) & spi_controller[dev->spi_controller].ssi_clkgr_clk_en)) {
return SPI_DEV_STATUS_CLOSED;
}
totlen = MAX(rlen + ignore_len, wlen);
if(totlen == 0) {
/* Nothing to do */
return SPI_DEV_STATUS_OK;
}
for(i = 0; i < totlen; i++) {
c = i < wlen ? write_buf[i] : 0;
ti_lib_ssi_data_put(spi_controller[dev->spi_controller].ssi_base, (uint8_t)c);
ti_lib_rom_ssi_data_get(spi_controller[dev->spi_controller].ssi_base, &c);
if(i < rlen) {
inbuf[i] = (uint8_t)c;
}
}
while(ti_lib_rom_ssi_data_get_non_blocking(spi_controller[dev->spi_controller].ssi_base, &c)) ;
return SPI_DEV_STATUS_OK;
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_arch_select(spi_device_t *dev)
{
if(!spi_arch_has_lock(dev)) {
return SPI_DEV_STATUS_BUS_NOT_OWNED;
}
ti_lib_gpio_clear_dio(dev->pin_spi_cs);
return SPI_DEV_STATUS_OK;
}
spi_status_t
spi_arch_deselect(spi_device_t *dev)
{
ti_lib_gpio_set_dio(dev->pin_spi_cs);
return SPI_DEV_STATUS_OK;
}

2
arch/cpu/msp430/cc2420-arch-sfd.c
View File

@ -29,7 +29,7 @@
*/
#include "contiki.h"
#include "dev/spi.h"
#include "dev/spi-legacy.h"
#include "cc2420.h"
#include "isr_compat.h"

2
arch/cpu/msp430/cc2420-arch.c
View File

@ -31,7 +31,7 @@
#include "contiki.h"
#include "contiki-net.h"
#include "dev/spi.h"
#include "dev/spi-legacy.h"
#include "cc2420.h"
#include "isr_compat.h"

2
arch/cpu/msp430/cc2520-arch-sfd.c
View File

@ -28,7 +28,7 @@
*/
#include "contiki.h"
#include "dev/spi.h"
#include "dev/spi-legacy.h"
#include "dev/cc2520/cc2520.h"
#include "isr_compat.h"

2
arch/cpu/msp430/cc2520-arch.c
View File

@ -30,7 +30,7 @@
#include "contiki.h"
#include "contiki-net.h"
#include "dev/spi.h"
#include "dev/spi-legacy.h"
#include "dev/cc2520/cc2520.h"
#include "isr_compat.h"

0
arch/cpu/msp430/f1xxx/spi.c → arch/cpu/msp430/f1xxx/spi-legacy.c
View File

0
arch/cpu/msp430/f2xxx/spi.c → arch/cpu/msp430/f2xxx/spi-legacy.c
View File

0
arch/cpu/msp430/f5xxx/spi.c → arch/cpu/msp430/f5xxx/spi-legacy.c
View File

2
arch/dev/cc2420/cc2420.c
View File

@ -39,7 +39,7 @@
#include "sys/energest.h"
#include "dev/leds.h"
#include "dev/spi.h"
#include "dev/spi-legacy.h"
#include "cc2420.h"
#include "cc2420_const.h"

2
arch/dev/cc2420/cc2420.h
View File

@ -43,7 +43,7 @@
#define CC2420_H_
#include "contiki.h"
#include "dev/spi.h"
#include "dev/spi-legacy.h"
#include "dev/radio.h"
#include "cc2420_const.h"
#include "lib/aes-128.h"

11
arch/dev/ext-flash/README.md Normal file
View File

@ -0,0 +1,11 @@
# Ext-flash Driver
This is a generic driver for external SPI flash memories. It has been tested with the following parts:
- Winbond W25X20CL
- Winbond W25X40CL
- Macronix MX25R8035F
- Macronix MX25R1635F
- Macronix MX25R6435F
- Macronix MX25U6435F
These parts have identical instruction sets; only the manufacturer and device ID differ, which must be specified in `board.h`.

351
arch/platform/srf06-cc26xx/common/ext-flash.c → arch/dev/ext-flash/ext-flash.c
View File

@ -38,12 +38,34 @@
/*---------------------------------------------------------------------------*/
#include "contiki.h"
#include "ext-flash.h"
#include "ti-lib.h"
#include "board-spi.h"
#include "dev/spi.h"
#include "gpio-hal.h"
#include "sys/log.h"
#include <stdint.h>
#include <stdbool.h>
/*---------------------------------------------------------------------------*/
#ifndef EXT_FLASH_SPI_CONTROLLER
#define EXT_FLASH_SPI_CONTROLLER 0xFF /* No controller */
#define EXT_FLASH_SPI_PIN_SCK GPIO_HAL_PIN_UNKNOWN
#define EXT_FLASH_SPI_PIN_MOSI GPIO_HAL_PIN_UNKNOWN
#define EXT_FLASH_SPI_PIN_MISO GPIO_HAL_PIN_UNKNOWN
#define EXT_FLASH_SPI_PIN_CS GPIO_HAL_PIN_UNKNOWN
#define EXT_FLASH_DEVICE_ID 0xFF
#define EXT_FLASH_MID 0xFF
#define EXT_FLASH_PROGRAM_PAGE_SIZE 256
#define EXT_FLASH_ERASE_SECTOR_SIZE 4096
#endif /* EXT_FLASH_SPI_CONTROLLER */
/*---------------------------------------------------------------------------*/
/* Log configuration */
#define LOG_MODULE "ext-flash"
#define LOG_LEVEL LOG_LEVEL_NONE
/*---------------------------------------------------------------------------*/
/* Instruction codes */
#define BLS_CODE_PROGRAM 0x02 /**< Page Program */
@ -72,38 +94,51 @@
#define BLS_STATUS_BIT_BUSY 0x01 /**< Busy bit of the status register */
/*---------------------------------------------------------------------------*/
/* Part specific constants */
#define BLS_DEVICE_ID_W25X20CL 0x11
#define BLS_DEVICE_ID_W25X40CL 0x12
#define BLS_DEVICE_ID_MX25R8035F 0x14
#define BLS_DEVICE_ID_MX25R1635F 0x15
#define BLS_WINBOND_MID 0xEF
#define BLS_MACRONIX_MID 0xC2
#define BLS_PROGRAM_PAGE_SIZE 256
#define BLS_ERASE_SECTOR_SIZE 4096
/*---------------------------------------------------------------------------*/
#define VERIFY_PART_LOCKED -2
#define VERIFY_PART_ERROR -1
#define VERIFY_PART_POWERED_DOWN 0
#define VERIFY_PART_OK 1
/*---------------------------------------------------------------------------*/
static spi_device_t flash_spi_configuration_default = {
.spi_controller = EXT_FLASH_SPI_CONTROLLER,
.pin_spi_sck = EXT_FLASH_SPI_PIN_SCK,
.pin_spi_miso = EXT_FLASH_SPI_PIN_MISO,
.pin_spi_mosi = EXT_FLASH_SPI_PIN_MOSI,
.pin_spi_cs = EXT_FLASH_SPI_PIN_CS,
.spi_bit_rate = 4000000,
.spi_pha = 0,
.spi_pol = 0
};
/*---------------------------------------------------------------------------*/
/**
* Get spi configuration, return default configuration if NULL
*/
static spi_device_t*
get_spi_conf(spi_device_t *conf) {
if(conf == NULL) {
return &flash_spi_configuration_default;
}
return conf;
}/*---------------------------------------------------------------------------*/
/**
* Clear external flash CSN line
*/
static void
select_on_bus(void)
static bool
select_on_bus(spi_device_t *flash_spi_configuration)
{
ti_lib_gpio_clear_dio(BOARD_IOID_FLASH_CS);
if(spi_select(flash_spi_configuration) == SPI_DEV_STATUS_OK) {
return true;
}
return false;
}
/*---------------------------------------------------------------------------*/
/**
* Set external flash CSN line
*/
static void
deselect(void)
deselect(spi_device_t *flash_spi_configuration)
{
ti_lib_gpio_set_dio(BOARD_IOID_FLASH_CS);
spi_deselect(flash_spi_configuration);
}
/*---------------------------------------------------------------------------*/
/**
@ -111,20 +146,19 @@ deselect(void)
* \return True when successful.
*/
static bool
wait_ready(void)
wait_ready(spi_device_t *flash_spi_configuration)
{
bool ret;
const uint8_t wbuf[1] = { BLS_CODE_READ_STATUS };
select_on_bus();
if(select_on_bus(flash_spi_configuration) == false) {
return false;
}
/* Throw away all garbages */
board_spi_flush();
ret = spi_write(flash_spi_configuration, wbuf, sizeof(wbuf));
ret = board_spi_write(wbuf, sizeof(wbuf));
if(ret == false) {
deselect();
if(ret != SPI_DEV_STATUS_OK) {
deselect(flash_spi_configuration);
return false;
}
@ -135,19 +169,20 @@ wait_ready(void)
* Thread could have yielded while waiting for flash
* erase/program to complete.
*/
ret = board_spi_read(&buf, sizeof(buf));
ret = spi_read(flash_spi_configuration, &buf, sizeof(buf));
if(ret == false) {
if(ret != SPI_DEV_STATUS_OK) {
/* Error */
deselect();
deselect(flash_spi_configuration);
return false;
}
if(!(buf & BLS_STATUS_BIT_BUSY)) {
/* Now ready */
break;
}
}
deselect();
deselect(flash_spi_configuration);
return true;
}
/*---------------------------------------------------------------------------*/
@ -159,32 +194,30 @@ wait_ready(void)
* was powered down
*/
static uint8_t
verify_part(void)
verify_part(spi_device_t *flash_spi_configuration)
{
const uint8_t wbuf[] = { BLS_CODE_MDID, 0xFF, 0xFF, 0x00 };
uint8_t rbuf[2] = { 0, 0 };
bool ret;
select_on_bus();
if(select_on_bus(flash_spi_configuration) == false) {
return VERIFY_PART_LOCKED;
}
ret = board_spi_write(wbuf, sizeof(wbuf));
if(ret == false) {
deselect();
if(spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) != SPI_DEV_STATUS_OK) {
deselect(flash_spi_configuration);
return VERIFY_PART_ERROR;
}
ret = board_spi_read(rbuf, sizeof(rbuf));
deselect();
if(ret == false) {
ret = spi_read(flash_spi_configuration, rbuf, sizeof(rbuf));
deselect(flash_spi_configuration);
if(ret != SPI_DEV_STATUS_OK) {
return VERIFY_PART_ERROR;
}
if((rbuf[0] != BLS_WINBOND_MID && rbuf[0] != BLS_MACRONIX_MID) ||
(rbuf[1] != BLS_DEVICE_ID_W25X20CL && rbuf[1] != BLS_DEVICE_ID_W25X40CL
&& rbuf[1] != BLS_DEVICE_ID_MX25R8035F
&& rbuf[1] != BLS_DEVICE_ID_MX25R1635F)) {
LOG_DBG("Verify: %02x %02x\n", rbuf[0], rbuf[1]);
if(rbuf[0] != EXT_FLASH_MID || rbuf[1] != EXT_FLASH_DEVICE_ID) {
return VERIFY_PART_POWERED_DOWN;
}
return VERIFY_PART_OK;
@ -194,34 +227,41 @@ verify_part(void)
* \brief Put the device in power save mode. No access to data; only
* the status register is accessible.
*/
static void
power_down(void)
static bool
power_down(spi_device_t *flash_spi_configuration)
{
uint8_t cmd;
uint8_t i;
/* First, wait for the device to be ready */
if(wait_ready() == false) {
if(wait_ready(flash_spi_configuration) == false) {
/* Entering here will leave the device in standby instead of powerdown */
return;
return false;
}
cmd = BLS_CODE_PD;
select_on_bus();
board_spi_write(&cmd, sizeof(cmd));
deselect();
if(select_on_bus(flash_spi_configuration) == false) {
return false;
}
if(spi_write_byte(flash_spi_configuration, cmd) != SPI_DEV_STATUS_OK) {
deselect(flash_spi_configuration);
return false;
}
deselect(flash_spi_configuration);
i = 0;
while(i < 10) {
if(verify_part() == VERIFY_PART_POWERED_DOWN) {
if(verify_part(flash_spi_configuration) == VERIFY_PART_POWERED_DOWN) {
/* Device is powered down */
return;
return true;
}
i++;
}
/* Should not be required */
deselect();
deselect(flash_spi_configuration);
return false;
}
/*---------------------------------------------------------------------------*/
/**
@ -229,20 +269,23 @@ power_down(void)
* \return True if the command was written successfully
*/
static bool
power_standby(void)
power_standby(spi_device_t *flash_spi_configuration)
{
uint8_t cmd;
bool success;
cmd = BLS_CODE_RPD;
select_on_bus();
success = board_spi_write(&cmd, sizeof(cmd));
if(success) {
success = wait_ready() == true ? true : false;
if(select_on_bus(flash_spi_configuration) == false) {
return false;
}
deselect();
success = (spi_write(flash_spi_configuration, &cmd, sizeof(cmd)) == SPI_DEV_STATUS_OK);
if(success) {
success = wait_ready(flash_spi_configuration) == true ? true : false;
}
deselect(flash_spi_configuration);
return success;
}
@ -252,14 +295,17 @@ power_standby(void)
* \return True when successful.
*/
static bool
write_enable(void)
write_enable(spi_device_t *flash_spi_configuration)
{
bool ret;
const uint8_t wbuf[] = { BLS_CODE_WRITE_ENABLE };
select_on_bus();
ret = board_spi_write(wbuf, sizeof(wbuf));
deselect();
if(select_on_bus(flash_spi_configuration) == false) {
return false;
}
ret = (spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) == SPI_DEV_STATUS_OK);
deselect(flash_spi_configuration);
if(ret == false) {
return false;
@ -268,39 +314,66 @@ write_enable(void)
}
/*---------------------------------------------------------------------------*/
bool
ext_flash_open()
ext_flash_open(spi_device_t *conf)
{
board_spi_open(4000000, BOARD_IOID_SPI_CLK_FLASH);
spi_device_t *flash_spi_configuration;
/* GPIO pin configuration */
ti_lib_ioc_pin_type_gpio_output(BOARD_IOID_FLASH_CS);
flash_spi_configuration = get_spi_conf(conf);
/* Check if platform has ext-flash */
if(flash_spi_configuration->pin_spi_sck == GPIO_HAL_PIN_UNKNOWN) {
return false;
}
if(spi_acquire(flash_spi_configuration) != SPI_DEV_STATUS_OK) {
return false;
}
/* Default output to clear chip select */
deselect();
deselect(flash_spi_configuration);
/* Put the part is standby mode */
power_standby();
power_standby(flash_spi_configuration);
return verify_part() == VERIFY_PART_OK ? true : false;
}
/*---------------------------------------------------------------------------*/
void
ext_flash_close()
{
/* Put the part in low power mode */
power_down();
if (verify_part(flash_spi_configuration) == VERIFY_PART_OK) {
return true;
}
board_spi_close();
/* Failed to verify */
spi_release(flash_spi_configuration);
return false;
}
/*---------------------------------------------------------------------------*/
bool
ext_flash_read(size_t offset, size_t length, uint8_t *buf)
ext_flash_close(spi_device_t *conf)
{
bool ret;
spi_device_t *flash_spi_configuration;
flash_spi_configuration = get_spi_conf(conf);
/* Put the part in low power mode */
ret = power_down(flash_spi_configuration);
/* SPI is released no matter if power_down() succeeds or fails */
if(spi_release(flash_spi_configuration) != SPI_DEV_STATUS_OK) {
return false;
}
return ret;
}
/*---------------------------------------------------------------------------*/
bool
ext_flash_read(spi_device_t *conf, uint32_t offset, uint32_t length, uint8_t *buf)
{
uint8_t wbuf[4];
bool ret;
spi_device_t *flash_spi_configuration;
flash_spi_configuration = get_spi_conf(conf);
/* Wait till previous erase/program operation completes */
bool ret = wait_ready();
if(ret == false) {
if(wait_ready(flash_spi_configuration) == false) {
return false;
}
@ -313,41 +386,44 @@ ext_flash_read(size_t offset, size_t length, uint8_t *buf)
wbuf[2] = (offset >> 8) & 0xff;
wbuf[3] = offset & 0xff;
select_on_bus();
if(board_spi_write(wbuf, sizeof(wbuf)) == false) {
/* failure */
deselect();
if(select_on_bus(flash_spi_configuration) == false) {
return false;
}
ret = board_spi_read(buf, length);
if(spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) != SPI_DEV_STATUS_OK) {
/* failure */
deselect(flash_spi_configuration);
return false;
}
deselect();
ret = (spi_read(flash_spi_configuration, buf, length) == SPI_DEV_STATUS_OK);
deselect(flash_spi_configuration);
return ret;
}
/*---------------------------------------------------------------------------*/
bool
ext_flash_write(size_t offset, size_t length, const uint8_t *buf)
ext_flash_write(spi_device_t *conf, uint32_t offset, uint32_t length, const uint8_t *buf)
{
uint8_t wbuf[4];
bool ret;
size_t ilen; /* interim length per instruction */
uint32_t ilen; /* interim length per instruction */
spi_device_t *flash_spi_configuration;
flash_spi_configuration = get_spi_conf(conf);
while(length > 0) {
/* Wait till previous erase/program operation completes */
ret = wait_ready();
if(ret == false) {
if(wait_ready(flash_spi_configuration) == false) {
return false;
}
ret = write_enable();
if(ret == false) {
if(write_enable(flash_spi_configuration) == false) {
return false;
}
ilen = BLS_PROGRAM_PAGE_SIZE - (offset % BLS_PROGRAM_PAGE_SIZE);
ilen = EXT_FLASH_PROGRAM_PAGE_SIZE - (offset % EXT_FLASH_PROGRAM_PAGE_SIZE);
if(length < ilen) {
ilen = length;
}
@ -365,28 +441,30 @@ ext_flash_write(size_t offset, size_t length, const uint8_t *buf)
* is not imposed here since above instructions
* should be enough to delay
* as much. */
select_on_bus();
if(board_spi_write(wbuf, sizeof(wbuf)) == false) {
/* failure */
deselect();
if(select_on_bus(flash_spi_configuration) == false) {
return false;
}
if(board_spi_write(buf, ilen) == false) {
if(spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) != SPI_DEV_STATUS_OK) {
/* failure */
deselect();
deselect(flash_spi_configuration);
return false;
}
if(spi_write(flash_spi_configuration, buf, ilen) != SPI_DEV_STATUS_OK) {
/* failure */
deselect(flash_spi_configuration);
return false;
}
buf += ilen;
deselect();
deselect(flash_spi_configuration);
}
return true;
}
/*---------------------------------------------------------------------------*/
bool
ext_flash_erase(size_t offset, size_t length)
ext_flash_erase(spi_device_t *conf, uint32_t offset, uint32_t length)
{
/*
* Note that Block erase might be more efficient when the floor map
@ -394,24 +472,25 @@ ext_flash_erase(size_t offset, size_t length)
* sector erase is used blindly.
*/
uint8_t wbuf[4];
bool ret;
size_t i, numsectors;
size_t endoffset = offset + length - 1;
uint32_t i, numsectors;
uint32_t endoffset = offset + length - 1;
spi_device_t *flash_spi_configuration;
offset = (offset / BLS_ERASE_SECTOR_SIZE) * BLS_ERASE_SECTOR_SIZE;
numsectors = (endoffset - offset + BLS_ERASE_SECTOR_SIZE - 1) / BLS_ERASE_SECTOR_SIZE;
flash_spi_configuration = get_spi_conf(conf);
offset = (offset / EXT_FLASH_ERASE_SECTOR_SIZE) * EXT_FLASH_ERASE_SECTOR_SIZE;
numsectors = (endoffset - offset + EXT_FLASH_ERASE_SECTOR_SIZE - 1) / EXT_FLASH_ERASE_SECTOR_SIZE;
wbuf[0] = BLS_CODE_SECTOR_ERASE;
for(i = 0; i < numsectors; i++) {
/* Wait till previous erase/program operation completes */
ret = wait_ready();
if(ret == false) {
if(wait_ready(flash_spi_configuration) == false) {
return false;
}
ret = write_enable();
if(ret == false) {
if(write_enable(flash_spi_configuration) == false) {
return false;
}
@ -419,37 +498,37 @@ ext_flash_erase(size_t offset, size_t length)
wbuf[2] = (offset >> 8) & 0xff;
wbuf[3] = offset & 0xff;
select_on_bus();
if(board_spi_write(wbuf, sizeof(wbuf)) == false) {
/* failure */
deselect();
if(select_on_bus(flash_spi_configuration) == false) {
return false;
}
deselect();
offset += BLS_ERASE_SECTOR_SIZE;
if(spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) != SPI_DEV_STATUS_OK) {
/* failure */
deselect(flash_spi_configuration);
return false;
}
deselect(flash_spi_configuration);
offset += EXT_FLASH_ERASE_SECTOR_SIZE;
}
return true;
}
/*---------------------------------------------------------------------------*/
bool
ext_flash_test(void)
ext_flash_init(spi_device_t *conf)
{
bool ret;
if(ext_flash_open(conf) == false) {
return false;
}
ret = ext_flash_open();
ext_flash_close();
if(ext_flash_close(conf) == false) {
return false;
}
return ret;
}
/*---------------------------------------------------------------------------*/
void
ext_flash_init()
{
ext_flash_open();
ext_flash_close();
LOG_INFO("Flash init successful\n");
return true;
}
/*---------------------------------------------------------------------------*/
/** @} */

26
arch/platform/srf06-cc26xx/common/ext-flash.h → arch/dev/ext-flash/ext-flash.h
View File

@ -42,25 +42,30 @@
#ifndef EXT_FLASH_H_
#define EXT_FLASH_H_
/*---------------------------------------------------------------------------*/
#include "dev/spi.h"
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
/*---------------------------------------------------------------------------*/
/**
* \brief Initialize storage driver.
* \param conf SPI bus configuration struct. NULL for default.
* \return True when successful.
*/
bool ext_flash_open(void);
bool ext_flash_open(spi_device_t *conf);
/**
* \brief Close the storage driver
* \param conf SPI bus configuration struct. NULL for default.
* \return True when successful.
*
* This call will put the device in its lower power mode (power down).
*/
void ext_flash_close(void);
bool ext_flash_close(spi_device_t *conf);
/**
* \brief Read storage content
* \param conf SPI bus configuration struct. NULL for default.
* \param offset Address to read from
* \param length Number of bytes to read
* \param buf Buffer where to store the read bytes
@ -68,10 +73,11 @@ void ext_flash_close(void);
*
* buf must be allocated by the caller
*/
bool ext_flash_read(size_t offset, size_t length, uint8_t *buf);
bool ext_flash_read(spi_device_t *conf, uint32_t offset, uint32_t length, uint8_t *buf);
/**
* \brief Erase storage sectors corresponding to the range.
* \param conf SPI bus configuration struct. NULL for default.
* \param offset Address to start erasing
* \param length Number of bytes to erase
* \return True when successful.
@ -79,26 +85,22 @@ bool ext_flash_read(size_t offset, size_t length, uint8_t *buf);
* The erase operation will be sector-wise, therefore a call to this function
* will generally start the erase procedure at an address lower than offset
*/
bool ext_flash_erase(size_t offset, size_t length);
bool ext_flash_erase(spi_device_t *conf, uint32_t offset, uint32_t length);
/**
* \brief Write to storage sectors.
* \param conf SPI bus configuration struct. NULL for default.
* \param offset Address to write to
* \param length Number of bytes to write
* \param buf Buffer holding the bytes to be written
*
* \return True when successful.
*/
bool ext_flash_write(size_t offset, size_t length, const uint8_t *buf);
/**
* \brief Test the flash (power on self-test)
* \return True when successful.
*/
bool ext_flash_test(void);
bool ext_flash_write(spi_device_t *conf, uint32_t offset, uint32_t length, const uint8_t *buf);
/**
* \brief Initialise the external flash
* \param conf SPI bus configuration struct. NULL for default.
*
* This function will explicitly put the part in its lowest power mode
* (power-down).
@ -106,7 +108,7 @@ bool ext_flash_test(void);
* In order to perform any operation, the caller must first wake the device
* up by calling ext_flash_open()
*/
void ext_flash_init(void);
bool ext_flash_init(spi_device_t *conf);
/*---------------------------------------------------------------------------*/
#endif /* EXT_FLASH_H_ */
/*---------------------------------------------------------------------------*/

2
arch/platform/sky/Makefile.common
View File

@ -1,6 +1,6 @@
# $Id: Makefile.common,v 1.3 2010/08/24 16:24:11 joxe Exp $
ARCH=spi.c ds2411.c xmem.c i2c.c node-id.c sensors.c cfs-coffee.c \
ARCH=spi-legacy.c ds2411.c xmem.c i2c.c node-id.c sensors.c cfs-coffee.c \
cc2420.c cc2420-arch.c cc2420-arch-sfd.c \
sky-sensors.c uip-ipchksum.c \
uart1.c slip_uart1.c uart1-putchar.c platform.c

2
arch/platform/sky/dev/i2c.c
View File

@ -41,7 +41,7 @@
#include <stdio.h>
#include <contiki.h>
#include <dev/spi.h>
#include "dev/spi-legacy.h"
#include <dev/leds.h>
#include "dev/i2c.h"

2
arch/platform/sky/dev/xmem.c
View File

@ -43,7 +43,7 @@
#include <stdio.h>
#include <string.h>
#include "dev/spi.h"
#include "dev/spi-legacy.h"
#include "dev/xmem.h"
#include "dev/watchdog.h"

163
arch/platform/srf06-cc26xx/common/board-spi.c
View File

@ -1,163 +0,0 @@
/*
* Copyright (c) 2014, Texas Instruments Incorporated - http://www.ti.com/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup sensortag-cc26xx-spi
* @{
*
* \file
* Board-specific SPI driver common to the Sensortag and LaunchPad
*/
/*---------------------------------------------------------------------------*/
#include "contiki.h"
#include "ti-lib.h"
#include "board-spi.h"
#include "board.h"
#include <stdbool.h>
/*---------------------------------------------------------------------------*/
static bool
accessible(void)
{
/* First, check the PD */
if(ti_lib_prcm_power_domain_status(PRCM_DOMAIN_SERIAL)
!= PRCM_DOMAIN_POWER_ON) {
return false;
}
/* Then check the 'run mode' clock gate */
if(!(HWREG(PRCM_BASE + PRCM_O_SSICLKGR) & PRCM_SSICLKGR_CLK_EN_SSI0)) {
return false;
}
return true;
}
/*---------------------------------------------------------------------------*/
bool
board_spi_write(const uint8_t *buf, size_t len)
{
if(accessible() == false) {
return false;
}
while(len > 0) {
uint32_t ul;
ti_lib_ssi_data_put(SSI0_BASE, *buf);
ti_lib_rom_ssi_data_get(SSI0_BASE, &ul);
len--;
buf++;
}
return true;
}
/*---------------------------------------------------------------------------*/
bool
board_spi_read(uint8_t *buf, size_t len)
{
if(accessible() == false) {
return false;
}
while(len > 0) {
uint32_t ul;
if(!ti_lib_rom_ssi_data_put_non_blocking(SSI0_BASE, 0)) {
/* Error */
return false;
}
ti_lib_rom_ssi_data_get(SSI0_BASE, &ul);
*buf = (uint8_t)ul;
len--;
buf++;
}
return true;
}
/*---------------------------------------------------------------------------*/
void
board_spi_flush()
{
if(accessible() == false) {
return;
}
uint32_t ul;
while(ti_lib_rom_ssi_data_get_non_blocking(SSI0_BASE, &ul));
}
/*---------------------------------------------------------------------------*/
void
board_spi_open(uint32_t bit_rate, uint32_t clk_pin)
{
uint32_t buf;
/* First, make sure the SERIAL PD is on */
ti_lib_prcm_power_domain_on(PRCM_DOMAIN_SERIAL);
while((ti_lib_prcm_power_domain_status(PRCM_DOMAIN_SERIAL)
!= PRCM_DOMAIN_POWER_ON));
/* Enable clock in active mode */
ti_lib_rom_prcm_peripheral_run_enable(PRCM_PERIPH_SSI0);
ti_lib_prcm_load_set();
while(!ti_lib_prcm_load_get());
/* SPI configuration */
ti_lib_ssi_int_disable(SSI0_BASE, SSI_RXOR | SSI_RXFF | SSI_RXTO | SSI_TXFF);
ti_lib_ssi_int_clear(SSI0_BASE, SSI_RXOR | SSI_RXTO);
ti_lib_rom_ssi_config_set_exp_clk(SSI0_BASE, ti_lib_sys_ctrl_clock_get(),
SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, bit_rate, 8);
ti_lib_rom_ioc_pin_type_ssi_master(SSI0_BASE, BOARD_IOID_SPI_MISO,
BOARD_IOID_SPI_MOSI, IOID_UNUSED, clk_pin);
ti_lib_ssi_enable(SSI0_BASE);
/* Get rid of residual data from SSI port */
while(ti_lib_ssi_data_get_non_blocking(SSI0_BASE, &buf));
}
/*---------------------------------------------------------------------------*/
void
board_spi_close()
{
/* Power down SSI0 */
ti_lib_rom_prcm_peripheral_run_disable(PRCM_PERIPH_SSI0);
ti_lib_prcm_load_set();
while(!ti_lib_prcm_load_get());
/* Restore pins to a low-consumption state */
ti_lib_ioc_pin_type_gpio_input(BOARD_IOID_SPI_MISO);
ti_lib_ioc_io_port_pull_set(BOARD_IOID_SPI_MISO, IOC_IOPULL_DOWN);
ti_lib_ioc_pin_type_gpio_input(BOARD_IOID_SPI_MOSI);
ti_lib_ioc_io_port_pull_set(BOARD_IOID_SPI_MOSI, IOC_IOPULL_DOWN);
ti_lib_ioc_pin_type_gpio_input(BOARD_IOID_SPI_CLK_FLASH);
ti_lib_ioc_io_port_pull_set(BOARD_IOID_SPI_CLK_FLASH, IOC_IOPULL_DOWN);
}
/*---------------------------------------------------------------------------*/
/** @} */

114
arch/platform/srf06-cc26xx/common/board-spi.h
View File

@ -1,114 +0,0 @@
/*
* Copyright (c) 2014, Texas Instruments Incorporated - http://www.ti.com/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup cc26xx-srf-tag
* @{
*
* \defgroup common-cc26xx-peripherals CC13xx/CC26xx peripheral driver pool
*
* Drivers for peripherals present on more than one CC13xx/CC26xx board. For
* example, the same external flash driver is used for both the part found on
* the Sensortag as well as the part on the LaunchPad.
*
* @{
*
* \defgroup sensortag-cc26xx-spi SensorTag/LaunchPad SPI functions
* @{
*
* \file
* Header file for the Sensortag/LaunchPad SPI Driver
*/
/*---------------------------------------------------------------------------*/
#ifndef BOARD_SPI_H_
#define BOARD_SPI_H_
/*---------------------------------------------------------------------------*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
/*---------------------------------------------------------------------------*/
/**
* \brief Initialize the SPI interface
* \param bit_rate The bit rate to use
* \param clk_pin The IOID for the clock pin. This can be IOID_0 etc
* \return none
*
* This function will make sure the peripheral is powered, clocked and
* initialised. A chain of calls to board_spi_read(), board_spi_write() and
* board_spi_flush() must be preceded by a call to this function. It is
* recommended to call board_spi_close() after such chain of calls.
*/
void board_spi_open(uint32_t bit_rate, uint32_t clk_pin);
/**
* \brief Close the SPI interface
* \return True when successful.
*
* This function will stop clocks to the SSI module and will set MISO, MOSI
* and CLK to a low leakage state. It is recommended to call this function
* after a chain of calls to board_spi_read() and board_spi_write()
*/
void board_spi_close(void);
/**
* \brief Clear data from the SPI interface
* \return none
*/
void board_spi_flush(void);
/**
* \brief Read from an SPI device
* \param buf The buffer to store data
* \param length The number of bytes to read
* \return True when successful.
*
* Calls to this function must be preceded by a call to board_spi_open(). It is
* recommended to call board_spi_close() at the end of an operation.
*/
bool board_spi_read(uint8_t *buf, size_t length);
/**
* \brief Write to an SPI device
* \param buf The buffer with the data to write
* \param length The number of bytes to write
* \return True when successful.
*
* Calls to this function must be preceded by a call to board_spi_open(). It is
* recommended to call board_spi_close() at the end of an operation.
*/
bool board_spi_write(const uint8_t *buf, size_t length);
/*---------------------------------------------------------------------------*/
#endif /* BOARD_SPI_H_ */
/*---------------------------------------------------------------------------*/
/**
* @}
* @}
* @}
*/

26
arch/platform/srf06-cc26xx/common/xmem.c
View File

@ -60,7 +60,7 @@
void
xmem_init(void)
{
ext_flash_open();
ext_flash_open(NULL);
}
@ -71,21 +71,21 @@ xmem_pread(void *_p, int size, unsigned long addr)
uint8_t x;
int i;
rv = ext_flash_open();
rv = ext_flash_open(NULL);
if(!rv) {
PRINTF("Could not open flash to save config\n");
ext_flash_close();
ext_flash_close(NULL);
return -1;
}
rv = ext_flash_read(addr, size, _p);
rv = ext_flash_read(NULL, addr, size, _p);
for (i = 0; i < size; i++){
x = ~*((uint8_t *)_p + i);
*((uint8_t *)_p+i) = x;
}
ext_flash_close();
ext_flash_close(NULL);
if(rv)
return size;
@ -104,11 +104,11 @@ xmem_pwrite(const void *_buf, int size, unsigned long addr)
uint8_t tmp_buf[XMEM_BUFF_LENGHT];
rv = ext_flash_open();
rv = ext_flash_open(NULL);
if(!rv) {
PRINTF("Could not open flash to save config!\n");
ext_flash_close();
ext_flash_close(NULL);
return -1;
}
@ -117,14 +117,14 @@ xmem_pwrite(const void *_buf, int size, unsigned long addr)
for (i = 0; i < to_write; i++) {
tmp_buf[i] = ~*((uint8_t *)_buf + j + i);
}
rv = ext_flash_write(addr + j, to_write, tmp_buf);
rv = ext_flash_write(NULL, addr + j, to_write, tmp_buf);
if (!rv) {
PRINTF("Could not write flash memory!\n");
return size - remain;
}
}
ext_flash_close();
ext_flash_close(NULL);
return size;
}
@ -135,12 +135,12 @@ xmem_erase(long size, unsigned long addr)
{
int rv;
rv = ext_flash_open();
rv = ext_flash_open(NULL);
if(!rv) {
PRINTF("Could not open flash to save config\n");
ext_flash_close();
ext_flash_close(NULL);
return -1;
}
@ -154,9 +154,9 @@ xmem_erase(long size, unsigned long addr)
return -1;
}
rv = ext_flash_erase(addr, size);
rv = ext_flash_erase(NULL, addr, size);
ext_flash_close();
ext_flash_close(NULL);
watchdog_periodic();

3
arch/platform/srf06-cc26xx/launchpad/Makefile.launchpad
View File

@ -3,7 +3,8 @@ CFLAGS += -DBOARD_LAUNCHPAD=1
CONTIKI_TARGET_DIRS += launchpad common
BOARD_SOURCEFILES += board.c board-buttons.c xmem.c
BOARD_SOURCEFILES += ext-flash.c board-spi.c
MODULES += arch/dev/ext-flash
### Signal that we can be programmed with cc2538-bsl
BOARD_SUPPORTS_BSL=1

2
arch/platform/srf06-cc26xx/launchpad/board.c
View File

@ -93,7 +93,7 @@ board_init()
while(!ti_lib_prcm_load_get());
/* Make sure the external flash is in the lower power mode */
ext_flash_init();
ext_flash_init(NULL);
lpm_register_module(&launchpad_module);

30
arch/platform/srf06-cc26xx/launchpad/cc1310/board.h
View File

@ -103,25 +103,29 @@
#define BOARD_KEY_RIGHT (1 << BOARD_IOID_KEY_RIGHT)
/** @} */
/*---------------------------------------------------------------------------*/
/**
* \brief SPI IOID mappings
*
* Those values are not meant to be modified by the user
* @{
*/
#define BOARD_IOID_SPI_MOSI IOID_9
#define BOARD_IOID_SPI_MISO IOID_8
/** @} */
/*---------------------------------------------------------------------------*/
/**
* \name External flash IOID mapping
*
* Those values are not meant to be modified by the user
* @{
*/
#define BOARD_IOID_FLASH_CS IOID_20
#define BOARD_FLASH_CS (1 << BOARD_IOID_FLASH_CS)
#define BOARD_IOID_SPI_CLK_FLASH IOID_10
#define EXT_FLASH_SPI_CONTROLLER SPI_CONTROLLER_SPI0
#define BOARD_IOID_FLASH_SCK IOID_10
#define BOARD_IOID_FLASH_MOSI IOID_9
#define BOARD_IOID_FLASH_MISO IOID_8
#define BOARD_IOID_FLASH_CS IOID_20
#define EXT_FLASH_SPI_PIN_SCK 10
#define EXT_FLASH_SPI_PIN_MOSI 9
#define EXT_FLASH_SPI_PIN_MISO 8
#define EXT_FLASH_SPI_PIN_CS 20
#define EXT_FLASH_DEVICE_ID 0x14
#define EXT_FLASH_MID 0xC2
#define EXT_FLASH_PROGRAM_PAGE_SIZE 256
#define EXT_FLASH_ERASE_SECTOR_SIZE 4096
/** @} */
/*---------------------------------------------------------------------------*/
/**

31
arch/platform/srf06-cc26xx/launchpad/cc1350/board.h
View File

@ -103,26 +103,29 @@
#define BOARD_KEY_RIGHT (1 << BOARD_IOID_KEY_RIGHT)
/** @} */
/*---------------------------------------------------------------------------*/
/**
* \brief SPI IOID mappings
*
* Those values are not meant to be modified by the user
* @{
*/
#define BOARD_IOID_SPI_MOSI IOID_9
#define BOARD_IOID_SPI_MISO IOID_8
/** @} */
/*---------------------------------------------------------------------------*/
/**
* \name External flash IOID mapping
*
* Those values are not meant to be modified by the user
* @{
*/
#define BOARD_IOID_FLASH_CS IOID_20
#define BOARD_FLASH_CS (1 << BOARD_IOID_FLASH_CS)
#define BOARD_IOID_SPI_CLK_FLASH IOID_10
/** @} */
#define EXT_FLASH_SPI_CONTROLLER SPI_CONTROLLER_SPI0
#define BOARD_IOID_FLASH_SCK IOID_10
#define BOARD_IOID_FLASH_MOSI IOID_9
#define BOARD_IOID_FLASH_MISO IOID_8
#define BOARD_IOID_FLASH_CS IOID_20
#define EXT_FLASH_SPI_PIN_SCK 10
#define EXT_FLASH_SPI_PIN_MOSI 9
#define EXT_FLASH_SPI_PIN_MISO 8
#define EXT_FLASH_SPI_PIN_CS 20
#define EXT_FLASH_DEVICE_ID 0x14
#define EXT_FLASH_MID 0xC2
#define EXT_FLASH_PROGRAM_PAGE_SIZE 256
#define EXT_FLASH_ERASE_SECTOR_SIZE 4096
/*---------------------------------------------------------------------------*/
/**
* \brief I2C IOID mappings

30
arch/platform/srf06-cc26xx/launchpad/cc2650/board.h
View File

@ -103,25 +103,29 @@
#define BOARD_KEY_RIGHT (1 << BOARD_IOID_KEY_RIGHT)
/** @} */
/*---------------------------------------------------------------------------*/
/**
* \brief SPI IOID mappings
*
* Those values are not meant to be modified by the user
* @{
*/
#define BOARD_IOID_SPI_MOSI IOID_9
#define BOARD_IOID_SPI_MISO IOID_8
/** @} */
/*---------------------------------------------------------------------------*/
/**
* \name External flash IOID mapping
*
* Those values are not meant to be modified by the user
* @{
*/
#define BOARD_IOID_FLASH_CS IOID_20
#define BOARD_FLASH_CS (1 << BOARD_IOID_FLASH_CS)
#define BOARD_IOID_SPI_CLK_FLASH IOID_10
#define EXT_FLASH_SPI_CONTROLLER SPI_CONTROLLER_SPI0
#define BOARD_IOID_FLASH_SCK IOID_10
#define BOARD_IOID_FLASH_MOSI IOID_9
#define BOARD_IOID_FLASH_MISO IOID_8
#define BOARD_IOID_FLASH_CS IOID_20
#define EXT_FLASH_SPI_PIN_SCK 10
#define EXT_FLASH_SPI_PIN_MOSI 9
#define EXT_FLASH_SPI_PIN_MISO 8
#define EXT_FLASH_SPI_PIN_CS 20
#define EXT_FLASH_DEVICE_ID 0x14
#define EXT_FLASH_MID 0xC2
#define EXT_FLASH_PROGRAM_PAGE_SIZE 256
#define EXT_FLASH_ERASE_SECTOR_SIZE 4096
/** @} */
/*---------------------------------------------------------------------------*/
/**

6
arch/platform/srf06-cc26xx/sensortag/Makefile.sensortag
View File

@ -6,5 +6,7 @@ CONTIKI_TARGET_DIRS += sensortag common
BOARD_SOURCEFILES += sensortag-sensors.c board-buttons.c sensor-common.c
BOARD_SOURCEFILES += bmp-280-sensor.c tmp-007-sensor.c opt-3001-sensor.c
BOARD_SOURCEFILES += hdc-1000-sensor.c mpu-9250-sensor.c xmem.c
BOARD_SOURCEFILES += ext-flash.c buzzer.c
BOARD_SOURCEFILES += board.c board-spi.c board-i2c.c
BOARD_SOURCEFILES += buzzer.c
BOARD_SOURCEFILES += board.c board-i2c.c
MODULES += arch/dev/ext-flash

2
arch/platform/srf06-cc26xx/sensortag/board.c
View File

@ -146,7 +146,7 @@ board_init()
buzzer_init();
/* Make sure the external flash is in the lower power mode */
ext_flash_init();
ext_flash_init(NULL);
lpm_register_module(&sensortag_module);

30
arch/platform/srf06-cc26xx/sensortag/cc1350/board.h
View File

@ -113,16 +113,6 @@
#define BOARD_KEY_RIGHT (1 << BOARD_IOID_KEY_RIGHT)
/** @} */
/*---------------------------------------------------------------------------*/
/**
* \brief SPI IOID mappings
*
* Those values are not meant to be modified by the user
* @{
*/
#define BOARD_IOID_SPI_MOSI IOID_19
#define BOARD_IOID_SPI_MISO IOID_18
/** @} */
/*---------------------------------------------------------------------------*/
/**
* \name Buzzer configuration
* @{
@ -145,9 +135,23 @@
* Those values are not meant to be modified by the user
* @{
*/
#define BOARD_IOID_FLASH_CS IOID_14
#define BOARD_FLASH_CS (1 << BOARD_IOID_FLASH_CS)
#define BOARD_IOID_SPI_CLK_FLASH IOID_17
#define EXT_FLASH_SPI_CONTROLLER SPI_CONTROLLER_SPI0
#define BOARD_IOID_FLASH_SCK IOID_17
#define BOARD_IOID_FLASH_MOSI IOID_19
#define BOARD_IOID_FLASH_MISO IOID_18
#define BOARD_IOID_FLASH_CS IOID_14
#define EXT_FLASH_SPI_PIN_SCK 17
#define EXT_FLASH_SPI_PIN_MOSI 19
#define EXT_FLASH_SPI_PIN_MISO 18
#define EXT_FLASH_SPI_PIN_CS 14
#define EXT_FLASH_DEVICE_ID 0x14
#define EXT_FLASH_MID 0xC2
#define EXT_FLASH_PROGRAM_PAGE_SIZE 256
#define EXT_FLASH_ERASE_SECTOR_SIZE 4096
/** @} */
/*---------------------------------------------------------------------------*/
/**

34
arch/platform/srf06-cc26xx/sensortag/cc2650/board.h
View File

@ -115,20 +115,6 @@
#define BOARD_KEY_RIGHT (1 << BOARD_IOID_KEY_RIGHT)
/** @} */
/*---------------------------------------------------------------------------*/
/**
* \brief SPI IOID mappings
*
* Those values are not meant to be modified by the user
* @{
*/
#define BOARD_IOID_SPI_SCK IOID_17
#define BOARD_IOID_SPI_MOSI IOID_19
#define BOARD_IOID_SPI_MISO IOID_18
#define BOARD_SPI_SCK (1 << BOARD_IOID_SPI_SCK)
#define BOARD_SPI_MOSI (1 << BOARD_IOID_SPI_MOSI)
#define BOARD_SPI_MISO (1 << BOARD_IOID_SPI_MISO)
/** @} */
/*---------------------------------------------------------------------------*/
/**
* \name Buzzer configuration
* @{
@ -151,9 +137,23 @@
* Those values are not meant to be modified by the user
* @{
*/
#define BOARD_IOID_FLASH_CS IOID_14
#define BOARD_FLASH_CS (1 << BOARD_IOID_FLASH_CS)
#define BOARD_IOID_SPI_CLK_FLASH IOID_17
#define EXT_FLASH_SPI_CONTROLLER SPI_CONTROLLER_SPI0
#define BOARD_IOID_FLASH_SCK IOID_17
#define BOARD_IOID_FLASH_MOSI IOID_19
#define BOARD_IOID_FLASH_MISO IOID_18
#define BOARD_IOID_FLASH_CS IOID_14
#define EXT_FLASH_SPI_PIN_SCK 17
#define EXT_FLASH_SPI_PIN_MOSI 19
#define EXT_FLASH_SPI_PIN_MISO 18
#define EXT_FLASH_SPI_PIN_CS 14
#define EXT_FLASH_DEVICE_ID 0x14
#define EXT_FLASH_MID 0xC2
#define EXT_FLASH_PROGRAM_PAGE_SIZE 256
#define EXT_FLASH_ERASE_SECTOR_SIZE 4096
/** @} */
/*---------------------------------------------------------------------------*/
/**

4
arch/platform/zoul/dev/cc1200-zoul-arch.c
View File

@ -46,10 +46,10 @@
#include "contiki-net.h"
#include "dev/leds.h"
#include "reg.h"
#include "spi-arch.h"
#include "dev/spi-arch-legacy.h"
#include "dev/ioc.h"
#include "dev/sys-ctrl.h"
#include "dev/spi.h"
#include "dev/spi-legacy.h"
#include "dev/ssi.h"
#include "dev/gpio.h"
#include "dev/gpio-hal.h"

4
arch/platform/zoul/dev/mmc-arch.c
View File

@ -39,10 +39,10 @@
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include "spi-arch.h"
#include "dev/spi-arch-legacy.h"
#include "dev/ioc.h"
#include "dev/gpio.h"
#include "dev/spi.h"
#include "dev/spi-legacy.h"
#include "mmc-arch.h"
#define USD_SEL_PORT_BASE GPIO_PORT_TO_BASE(USD_SEL_PORT)

4
arch/platform/zoul/orion/enc28j60-arch-spi.c
View File

@ -43,8 +43,8 @@
* eth-gw SPI arch specifics
*/
/*---------------------------------------------------------------------------*/
#include "spi-arch.h"
#include "spi.h"
#include "dev/spi-arch-legacy.h"
#include "dev/spi-legacy.h"
#include "dev/gpio.h"
/*---------------------------------------------------------------------------*/
#define RESET_PORT GPIO_PORT_TO_BASE(ETH_RESET_PORT)

18
examples/platform-specific/cc26xx/cc26xx-web-demo/cc26xx-web-demo.c
View File

@ -195,15 +195,15 @@ save_config()
int rv;
cc26xx_web_demo_sensor_reading_t *reading = NULL;
rv = ext_flash_open();
rv = ext_flash_open(NULL);
if(!rv) {
printf("Could not open flash to save config\n");
ext_flash_close();
ext_flash_close(NULL);
return;
}
rv = ext_flash_erase(CONFIG_FLASH_OFFSET, sizeof(cc26xx_web_demo_config_t));
rv = ext_flash_erase(NULL, CONFIG_FLASH_OFFSET, sizeof(cc26xx_web_demo_config_t));
if(!rv) {
printf("Error erasing flash\n");
@ -220,14 +220,14 @@ save_config()
}
}
rv = ext_flash_write(CONFIG_FLASH_OFFSET, sizeof(cc26xx_web_demo_config_t),
rv = ext_flash_write(NULL, CONFIG_FLASH_OFFSET, sizeof(cc26xx_web_demo_config_t),
(uint8_t *)&cc26xx_web_demo_config);
if(!rv) {
printf("Error saving config\n");
}
}
ext_flash_close();
ext_flash_close(NULL);
#endif
}
/*---------------------------------------------------------------------------*/
@ -239,18 +239,18 @@ load_config()
cc26xx_web_demo_config_t tmp_cfg;
cc26xx_web_demo_sensor_reading_t *reading = NULL;
int rv = ext_flash_open();
int rv = ext_flash_open(NULL);
if(!rv) {
printf("Could not open flash to load config\n");
ext_flash_close();
ext_flash_close(NULL);
return;
}
rv = ext_flash_read(CONFIG_FLASH_OFFSET, sizeof(tmp_cfg),
rv = ext_flash_read(NULL, CONFIG_FLASH_OFFSET, sizeof(tmp_cfg),
(uint8_t *)&tmp_cfg);
ext_flash_close();
ext_flash_close(NULL);
if(!rv) {
printf("Error loading config\n");

7
os/dev/gpio-hal.h
View File

@ -130,6 +130,13 @@ typedef struct gpio_hal_event_handler_s {
gpio_hal_pin_mask_t pin_mask;
} gpio_hal_event_handler_t;
/*---------------------------------------------------------------------------*/
/**
* \brief Unknown GPIO
*
* A default GPIO value for unknown GPIO
*/
#define GPIO_HAL_PIN_UNKNOWN 0xFF
/*---------------------------------------------------------------------------*/
/**
* \name Core GPIO functions
*

92
os/dev/spi-legacy.h Normal file
View File

@ -0,0 +1,92 @@
/*
* Copyright (c) 2010, Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
/**
* \file
* Basic SPI macros
* \author
* Joakim Eriksson <joakime@sics.se>
* Niclas Finne <nfi@sics.se>
*/
#ifndef SPI_LEGACY_H_
#define SPI_LEGACY_H_
/* Define macros to use for checking SPI transmission status depending
on if it is possible to wait for TX buffer ready. This is possible
on for example MSP430 but not on AVR. */
#ifdef SPI_WAITFORTxREADY
#define SPI_WAITFORTx_BEFORE() SPI_WAITFORTxREADY()
#define SPI_WAITFORTx_AFTER()
#define SPI_WAITFORTx_ENDED() SPI_WAITFOREOTx()
#else /* SPI_WAITFORTxREADY */
#define SPI_WAITFORTx_BEFORE()
#define SPI_WAITFORTx_AFTER() SPI_WAITFOREOTx()
#define SPI_WAITFORTx_ENDED()
#endif /* SPI_WAITFORTxREADY */
extern unsigned char spi_busy;
void spi_init(void);
/* Write one character to SPI */
#define SPI_WRITE(data) \
do { \
SPI_WAITFORTx_BEFORE(); \
SPI_TXBUF = data; \
SPI_WAITFOREOTx(); \
} while(0)
/* Write one character to SPI - will not wait for end
useful for multiple writes with wait after final */
#define SPI_WRITE_FAST(data) \
do { \
SPI_WAITFORTx_BEFORE(); \
SPI_TXBUF = data; \
SPI_WAITFORTx_AFTER(); \
} while(0)
/* Read one character from SPI */
#define SPI_READ(data) \
do { \
SPI_TXBUF = 0; \
SPI_WAITFOREORx(); \
data = SPI_RXBUF; \
} while(0)
/* Flush the SPI read register */
#ifndef SPI_FLUSH
#define SPI_FLUSH() \
do { \
SPI_RXBUF; \
} while(0)
#endif
#endif /* SPI_LEGACY_H_ */

222
os/dev/spi.c Normal file
View File

@ -0,0 +1,222 @@
/*
* Copyright (c) 2016-2017, Yanzi Networks.
* Copyright (c) 2017, University of Bristol - http://www.bristol.ac.uk/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup spi-hal
* @{
*
* \file
* Implementation of the platform-independent aspects of the SPI HAL
*/
/*---------------------------------------------------------------------------*/
#include <dev/spi.h>
#include "contiki.h"
#include <stdint.h>
#include <stdbool.h>
/*---------------------------------------------------------------------------*/
spi_status_t
spi_acquire(spi_device_t *dev)
{
if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) {
return SPI_DEV_STATUS_EINVAL;
}
/* lock and open the bus */
return spi_arch_lock_and_open(dev);
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_release(spi_device_t *dev)
{
if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) {
return SPI_DEV_STATUS_EINVAL;
}
/* close and unlock the bus */
return spi_arch_close_and_unlock(dev);
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_select(spi_device_t *dev)
{
return spi_arch_select(dev);
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_deselect(spi_device_t *dev)
{
return spi_arch_deselect(dev);
}
/*---------------------------------------------------------------------------*/
bool
spi_has_bus(spi_device_t *dev)
{
if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) {
return false;
}
return spi_arch_has_lock(dev);
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_write_byte(spi_device_t *dev, uint8_t data)
{
if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) {
return SPI_DEV_STATUS_EINVAL;
}
if(!spi_arch_has_lock(dev)) {
return SPI_DEV_STATUS_BUS_LOCKED;
}
return spi_arch_transfer(dev, &data, 1, 0, 0, 0);
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_write(spi_device_t *dev, const uint8_t *data, int size)
{
if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) {
return SPI_DEV_STATUS_EINVAL;
}
if(!spi_arch_has_lock(dev)) {
return SPI_DEV_STATUS_BUS_LOCKED;
}
return spi_arch_transfer(dev, data, size, 0, 0, 0);
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_read_byte(spi_device_t *dev, uint8_t *buf)
{
if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) {
return SPI_DEV_STATUS_EINVAL;
}
if(!spi_arch_has_lock(dev)) {
return SPI_DEV_STATUS_BUS_LOCKED;
}
return spi_arch_transfer(dev, NULL, 0, buf, 1, 0);
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_read(spi_device_t *dev, uint8_t *buf, int size)
{
if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) {
return SPI_DEV_STATUS_EINVAL;
}
if(!spi_arch_has_lock(dev)) {
return SPI_DEV_STATUS_BUS_LOCKED;
}
return spi_arch_transfer(dev, NULL, 0, buf, size, 0);
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_read_skip(spi_device_t *dev, int size)
{
if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) {
return SPI_DEV_STATUS_EINVAL;
}
if(!spi_arch_has_lock(dev)) {
return SPI_DEV_STATUS_BUS_LOCKED;
}
return spi_arch_transfer(dev, NULL, 0, NULL, 0, size);
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_transfer(spi_device_t *dev,
const uint8_t *wdata, int wsize,
uint8_t *rbuf, int rsize, int ignore)
{
if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) {
return SPI_DEV_STATUS_EINVAL;
}
if(!spi_arch_has_lock(dev)) {
return SPI_DEV_STATUS_BUS_LOCKED;
}
if(wdata == NULL && wsize > 0) {
return SPI_DEV_STATUS_EINVAL;
}
if(rbuf == NULL && rsize > 0) {
return SPI_DEV_STATUS_EINVAL;
}
return spi_arch_transfer(dev, wdata, wsize, rbuf, rsize, ignore);
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_read_register(spi_device_t *dev, uint8_t reg, uint8_t *data, int size)
{
spi_status_t status;
if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) {
return SPI_DEV_STATUS_EINVAL;
}
/* write the register first (will read a status) */
status = spi_write_byte(dev, reg);
if(status != SPI_DEV_STATUS_OK) {
return status;
}
/* then read the value (will read the value) */
status = spi_read(dev, data, size);
if(status != SPI_DEV_STATUS_OK) {
return status;
}
return status;
}
/*---------------------------------------------------------------------------*/
spi_status_t
spi_strobe(spi_device_t *dev, uint8_t strobe, uint8_t *result)
{
if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) {
return SPI_DEV_STATUS_EINVAL;
}
if(!spi_arch_has_lock(dev)) {
return SPI_DEV_STATUS_BUS_LOCKED;
}
return spi_arch_transfer(dev, &strobe, 1, result, 1, 0);
}
/*---------------------------------------------------------------------------*/
/**
* @}
*/

397
os/dev/spi.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2010, Swedish Institute of Computer Science.
* Copyright (c) 2016-2017, Yanzi Networks.
* Copyright (c) 2017, University of Bristol - http://www.bristol.ac.uk/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -10,83 +11,339 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup dev
* @{
*
* \defgroup spi-hal SPI Hardware Abstraction Layer
*
* The SPI HAL provides a set of common functions that can be used in a
* platform-independent fashion.
*
*
* @{
*
* \file
* Basic SPI macros
* \author
* Joakim Eriksson <joakime@sics.se>
* Niclas Finne <nfi@sics.se>
* Header file for the SPI HAL
*/
/*---------------------------------------------------------------------------*/
#ifndef SPI_H_
#define SPI_H_
/*---------------------------------------------------------------------------*/
#include "contiki.h"
#include "gpio-hal.h"
/* Define macros to use for checking SPI transmission status depending
on if it is possible to wait for TX buffer ready. This is possible
on for example MSP430 but not on AVR. */
#ifdef SPI_WAITFORTxREADY
#define SPI_WAITFORTx_BEFORE() SPI_WAITFORTxREADY()
#define SPI_WAITFORTx_AFTER()
#define SPI_WAITFORTx_ENDED() SPI_WAITFOREOTx()
#else /* SPI_WAITFORTxREADY */
#define SPI_WAITFORTx_BEFORE()
#define SPI_WAITFORTx_AFTER() SPI_WAITFOREOTx()
#define SPI_WAITFORTx_ENDED()
#endif /* SPI_WAITFORTxREADY */
extern unsigned char spi_busy;
void spi_init(void);
/* Write one character to SPI */
#define SPI_WRITE(data) \
do { \
SPI_WAITFORTx_BEFORE(); \
SPI_TXBUF = data; \
SPI_WAITFOREOTx(); \
} while(0)
/* Write one character to SPI - will not wait for end
useful for multiple writes with wait after final */
#define SPI_WRITE_FAST(data) \
do { \
SPI_WAITFORTx_BEFORE(); \
SPI_TXBUF = data; \
SPI_WAITFORTx_AFTER(); \
} while(0)
/* Read one character from SPI */
#define SPI_READ(data) \
do { \
SPI_TXBUF = 0; \
SPI_WAITFOREORx(); \
data = SPI_RXBUF; \
} while(0)
/* Flush the SPI read register */
#ifndef SPI_FLUSH
#define SPI_FLUSH() \
do { \
SPI_RXBUF; \
} while(0)
#include <stdint.h>
#include <stdbool.h>
/*---------------------------------------------------------------------------*/
/* Include Arch-Specific conf */
#ifdef SPI_HAL_CONF_ARCH_HDR_PATH
#include SPI_HAL_CONF_ARCH_HDR_PATH
#endif /* SPI_HAL_CONF_ARCH_HDR_PATH */
/*---------------------------------------------------------------------------*/
#ifdef SPI_CONF_CONTROLLER_COUNT
/**
* \brief Number of SPI module instances on a chip
*/
#define SPI_CONTROLLER_COUNT SPI_CONF_CONTROLLER_COUNT
#else
#define SPI_CONTROLLER_COUNT 0
#endif
/*---------------------------------------------------------------------------*/
/* Convenience macros to enumerate SPI module instances on a chip */
#define SPI_CONTROLLER_SPI0 0
#define SPI_CONTROLLER_SPI1 1
/*---------------------------------------------------------------------------*/
/**
* \brief SPI return codes
*
* @{
*/
typedef enum {
SPI_DEV_STATUS_OK, /* Everything OK */
SPI_DEV_STATUS_EINVAL, /* Erroneous input value */
SPI_DEV_STATUS_BUS_LOCKED, /* SPI bus is already locked */
SPI_DEV_STATUS_BUS_NOT_OWNED, /* SPI bus is locked by someone else */
SPI_DEV_STATUS_CLOSED /* SPI bus has not opened properly */
} spi_status_t;
/** @} */
/*---------------------------------------------------------------------------*/
/**
* \brief SPI Device Configuration
*
* This is a structure to an architecture-independent SPI configuration.
*
* @{
*/
typedef struct spi_device {
gpio_hal_pin_t pin_spi_sck; /* SPI SCK pin */
gpio_hal_pin_t pin_spi_miso; /* SPI MISO pin */
gpio_hal_pin_t pin_spi_mosi; /* SPI MOSI pin */
gpio_hal_pin_t pin_spi_cs; /* SPI Chip Select pin */
uint32_t spi_bit_rate; /* SPI bit rate */
uint8_t spi_pha; /* SPI mode phase */
uint8_t spi_pol; /* SPI mode polarity */
uint8_t spi_controller; /* ID of SPI controller to use */
} spi_device_t;
/** @} */
/*---------------------------------------------------------------------------*/
/* These are architecture-independent functions to be used by SPI devices. */
/*---------------------------------------------------------------------------*/
/**
* \brief Locks and then opens an SPI controller
* \param dev An SPI device configuration which defines the controller
* to be locked and the opening configuration.
* \return SPI return code
*/
spi_status_t spi_acquire(spi_device_t *dev);
/**
* \brief Closes and then unlocks an SPI controller
* \param dev An SPI device configuration which defines the controller
* to be closed and unlocked.
* \return SPI return code
*
* Releasing an SPI controller should put it in low-power mode.
* This should work only if the device has already locked the SPI
* controller.
*/
spi_status_t spi_release(spi_device_t *dev);
/**
* \brief Selects the SPI peripheral
* \param dev An SPI device configuration which defines the CS pin.
* \return SPI return code
*
* Clears the CS pin. This should work only if the device has
* already locked the SPI controller.
*/
spi_status_t spi_select(spi_device_t *dev);
/**
* \brief Deselects the SPI peripheral
* \param dev An SPI device configuration which defines the CS pin.
* \return SPI return code
*
* Sets the CS pin. Lock is not required.
*/
spi_status_t spi_deselect(spi_device_t *dev);
/**
* \brief Checks if a device has locked an SPI controller
* \param dev An SPI device configuration which defines the controller.
* \return true if the device has the lock, false otherwise.
*/
bool spi_has_bus(spi_device_t *dev);
/**
* \brief Writes a single byte to an SPI device
* \param dev An SPI device configuration.
* \param data A byte of data
* \return SPI return code
*
* It should work only if the device has already locked the SPI controller.
*/
spi_status_t spi_write_byte(spi_device_t *dev, uint8_t data);
/**
* \brief Reads a single byte from an SPI device
* \param dev An SPI device configuration.
* \param data A pointer to a byte of data
* \return SPI return code
*
* It should work only if the device has already locked the SPI controller.
*/
spi_status_t spi_read_byte(spi_device_t *dev, uint8_t *data);
/**
* \brief Writes a buffer to an SPI device
* \param dev An SPI device configuration.
* \param data A pointer to the data
* \param size Size of the data to write
* \return SPI return code
*
* It should work only if the device has already locked the SPI controller.
*/
spi_status_t spi_write(spi_device_t *dev,
const uint8_t *data, int size);
/**
* \brief Reads a buffer from an SPI device
* \param dev An SPI device configuration.
* \param data A pointer to the data
* \param size Size of the data to read
* \return SPI return code
*
* It should work only if the device has already locked the SPI controller.
*/
spi_status_t spi_read(spi_device_t *dev, uint8_t *data, int size);
/**
* \brief Reads and ignores data from an SPI device
* \param dev An SPI device configuration.
* \param size Size of the data to read and ignore
* \return SPI return code
*
* Reads size bytes from the SPI and throws them away.
* It should work only if the device has already locked the SPI controller.
*/
spi_status_t spi_read_skip(spi_device_t *dev, int size);
/**
* \brief Performs a generic SPI transfer
* \param dev An SPI device configuration.
* \param data A pointer to the data to be written. Set it to NULL to
* skip writing.
* \param wsize Size of data to write.
* \param buf A pointer to buffer to copy the data read. Set to NULL
* to skip reading.
* \param rsize Size of data to read.
* \param ignore Size of data to read and ignore.
* \return SPI return code
*
* It should work only if the device has already locked the SPI controller.
* A total of rlen+ignore_len bytes will be read. The first rlen bytes will
* be copied to buf. The remaining ignore_len bytes won't be copied to the
* buffer. The maximum of wlen and rlen+ignore_len of bytes will be transfered.
*/
spi_status_t spi_transfer(spi_device_t *dev,
const uint8_t *data, int wsize,
uint8_t *buf, int rsize, int ignore);
/**
* \brief Reads and Writes one byte from/to an SPI device
* \param dev An SPI device configuration.
* \param strobe Byte to write
* \param status Pointer to byte to read
* \return SPI return code
*
* It should work only if the device has already locked the SPI controller.
*/
spi_status_t spi_strobe(spi_device_t *dev, uint8_t strobe,
uint8_t *status);
/**
* \brief Reads a buffer of bytes from a register of an SPI device
* \param dev An SPI device configuration.
* \param reg Register
* \param data A pointer to the data
* \param size Size of the data to read
* \return SPI return code
*
* It should work only if the device has already locked the SPI controller.
*/
spi_status_t spi_read_register(spi_device_t *dev, uint8_t reg,
uint8_t *data, int size);
/*---------------------------------------------------------------------------*/
/* These are architecture-specific functions to be implemented by each CPU. */
/*---------------------------------------------------------------------------*/
/**
* \brief Checks if a device has locked an SPI controller
* \param dev An SPI device configuration which defines the controller
* to be checked if it is locked and the respective device.
* \return 1 if the device has the lock, 0 otherwise.
*
*/
bool spi_arch_has_lock(spi_device_t *dev);
/**
* \brief Checks if an SPI controller is locked by any device
* \param dev An SPI device configuration which defines the controller
* to be checked.
* \return 1 if the controller is locked, 0 otherwise.
*
*/
bool spi_arch_is_bus_locked(spi_device_t *dev);
/**
* \brief Locks and opens an SPI controller to the configuration specified.
* \param dev An SPI device configuration.
* \return SPI return code
*
* This should work only if the device has already locked the SPI
* controller.
*
*/
spi_status_t spi_arch_lock_and_open(spi_device_t *dev);
/**
* \brief Closes and unlocks an SPI controller
* \param dev An SPI device configuration that specifies the controller.
* \return SPI return code
*
* This should turn off the SPI controller to put it in low power mode
* and unlock it.
* It should work only if the device has already locked the SPI
* controller.
*
*/
spi_status_t spi_arch_close_and_unlock(spi_device_t *dev);
/**
* \brief Performs an SPI transfer
* \param dev An SPI device configuration that specifies the controller.
* \param data A pointer to the data to be written. Set it to NULL to
* skip writing.
* \param wlen Length of data to write.
* \param buf A pointer to buffer to copy the data read. Set to NULL
* to skip reading.
* \param rlen Length of data to read.
* \param ignore_len Length of data to read and ignore.
* \return SPI return code
*
* It should work only if the device has already locked the SPI controller.
* A total of rlen+ignore_len bytes will be read. The first rlen bytes will
* be copied to buf. The remaining ignore_len bytes won't be copied to the
* buffer. The maximum of wlen and rlen+ignore_len of bytes will be transfered.
*/
spi_status_t spi_arch_transfer(spi_device_t *dev,
const uint8_t *data, int wlen,
uint8_t *buf, int rlen,
int ignore_len);
/**
* \brief Selects an SPI device
* \param dev An SPI device configuration that specifies the CS pin.
* \return SPI return code
*
* Clears the CS pin. It should work only if the device has already
* locked the SPI controller.
*/
spi_status_t spi_arch_select(spi_device_t *dev);
/**
* \brief Deselects an SPI device
* \param dev An SPI device configuration that specifies the CS pin.
* \return SPI return code
*
* Set the CS pin. Locking the SPI controller is not needed.
*/
spi_status_t spi_arch_deselect(spi_device_t *dev);
#endif /* SPI_H_ */
/*---------------------------------------------------------------------------*/
/**
* @}
* @}
*/