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enable interrupt later.
This commit is contained in:
nvt-se 2007-09-14 19:20:24 +00:00
parent ca733ddfce
commit 290f41db06
1 changed files with 6 additions and 6 deletions
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10
platform/msb430/dev/dma.c
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@ -105,16 +105,16 @@ dma_transfer(unsigned char *buf, unsigned len)
* The source address is incremented for each byte, while the * The source address is incremented for each byte, while the
* destination address remains constant. * destination address remains constant.
* *
* Important to use DMALEVEL when using USART TX * In order to avoid missing the first rising edge of the trigger
* interrupts so first edge * signal, it is important to use the level-sensitive trigger when
* doesn't get lost (hangs every 50. - 100. time)! * using USART transfer interrupts.
*/ */
DMA0CTL = DMADT_0 | DMADSTINCR_0 | DMASRCINCR_3 | DMASBDB | DMALEVEL | DMAIE; DMA0CTL = DMADT_0 | DMADSTINCR_0 | DMASRCINCR_3 | DMASBDB | DMALEVEL;
DMA0SA = (unsigned) buf; DMA0SA = (unsigned) buf;
DMA0DA = (unsigned) &TXBUF0; DMA0DA = (unsigned) &TXBUF0;
DMA0SZ = len; DMA0SZ = len;
DMA0CTL |= DMAEN; // enable DMA DMA0CTL |= DMAEN | DMAIE; // enable DMA and interrupts
U0CTL &= ~SWRST; // enable UART state machine, starts transfer U0CTL &= ~SWRST; // enable UART state machine, starts transfer
} }