diff --git a/cpu/mc1322x/board/freescale-ncb.h b/cpu/mc1322x/board/freescale-ncb.h index 5de8c8ef1..3b038ee59 100644 --- a/cpu/mc1322x/board/freescale-ncb.h +++ b/cpu/mc1322x/board/freescale-ncb.h @@ -46,7 +46,7 @@ /* XTAL TUNE parameters */ /* see http://devl.org/pipermail/mc1322x/2009-December/000162.html */ -/* for details about how to make this measurment */ +/* for details about how to make this measurement */ /* Coarse tune: add 4pf */ #define CTUNE_4PF 1 diff --git a/cpu/mc1322x/board/m12.h b/cpu/mc1322x/board/m12.h new file mode 100644 index 000000000..fdd6b2d99 --- /dev/null +++ b/cpu/mc1322x/board/m12.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2010, Mariano Alvira and other contributors + * to the MC1322x project (http://mc1322x.devl.org) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of libmc1322x: see http://mc1322x.devl.org + * for details. + * + * + */ + +#ifndef BOARD_M12_H +#define BOARD_M12_H + +/* XTAL TUNE parameters */ +/* see http://devl.org/pipermail/mc1322x/2009-December/000162.html */ +/* for details about how to make this measurement */ + +/* Econotag also needs an addtional 12pf on board */ +/* Coarse tune: add 4pf */ +#define CTUNE_4PF 1 +/* Coarse tune: add 0-15 pf (CTUNE is 4 bits) */ +#define CTUNE 3 +/* Fine tune: add FTUNE * 156fF (FTUNE is 5bits) */ +#define FTUNE 3 + +#define vreg_init buck_init +#define board_init m12_init +#include + +#endif diff --git a/cpu/mc1322x/board/quahogcon.h b/cpu/mc1322x/board/quahogcon.h index 182e22c06..647b17644 100644 --- a/cpu/mc1322x/board/quahogcon.h +++ b/cpu/mc1322x/board/quahogcon.h @@ -65,7 +65,7 @@ /* XTAL TUNE parameters */ /* see http://devl.org/pipermail/mc1322x/2009-December/000162.html */ -/* for details about how to make this measurment */ +/* for details about how to make this measurement */ /* Econotag also needs an addtional 12pf on board */ /* Coarse tune: add 4pf */ diff --git a/cpu/mc1322x/board/redbee-dev.h b/cpu/mc1322x/board/redbee-dev.h index d961ac081..62dd3c016 100644 --- a/cpu/mc1322x/board/redbee-dev.h +++ b/cpu/mc1322x/board/redbee-dev.h @@ -46,7 +46,7 @@ /* XTAL TUNE parameters */ /* see http://devl.org/pipermail/mc1322x/2009-December/000162.html */ -/* for details about how to make this measurment */ +/* for details about how to make this measurement */ /* Coarse tune: add 4pf */ #define CTUNE_4PF 1 diff --git a/cpu/mc1322x/board/redbee-econotag.h b/cpu/mc1322x/board/redbee-econotag.h index d710578b9..bca65cafb 100644 --- a/cpu/mc1322x/board/redbee-econotag.h +++ b/cpu/mc1322x/board/redbee-econotag.h @@ -48,7 +48,7 @@ /* XTAL TUNE parameters */ /* see http://devl.org/pipermail/mc1322x/2009-December/000162.html */ -/* for details about how to make this measurment */ +/* for details about how to make this measurement */ /* Econotag also needs an addtional 12pf on board */ /* Coarse tune: add 4pf */ diff --git a/cpu/mc1322x/board/redbee-r1.h b/cpu/mc1322x/board/redbee-r1.h index 0bc6ef0c9..66f95a118 100644 --- a/cpu/mc1322x/board/redbee-r1.h +++ b/cpu/mc1322x/board/redbee-r1.h @@ -46,7 +46,7 @@ /* XTAL TUNE parameters */ /* see http://devl.org/pipermail/mc1322x/2009-December/000162.html */ -/* for details about how to make this measurment */ +/* for details about how to make this measurement */ /* Coarse tune: add 4pf */ #define CTUNE_4PF 1 diff --git a/cpu/mc1322x/board/redbee-usb.h b/cpu/mc1322x/board/redbee-usb.h index 88ee4e8cf..d3deabc5d 100644 --- a/cpu/mc1322x/board/redbee-usb.h +++ b/cpu/mc1322x/board/redbee-usb.h @@ -46,7 +46,7 @@ /* XTAL TUNE parameters */ /* see http://devl.org/pipermail/mc1322x/2009-December/000162.html */ -/* for details about how to make this measurment */ +/* for details about how to make this measurement */ /* Coarse tune: add 4pf */ #define CTUNE_4PF 1 diff --git a/cpu/mc1322x/board/std_conf.h b/cpu/mc1322x/board/std_conf.h index 4c1c9b82c..f263d0fe7 100644 --- a/cpu/mc1322x/board/std_conf.h +++ b/cpu/mc1322x/board/std_conf.h @@ -42,6 +42,28 @@ #define vreg_init() default_vreg_init() #endif + +#ifndef GPIO_LED_RED +#define GPIO_LED_RED GPIO_40 +#endif +#ifndef GPIO_LED_GREEN +#define GPIO_LED_GREEN GPIO_41 +#endif +#ifndef GPIO_LED_BLUE +#define GPIO_LED_BLUE GPIO_42 +#endif + +#ifndef LED_RED +#define LED_RED 40 +#endif +#ifndef LED_GREEN +#define LED_GREEN 41 +#endif +#ifndef LED_BLUE +#define LED_BLUE 42 +#endif + + /* XTAL TUNE parameters */ /* recommended defaults from the datasheet */ diff --git a/cpu/mc1322x/doc/buck b/cpu/mc1322x/doc/buck new file mode 100644 index 000000000..cebe4cbdb --- /dev/null +++ b/cpu/mc1322x/doc/buck @@ -0,0 +1,18 @@ +no buck +------- +vsupply, +3.6, rftest-rx 46mA +3.27, rftest-rx 42mA +3.03, rftest-rx, 39.5mA +2.56, rftest-rx 35mA +2.2, rftest-rx 32mA + +buck +----- +3.58V, 39mA +3.3, 37mA +vsupply 3.03, rftest, 35.3mA +2.47, 32.9mA +2.2V, 31.2mA + +might have a hard time starting up everything in the <2.7V range diff --git a/cpu/mc1322x/doc/pow-rssi-lqi.gnumeric b/cpu/mc1322x/doc/pow-rssi-lqi.gnumeric new file mode 100644 index 000000000..6d7a0200e Binary files /dev/null and b/cpu/mc1322x/doc/pow-rssi-lqi.gnumeric differ diff --git a/cpu/mc1322x/lib/adc.c b/cpu/mc1322x/lib/adc.c index 841855107..efde94019 100644 --- a/cpu/mc1322x/lib/adc.c +++ b/cpu/mc1322x/lib/adc.c @@ -34,9 +34,7 @@ */ #include -#include "crm.h" -#include "adc.h" -#include "gpio-util.h" +#include "mc1322x.h" //#define ADC_CHANS_ENABLED 0x3F // channels 0-5 enabled //#define ADC_CHANS_ENABLED 0x7E // channels 1-6 enabled @@ -73,9 +71,26 @@ void adc_service(void) { } } -void adc_init(void) { - uint8_t n; +#define _adc_setup_chan(x) do { \ + if ( channel == x ) { \ + ADC->SEQ_1bits.CH##x = 1; \ + GPIO->FUNC_SEL.ADC##x = 1; \ + GPIO->PAD_DIR.ADC##x = 0; \ + GPIO->PAD_PU_EN.ADC##x = 0; \ +}} while (0) +void adc_setup_chan(uint8_t channel) { + _adc_setup_chan(0); + _adc_setup_chan(1); + _adc_setup_chan(2); + _adc_setup_chan(3); + _adc_setup_chan(4); + _adc_setup_chan(5); + _adc_setup_chan(6); + _adc_setup_chan(7); +} + +void adc_init(void) { ADC->CLOCK_DIVIDER = 80; // 300 KHz ADC->PRESCALE = ADC_PRESCALE_VALUE - 1; // divide by 24 for 1MHz. @@ -114,13 +129,13 @@ void adc_init(void) { ADC->SR_1_LOW = (REF_OSC / ADC_PRESCALE_VALUE) / (115200 / 8) + 1; #endif - ADC->SEQ_1 = 0 + ADC->SEQ_1 = 0; #if ADC_USE_TIMER - | (1 << 15) // sequence based on Timer 1. + ADC->SEQ_1bits.SEQ_MODE = 1; // sequence based on Timer 1 #else - | (0 << 15) // sequence based on convert time. + ADC->SEQ_1bits.SEQ_MODE = 0; // sequence based on convert time. #endif - | ADC_CHANS_ENABLED; + ADC->SEQ_1bits.BATT = 1; ADC->CONTROL = 0xF001 //#if ADC_USE_TIMER @@ -129,10 +144,4 @@ void adc_init(void) { ; ADC->OVERRIDE = (1 << 8); - for (n=0; n<=8; n++) { - if ((ADC_CHANS_ENABLED >> n) & 1) { - gpio_select_function(30 + n, 1); // Function 1 = ADC - gpio_set_pad_dir(30 + n, PAD_DIR_INPUT); - } - } } diff --git a/cpu/mc1322x/lib/include/adc.h b/cpu/mc1322x/lib/include/adc.h index 580e3545e..7f8df79d4 100644 --- a/cpu/mc1322x/lib/include/adc.h +++ b/cpu/mc1322x/lib/include/adc.h @@ -39,6 +39,21 @@ #include #include "utils.h" +/* the Vbatt measurment reads about 200mV low --- trim by ADC_VBATT_TRIM */ +/* correction tracks well --- within 50mV over 2.1V to 3.6V */ +/* offset from correct for tags running from 3.29 vreg */ +/* trim = 146 */ +/* tag 1: -90mV */ +/* tag 2: -30mV */ +/* tag 3: -30mV */ +/* tag 4: -40mV */ +/* tag 5: +10mV */ +/* tag 6: -40mV */ +/* new trim 183 */ + +/* without per unit calibration, vbatt is probably +/- 75mV */ +#define ADC_VBATT_TRIM 183 + /* ADC registers are all 16-bit wide with 16-bit access only */ #define ADC_BASE (0x8000D000) @@ -98,7 +113,7 @@ struct ADC_struct { uint16_t TIMER1_ON:1; uint16_t TIMER2_ON:1; uint16_t SOFT_RESET:1; - uint16_t AD1_FREFHL_EN:1; + uint16_t AD1_VREFHL_EN:1; uint16_t AD2_VREFHL_EN:1; uint16_t :6; uint16_t COMPARE_IRQ_MASK:1; @@ -153,8 +168,14 @@ static volatile struct ADC_struct * const ADC = (void *) (ADC_BASE); #define adc_enable() (ADC->CONTROLbits.ON = 1) #define adc_disable() (ADC->CONTROLbits.ON = 0) #define adc_select_channels(chans) (ADC->SEQ_1 = (ADC->SEQ_1 & 0xFE00) | chans) +void adc_setup_chan(uint8_t channel); extern uint16_t adc_reading[NUM_ADC_CHAN]; +/* use the internal reference to return adc_readings in mV */ +#define adc_voltage(x) (adc_reading[x] * 1200/adc_reading[8]) +/* return vbatt voltage in mV */ +#define adc_vbatt 4095 * 1200/adc_reading[8] + ADC_VBATT_TRIM + void ADC_flush(void); uint16_t ADC_READ(void); void read_scanners(void); diff --git a/cpu/mc1322x/lib/include/gpio.h b/cpu/mc1322x/lib/include/gpio.h index 58b868946..b0f509cf2 100644 --- a/cpu/mc1322x/lib/include/gpio.h +++ b/cpu/mc1322x/lib/include/gpio.h @@ -51,6 +51,75 @@ gpio_reset(GPIO_08); */ +// GPIO to Function Alias macros: + +#define ADC0 GPIO_30 +#define ADC1 GPIO_31 +#define ADC2 GPIO_32 +#define ADC3 GPIO_33 +#define ADC4 GPIO_34 +#define ADC5 GPIO_35 +#define ADC6 GPIO_36 +#define ADC7 GPIO_37 +#define TDO GPIO_49 +#define TDI GPIO_48 +#define TCK GPIO_47 +#define TMS GPIO_46 +#define U2RTS GPIO_21 +#define U2CTS GPIO_20 +#define U2RX GPIO_19 +#define U2TX GPIO_18 +#define U1RTS GPIO_17 +#define U1CTS GPIO_16 +#define U1RX GPIO_15 +#define U1TX GPIO_14 +#define SDA GPIO_13 +#define SCL GPIO_12 +#define TMR3 GPIO_11 +#define TMR2 GPIO_10 +#define TMR1 GPIO_09 +#define TMR0 GPIO_08 +#define SCK GPIO_07 +#define MOSI GPIO_06 +#define MISO GPIO_05 +#define SS GPIO_04 +#define BTCK GPIO_03 +#define FSYN GPIO_02 +#define SSIRX GPIO_01 +#define SSITX GPIO_00 +#define KBI7 GPIO_29 +#define KBI6 GPIO_28 +#define KBI5 GPIO_27 +#define KBI4 GPIO_26 +#define KBI3 GPIO_25 +#define KBI2 GPIO_24 +#define KBI1 GPIO_23 +#define KBI0 GPIO_22 +#define TXON GPIO_44 +#define RXON GPIO_45 +#define ANT1 GPIO_42 +#define ANT2 GPIO_43 +#define VREF2H GPIO_38 +#define VREF2L GPIO_39 +#define VREF1H GPIO_40 +#define VREF1L GPIO_41 +#define MDO0 GPIO_51 +#define MDO1 GPIO_52 +#define MDO2 GPIO_53 +#define MDO3 GPIO_54 +#define MDO4 GPIO_55 +#define MDO5 GPIO_56 +#define MDO6 GPIO_57 +#define MDO7 GPIO_58 +#define MSEO0 GPIO_59 +#define MSEO1 GPIO_60 +#define RDY GPIO_61 +#define EVTO GPIO_62 +#define MCKO GPIO_50 +#define EVTI GPIO_63 + + + #define _V(x,n,i) uint32_t x##_##i : n; #define _REP(x,n) \ _V(x,n,00) _V(x,n,01) _V(x,n,02) _V(x,n,03) _V(x,n,04) _V(x,n,05) _V(x,n,06) _V(x,n,07) \ diff --git a/cpu/mc1322x/lib/include/mc1322x.h b/cpu/mc1322x/lib/include/mc1322x.h index 1f82701aa..d50cba2e3 100644 --- a/cpu/mc1322x/lib/include/mc1322x.h +++ b/cpu/mc1322x/lib/include/mc1322x.h @@ -50,5 +50,6 @@ #include "i2c.h" #include "rtc.h" #include "adc.h" +#include "pwm.h" #endif diff --git a/cpu/mc1322x/lib/include/uart.h b/cpu/mc1322x/lib/include/uart.h index ed714880a..353c24ca7 100644 --- a/cpu/mc1322x/lib/include/uart.h +++ b/cpu/mc1322x/lib/include/uart.h @@ -46,71 +46,71 @@ struct UART_struct { union { uint32_t CON; struct UART_CON { - uint32_t :16; - uint32_t TST:1; - uint32_t MRXR:1; - uint32_t MTXR:1; - uint32_t FCE:1; - uint32_t FCP:1; - uint32_t XTIM:1; - uint32_t :2; - uint32_t TXOENB:1; - uint32_t CONTX:1; - uint32_t SB:1; - uint32_t ST2:1; - uint32_t EP:1; - uint32_t PEN:1; - uint32_t RXE:1; uint32_t TXE:1; + uint32_t RXE:1; + uint32_t PEN:1; + uint32_t EP:1; + uint32_t ST2:1; + uint32_t SB:1; + uint32_t CONTX:1; + uint32_t TXOENB:1; + uint32_t :2; + uint32_t XTIM:1; + uint32_t FCP:1; + uint32_t FCE:1; + uint32_t MTXR:1; + uint32_t MRXR:1; + uint32_t TST:1; + uint32_t :16; } CONbits; }; union { uint32_t STAT; struct UART_STAT { - uint32_t :24; - uint32_t TXRDY:1; - uint32_t RXRDY:1; - uint32_t RUE:1; - uint32_t ROE:1; - uint32_t TOE:1; - uint32_t FE:1; - uint32_t PE:1; uint32_t SE:1; + uint32_t PE:1; + uint32_t FE:1; + uint32_t TOE:1; + uint32_t ROE:1; + uint32_t RUE:1; + uint32_t RXRDY:1; + uint32_t TXRDY:1; + uint32_t :24; } USTATbits; }; union { uint32_t DATA; struct UART_DATA { - uint32_t :24; uint32_t DATA:8; + uint32_t :24; } DATAbits; }; union { uint32_t RXCON; struct UART_URXCON { - uint32_t :26; uint32_t LVL:6; + uint32_t :26; } RXCONbits; }; union { uint32_t TXCON; struct UART_TXCON { - uint32_t :26; uint32_t LVL:6; + uint32_t :26; } TXCONbits; }; union { uint32_t CTS; struct UART_CTS { - uint32_t :27; uint32_t LVL:5; + uint32_t :27; } CTSbits; }; union { uint32_t BR; struct UART_BR { - uint32_t INC:16; uint32_t MOD:16; + uint32_t INC:16; } BRbits; }; }; @@ -152,6 +152,11 @@ static volatile struct UART_struct * const UART2 = (void *) (UART2_BASE); #endif /* REG_NO_COMPAT */ +void uart_init(volatile struct UART_struct * uart, uint32_t baud); +void uart_setbaud(volatile struct UART_struct * uart, uint32_t baud); +void uart_flowctl(volatile struct UART_struct * uart, uint8_t on); + + /* The mc1322x has a 32 byte hardware FIFO for transmitted characters. * Currently it is always filled from a larger RAM buffer. It would be * possible to eliminate that overhead by filling directly from a chain @@ -192,3 +197,4 @@ extern volatile uint32_t u2_rx_head, u2_rx_tail; uint8_t uart2_getc(void); #endif + diff --git a/cpu/mc1322x/lib/maca.c b/cpu/mc1322x/lib/maca.c index 308b63c7c..475f75700 100644 --- a/cpu/mc1322x/lib/maca.c +++ b/cpu/mc1322x/lib/maca.c @@ -932,7 +932,9 @@ void radio_init(void) { volatile uint32_t i; /* sequence 1 */ for(i=0; i>17) & 1) !=1) { continue; } /* wait for the bypass to take */ - *(volatile uint32_t *)(0x80003048) = 0x00000fa4; /* start the regulators */ - for(i=0; i<0x161a8; i++) { continue; } /* wait for the bypass to take */ - init_from_flash(0x1F000); PRINTF("ram_values:\n\r"); @@ -1203,7 +1201,11 @@ uint32_t exec_init_entry(volatile uint32_t *entries, uint8_t *valbuf) PRINTF("init_entry: address value pair - *0x%08x = 0x%08x\n\r", (unsigned int)entries[0], (unsigned int)entries[1]); - reg(entries[0]) = entries[1]; + if ((unsigned int)entries[0] != (unsigned int)CRM_VREG_CNTL) { + reg(entries[0]) = entries[1]; + } else { + PRINTF("skipping VREG_CNTL\n\r"); + } return 2; } } diff --git a/cpu/mc1322x/lib/uart.c b/cpu/mc1322x/lib/uart.c new file mode 100644 index 000000000..d56735901 --- /dev/null +++ b/cpu/mc1322x/lib/uart.c @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2010, Mariano Alvira and other contributors + * to the MC1322x project (http://mc1322x.devl.org) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of libmc1322x: see http://mc1322x.devl.org + * for details. + * + * + */ + +#include +#include + +#define MOD 9999 +#define CLK 24000000 +#define DIV 16 /* uart->CON.XTIM = 0 is 16x oversample (datasheet is incorrect) */ + +void uart_setbaud(volatile struct UART_struct * uart, uint32_t baud) { + uint64_t inc; + + /* baud rate eqn from reference manual */ + /* multiply by an additional 10 to do a fixed point round later */ + inc = ((uint64_t) baud * DIV * MOD * 10 / CLK ) - 10 ; + /* add 5 and divide by 10 to get a rounding */ + inc = (inc + 5) / 10; + + /* UART must be disabled to set the baudrate */ + uart->CONbits.TXE = 0; + uart->CONbits.RXE = 0; + + uart->BR = ( (uint16_t)inc << 16 ) | MOD; + + uart->CONbits.XTIM = 0; + uart->CONbits.TXE = 1; + uart->CONbits.RXE = 1; +} + +void uart_flowctl(volatile struct UART_struct * uart, uint8_t on) { + if (on) { + if( uart == UART1 ) { + /* CTS and RTS directions */ + GPIO->PAD_DIR_SET.U1CTS = 1; + GPIO->PAD_DIR_RESET.U1RTS = 1; + /* function select to uart */ + GPIO->FUNC_SEL.U1CTS = 1; + GPIO->FUNC_SEL.U1RTS = 1; + } else { + /* UART 2 */ + /* CTS and RTS directions */ + GPIO->PAD_DIR_SET.U2CTS = 1; + GPIO->PAD_DIR_RESET.U2RTS = 1; + /* function select to uart */ + GPIO->FUNC_SEL.U2CTS = 1; + GPIO->FUNC_SEL.U2RTS = 1; + } + /* enable flow control */ + uart->CONbits.FCE = 1; + } else { + /* off */ + /* disable flow control */ + uart->CONbits.FCE = 0; + if( uart == UART1 ) { + /* CTS and RTS to inputs */ + GPIO->PAD_DIR_RESET.U1CTS = 1; + GPIO->PAD_DIR_RESET.U1RTS = 1; + /* function select to gpio */ + GPIO->FUNC_SEL.U1CTS = 3; + GPIO->FUNC_SEL.U1RTS = 3; + } else { + /* UART 2 */ + /* CTS and RTS to inputs */ + GPIO->PAD_DIR_RESET.U2CTS = 1; + GPIO->PAD_DIR_RESET.U2RTS = 1; + /* function select to gpio */ + GPIO->FUNC_SEL.U2CTS = 3; + GPIO->FUNC_SEL.U2RTS = 3; + } + } +} + +void uart_init(volatile struct UART_struct * uart, uint32_t baud) { + /* enable the uart so we can set the gpio mode */ + /* see Section 11.5.1.2 Alternate Modes */ + /* you must enable the peripheral first BEFORE setting the function in GPIO_FUNC_SEL */ + /* From the datasheet: "The peripheral function will control operation of the pad IF */ + /* THE PERIPHERAL IS ENABLED. */ + uart->CONbits = (struct UART_CON) { + .TXE = 1, + .RXE = 1, + }; + + /* interrupt when there are this number or more bytes free in the TX buffer*/ + uart->TXCON = 16; + + if( uart == UART1 ) { + /* TX and RX directions */ + GPIO->PAD_DIR_SET.U1TX = 1; + GPIO->PAD_DIR_RESET.U1RX = 1; + + /* set func sel to UART */ + GPIO->FUNC_SEL.U1TX = 1; + GPIO->FUNC_SEL.U1RX = 1; + +#if UART1_RX_BUFFERSIZE > 32 + *UART1_UCON = (1 << 0) | (1 << 1) ; /* enable receive, transmit, and both interrupts */ + *UART1_URXCON = 30; /* interrupt when fifo is nearly full */ + u1_rx_head = 0; u1_rx_tail = 0; +#elif UART1_RX_BUFFERSIZE < 32 /* enable receive, transmit, flow control, disable rx interrupt */ + *UART1_UCON = (1 << 0) | (1 << 1) | (1 << 12) | (1 << 14); + *UART1_UCTS = UART1_RX_BUFFERSIZE; /* drop cts when tx buffer at trigger level */ + *GPIO_FUNC_SEL1 = ( (0x01 << (0*2)) | (0x01 << (1*2)) ); /* set GPIO17-16 to UART1 CTS and RTS */ +#else + *UART1_UCON = (1 << 0) | (1 << 1) | (1 << 14); /* enable receive, transmit, disable rx interrupt */ +#endif + + u1_tx_head = 0; u1_tx_tail = 0; + + /* tx and rx interrupts are enabled in the UART by default */ + /* see status register bits 13 and 14 */ + /* enable UART1 interrupts in the interrupt controller */ + enable_irq(UART1); + + } else { + /* UART2 */ + /* TX and RX directions */ + GPIO->PAD_DIR_SET.U2TX = 1; + GPIO->PAD_DIR_RESET.U1RX = 1; + + /* set func sel to UART */ + GPIO->FUNC_SEL.U2TX = 1; + GPIO->FUNC_SEL.U2RX = 1; + +#if UART2_RX_BUFFERSIZE > 32 + *UART2_UCON = (1 << 0) | (1 << 1) ; /* enable receive, transmit, and both interrupts */ + *UART2_URXCON = 30; /* interrupt when fifo is nearly full */ + u2_rx_head = 0; u2_rx_tail = 0; +#elif UART2_RX_BUFFERSIZE < 32 /* enable receive, transmit, disable flow control, disable rx interrupt */ + *UART2_UCON = (1 << 0) | (1 << 1) | (0 << 12) | (1 << 14); + *UART2_UCTS = UART2_RX_BUFFERSIZE; /* drop cts when tx buffer at trigger level */ + *GPIO_FUNC_SEL1 = ( (0x01 << (0*2)) | (0x01 << (1*2)) ); /* set GPIO17-16 to UART2 CTS and RTS */ +#else + *UART2_UCON = (1 << 0) | (1 << 1) | (1 << 14); /* enable receive, transmit, disable rx interrupt */ +#endif + + u2_tx_head = 0; u2_tx_tail = 0; + + enable_irq(UART2); + } + + uart_setbaud(uart, baud); + +} + diff --git a/cpu/mc1322x/lib/uart1.c b/cpu/mc1322x/lib/uart1.c index ee570aad6..f45ccbeae 100644 --- a/cpu/mc1322x/lib/uart1.c +++ b/cpu/mc1322x/lib/uart1.c @@ -57,7 +57,7 @@ void uart1_isr(void) { u1_rx_buf[u1_rx_tail]= *UART1_UDATA; u1_rx_tail = u1_rx_tail_next; } else { //buffer is full, flush the fifo - while (*UART1_URXCON !=0) if (*UART1_UDATA); + while (*UART1_URXCON !=0) { if (*UART1_UDATA) { } } } } return; diff --git a/cpu/mc1322x/lib/uart2.c b/cpu/mc1322x/lib/uart2.c index 239d010e4..b5b2f22de 100644 --- a/cpu/mc1322x/lib/uart2.c +++ b/cpu/mc1322x/lib/uart2.c @@ -28,7 +28,7 @@ * SUCH DAMAGE. * * This file is part of libmc1322x: see http://mc1322x.devl.org - * for details. + * for details. * * */ @@ -57,7 +57,7 @@ void uart2_isr(void) { u2_rx_buf[u2_rx_tail]= *UART2_UDATA; u2_rx_tail = u2_rx_tail_next; } else { //buffer is full, flush the fifo - while (*UART2_URXCON !=0) if (*UART2_UDATA); + while (*UART2_URXCON !=0) { if (*UART2_UDATA) { } } } } return; @@ -73,12 +73,12 @@ void uart2_isr(void) { #endif return; } - *UART2_UDATA = u2_tx_buf[u2_tx_tail]; u2_tx_tail++; if (u2_tx_tail >= sizeof(u2_tx_buf)) u2_tx_tail = 0; } + } void uart2_putc(char c) { diff --git a/cpu/mc1322x/src/default_lowlevel.c b/cpu/mc1322x/src/default_lowlevel.c index 25cf87764..44496d279 100644 --- a/cpu/mc1322x/src/default_lowlevel.c +++ b/cpu/mc1322x/src/default_lowlevel.c @@ -45,96 +45,27 @@ void default_vreg_init(void) { *CRM_VREG_CNTL = 0x00000ff8; /* start the regulators */ } -void uart1_init(volatile uint16_t inc, volatile uint16_t mod, volatile uint8_t samp) { - - /* UART must be disabled to set the baudrate */ - UART1->CON = 0; - - UART1->BR = ( inc << 16 ) | mod; - - /* TX and CTS as outputs */ - GPIO->PAD_DIR_SET.GPIO_14 = 1; - GPIO->PAD_DIR_SET.GPIO_16 = 1; - - /* RX and RTS as inputs */ - GPIO->PAD_DIR_RESET.GPIO_15 = 1; - GPIO->PAD_DIR_RESET.GPIO_17 = 1; - - /* see Section 11.5.1.2 Alternate Modes */ - /* you must enable the peripheral first BEFORE setting the function in GPIO_FUNC_SEL */ - /* From the datasheet: "The peripheral function will control operation of the pad IF */ - /* THE PERIPHERAL IS ENABLED. */ - -#if UART1_RX_BUFFERSIZE > 32 - *UART1_UCON = (1 << 0) | (1 << 1) ; /* enable receive, transmit, and both interrupts */ - *UART1_URXCON = 30; /* interrupt when fifo is nearly full */ - u1_rx_head = 0; u1_rx_tail = 0; -#elif UART1_RX_BUFFERSIZE < 32 /* enable receive, transmit, flow control, disable rx interrupt */ - *UART1_UCON = (1 << 0) | (1 << 1) | (1 << 12) | (1 << 14); - *UART1_UCTS = UART1_RX_BUFFERSIZE; /* drop cts when tx buffer at trigger level */ - *GPIO_FUNC_SEL1 = ( (0x01 << (0*2)) | (0x01 << (1*2)) ); /* set GPIO17-16 to UART1 CTS and RTS */ -#else - *UART1_UCON = (1 << 0) | (1 << 1) | (1 << 14); /* enable receive, transmit, disable rx interrupt */ -#endif - - if(samp == UCON_SAMP_16X) - set_bit(*UART1_UCON,UCON_SAMP); - - /* set GPIO15-14 to UART (UART1 TX and RX)*/ - GPIO->FUNC_SEL.GPIO_14 = 1; - GPIO->FUNC_SEL.GPIO_15 = 1; - - /* interrupt when there are this number or more bytes free in the TX buffer*/ - UART1->TXCON = 16; - u1_tx_head = 0; u1_tx_tail = 0; - - /* enable UART1 interrupts in the interrupt controller */ - enable_irq(UART1); +void buck_init(void) { + CRM->SYS_CNTLbits.PWR_SOURCE = 1; + CRM->VREG_CNTLbits.BUCK_SYNC_REC_EN = 1; + CRM->VREG_CNTLbits.BUCK_BYPASS_EN = 0; + CRM->VREG_CNTLbits.BUCK_EN = 1; + while(CRM->STATUSbits.VREG_BUCK_RDY == 0) { continue; } + CRM->VREG_CNTLbits.VREG_1P5V_SEL = 3; + CRM->VREG_CNTLbits.VREG_1P5V_EN = 3; + CRM->VREG_CNTLbits.VREG_1P8V_EN = 1; + while(CRM->STATUSbits.VREG_1P5V_RDY == 0) { continue; } + while(CRM->STATUSbits.VREG_1P8V_RDY == 0) { continue; } } -void uart2_init(volatile uint16_t inc, volatile uint16_t mod, volatile uint8_t samp) { - - /* UART must be disabled to set the baudrate */ - UART2->CON = 0; - - UART2->BR = ( inc << 16 ) | mod; - - /* TX and CTS as outputs */ - GPIO->PAD_DIR_SET.GPIO_18 = 1; - GPIO->PAD_DIR_SET.GPIO_20 = 1; - - /* RX and RTS as inputs */ - GPIO->PAD_DIR_RESET.GPIO_19 = 1; - GPIO->PAD_DIR_RESET.GPIO_21 = 1; - - /* see Section 11.5.1.2 Alternate Modes */ - /* you must enable the peripheral first BEFORE setting the function in GPIO_FUNC_SEL */ - /* From the datasheet: "The peripheral function will control operation of the pad IF */ - /* THE PERIPHERAL IS ENABLED. */ - -#if UART2_RX_BUFFERSIZE > 32 - *UART2_UCON = (1 << 0) | (1 << 1) ; /* enable receive, transmit, and both interrupts */ - *UART2_URXCON = 30; /* interrupt when fifo is nearly full */ - u2_rx_head = 0; u2_rx_tail = 0; -#elif UART2_RX_BUFFERSIZE < 32 /* enable receive, transmit, disable flow control, disable rx interrupt */ - *UART2_UCON = (1 << 0) | (1 << 1) | (0 << 12) | (1 << 14); - *UART2_UCTS = UART2_RX_BUFFERSIZE; /* drop cts when tx buffer at trigger level */ - *GPIO_FUNC_SEL1 = ( (0x01 << (0*2)) | (0x01 << (1*2)) ); /* set GPIO17-16 to UART2 CTS and RTS */ -#else - *UART2_UCON = (1 << 0) | (1 << 1) | (1 << 14); /* enable receive, transmit, disable rx interrupt */ -#endif - - if(samp == UCON_SAMP_16X) - set_bit(*UART2_UCON,UCON_SAMP); - - /* set GPIO15-14 to UART (UART2 TX and RX)*/ - GPIO->FUNC_SEL.GPIO_18 = 1; - GPIO->FUNC_SEL.GPIO_19 = 1; - - /* interrupt when there are this number or more bytes free in the TX buffer*/ - UART2->TXCON = 16; - u2_tx_head = 0; u2_tx_tail = 0; - - /* enable UART2 interrupts in the interrupt controller */ - enable_irq(UART2); +void m12_init(void) { + /* configure pullups for low power */ + GPIO->FUNC_SEL.GPIO_63 = 3; + GPIO->PAD_PU_SEL.GPIO_63 = 0; + GPIO->FUNC_SEL.SS = 3; + GPIO->PAD_PU_SEL.SS = 1; + GPIO->FUNC_SEL.VREF2H = 3; + GPIO->PAD_PU_SEL.VREF2H = 1; + GPIO->FUNC_SEL.U1RTS = 3; + GPIO->PAD_PU_SEL.U1RTS = 1; } diff --git a/cpu/mc1322x/src/default_lowlevel.h b/cpu/mc1322x/src/default_lowlevel.h index 20fc43e66..f6b92e085 100644 --- a/cpu/mc1322x/src/default_lowlevel.h +++ b/cpu/mc1322x/src/default_lowlevel.h @@ -41,8 +41,8 @@ #define trim_xtal() pack_XTAL_CNTL(CTUNE_4PF, CTUNE, FTUNE, IBIAS) void default_vreg_init(void); -void uart1_init(uint16_t inc, uint16_t mod, uint8_t samp); -void uart2_init(uint16_t inc, uint16_t mod, uint8_t samp); +void buck_init(void); +void m12_init(void); void irq_register_timer_handler(int timer, void (*isr)(void)); diff --git a/cpu/mc1322x/tests/Makefile b/cpu/mc1322x/tests/Makefile index 1611c0640..dc1fea01f 100644 --- a/cpu/mc1322x/tests/Makefile +++ b/cpu/mc1322x/tests/Makefile @@ -22,8 +22,8 @@ TARGETS := blink-red blink-green blink-blue blink-white blink-allio \ # this space is initialized with a rom call to rom_data_init TARGETS_WITH_ROM_VARS := nvm-read nvm-write romimg flasher \ rftest-rx rftest-tx \ - autoack-rx autoack-tx \ - per + autoack-rx autoack-tx \ + per ################################################## # you shouldn't need to edit anything below here # diff --git a/cpu/mc1322x/tests/adc.c b/cpu/mc1322x/tests/adc.c index 28a98ce75..92fec985e 100644 --- a/cpu/mc1322x/tests/adc.c +++ b/cpu/mc1322x/tests/adc.c @@ -45,19 +45,24 @@ int main(void) uint8_t c; trim_xtal(); - uart1_init(INC,MOD,SAMP); + uart_init(UART1, 115200); adc_init(); printf("adc test\r\n"); printf("\x1B[2J"); // clear screen + for (c=0; c<=7; c++) { + adc_setup_chan(c); + } + for(;;) { printf("\x1B[H"); // cursor home printf("# Value\r\n"); for (c=0; c #include +#include #include "tests.h" #include "config.h" @@ -45,33 +46,43 @@ void main(void) { uint32_t buf[READ_NBYTES/4]; uint32_t i; - uart_init(INC, MOD, SAMP); + uart_init(UART1, 115200); print_welcome("nvm-read"); vreg_init(); +// buck_init(); + while(CRM->STATUSbits.VREG_1P5V_RDY == 0) { continue; } + while(CRM->STATUSbits.VREG_1P8V_RDY == 0) { continue; } - putstr("Detecting internal nvm\n\r"); + printf("Sys cntl %08x\n\r", (unsigned int)CRM->SYS_CNTL); + printf("vreg cntl %08x\n\r", (unsigned int)CRM->VREG_CNTL); + printf("crm status %08x\n\r", (unsigned int)CRM->STATUS); - err = nvm_detect(gNvmInternalInterface_c, &type); + if(NVM_INTERFACE == gNvmInternalInterface_c) + { + printf("Detecting internal nvm\n\r"); + } else { + printf("Setting up gpio\r\n"); + /* set SPI func */ + GPIO->FUNC_SEL.GPIO_04 = 1; + GPIO->FUNC_SEL.GPIO_05 = 1; + GPIO->FUNC_SEL.GPIO_06 = 1; + GPIO->FUNC_SEL.GPIO_07 = 1; + printf("Detecting external nvm\n\r"); + } + + err = nvm_detect(NVM_INTERFACE, &type); - putstr("nvm_detect returned: 0x"); - put_hex(err); - putstr(" type is: 0x"); - put_hex32(type); - putstr("\n\r"); + printf("nvm_detect returned: 0x%02x type is: 0x%08x\r\n", err, (unsigned int)type); nvm_setsvar(0); - err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)buf, READ_ADDR, READ_NBYTES); - putstr("nvm_read returned: 0x"); - put_hex(err); - putstr("\n\r"); + err = nvm_read(NVM_INTERFACE, type, (uint8_t *)buf, READ_ADDR, READ_NBYTES); + printf("nvm_read returned: 0x%02x\r\n", err); - for(i=0; i #include +#include #include "tests.h" #include "config.h" @@ -45,52 +46,50 @@ void main(void) { uint32_t buf[WRITE_NBYTES/4]; uint32_t i; - uart_init(INC, MOD, SAMP); + uart_init(UART1, 115200); print_welcome("nvm-write"); vreg_init(); - putstr("Detecting internal nvm\n\r"); + if(NVM_INTERFACE == gNvmInternalInterface_c) + { + printf("Detecting internal nvm\n\r"); + } else { + printf("Setting up gpio\r\n"); + /* set SPI func */ + GPIO->FUNC_SEL.GPIO_04 = 1; + GPIO->FUNC_SEL.GPIO_05 = 1; + GPIO->FUNC_SEL.GPIO_06 = 1; + GPIO->FUNC_SEL.GPIO_07 = 1; + printf("Detecting external nvm\n\r"); + } - err = nvm_detect(gNvmInternalInterface_c, &type); + err = nvm_detect(NVM_INTERFACE, &type); - putstr("nvm_detect returned: 0x"); - put_hex(err); - putstr(" type is: 0x"); - put_hex32(type); - putstr("\n\r"); - + printf("nvm_detect returned: 0x%02x type is: 0x%08x\r\n", err, (unsigned int)type); buf[0] = WRITEVAL0; buf[1] = WRITEVAL1; - err = nvm_erase(gNvmInternalInterface_c, type, 0x40000000); /* erase sector 30 --- sector 31 is the 'secret zone' */ - putstr("nvm_erase returned: 0x"); - put_hex(err); - putstr("\n\r"); + err = nvm_erase(NVM_INTERFACE, type, 1 << WRITE_ADDR/4096); + printf("nvm_erase returned: 0x%02x\r\n", err); - err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)buf, WRITE_ADDR, WRITE_NBYTES); - putstr("nvm_write returned: 0x"); - put_hex(err); - putstr("\n\r"); - putstr("writing\n\r"); + err = nvm_write(NVM_INTERFACE, type, (uint8_t *)buf, WRITE_ADDR, WRITE_NBYTES); + printf("nvm_write returned: 0x%02x\r\n", err); + + printf("writing\n\r"); for(i=0; i + * Copyright (c) 2010, Mariano Alvira and other contributors + * to the MC1322x project (http://mc1322x.devl.org) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +char* filename; +char* second; +char* term = "/dev/ttyUSB0"; +int baud = B115200; +int verbose = 0; +char* rts = "rts"; +char* command; +int first_delay = 50; +int second_delay = 100; +int do_exit = 0; +int zerolen = 0; +char *args = NULL; + +struct stat sbuf; +struct termios options; +char buf[256]; +int pfd; +int ffd; +int sfd; + +void help(void); + +int main(int argc, char **argv) +{ + int c = 0; + int r = 0; + int i = 0; + uint32_t s = 0; + opterr = 0; + + /* Parse options */ + while ((c = getopt(argc, argv, "f:s:zt:vu:r:c:a:b:eh")) != -1) { + switch (c) + { + case 'f': + filename = optarg; + break; + case 's': + second = optarg; + break; + case 'z': + zerolen = 1; + break; + case 't': + term = optarg; + break; + case 'v': + verbose = 1; + break; + case 'u': + if (strcmp(optarg, "115200")) { + baud = B115200; + } else if (strcmp(optarg, "57600")) { + baud = B115200; + } else if (strcmp(optarg, "19200")) { + baud = B19200; + } else if (strcmp(optarg, "9600")) { + baud = B9600; + } else { + printf("Unknown baud rate %s!\n", optarg); + return -1; + } + break; + case 'r': + rts = optarg; + break; + case 'c': + command = optarg; + break; + case 'a': + first_delay = atoi(optarg); + break; + case 'b': + second_delay = atoi(optarg); + break; + case 'e': + do_exit = 1; + break; + case 'h': + case '?': + help(); + return 0; + default: + abort(); + } + } + /* Get other arguments */ + if (optind < argc) + args = argv[optind]; + + /* Print settings */ + if (verbose) { + printf("Primary file (RAM): %s\n", filename); + printf("Secondary file (Flash): %s\n", second); + printf("Zero secondary file: %s\n", zerolen == 1 ? "Yes" : "No"); + printf("Port: %s\n", term); + printf("Baud rate: %i\n", baud); + printf("Flow control: %s\n", rts); + printf("Reset command: %s\n", command); + printf("Exit after load: %s\n", do_exit == 1 ? "Yes" : "No"); + printf("Delay 1: %i\n", first_delay); + printf("Delay 2: %i\n", second_delay); + } + + /* Open and configure serial port */ + pfd = open(term, O_RDWR | O_NOCTTY | O_NDELAY); + if (pfd == -1) { + printf("Cannot open serial port %s!\n", term); + return -1; + } + fcntl(pfd, F_SETFL, FNDELAY); + tcgetattr(pfd, &options); + cfsetispeed(&options, baud); + options.c_cflag |= (CLOCAL | CREAD); + options.c_cflag &= ~PARENB; + options.c_cflag &= ~CSTOPB; + options.c_cflag &= ~CSIZE; + options.c_cflag |= CS8; + if (strcmp(rts, "rts")) { + options.c_cflag &= ~CRTSCTS; + } else { + options.c_cflag |= CRTSCTS; + } + options.c_lflag &= ~(ICANON | ECHO | ECHOE | ISIG); + options.c_oflag &= ~OPOST; + tcsetattr(pfd, TCSANOW, &options); + + /* Reset the board if we can */ + printf("Reset the board to enter bootloader (waiting for CONNECT)...\n"); + if (command) { + printf("Performing reset: %s\n", command); + system(command); + } + + /* Primary bootloader wait loop */ + i = 0; + while (1) { + /* Wait for CONNECT */ + r = write(pfd, (const void*)"\0", 1); + sleep(1); + r = read(pfd, &buf[i], sizeof(buf)-1-i); + if (r > 0) { + buf[i+r] = '\0'; + printf("%s", &buf[i]); fflush(stdout); + if (strstr(&buf[i], "CONNECT")) { + printf("\n"); + break; + } + i += r; + if (i >= sizeof(buf)-1) { + i = 0; + } + } else { + printf("."); fflush(stdout); + } + } + + /* Send primary file */ + if (!filename) { + printf("Please specify firmware file name (-f option)!\n"); + return -1; + } + if (stat(filename, &sbuf)) { + printf("Cannot open firmware file %s!\n", filename); + return -1; + } + ffd = open(filename, O_RDONLY); + if (ffd == -1) { + printf("Cannot open firmware file %s!\n", filename); + return -1; + } + s = sbuf.st_size; + printf("Sending %s (%i bytes)...\n", filename, s); + r = write(pfd, (const void*)&s, 4); + i = 0; + r = read(ffd, buf, 1); + while (r > 0) { + do { + usleep(first_delay); + c = write(pfd, (const void*)buf, r); + } while(c < r); + i += r; + printf("Written %i\r", i); fflush(stdout); + r = read(ffd, buf, 1); + } + printf("\n"); + + /* Secondary loader wait loop */ + if (second || zerolen) { + /* Wait for ready */ + printf("Sending secondary file (waiting for ready)...\n"); + i = 0; + while (1) { + sleep(1); + r = read(pfd, &buf[i], sizeof(buf)-1-i); + if (r > 0) { + buf[i+r] = '\0'; + printf("%s", &buf[i]); fflush(stdout); + if (strstr(buf, "ready")) { + printf("\n"); + break; + } + i += r; + if (i >= sizeof(buf)-1) { + i = 0; + } + } else { + printf("."); fflush(stdout); + } + } + + /* Send secondary file */ + if (second) { + if (stat(second, &sbuf)) { + printf("Cannot open secondary file %s!\n", second); + return -1; + } + sfd = open(second, O_RDONLY); + if (sfd == -1) { + printf("Cannot open secondary file %s!\n", second); + return -1; + } + s = sbuf.st_size; + printf("Sending %s (%i bytes)...\n", second, s); + r = write(pfd, (const void*)&s, 4); + i = 0; + r = read(sfd, buf, 1); + while (r > 0) { + do { + usleep(second_delay); + c = write(pfd, (const void*)buf, r); + } while(c < r); + i += r; + printf("Written %i\r", i); fflush(stdout); + r = read(sfd, buf, 1); + } + printf("\n"); + } else if (zerolen) { + s = 0; + printf("Sending %i...\n", s); + write(pfd, (const void*)&s, 4); + } + } + + /* Send the remaining arguments */ + if (args) { + printf("Sending %s\n", args); + r = write(pfd, (const void*)args, strlen(args)); + r = write(pfd, (const void*)",", 1); + } + + /* Drop in echo mode */ + if (!do_exit) { + while (1) { + r = read(pfd, buf, sizeof(buf)); + if (r > 0) { + buf[r] = '\0'; + printf("%s", buf); fflush(stdout); + } + } + } +} + + +void help(void) +{ + printf("Example usage: mc1322x-load -f foo.bin -t /dev/ttyS0 -b 9600\n"); + printf(" or : mc1322x-load -f flasher.bin -s flashme.bin 0x1e000,0x11223344,0x55667788\n"); + printf(" or : mc1322x-load -f flasher.bin -z 0x1e000,0x11223344,0x55667788\n"); + printf(" -f required: binary file to load\n"); + printf(" -s optional: secondary binary file to send\n"); + printf(" -z optional: send a zero length file as secondary\n"); + printf(" -t, terminal default: /dev/ttyUSB0\n"); + printf(" -u, baud rate default: 115200\n"); + printf(" -r [none|rts] flow control default: rts\n"); + printf(" -c command to run for autoreset: \n"); + printf(" e.g. -c 'bbmc -l redbee-econotag -i 0 reset'\n"); + printf(" -e exit instead of dropping to terminal display\n"); + printf(" -a first intercharacter delay, passed to usleep\n"); + printf(" -b second intercharacter delay, passed to usleep\n"); + printf("\n"); + printf("Anything on the command line is sent after all of the files.\n\n"); +} diff --git a/cpu/mc1322x/tools/rftestrx2pcap.py b/cpu/mc1322x/tools/rftestrx2pcap.py new file mode 100755 index 000000000..7199cad69 --- /dev/null +++ b/cpu/mc1322x/tools/rftestrx2pcap.py @@ -0,0 +1,119 @@ +#!/usr/bin/python +# (C) 2012, Mariano Alvira + +import sys,os,time +from struct import * +import re +import serial + +if len(sys.argv) < 3: + sys.stderr.write( "Usage: %s tty channel [outfile]\n" %(sys.argv[0])) + sys.stderr.write( " channel = 11-26\n") + sys.exit(2) + +# change the channel +# rftest-rx increments it's channel everytime you send a character and returns "channel: num" +# send a character until we get to the right channel + +try: + serport = serial.Serial(sys.argv[1], 115200, timeout=1) +except IOError: + print "error opening port" + sys.exit(2) + +chan = '' +while chan != int(sys.argv[2]) - 11: + serport.write(' ') + chanstr = '' + while 1: + chanstr += serport.read(1) + m = re.match(".*channel: (\w+)\s+", chanstr) + if m is not None: + chan = int(m.group(1)) + break + +try: + sys.stderr.write('writing to file %s \n' % (sys.argv[3])) + outfile = open(sys.argv[3], 'w+b') +except IndexError: + outfile = sys.stdout + +sys.stderr.write("RX: 0\r") + +### PCAP setup +MAGIC = 0xa1b2c3d4; +MAJOR = 2; +MINOR = 4; +ZONE = 0; +SIG = 0; +SNAPLEN = 0xffff; +NETWORK = 230; # 802.15.4 no FCS + +# output overall PCAP header +outfile.write(pack('