From 4217eb2ebc0e6fad9dd639aa54aadc72afbc6783 Mon Sep 17 00:00:00 2001
From: maralvira <maralvira>
Date: Sun, 7 Nov 2010 14:27:01 +0000
Subject: [PATCH] Provide a function to change timer interrrupt handlers

Function irq_register_timer_handler(int timer, void (*isr)(void))
lets you change the handler at runtime.  This lets us set handlers
without necessarily knowing the name at link-time.  The old way of
having weakly-linked tmr0_isr functions should still work.
---
 cpu/mc1322x/src/default_lowlevel.h |  4 +++-
 cpu/mc1322x/src/isr.c              | 28 +++++++++++++++++++++-------
 2 files changed, 24 insertions(+), 8 deletions(-)

diff --git a/cpu/mc1322x/src/default_lowlevel.h b/cpu/mc1322x/src/default_lowlevel.h
index 527a79e1a..8f23bce93 100644
--- a/cpu/mc1322x/src/default_lowlevel.h
+++ b/cpu/mc1322x/src/default_lowlevel.h
@@ -30,7 +30,7 @@
  * This file is part of libmc1322x: see http://mc1322x.devl.org
  * for details. 
  *
- * $Id: default_lowlevel.h,v 1.1 2010/06/10 14:49:31 maralvira Exp $
+ * $Id: default_lowlevel.h,v 1.2 2010/11/07 14:27:01 maralvira Exp $
  */
 
 #ifndef LOWLEVEL_H
@@ -42,4 +42,6 @@
 void default_vreg_init(void);
 void uart1_init(uint16_t inc, uint16_t mod, uint8_t samp);
 
+void irq_register_timer_handler(int timer, void (*isr)(void));
+
 #endif
diff --git a/cpu/mc1322x/src/isr.c b/cpu/mc1322x/src/isr.c
index 9f7f92f5f..485b2b707 100644
--- a/cpu/mc1322x/src/isr.c
+++ b/cpu/mc1322x/src/isr.c
@@ -30,12 +30,25 @@
  * This file is part of libmc1322x: see http://mc1322x.devl.org
  * for details. 
  *
- * $Id: isr.c,v 1.3 2010/11/07 14:24:11 maralvira Exp $
+ * $Id: isr.c,v 1.4 2010/11/07 14:27:01 maralvira Exp $
  */
 
 #include <mc1322x.h>
 #include <types.h>
 
+static void (*tmr_isr_funcs[4])(void) = {
+	tmr0_isr,
+	tmr1_isr,
+	tmr2_isr,
+	tmr3_isr
+};
+
+void irq_register_timer_handler(int timer, void (*isr)(void))
+{
+	tmr_isr_funcs[timer] = isr;
+}
+
+
 __attribute__ ((section (".irq")))
 __attribute__ ((interrupt("IRQ"))) 
 void irq(void)
@@ -44,16 +57,17 @@ void irq(void)
 
 	while ((pending = *NIPEND)) {
 		
-	 	if(bit_is_set(pending, INT_NUM_TMR)) { 
+		if(bit_is_set(pending, INT_NUM_TMR)) { 
 			/* dispatch to individual timer isrs if they exist */
 			/* timer isrs are responsible for determining if they
 			 * caused an interrupt */
 			/* and clearing their own interrupt flags */
-	 		if(tmr0_isr != 0) { tmr0_isr(); } 
-	 		if(tmr1_isr != 0) { tmr1_isr(); } 
-	 		if(tmr2_isr != 0) { tmr2_isr(); } 
-	 		if(tmr3_isr != 0) { tmr3_isr(); } 
-	 	}
+			if (tmr_isr_funcs[0] != 0) { (tmr_isr_funcs[0])(); }
+			if (tmr_isr_funcs[1] != 0) { (tmr_isr_funcs[1])(); }
+			if (tmr_isr_funcs[2] != 0) { (tmr_isr_funcs[2])(); }
+			if (tmr_isr_funcs[3] != 0) { (tmr_isr_funcs[3])(); }
+		}
+
 		if(bit_is_set(pending, INT_NUM_MACA)) {
 	 		if(maca_isr != 0) { maca_isr(); } 
 		}