TSCH: timeslot timings as a structure, for flexible configuration
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@ -42,6 +42,7 @@
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#include "net/packetbuf.h"
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#include "net/linkaddr.h"
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#include "net/netstack.h"
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#include "net/mac/tsch/tsch.h"
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#include "sys/energest.h"
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#include "dev/cc2538-rf.h"
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#include "dev/rfcore.h"
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@ -17,11 +17,12 @@
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#define NETSTACK_CONF_RADIO cc2420_driver
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#endif /* NETSTACK_CONF_RADIO */
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extern uint16_t tsch_timeslot_timing_us_15000[];
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/* The TSCH default slot length of 10ms is a bit too short for this platform,
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* use 15ms instead. */
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#ifndef TSCH_CONF_DEFAULT_TIMESLOT_LENGTH
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#define TSCH_CONF_DEFAULT_TIMESLOT_LENGTH 15000
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#endif /* TSCH_CONF_DEFAULT_TIMESLOT_LENGTH */
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#ifndef TSCH_CONF_DEFAULT_TIMESLOT_TIMING
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#define TSCH_CONF_DEFAULT_TIMESLOT_TIMING tsch_timeslot_timing_us_15000
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#endif /* TSCH_CONF_DEFAULT_TIMESLOT_TIMING */
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/* Save RAM through a smaller uIP buffer */
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#ifndef UIP_CONF_BUFFER_SIZE
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@ -43,6 +43,7 @@
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#include "lib/random.h"
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#include "net/netstack.h"
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#include "net/mac/framer/frame802154.h"
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#include "net/mac/tsch/tsch.h"
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#if NETSTACK_CONF_WITH_IPV6
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#include "net/ipv6/uip-ds6.h"
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@ -63,6 +64,22 @@ extern int msp430_dco_required;
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#include "experiment-setup.h"
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#endif
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/* TSCH timeslot timing for platforms requiring 15ms slots */
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uint16_t tsch_timeslot_timing_us_15000[tsch_ts_elements_count] = {
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1800, /* CCAOffset */
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128, /* CCA */
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4000, /* TxOffset */
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(4000 - (TSCH_CONF_RX_WAIT / 2)), /* RxOffset */
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3600, /* RxAckDelay */
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4000, /* TxAckDelay */
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TSCH_CONF_RX_WAIT, /* RxWait */
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800, /* AckWait */
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2072, /* RxTx */
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2400, /* MaxAck */
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4256, /* MaxTx */
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15000, /* TimeslotLength */
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};
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void init_platform(void);
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/*---------------------------------------------------------------------------*/
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/* Log configuration */
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@ -415,12 +415,12 @@ by default, useful in case of duplicate seqno */
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#define TSCH_RADIO_ON_DURING_TIMESLOT 0
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#endif
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/* Timeslot timing */
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#ifndef TSCH_CONF_DEFAULT_TIMESLOT_LENGTH
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#define TSCH_CONF_DEFAULT_TIMESLOT_LENGTH 10000
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#endif /* TSCH_CONF_DEFAULT_TIMESLOT_LENGTH */
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/* TSCH timeslot timing template */
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#ifdef TSCH_CONF_DEFAULT_TIMESLOT_TIMING
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#define TSCH_DEFAULT_TIMESLOT_TIMING TSCH_CONF_DEFAULT_TIMESLOT_TIMING
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#else
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#define TSCH_DEFAULT_TIMESLOT_TIMING tsch_timeslot_timing_us_10000
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#endif
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/* Configurable Rx guard time is micro-seconds */
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#ifndef TSCH_CONF_RX_WAIT
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@ -86,76 +86,5 @@
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#define TSCH_CLOCK_TO_TICKS(c) (((c) * RTIMER_SECOND) / CLOCK_SECOND)
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#define TSCH_CLOCK_TO_SLOTS(c, timeslot_length) (TSCH_CLOCK_TO_TICKS(c) / timeslot_length)
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/* The default timeslot timing in the standard is a guard time of
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* 2200 us, a Tx offset of 2120 us and a Rx offset of 1120 us.
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* As a result, the listening device has a guard time not centered
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* on the expected Tx time. This is to be fixed in the next iteration
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* of the standard. This can be enabled with:
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* #define TSCH_DEFAULT_TS_TX_OFFSET 2120
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* #define TSCH_DEFAULT_TS_RX_OFFSET 1120
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* #define TSCH_DEFAULT_TS_RX_WAIT 2200
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*
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* Instead, we align the Rx guard time on expected Tx time. The Rx
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* guard time is user-configurable with TSCH_CONF_RX_WAIT.
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* (TS_TX_OFFSET - (TS_RX_WAIT / 2)) instead */
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#if TSCH_CONF_DEFAULT_TIMESLOT_LENGTH == 10000
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/* Default timeslot timing as per IEEE 802.15.4e */
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#define TSCH_DEFAULT_TS_CCA_OFFSET 1800
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#define TSCH_DEFAULT_TS_CCA 128
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#define TSCH_DEFAULT_TS_TX_OFFSET 2120
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#define TSCH_DEFAULT_TS_RX_OFFSET (TSCH_DEFAULT_TS_TX_OFFSET - (TSCH_CONF_RX_WAIT / 2))
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#define TSCH_DEFAULT_TS_RX_ACK_DELAY 800
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#define TSCH_DEFAULT_TS_TX_ACK_DELAY 1000
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#define TSCH_DEFAULT_TS_RX_WAIT TSCH_CONF_RX_WAIT
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#define TSCH_DEFAULT_TS_ACK_WAIT 400
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#define TSCH_DEFAULT_TS_RX_TX 192
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#define TSCH_DEFAULT_TS_MAX_ACK 2400
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#define TSCH_DEFAULT_TS_MAX_TX 4256
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#define TSCH_DEFAULT_TS_TIMESLOT_LENGTH 10000
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#elif TSCH_CONF_DEFAULT_TIMESLOT_LENGTH == 15000
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/* Default timeslot timing for platforms requiring 15ms slots */
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#define TSCH_DEFAULT_TS_CCA_OFFSET 1800
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#define TSCH_DEFAULT_TS_CCA 128
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#define TSCH_DEFAULT_TS_TX_OFFSET 4000
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#define TSCH_DEFAULT_TS_RX_OFFSET (TSCH_DEFAULT_TS_TX_OFFSET - (TSCH_CONF_RX_WAIT / 2))
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#define TSCH_DEFAULT_TS_RX_ACK_DELAY 3600
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#define TSCH_DEFAULT_TS_TX_ACK_DELAY 4000
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#define TSCH_DEFAULT_TS_RX_WAIT TSCH_CONF_RX_WAIT
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#define TSCH_DEFAULT_TS_ACK_WAIT 800
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#define TSCH_DEFAULT_TS_RX_TX 2072
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#define TSCH_DEFAULT_TS_MAX_ACK 2400
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#define TSCH_DEFAULT_TS_MAX_TX 4256
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#define TSCH_DEFAULT_TS_TIMESLOT_LENGTH 15000
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#elif TSCH_CONF_DEFAULT_TIMESLOT_LENGTH == 65000U
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/* 65ms timeslot, i.e. nearly the max length allowed by standard (16-bit unsigned in micro-seconds).
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* Useful for running link-layer security on sky in Cooja, where only S/W security is supported.
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* Note: this slot timing would require a total of 120ms. If a slot overlaps with the next active slot,
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* the latter will be skipped.
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* This configuration is mostly a work-around to test link-layer security in Cooja, it is recommended
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* to use it with a 6TiSCH minimal schedule of length >= 2. */
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#define TSCH_DEFAULT_TS_CCA_OFFSET 1800
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#define TSCH_DEFAULT_TS_CCA 128
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#define TSCH_DEFAULT_TS_TX_OFFSET 52000
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#define TSCH_DEFAULT_TS_RX_OFFSET (TSCH_DEFAULT_TS_TX_OFFSET - (TSCH_CONF_RX_WAIT / 2))
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#define TSCH_DEFAULT_TS_RX_ACK_DELAY 58600
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#define TSCH_DEFAULT_TS_TX_ACK_DELAY 59000
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#define TSCH_DEFAULT_TS_RX_WAIT TSCH_CONF_RX_WAIT
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#define TSCH_DEFAULT_TS_ACK_WAIT 800
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#define TSCH_DEFAULT_TS_RX_TX 2072
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#define TSCH_DEFAULT_TS_MAX_ACK 2400
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#define TSCH_DEFAULT_TS_MAX_TX 4256
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#define TSCH_DEFAULT_TS_TIMESLOT_LENGTH 65000
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#else
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#error "TSCH: Unsupported default timeslot length"
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#endif
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#endif /* __TSCH_CONST_H__ */
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/** @} */
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@ -101,21 +101,38 @@ NBR_TABLE(struct eb_stat, eb_stats);
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uint8_t tsch_hopping_sequence[TSCH_HOPPING_SEQUENCE_MAX_LEN];
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struct tsch_asn_divisor_t tsch_hopping_sequence_length;
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/* Default TSCH timeslot timing (in micro-second) */
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static const uint16_t tsch_default_timing_us[tsch_ts_elements_count] = {
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TSCH_DEFAULT_TS_CCA_OFFSET,
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TSCH_DEFAULT_TS_CCA,
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TSCH_DEFAULT_TS_TX_OFFSET,
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TSCH_DEFAULT_TS_RX_OFFSET,
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TSCH_DEFAULT_TS_RX_ACK_DELAY,
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TSCH_DEFAULT_TS_TX_ACK_DELAY,
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TSCH_DEFAULT_TS_RX_WAIT,
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TSCH_DEFAULT_TS_ACK_WAIT,
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TSCH_DEFAULT_TS_RX_TX,
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TSCH_DEFAULT_TS_MAX_ACK,
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TSCH_DEFAULT_TS_MAX_TX,
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TSCH_DEFAULT_TS_TIMESLOT_LENGTH,
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/* The default timeslot timing in the standard is a guard time of
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* 2200 us, a Tx offset of 2120 us and a Rx offset of 1120 us.
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* As a result, the listening device has a guard time not centered
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* on the expected Tx time. This is to be fixed in the next iteration
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* of the standard. This can be enabled with:
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* TxOffset: 2120
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* RxOffset: 1120
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* RxWait: 2200
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*
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* Instead, we align the Rx guard time on expected Tx time. The Rx
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* guard time is user-configurable with TSCH_CONF_RX_WAIT.
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* (TxOffset - (RxWait / 2)) instead */
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uint16_t tsch_timeslot_timing_us_10000[tsch_ts_elements_count] = {
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1800, /* CCAOffset */
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128, /* CCA */
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2120, /* TxOffset */
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(2120 - (TSCH_CONF_RX_WAIT / 2)), /* RxOffset */
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800, /* RxAckDelay */
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1000, /* TxAckDelay */
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TSCH_CONF_RX_WAIT, /* RxWait */
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400, /* AckWait */
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192, /* RxTx */
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2400, /* MaxAck */
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4256, /* MaxTx */
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10000, /* TimeslotLength */
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};
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/* Default TSCH timeslot timing (in micro-second) */
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static const uint16_t *tsch_default_timing_us;
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/* TSCH timeslot timing (in micro-second) */
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uint16_t tsch_timing_us[tsch_ts_elements_count];
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/* TSCH timeslot timing (in rtimer ticks) */
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rtimer_clock_t tsch_timing[tsch_ts_elements_count];
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@ -231,8 +248,10 @@ tsch_reset(void)
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TSCH_ASN_INIT(tsch_current_asn, 0, 0);
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current_link = NULL;
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/* Reset timeslot timing to defaults */
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tsch_default_timing_us = TSCH_DEFAULT_TIMESLOT_TIMING;
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for(i = 0; i < tsch_ts_elements_count; i++) {
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tsch_timing[i] = US_TO_RTIMERTICKS(tsch_default_timing_us[i]);
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tsch_timing_us[i] = tsch_default_timing_us[i];
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tsch_timing[i] = US_TO_RTIMERTICKS(tsch_timing_us[i]);
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}
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#ifdef TSCH_CALLBACK_LEAVING_NETWORK
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TSCH_CALLBACK_LEAVING_NETWORK();
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@ -581,10 +600,11 @@ tsch_associate(const struct input_packet *input_eb, rtimer_clock_t timestamp)
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/* TSCH timeslot timing */
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for(i = 0; i < tsch_ts_elements_count; i++) {
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if(ies.ie_tsch_timeslot_id == 0) {
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tsch_timing[i] = US_TO_RTIMERTICKS(tsch_default_timing_us[i]);
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tsch_timing_us[i] = tsch_default_timing_us[i];
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} else {
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tsch_timing[i] = US_TO_RTIMERTICKS(ies.ie_tsch_timeslot[i]);
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tsch_timing_us[i] = ies.ie_tsch_timeslot[i];
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}
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tsch_timing[i] = US_TO_RTIMERTICKS(tsch_timing_us[i]);
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}
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/* TSCH hopping sequence */
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/* TSCH channel hopping sequence */
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extern uint8_t tsch_hopping_sequence[TSCH_HOPPING_SEQUENCE_MAX_LEN];
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extern struct tsch_asn_divisor_t tsch_hopping_sequence_length;
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/* TSCH timeslot timing (in micro-second) */
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uint16_t tsch_timing_us[tsch_ts_elements_count];
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/* TSCH timeslot timing (in rtimer ticks) */
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extern rtimer_clock_t tsch_timing[tsch_ts_elements_count];
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/* Statistics on the current session */
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@ -179,6 +181,8 @@ extern unsigned long sync_count;
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extern int32_t min_drift_seen;
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extern int32_t max_drift_seen;
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extern uint16_t tsch_timeslot_timing_us_10000[tsch_ts_elements_count];
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/* TSCH processes */
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PROCESS_NAME(tsch_process);
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PROCESS_NAME(tsch_send_eb_process);
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##### "TSCH_CONF_MAX_EB_PERIOD": _______________ -> TSCH_MAX_EB_PERIOD
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#endif
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#if TSCH_CONF_DEFAULT_TIMESLOT_LENGTH
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##### "TSCH_CONF_DEFAULT_TIMESLOT_LENGTH": _____ == TSCH_CONF_DEFAULT_TIMESLOT_LENGTH
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#ifdef TSCH_CONF_DEFAULT_TIMESLOT_TIMING
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##### "TSCH_CONF_DEFAULT_TIMESLOT_TIMING": _____ == TSCH_CONF_DEFAULT_TIMESLOT_TIMING
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#else
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##### "TSCH_CONF_DEFAULT_TIMESLOT_LENGTH": _____ -> TSCH_DEFAULT_TIMESLOT_LENGTH
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##### "TSCH_CONF_DEFAULT_TIMESLOT_TIMING": _____ -> TSCH_DEFAULT_TIMESLOT_TIMING
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#endif
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#ifdef TSCH_SCHEDULE_CONF_DEFAULT_LENGTH
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