TSCH: timeslot timings as a structure, for flexible configuration

This commit is contained in:
Simon Duquennoy 2018-10-03 13:36:46 +02:00
parent ddde2aebdc
commit 5497dc1e20
8 changed files with 72 additions and 100 deletions

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@ -42,6 +42,7 @@
#include "net/packetbuf.h"
#include "net/linkaddr.h"
#include "net/netstack.h"
#include "net/mac/tsch/tsch.h"
#include "sys/energest.h"
#include "dev/cc2538-rf.h"
#include "dev/rfcore.h"

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@ -17,11 +17,12 @@
#define NETSTACK_CONF_RADIO cc2420_driver
#endif /* NETSTACK_CONF_RADIO */
extern uint16_t tsch_timeslot_timing_us_15000[];
/* The TSCH default slot length of 10ms is a bit too short for this platform,
* use 15ms instead. */
#ifndef TSCH_CONF_DEFAULT_TIMESLOT_LENGTH
#define TSCH_CONF_DEFAULT_TIMESLOT_LENGTH 15000
#endif /* TSCH_CONF_DEFAULT_TIMESLOT_LENGTH */
#ifndef TSCH_CONF_DEFAULT_TIMESLOT_TIMING
#define TSCH_CONF_DEFAULT_TIMESLOT_TIMING tsch_timeslot_timing_us_15000
#endif /* TSCH_CONF_DEFAULT_TIMESLOT_TIMING */
/* Save RAM through a smaller uIP buffer */
#ifndef UIP_CONF_BUFFER_SIZE

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@ -43,6 +43,7 @@
#include "lib/random.h"
#include "net/netstack.h"
#include "net/mac/framer/frame802154.h"
#include "net/mac/tsch/tsch.h"
#if NETSTACK_CONF_WITH_IPV6
#include "net/ipv6/uip-ds6.h"
@ -63,6 +64,22 @@ extern int msp430_dco_required;
#include "experiment-setup.h"
#endif
/* TSCH timeslot timing for platforms requiring 15ms slots */
uint16_t tsch_timeslot_timing_us_15000[tsch_ts_elements_count] = {
1800, /* CCAOffset */
128, /* CCA */
4000, /* TxOffset */
(4000 - (TSCH_CONF_RX_WAIT / 2)), /* RxOffset */
3600, /* RxAckDelay */
4000, /* TxAckDelay */
TSCH_CONF_RX_WAIT, /* RxWait */
800, /* AckWait */
2072, /* RxTx */
2400, /* MaxAck */
4256, /* MaxTx */
15000, /* TimeslotLength */
};
void init_platform(void);
/*---------------------------------------------------------------------------*/
/* Log configuration */

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@ -415,12 +415,12 @@ by default, useful in case of duplicate seqno */
#define TSCH_RADIO_ON_DURING_TIMESLOT 0
#endif
/* Timeslot timing */
#ifndef TSCH_CONF_DEFAULT_TIMESLOT_LENGTH
#define TSCH_CONF_DEFAULT_TIMESLOT_LENGTH 10000
#endif /* TSCH_CONF_DEFAULT_TIMESLOT_LENGTH */
/* TSCH timeslot timing template */
#ifdef TSCH_CONF_DEFAULT_TIMESLOT_TIMING
#define TSCH_DEFAULT_TIMESLOT_TIMING TSCH_CONF_DEFAULT_TIMESLOT_TIMING
#else
#define TSCH_DEFAULT_TIMESLOT_TIMING tsch_timeslot_timing_us_10000
#endif
/* Configurable Rx guard time is micro-seconds */
#ifndef TSCH_CONF_RX_WAIT

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@ -86,76 +86,5 @@
#define TSCH_CLOCK_TO_TICKS(c) (((c) * RTIMER_SECOND) / CLOCK_SECOND)
#define TSCH_CLOCK_TO_SLOTS(c, timeslot_length) (TSCH_CLOCK_TO_TICKS(c) / timeslot_length)
/* The default timeslot timing in the standard is a guard time of
* 2200 us, a Tx offset of 2120 us and a Rx offset of 1120 us.
* As a result, the listening device has a guard time not centered
* on the expected Tx time. This is to be fixed in the next iteration
* of the standard. This can be enabled with:
* #define TSCH_DEFAULT_TS_TX_OFFSET 2120
* #define TSCH_DEFAULT_TS_RX_OFFSET 1120
* #define TSCH_DEFAULT_TS_RX_WAIT 2200
*
* Instead, we align the Rx guard time on expected Tx time. The Rx
* guard time is user-configurable with TSCH_CONF_RX_WAIT.
* (TS_TX_OFFSET - (TS_RX_WAIT / 2)) instead */
#if TSCH_CONF_DEFAULT_TIMESLOT_LENGTH == 10000
/* Default timeslot timing as per IEEE 802.15.4e */
#define TSCH_DEFAULT_TS_CCA_OFFSET 1800
#define TSCH_DEFAULT_TS_CCA 128
#define TSCH_DEFAULT_TS_TX_OFFSET 2120
#define TSCH_DEFAULT_TS_RX_OFFSET (TSCH_DEFAULT_TS_TX_OFFSET - (TSCH_CONF_RX_WAIT / 2))
#define TSCH_DEFAULT_TS_RX_ACK_DELAY 800
#define TSCH_DEFAULT_TS_TX_ACK_DELAY 1000
#define TSCH_DEFAULT_TS_RX_WAIT TSCH_CONF_RX_WAIT
#define TSCH_DEFAULT_TS_ACK_WAIT 400
#define TSCH_DEFAULT_TS_RX_TX 192
#define TSCH_DEFAULT_TS_MAX_ACK 2400
#define TSCH_DEFAULT_TS_MAX_TX 4256
#define TSCH_DEFAULT_TS_TIMESLOT_LENGTH 10000
#elif TSCH_CONF_DEFAULT_TIMESLOT_LENGTH == 15000
/* Default timeslot timing for platforms requiring 15ms slots */
#define TSCH_DEFAULT_TS_CCA_OFFSET 1800
#define TSCH_DEFAULT_TS_CCA 128
#define TSCH_DEFAULT_TS_TX_OFFSET 4000
#define TSCH_DEFAULT_TS_RX_OFFSET (TSCH_DEFAULT_TS_TX_OFFSET - (TSCH_CONF_RX_WAIT / 2))
#define TSCH_DEFAULT_TS_RX_ACK_DELAY 3600
#define TSCH_DEFAULT_TS_TX_ACK_DELAY 4000
#define TSCH_DEFAULT_TS_RX_WAIT TSCH_CONF_RX_WAIT
#define TSCH_DEFAULT_TS_ACK_WAIT 800
#define TSCH_DEFAULT_TS_RX_TX 2072
#define TSCH_DEFAULT_TS_MAX_ACK 2400
#define TSCH_DEFAULT_TS_MAX_TX 4256
#define TSCH_DEFAULT_TS_TIMESLOT_LENGTH 15000
#elif TSCH_CONF_DEFAULT_TIMESLOT_LENGTH == 65000U
/* 65ms timeslot, i.e. nearly the max length allowed by standard (16-bit unsigned in micro-seconds).
* Useful for running link-layer security on sky in Cooja, where only S/W security is supported.
* Note: this slot timing would require a total of 120ms. If a slot overlaps with the next active slot,
* the latter will be skipped.
* This configuration is mostly a work-around to test link-layer security in Cooja, it is recommended
* to use it with a 6TiSCH minimal schedule of length >= 2. */
#define TSCH_DEFAULT_TS_CCA_OFFSET 1800
#define TSCH_DEFAULT_TS_CCA 128
#define TSCH_DEFAULT_TS_TX_OFFSET 52000
#define TSCH_DEFAULT_TS_RX_OFFSET (TSCH_DEFAULT_TS_TX_OFFSET - (TSCH_CONF_RX_WAIT / 2))
#define TSCH_DEFAULT_TS_RX_ACK_DELAY 58600
#define TSCH_DEFAULT_TS_TX_ACK_DELAY 59000
#define TSCH_DEFAULT_TS_RX_WAIT TSCH_CONF_RX_WAIT
#define TSCH_DEFAULT_TS_ACK_WAIT 800
#define TSCH_DEFAULT_TS_RX_TX 2072
#define TSCH_DEFAULT_TS_MAX_ACK 2400
#define TSCH_DEFAULT_TS_MAX_TX 4256
#define TSCH_DEFAULT_TS_TIMESLOT_LENGTH 65000
#else
#error "TSCH: Unsupported default timeslot length"
#endif
#endif /* __TSCH_CONST_H__ */
/** @} */

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@ -101,21 +101,38 @@ NBR_TABLE(struct eb_stat, eb_stats);
uint8_t tsch_hopping_sequence[TSCH_HOPPING_SEQUENCE_MAX_LEN];
struct tsch_asn_divisor_t tsch_hopping_sequence_length;
/* Default TSCH timeslot timing (in micro-second) */
static const uint16_t tsch_default_timing_us[tsch_ts_elements_count] = {
TSCH_DEFAULT_TS_CCA_OFFSET,
TSCH_DEFAULT_TS_CCA,
TSCH_DEFAULT_TS_TX_OFFSET,
TSCH_DEFAULT_TS_RX_OFFSET,
TSCH_DEFAULT_TS_RX_ACK_DELAY,
TSCH_DEFAULT_TS_TX_ACK_DELAY,
TSCH_DEFAULT_TS_RX_WAIT,
TSCH_DEFAULT_TS_ACK_WAIT,
TSCH_DEFAULT_TS_RX_TX,
TSCH_DEFAULT_TS_MAX_ACK,
TSCH_DEFAULT_TS_MAX_TX,
TSCH_DEFAULT_TS_TIMESLOT_LENGTH,
/* The default timeslot timing in the standard is a guard time of
* 2200 us, a Tx offset of 2120 us and a Rx offset of 1120 us.
* As a result, the listening device has a guard time not centered
* on the expected Tx time. This is to be fixed in the next iteration
* of the standard. This can be enabled with:
* TxOffset: 2120
* RxOffset: 1120
* RxWait: 2200
*
* Instead, we align the Rx guard time on expected Tx time. The Rx
* guard time is user-configurable with TSCH_CONF_RX_WAIT.
* (TxOffset - (RxWait / 2)) instead */
uint16_t tsch_timeslot_timing_us_10000[tsch_ts_elements_count] = {
1800, /* CCAOffset */
128, /* CCA */
2120, /* TxOffset */
(2120 - (TSCH_CONF_RX_WAIT / 2)), /* RxOffset */
800, /* RxAckDelay */
1000, /* TxAckDelay */
TSCH_CONF_RX_WAIT, /* RxWait */
400, /* AckWait */
192, /* RxTx */
2400, /* MaxAck */
4256, /* MaxTx */
10000, /* TimeslotLength */
};
/* Default TSCH timeslot timing (in micro-second) */
static const uint16_t *tsch_default_timing_us;
/* TSCH timeslot timing (in micro-second) */
uint16_t tsch_timing_us[tsch_ts_elements_count];
/* TSCH timeslot timing (in rtimer ticks) */
rtimer_clock_t tsch_timing[tsch_ts_elements_count];
@ -231,8 +248,10 @@ tsch_reset(void)
TSCH_ASN_INIT(tsch_current_asn, 0, 0);
current_link = NULL;
/* Reset timeslot timing to defaults */
tsch_default_timing_us = TSCH_DEFAULT_TIMESLOT_TIMING;
for(i = 0; i < tsch_ts_elements_count; i++) {
tsch_timing[i] = US_TO_RTIMERTICKS(tsch_default_timing_us[i]);
tsch_timing_us[i] = tsch_default_timing_us[i];
tsch_timing[i] = US_TO_RTIMERTICKS(tsch_timing_us[i]);
}
#ifdef TSCH_CALLBACK_LEAVING_NETWORK
TSCH_CALLBACK_LEAVING_NETWORK();
@ -581,10 +600,11 @@ tsch_associate(const struct input_packet *input_eb, rtimer_clock_t timestamp)
/* TSCH timeslot timing */
for(i = 0; i < tsch_ts_elements_count; i++) {
if(ies.ie_tsch_timeslot_id == 0) {
tsch_timing[i] = US_TO_RTIMERTICKS(tsch_default_timing_us[i]);
tsch_timing_us[i] = tsch_default_timing_us[i];
} else {
tsch_timing[i] = US_TO_RTIMERTICKS(ies.ie_tsch_timeslot[i]);
tsch_timing_us[i] = ies.ie_tsch_timeslot[i];
}
tsch_timing[i] = US_TO_RTIMERTICKS(tsch_timing_us[i]);
}
/* TSCH hopping sequence */

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@ -170,6 +170,8 @@ extern uint8_t tsch_current_channel;
/* TSCH channel hopping sequence */
extern uint8_t tsch_hopping_sequence[TSCH_HOPPING_SEQUENCE_MAX_LEN];
extern struct tsch_asn_divisor_t tsch_hopping_sequence_length;
/* TSCH timeslot timing (in micro-second) */
uint16_t tsch_timing_us[tsch_ts_elements_count];
/* TSCH timeslot timing (in rtimer ticks) */
extern rtimer_clock_t tsch_timing[tsch_ts_elements_count];
/* Statistics on the current session */
@ -179,6 +181,8 @@ extern unsigned long sync_count;
extern int32_t min_drift_seen;
extern int32_t max_drift_seen;
extern uint16_t tsch_timeslot_timing_us_10000[tsch_ts_elements_count];
/* TSCH processes */
PROCESS_NAME(tsch_process);
PROCESS_NAME(tsch_send_eb_process);

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@ -54,10 +54,10 @@
##### "TSCH_CONF_MAX_EB_PERIOD": _______________ -> TSCH_MAX_EB_PERIOD
#endif
#if TSCH_CONF_DEFAULT_TIMESLOT_LENGTH
##### "TSCH_CONF_DEFAULT_TIMESLOT_LENGTH": _____ == TSCH_CONF_DEFAULT_TIMESLOT_LENGTH
#ifdef TSCH_CONF_DEFAULT_TIMESLOT_TIMING
##### "TSCH_CONF_DEFAULT_TIMESLOT_TIMING": _____ == TSCH_CONF_DEFAULT_TIMESLOT_TIMING
#else
##### "TSCH_CONF_DEFAULT_TIMESLOT_LENGTH": _____ -> TSCH_DEFAULT_TIMESLOT_LENGTH
##### "TSCH_CONF_DEFAULT_TIMESLOT_TIMING": _____ -> TSCH_DEFAULT_TIMESLOT_TIMING
#endif
#ifdef TSCH_SCHEDULE_CONF_DEFAULT_LENGTH