Merge pull request #749 from contiki-ng/release-4.2

Release v4.2

.gitignore

@@ -12,13 +12,15 @@
 *.ihex
 *.pyc
 *~
-obj_*
+build/*
 Makefile.target
 Makefile.*.defines
 tools/doxygen/html
+tools/readthedocs/_build
 patches-*
-tools/tunslip
-tools/tunslip6
+tools/serial-io/tunslip6
+tools/serial-io/serialdump
+serialdump-*
 build
 tools/coffee-manager/build/
 tools/coffee-manager/coffee.jar
@@ -31,6 +33,7 @@ COOJA.testlog
 *.native
 *.nrf52dk
 *.openmote-cc2538
+*.simplelink
 *.sky
 *.firmware
 *.srf06-cc26xx
@@ -58,6 +61,8 @@ COOJA.testlog
 *.err
 summary
 tests/[0-9][0-9]-*/org/
+tests/18-coap-lwm2m/Californium.properties
+tests/18-coap-lwm2m/leshan-server-demo*.jar
 
 # x86 UEFI files
 cpu/x86/uefi/Makefile.uefi

.gitmodules

@@ -19,3 +19,12 @@
 [submodule "tests/18-coap-lwm2m/example-lwm2m-standalone"]
 	path = tests/18-coap-lwm2m/example-lwm2m-standalone
 	url = https://github.com/contiki-ng/example-lwm2m-standalone.git
+[submodule "tools/motelist"]
+	path = tools/motelist
+	url = https://github.com/contiki-ng/motelist
+[submodule "arch/cpu/simplelink-cc13xx-cc26xx/lib/coresdk_cc13xx_cc26xx"]
+	path = arch/cpu/simplelink-cc13xx-cc26xx/lib/coresdk_cc13xx_cc26xx
+	url = https://github.com/contiki-ng/coresdk_cc13xx_cc26xx.git
+[submodule "arch/cpu/cc26xx-cc13xx/lib/cc2640r2-sdk"]
+	path = arch/cpu/cc26xx-cc13xx/lib/cc2640r2-sdk
+	url = https://github.com/contiki-ng/cc2640r2-sdk.git

.travis.yml

@@ -1,35 +1,83 @@
 # Setup environment for Docker
 language: generic
 services: docker
-
 notifications:
-  - email: false
+  email: false
 
+# Environment setup before test script. Runs for each build
 before_install:
-  # Environment setup before test script
-  - export CNG_HOST_PATH=`pwd`
-  - export DOCKER_IMG='simonduq/contiki-ng:latest'
-  - sudo chgrp -hR 1000 $CNG_HOST_PATH
-  - docker pull $DOCKER_IMG
-  - ant -q -f $CNG_HOST_PATH/tools/cooja/build.xml jar
+  # Check if anything has changed within the docker directory
+  - DOCKER_CHANGED=`git diff --name-only $TRAVIS_COMMIT_RANGE -- tools/docker | wc -l`
+  # If Docker directory has not changed, pull image from Dockerhub. Else, build
+  # image from Dockerifle. This needs to be done for each job. Any build error
+  # will count as Travis test failure. In case this updates develop, push new
+  # image to Dockerhub (secure credentials only readable on bulids to
+  # contiki-ng/contiki-ng branches, not forks or PRs)
+  - >
+    if [ $DOCKER_CHANGED == 0 ]; then
+      echo "Docker image unchanged, pull from Dockerhub"
+      docker pull $DOCKER_IMG;
+    else
+      echo "Docker image changed, build from Dockerfile"
+      docker build tools/docker -t $DOCKER_IMG;
+      if [ $? != 0 ]; then
+        echo "Failed to build Docker image"
+        exit 1
+      fi
+      if [ $TRAVIS_SECURE_ENV_VARS == true ] && [ $TRAVIS_PULL_REQUEST == false ] && [ $TRAVIS_BRANCH == 'develop' ]; then
+        echo "This build is for an update of branch develop. Push image to Dockerhub"
+        echo $DOCKERHUB_PASSWD | docker login --username contiker --password-stdin
+        docker push $DOCKER_IMG;
+      fi
+    fi
+  # Build Cooja conditionally
+  - if [ ${BUILD_COOJA:-false} = true ] ; then
+      ant -q -f $CNG_HOST_PATH/tools/cooja/build.xml jar ;
+    fi
 
-script: # The test script for each build.
-  - docker run --privileged -v $CNG_HOST_PATH:/home/user/contiki-ng -ti $DOCKER_IMG bash --login -c "make -C tests/??-$TEST_NAME";
+  # Create a directory for out of tree tests and clone the test repo therein
+  # The directory will need created unconditionally so we can always chgrp and
+  # mount it, even if empty. Checkout a pre-defined version.
+  - mkdir -p $OUT_OF_TREE_TEST_PATH
+  - if [ ${TEST_NAME} = "out-of-tree-build" ] ; then
+      git clone --depth 1 https://github.com/contiki-ng/out-of-tree-tests $OUT_OF_TREE_TEST_PATH &&
+      cd $OUT_OF_TREE_TEST_PATH &&
+      git checkout $OUT_OF_TREE_TEST_VER ;
+    fi
+  # Set permissions for Docker mount
+  - sudo chgrp -hR 1000 $CNG_HOST_PATH $OUT_OF_TREE_TEST_PATH
+
+# The test script for each build
+script:
+  - docker run --privileged -v $OUT_OF_TREE_TEST_PATH:/home/user/out-of-tree-tests -v $CNG_HOST_PATH:/home/user/contiki-ng -ti $DOCKER_IMG bash --login -c "make -C tests/??-$TEST_NAME";
   # Check outcome of the test
   - $CNG_HOST_PATH/tests/check-test.sh $CNG_HOST_PATH/tests/??-$TEST_NAME; exit $?;
 
+# Environment variables
 env:
-  # Parallel builds
-  - TEST_NAME='compile-base'
-  - TEST_NAME='compile-arm-ports-01'
-  - TEST_NAME='compile-arm-ports-02'
-  - TEST_NAME='rpl-lite'
-  - TEST_NAME='rpl-classic'
-  - TEST_NAME='tun-rpl-br'
-  - TEST_NAME='coap-lwm2m'
-  - TEST_NAME='simulation-base'
-  - TEST_NAME='ieee802154'
-  - TEST_NAME='compile-nxp-ports'
-  - TEST_NAME='doxygen'
-  - TEST_NAME='compile-tools'
-  - TEST_NAME='native-runs'
+  # Global environment variables, i.e., set for all builds
+  global:
+    - DOCKER_IMG='contiker/contiki-ng'
+    - CNG_HOST_PATH=`pwd`
+    - OUT_OF_TREE_TEST_PATH=$HOME/out-of-tree-tests
+    - OUT_OF_TREE_TEST_VER=2869ae7
+    # Encrypted environment variables.
+    # Only available on builds of contiki-ng/contiki-ng branches, not PRs or forks.
+    - secure: 0nrV5yjpT2kE19Hlm7t619Qbmyjx/G7bSUI1c+U3kZbyuxnRlASjVcDN5uPBoimIfGiBRI0nRq690BogAJt4EKwbC1Dy8kC1XD8mRtQ2AIZ6PHaUoG9iS5sBhFBQK0XkB83bwh6omRn/04O0uuX74ooSWT7fDrWxi/y5+0ysXK6gRtOhdrJ3FU5OkNVewX8NeCdx3pOWhMOtXWdFkMIi1XRdDnvMM5/hHlHMkdXXtaZQX9UsK3Q3DSjPRLZjKRiOlcx9MIg2ebh9ITmd2Du2p2q/LKtoutJckvhbKQPWcZi/B+1ZTSff0FHBIg+EYxf6TeFuia7XSTWH7sr2CDCCtcvSR9bB5yW6jdmGfa8Af8I1TCBuqoSUo0Re50BZBZF7COleEh+IojbjXn2CIDMg5rT4Sh3qcMGvFn9OW1cz5h5UNSOk7EIAXXPcI7Aloxh2sBo4/DrvvbfIsKrvxV9Fx4bdyNtR7dZ7xsoOw6L0zttC3K9naf3VAOeBAyjBiRwm0tWxJC/buhTsKlYrthhyUrwLtYAFL4UHcazvz57hY/cEzR2X6F//9Hp7HFoNtn1E36doX3ZfeI22yxHMo9SYW7O69C45wbhJ29lAA9XXbYVyGBKFkY8C1NCZ0Xckt9H8/Ow5Sz8HmW/NNBJCn0Fsx+jezdGc4ED5naugNbLAyNg=
+  # Each line in the 'matrix' triggers a separate Travis build
+  matrix:
+    - TEST_NAME='compile-base'
+    - TEST_NAME='compile-arm-ports-01'
+    - TEST_NAME='compile-arm-ports-02'
+    - TEST_NAME='rpl-lite' BUILD_COOJA=true
+    - TEST_NAME='rpl-classic' BUILD_COOJA=true
+    - TEST_NAME='tun-rpl-br' BUILD_COOJA=true
+    - TEST_NAME='coap-lwm2m'
+    - TEST_NAME='simulation-base' BUILD_COOJA=true
+    - TEST_NAME='ieee802154' BUILD_COOJA=true
+    - TEST_NAME='compile-nxp-ports'
+    - TEST_NAME='documentation'
+    - TEST_NAME='compile-tools'
+    - TEST_NAME='native-runs'
+    - TEST_NAME='ipv6' BUILD_COOJA=true
+    - TEST_NAME='out-of-tree-build'

LICENSE.md

@@ -1,41 +1,30 @@
-Contiki-NG is licensed under the 3-clause BSD license. This license gives
-everyone the right to use and distribute the code, either in binary or
-source code format, as long as the copyright license is retained in
-the source code.
+Copyright (c) (Year), (Name of copyright holder)
+All rights reserved.
 
-The copyright for different parts of the code is held by different
-people and organizations, but the code is licensed under the same type
-of license. The license text is:
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
 
-```
-/*
- * Copyright (c) (Year), (Name of copyright holder)
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
- * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-```
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its
+   contributors may be used to endorse or promote products derived
+   from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+OF THE POSSIBILITY OF SUCH DAMAGE.

Makefile.embedded

@@ -0,0 +1,47 @@
+# This Makefile contains make variables and rules that are only applicable
+# to builds for embedded devices (i.e. excluding platforms native and cooja).
+# Future extensions to the build system that are of a similar nature (for
+# embedded devices only), can be achieved by extending this Makefile here.
+
+###
+### Targets using the tools/serial-io
+###
+RLWRAPGOALS = login serialdump serialview
+
+.PHONY: $(RLWRAPGOALS)
+
+BAUDRATE ?= 115200
+SERIALDUMP_TIME_FMT ?=
+
+ifeq ($(HOST_OS),Windows)
+  SERIALDUMP = $(SERIAL_DUMP_BIN)
+else
+  RLWRAP = $(notdir $(shell which rlwrap))
+  ifeq ($(RLWRAP),)
+    ifneq ($(filter $(RLWRAPGOALS),$(MAKECMDGOALS)),)
+      $(info Running serialdump without rlwrap support.)
+      $(info Consider installing rlwarp in order to be able to use command history)
+    endif
+  endif
+  SERIALDUMP = $(RLWRAP) $(SERIAL_DUMP_BIN)
+endif
+
+serialdump: $(SERIAL_DUMP_BIN)
+	$(SERIALDUMP) -b$(BAUDRATE) -T$(SERIALDUMP_TIME_FMT) $(PORT) | tee serialdump-`date +%Y%m%d-%H%M`
+
+serialview: $(SERIAL_DUMP_BIN)
+	$(SERIALDUMP) -b$(BAUDRATE) -T$(SERIALDUMP_TIME_FMT) $(PORT)
+
+login: $(SERIAL_DUMP_BIN)
+	$(SERIALDUMP) -b$(BAUDRATE) $(PORT)
+
+###
+### Targets using tools/motelist
+###
+CONTIKI_NG_MOTELIST_DIR = $(TOOLS_DIR)/motelist
+CONTIKI_NG_MOTELIST = python $(CONTIKI_NG_MOTELIST_DIR)/motelist.py
+
+.PHONY: motelist-all
+
+motelist-all:
+	$(CONTIKI_NG_MOTELIST)

Makefile.help

@@ -0,0 +1,29 @@
+usage:
+	@echo "Usage:"
+	@echo "    make [TARGET=(TARGET)] [BOARD=(BOARD)] [DEFINES=(DEFINES)] [PORT=(PORT)] [target]"
+	@echo ""
+	@echo "Typical usage:"
+	@echo "    make [TARGET=(TARGET)] [BOARD=(BOARD)] [all]"
+	@echo ""
+	@echo "    Will build Contiki-NG firmware(s) from the current example dir"
+	@echo "    for platform TARGET, board BOARD."
+	@echo ""
+	@echo "Miscellaneous targets:"
+	@echo "    targets         Prints list of supported platforms"
+	@echo "    boards          Prints a list of supported boards for TARGET"
+	@echo "    savetarget      Saves TARGET and BOARD for future invocations of make"
+	@echo "    savedefines     Saves DEFINES for future invocations of make"
+	@echo "    clean           Removes all compiled files for TARGET"
+	@echo "    distclean       Removes all compiled files for all TARGETs"
+	@echo "    viewconf        Prints Contiki-NG build configuration for TARGET"
+	@echo "    %.flashprof     Shows a Flash/ROM profile of a given firmware (e.g. hello-world.flashprof)"
+	@echo "    %.ramprof       Shows a RAM profile of a given firmware (e.g. hello-world.ramprof)"
+	@echo "    %.o             Produces an object file from a given source file (e.g. hello-world.o)"
+	@echo "    %.e             Produces the pre-processed version of a given source file (e.g. hello-world.e)"
+	@echo "    %.s             Produces an assembly file from a given source file (e.g. hello-world.s)"
+	@echo "    login           View the serial output of the device connected to PORT"
+	@echo "    serialview      Same as login, but prepend serial output with a unix timestamp"
+	@echo "    serialdump      same as serialview, but also save the output to a file"
+	@echo "    motelist-all    Prints a list of connected devices"
+
+help: usage

Makefile.identify-target

@@ -1,3 +1,8 @@
+# This Makefile can be used to identify the selected TARGET used for a
+# specific build. It can be included by example Makefiles that need to take
+# decisions based on TARGET. It is also automatically included by the
+# top-level Makefile.include.
+
 ifeq ($(TARGET),)
   -include Makefile.target
   ifeq ($(TARGET),)

Makefile.include

@@ -10,7 +10,8 @@ WERROR ?= 1
 
 include $(CONTIKI)/Makefile.identify-target
 
-CONTIKI_NG_TARGET_LIB = contiki-ng-$(TARGET).a
+### Include Makefile.tools to pull in targets that allow us to build tools dir
+include $(CONTIKI)/Makefile.tools
 
 ifeq ($(DEFINES),)
   -include Makefile.$(TARGET).defines
@@ -36,17 +37,25 @@ ifdef CI
   endif
 endif
 
-OBJECTDIR = obj_$(TARGET)
+BUILD_DIR = build
+BUILD_DIR_TARGET = $(BUILD_DIR)/$(TARGET)
+BUILD_DIR_BOARD = $(BUILD_DIR_TARGET)/$(BOARD)/$(BUILD_DIR_CONFIG)
+OBJECTDIR = $(BUILD_DIR_BOARD)/obj
+
+CONTIKI_NG_TARGET_LIB = $(BUILD_DIR_BOARD)/contiki-ng-$(TARGET).a
 
 LOWERCASE = -abcdefghijklmnopqrstuvwxyz/
 UPPERCASE = _ABCDEFGHIJKLMNOPQRSTUVWXYZ_
 TARGET_UPPERCASE := ${strip ${shell echo $(TARGET) | sed y!$(LOWERCASE)!$(UPPERCASE)!}}
 CFLAGS += -DCONTIKI=1 -DCONTIKI_TARGET_$(TARGET_UPPERCASE)=1
 CFLAGS += -DCONTIKI_TARGET_STRING=\"$(TARGET)\"
-ifneq ($(BOARD),)
-TARGET_BOARD_UPPERCASE := ${strip ${shell echo $(BOARD) | sed y!$(LOWERCASE)!$(UPPERCASE)!}}
-CFLAGS += -DCONTIKI_BOARD_$(TARGET_BOARD_UPPERCASE)=1
-CFLAGS += -DCONTIKI_BOARD_STRING=\"$(BOARD)\"
+
+CFLAGS += -Wno-unused-const-variable
+
+LDFLAGS_WERROR ?= -Wl,--fatal-warnings
+
+ifeq ($(WERROR),1)
+ LDFLAGS += $(LDFLAGS_WERROR)
 endif
 
 MODULES += os os/sys os/dev os/lib os/services
@@ -69,10 +78,6 @@ endef
 CONTIKI_OBJECTFILES = ${addprefix $(OBJECTDIR)/,${call oname, $(CONTIKI_SOURCEFILES)}}
 PROJECT_OBJECTFILES = ${addprefix $(OBJECTDIR)/,${call oname, $(PROJECT_SOURCEFILES)}}
 
-# Provide way to create $(OBJECTDIR) if it has been removed by make clean
-$(OBJECTDIR):
-	mkdir $@
-
 uniq = $(if $1,$(firstword $1) $(call uniq,$(filter-out $(firstword $1),$1)))
 
 ### Include target makefile (TODO Unsafe?)
@@ -118,6 +123,17 @@ endif # $(BOARD) not empty
 
 PLATFORM_ACTION ?= build
 
+# Provide way to create $(OBJECTDIR) if it has been removed by make clean
+$(OBJECTDIR):
+	$(TRACE_MKDIR)
+	$(Q)mkdir -p $@
+
+ifneq ($(BOARD),)
+  TARGET_BOARD_UPPERCASE := ${strip ${shell echo $(BOARD) | sed y!$(LOWERCASE)!$(UPPERCASE)!}}
+  CFLAGS += -DCONTIKI_BOARD_$(TARGET_BOARD_UPPERCASE)=1
+  CFLAGS += -DCONTIKI_BOARD_STRING=\"$(BOARD)\"
+endif
+
 # Configure MAC layer
 
 # The different options
@@ -165,14 +181,12 @@ MAKE_NET ?= MAKE_NET_IPV6
 
 ifeq ($(MAKE_NET),MAKE_NET_NULLNET)
   CFLAGS += -DNETSTACK_CONF_WITH_NULLNET=1
+  MODULES += os/net/nullnet
 endif
 
 ifeq ($(MAKE_NET),MAKE_NET_IPV6)
   CFLAGS += -DNETSTACK_CONF_WITH_IPV6=1
   MODULES += os/net/ipv6
-else
-  CFLAGS += -DNETSTACK_CONF_WITH_NULLNET=1
-  MODULES += os/net/nullnet
 endif
 
 ifeq ($(MAKE_NET),MAKE_NET_OTHER)
@@ -231,12 +245,20 @@ ifeq ($(V),1)
   TRACE_LD =
   TRACE_AR =
   TRACE_AS =
+  TRACE_OBJCOPY  =
+  TRACE_OBJDUMP  =
+  TRACE_MKDIR =
+  TRACE_CP =
   Q=
 else
   TRACE_CC = @echo "  CC       " $<
   TRACE_LD = @echo "  LD       " $@
   TRACE_AR = @echo "  AR       " $@
   TRACE_AS = @echo "  AS       " $<
+  TRACE_OBJCOPY  = @echo "  OBJCOPY  " $< "-->" $@
+  TRACE_OBJDUMP  = @echo "  OBJDUMP  " $< "-->" $@
+  TRACE_MKDIR = @echo "  MKDIR    " $@
+  TRACE_CP       = @echo "  CP       " $< "-->" $@
   Q=@
 endif
 
@@ -293,21 +315,22 @@ endef
 
 ### Harmonize filename of a .map file, if the platform's build system wants
 ### to create one
-CONTIKI_NG_PROJECT_MAP = $(addsuffix -$(TARGET).map, $(basename $@))
+CONTIKI_NG_PROJECT_MAP = $(BUILD_DIR_BOARD)/$(basename $(notdir $@)).map
 
 .PHONY: clean distclean usage help targets boards savetarget savedefines viewconf
 
 clean:
-	-rm -f *.d *.e *.o $(CONTIKI_NG_TARGET_LIB) $(CLEAN)
-	-rm -rf $(OBJECTDIR)
-	-rm -f $(addsuffix -$(TARGET).map, $(CONTIKI_PROJECT))
-	-rm -f $(addsuffix .$(TARGET), $(CONTIKI_PROJECT))
+	-$(Q)rm -f *.d *.e *.o $(CLEAN)
+	-$(Q)rm -rf $(BUILD_DIR_TARGET)
+	-$(Q)rm -f $(addsuffix .$(TARGET), $(CONTIKI_PROJECT))
+	@echo Target $(TARGET) cleaned
 
 distclean:
 	@for TARG in `ls $(CONTIKI)/arch/platform $(TARGETDIRS)`; do \
-		echo make $$TARG clean; \
-		make TARGET=$$TARG clean; \
+		echo Running: $(MAKE) TARGET=$$TARG clean; \
+		$(MAKE) TARGET=$$TARG clean; \
 	done
+	-$(Q)rm -rf $(BUILD_DIR)
 
 -include $(CONTIKI)/arch/platform/$(TARGET)/Makefile.customrules-$(TARGET)
 
@@ -372,38 +395,23 @@ ifndef LD
 endif
 
 ifndef CUSTOM_RULE_LINK
-%.$(TARGET): %.o $(PROJECT_OBJECTFILES) $(PROJECT_LIBRARIES) $(CONTIKI_NG_TARGET_LIB)
+$(BUILD_DIR_BOARD)/%.$(TARGET): %.o $(PROJECT_OBJECTFILES) $(PROJECT_LIBRARIES) $(CONTIKI_NG_TARGET_LIB)
 	$(TRACE_LD)
 	$(Q)$(LD) $(LDFLAGS) $(TARGET_STARTFILES) ${filter-out %.a,$^} \
 	    ${filter %.a,$^} $(TARGET_LIBFILES) -o $@
 endif
 
+%.$(TARGET): $(BUILD_DIR_BOARD)/%.$(TARGET)
+	$(TRACE_CP)
+	$(Q)cp $< $@
+
 %.ramprof: %.$(TARGET)
 	$(NM) -S -td --size-sort $< | grep -i " [abdrw] " | cut -d' ' -f2,4
 
 %.flashprof: %.$(TARGET)
 	$(NM) -S -td --size-sort $< | grep -i " [t] " | cut -d' ' -f2,4
 
-usage:
-	@echo "Usage:"
-	@echo "    make [TARGET=(TARGET)] [BOARD=(BOARD)] [DEFINES=(DEFINES)] [target]"
-	@echo ""
-	@echo "Typical usage:"
-	@echo "    make [TARGET=(TARGET)] [BOARD=(BOARD)] [all]"
-	@echo ""
-	@echo "    Will build Contiki-NG firmware(s) from the current example dir"
-	@echo "    for platform TARGET, board BOARD."
-	@echo ""
-	@echo "Miscellaneous targets:"
-	@echo "    targets         Prints list of supported platforms"
-	@echo "    boards          Prints a list of supported boards for TARGET"
-	@echo "    savegtarget     Saves TARGET and BOARD for future invocations of make"
-	@echo "    savedefines     Saves DEFINES for future invocations of make"
-	@echo "    clean           Removes all compiled files for TARGET"
-	@echo "    distclean       Removes all compiled files for all TARGETs"
-	@echo "    viewconf        Prints Contiki-NG build configuration for TARGET"
-
-help: usage
+include $(CONTIKI)/Makefile.help
 
 targets:
 	@ls $(CONTIKI)/arch/platform $(TARGETDIRS)
@@ -428,6 +436,7 @@ savedefines:
 	@echo "saving Makefile.$(TARGET).defines"
 	@echo >Makefile.$(TARGET).defines "DEFINES = $(DEFINES)"
 
+VIEWCONF = $(CONTIKI)/tools/viewconf/viewconf.c
 viewconf:
 	@echo "----------------- Make variables: --------------"
 	@echo "##### \"TARGET\": ________________________________ $(TARGET)"
@@ -439,17 +448,23 @@ ifdef MAKE_COAP_DTLS_KEYSTORE
 	@echo "##### \"MAKE_COAP_DTLS_KEYSTORE\": _______________ $(MAKE_COAP_DTLS_KEYSTORE)"
 endif
 	@echo "----------------- C variables: -----------------"
-	$(Q)$(CC) $(CFLAGS) -E $(CONTIKI)/tools/viewconf.c | grep \#\#\#\#\#
+	$(Q)$(CC) $(CFLAGS) -E $(VIEWCONF) | grep \#\#\#\#\#
 	@echo "------------------------------------------------"
 	@echo "'==' Means the flag is set to a given a value"
 	@echo "'->' Means the flag is unset, but will default to a given value"
 	@echo "'><' Means the flag is unset and has no default value"
 	@echo "To view more Make variables, edit $(CONTIKI)/Makefile.include, rule 'viewconf'"
-	@echo "To view more C variables, edit $(CONTIKI)/tools/viewconf.c"
+	@echo "To view more C variables, edit $(VIEWCONF)"
 
-# Don't treat %.$(TARGET) as an intermediate file because it is
-# in fact the primary target.
-.PRECIOUS: %.$(TARGET)
+### Include Makefile.embedded for relevant platforms, in order to pull in
+### rules for login, serialview etc
+ifeq ($(findstring $(TARGET),native cooja),)
+  include $(CONTIKI)/Makefile.embedded
+endif
+
+# Don't treat $(BUILD_DIR_BOARD)/%.$(TARGET) and $(TARGET) as intermediate
+# files because for many platforms they are in fact the primary target.
+.PRECIOUS: $(BUILD_DIR_BOARD)/%.$(TARGET) %.$(TARGET)
 
 # Cancel the predefined implict rule for compiling and linking
 # a single C source into a binary to force GNU make to consider

Makefile.tools

@@ -0,0 +1,17 @@
+# Some make rules in the main build system depend on the presence of utilities
+# under the tools/ dir. For those dependencies, we use this makefile here to
+# recursively invoke the respective build under tools/.
+
+TOOLS_DIR = $(CONTIKI)/tools
+SERIAL_IO_TOOL_DIR = $(TOOLS_DIR)/serial-io
+
+SERIAL_IO_TOOL_DEPS = $(addprefix $(SERIAL_IO_TOOL_DIR)/, tools-utils.c tools-utils.h)
+
+TUNSLIP6 = $(SERIAL_IO_TOOL_DIR)/tunslip6
+SERIAL_DUMP_BIN = $(SERIAL_IO_TOOL_DIR)/serialdump
+
+$(SERIAL_DUMP_BIN): $(SERIAL_IO_TOOL_DIR)/serialdump.c $(SERIAL_IO_TOOL_DEPS)
+	$(MAKE) -C $(SERIAL_IO_TOOL_DIR) serialdump
+
+$(TUNSLIP6): $(SERIAL_IO_TOOL_DIR)/tunslip6.c $(SERIAL_IO_TOOL_DEPS)
+	$(MAKE) -C $(SERIAL_IO_TOOL_DIR) tunslip6

README.md

@@ -9,7 +9,10 @@
 Contiki-NG is an open-source, cross-platform operating system for Next-Generation IoT devices. It focuses on dependable (secure and reliable) low-power communication and standard protocols, such as IPv6/6LoWPAN, 6TiSCH, RPL, and CoAP. Contiki-NG comes with extensive documentation, tutorials, a roadmap, release cycle, and well-defined development flow for smooth integration of community contributions.
 
 Unless excplicitly stated otherwise, Contiki-NG sources are distributed under
-the terms of the [3-clause BSD license](LICENSE.md).
+the terms of the [3-clause BSD license](LICENSE.md). This license gives
+everyone the right to use and distribute the code, either in binary or
+source code format, as long as the copyright license is retained in
+the source code.
 
 Contiki-NG started as a fork of the Contiki OS and retains some of its original features.
 

arch/cpu/arm/Makefile.arm

@@ -1,3 +1,11 @@
+### Verbosity control. Use  make V=1 to get verbose builds.
+### Extends what we already have in the top-level Makefile
+ifeq ($(V),1)
+  TRACE_SREC_CAT =
+else
+  TRACE_SREC_CAT = @echo "  SREC_CAT " $< "-->" $@
+endif
+
 CC       = arm-none-eabi-gcc
 CPP      = arm-none-eabi-cpp
 LD       = arm-none-eabi-gcc
@@ -9,10 +17,13 @@ SIZE     = arm-none-eabi-size
 SREC_CAT = srec_cat
 
 CFLAGS += -mthumb -mabi=aapcs -mlittle-endian
-CFLAGS += -Werror -Wall
+CFLAGS += -Wall
 CFLAGS += -std=c99
 CFLAGS += -ffunction-sections -fdata-sections -fno-strict-aliasing
 CFLAGS += -fshort-enums -fomit-frame-pointer -fno-builtin
+ifeq ($(WERROR),1)
+  CFLAGS += -Werror
+endif
 
 LDFLAGS += -mthumb -mlittle-endian
 
@@ -26,29 +37,46 @@ else
   CFLAGS += -O2
 endif
 
-### Use CMSIS and the existing dbg-io from arch/cpu/arm/common
-CONTIKI_ARM_DIRS += . common/dbg-io
+### Use CMSIS from arch/cpu/arm/common
+CONTIKI_ARM_DIRS += . 
 CONTIKI_CPU_DIRS += $(addprefix ../arm/, $(CONTIKI_ARM_DIRS))
 
+### Default to use os/lib/dbg-io unless configured to do otherwise
+MAKE_WITH_LIB_DBG_IO ?= 1
+
+ifeq ($(MAKE_WITH_LIB_DBG_IO),1)
+  MODULES += os/lib/dbg-io
+endif
+
 ### CPU-dependent cleanup files
 CLEAN += *.elf *.bin *.lst *.hex *.i16hex
 
+OUT_HEX = $(BUILD_DIR_BOARD)/%.hex
+OUT_I16HEX = $(BUILD_DIR_BOARD)/%.i16hex
+OUT_BIN = $(BUILD_DIR_BOARD)/%.bin
+OUT_LST = $(BUILD_DIR_BOARD)/%.lst
+
 ### Don't treat the following files as intermediate
-.PRECIOUS: %.elf %.hex %.bin
+.PRECIOUS: $(OUT_ELF) $(OUT_HEX) $(OUT_BIN)
 
-%.i16hex: %.elf
-	$(OBJCOPY) -O ihex $< $@
+$(OUT_I16HEX): $(OUT_ELF)
+	$(TRACE_OBJCOPY)
+	$(Q)$(OBJCOPY) -O ihex $< $@
 
-%.hex: %.i16hex
-	$(SREC_CAT) $< -intel -o $@ -intel
+$(OUT_HEX): $(OUT_I16HEX)
+	$(TRACE_SREC_CAT)
+	$(Q)$(SREC_CAT) $< -intel -o $@ -intel
 
-%.bin: %.elf
-	$(OBJCOPY) -O binary $(OBJCOPY_FLAGS) $< $@
+$(OUT_BIN): $(OUT_ELF)
+	$(TRACE_OBJCOPY)
+	$(Q)$(OBJCOPY) -O binary $(OBJCOPY_FLAGS) $< $@
 
-%.lst: %.elf
-	$(OBJDUMP) $(OBJDUMP_FLAGS) $< > $@
+$(OUT_LST): $(OUT_ELF)
+	$(TRACE_OBJDUMP)
+	$(Q)$(OBJDUMP) $(OBJDUMP_FLAGS) $< > $@
 
 ### We don't really need the .hex and .bin for the .$(TARGET) but let's make
 ### sure they get built
-%.$(TARGET): %.elf %.hex %.bin
-	cp $< $@
+$(BUILD_DIR_BOARD)/%.$(TARGET): $(OUT_ELF) $(OUT_HEX) $(OUT_BIN)
+	$(TRACE_CP)
+	$(Q)cp $< $@

arch/cpu/arm/arm-def.h

@@ -57,8 +57,6 @@
 typedef uint32_t clock_time_t;
 typedef uint32_t uip_stats_t;
 
-typedef uint32_t rtimer_clock_t;
-#define RTIMER_CLOCK_DIFF(a, b)     ((int32_t)((a) - (b)))
 /** @} */
 
 /*

arch/cpu/arm/cortex-m/Makefile.cortex-m

@@ -1,3 +1,28 @@
 CONTIKI_ARM_DIRS += cortex-m cortex-m/CMSIS
 
+### Build syscalls for newlib
+MODULES += os/lib/newlib
+
+LDFLAGS += -T $(LDSCRIPT)
+LDFLAGS += -Wl,--gc-sections,--sort-section=alignment
+LDFLAGS += -Wl,-Map=$(CONTIKI_NG_PROJECT_MAP),--cref,--no-warn-mismatch
+
+OBJCOPY_FLAGS += --gap-fill 0xff
+
+CPU_STARTFILES = ${addprefix $(OBJECTDIR)/,${call oname, $(CPU_START_SOURCEFILES)}}
+
+### Resolve any potential circular dependencies between the linked libraries
+### See: https://stackoverflow.com/questions/5651869/gcc-what-are-the-start-group-and-end-group-command-line-options/5651895
+TARGET_LIBFLAGS := -Wl,--start-group $(TARGET_LIBFILES) -Wl,--end-group
+
+CUSTOM_RULE_LINK = 1
+
+OUT_ELF = $(BUILD_DIR_BOARD)/%.elf
+
+.SECONDEXPANSION:
+
+$(OUT_ELF): $(CPU_STARTFILES) $$(CONTIKI_OBJECTFILES) %.o $(PROJECT_OBJECTFILES) $(PROJECT_LIBRARIES) $(LDSCRIPT) $(TARGET_LIBS)
+	$(TRACE_LD)
+	$(Q)$(LD) $(LDFLAGS) ${filter-out $(LDSCRIPT) %.a,$^} ${filter %.a,$^} $(TARGET_LIBFLAGS) -o $@
+
 include $(CONTIKI)/arch/cpu/arm/Makefile.arm

arch/cpu/arm/cortex-m/cm3/Makefile.cm3

@@ -3,24 +3,7 @@ CONTIKI_ARM_DIRS += cortex-m/cm3
 CFLAGS += -mcpu=cortex-m3
 
 LDFLAGS += -mcpu=cortex-m3 -nostartfiles
-LDFLAGS += -T $(LDSCRIPT)
-LDFLAGS += -Wl,--gc-sections,--sort-section=alignment
-LDFLAGS += -Wl,-Map=$(CONTIKI_NG_PROJECT_MAP),--cref,--no-warn-mismatch
 
-OBJCOPY_FLAGS += --gap-fill 0xff
-
-### Build syscalls for newlib
-MODULES += os/lib/newlib
-
-CPU_STARTFILES = ${addprefix $(OBJECTDIR)/,${call oname, $(CPU_START_SOURCEFILES)}}
-
-### Compilation rules
-CUSTOM_RULE_LINK = 1
-
-.SECONDEXPANSION:
-
-%.elf: $(CPU_STARTFILES) $$(CONTIKI_OBJECTFILES) %.o $(PROJECT_OBJECTFILES) $(PROJECT_LIBRARIES) $(LDSCRIPT)
-	$(TRACE_LD)
-	$(Q)$(LD) $(LDFLAGS) ${filter-out $(LDSCRIPT) %.a,$^} ${filter %.a,$^} $(TARGET_LIBFILES) -lm -o $@
+TARGET_LIBFILES += -lm
 
 include $(CONTIKI)/arch/cpu/arm/cortex-m/Makefile.cortex-m

arch/cpu/arm/cortex-m/cm4/Makefile.cm4

@@ -1,13 +1,7 @@
 CONTIKI_ARM_DIRS += cortex-m/cm4
 
 CFLAGS += -mcpu=cortex-m4
+
 LDFLAGS += -mcpu=cortex-m4
 
-### Compilation rules
-CUSTOM_RULE_LINK=1
-
-%.elf: $(TARGET_STARTFILES) %.o $(PROJECT_OBJECTFILES) $(PROJECT_LIBRARIES) $(CONTIKI_NG_TARGET_LIB) $(TARGET_LIBS)
-	$(TRACE_LD)
-	$(Q)$(CC) $(LDFLAGS) ${filter %.o %.a,$^} -o $@
-
 include $(CONTIKI)/arch/cpu/arm/cortex-m/Makefile.cortex-m

arch/cpu/cc2538/Makefile.cc2538

@@ -28,8 +28,6 @@ CONTIKI_CPU_SOURCEFILES += slip-arch.c slip.c
 CONTIKI_CPU_SOURCEFILES += i2c.c cc2538-temp-sensor.c vdd3-sensor.c
 CONTIKI_CPU_SOURCEFILES += cfs-coffee.c cfs-coffee-arch.c pwm.c
 
-MODULES += os/lib/dbg-io
-
 USB_SOURCEFILES += usb-core.c cdc-acm.c usb-arch.c usb-serial.c cdc-acm-descriptors.c
 
 CPU_START_SOURCEFILES = startup-gcc.c

arch/cpu/cc2538/cc2538-conf.h

@@ -219,14 +219,6 @@
  */
 /* RF Config */
 
-#ifdef RF_CHANNEL
-#define CC2538_RF_CONF_CHANNEL      RF_CHANNEL
-#endif
-
-#ifndef CC2538_RF_CONF_CHANNEL
-#define CC2538_RF_CONF_CHANNEL              26
-#endif /* CC2538_RF_CONF_CHANNEL */
-
 #ifndef CC2538_RF_CONF_AUTOACK
 #define CC2538_RF_CONF_AUTOACK               1 /**< RF H/W generates ACKs */
 #endif /* CC2538_CONF_AUTOACK */

arch/cpu/cc2538/cc2538-def.h

@@ -36,11 +36,16 @@
 /*---------------------------------------------------------------------------*/
 #define RTIMER_ARCH_SECOND 32768
 /*---------------------------------------------------------------------------*/
+#define CC2538_PHY_OVERHEAD          3
+#define CC2538_BYTE_AIR_TIME         32
 /* 352us from calling transmit() until the SFD byte has been sent */
-#define RADIO_DELAY_BEFORE_TX     ((unsigned)US_TO_RTIMERTICKS(352))
+#define CC2538_DELAY_BEFORE_TX       ((unsigned)US_TO_RTIMERTICKS(352))
 /* 192us as in datasheet but ACKs are not always received, so adjusted to 250us */
-#define RADIO_DELAY_BEFORE_RX     ((unsigned)US_TO_RTIMERTICKS(250))
-#define RADIO_DELAY_BEFORE_DETECT 0
+#define CC2538_DELAY_BEFORE_RX       ((unsigned)US_TO_RTIMERTICKS(250))
+#define CC2538_DELAY_BEFORE_DETECT   0
+/* Frame filtering done in software */
+#define TSCH_CONF_HW_FRAME_FILTERING  0
+
 #ifndef TSCH_CONF_BASE_DRIFT_PPM
 /* The drift compared to "true" 10ms slots.
  * Enable adaptive sync to enable compensation for this.
@@ -54,9 +59,6 @@
 #define TSCH_CONF_BASE_DRIFT_PPM -977
 #endif
 
-#if MAC_CONF_WITH_TSCH
-#define TSCH_CONF_HW_FRAME_FILTERING  0
-#endif /* MAC_CONF_WITH_TSCH */
 /*---------------------------------------------------------------------------*/
 #define SPI_CONF_CONTROLLER_COUNT 2
 /*---------------------------------------------------------------------------*/

arch/cpu/cc2538/dev/cc2538-rf.c

@@ -42,6 +42,7 @@
 #include "net/packetbuf.h"
 #include "net/linkaddr.h"
 #include "net/netstack.h"
+#include "net/mac/tsch/tsch.h"
 #include "sys/energest.h"
 #include "dev/cc2538-rf.h"
 #include "dev/rfcore.h"
@@ -68,13 +69,10 @@
  */
 #define UDMA_RX_SIZE_THRESHOLD 3
 /*---------------------------------------------------------------------------*/
-#include <stdio.h>
-#define DEBUG 0
-#if DEBUG
-#define PRINTF(...) printf(__VA_ARGS__)
-#else
-#define PRINTF(...)
-#endif
+/* Log configuration */
+#include "sys/log.h"
+#define LOG_MODULE "cc2538-rf"
+#define LOG_LEVEL LOG_LEVEL_NONE
 /*---------------------------------------------------------------------------*/
 /* Local RF Flags */
 #define RX_ACTIVE     0x80
@@ -86,6 +84,7 @@
 #define LQI_BIT_MASK 0x7F
 /* RSSI Offset */
 #define RSSI_OFFSET    73
+#define RSSI_INVALID -128
 
 /* 192 usec off -> on interval (RX Callib -> SFD Wait). We wait a bit more */
 #define ONOFF_TIME                    RTIMER_ARCH_SECOND / 3125
@@ -113,7 +112,7 @@ static int8_t rssi;
 static uint8_t crc_corr;
 /*---------------------------------------------------------------------------*/
 static uint8_t rf_flags;
-static uint8_t rf_channel = CC2538_RF_CHANNEL;
+static uint8_t rf_channel = IEEE802154_DEFAULT_CHANNEL;
 
 static int on(void);
 static int off(void);
@@ -156,28 +155,19 @@ PROCESS(cc2538_rf_process, "cc2538 RF driver");
 static uint8_t
 get_channel()
 {
-  uint8_t chan = REG(RFCORE_XREG_FREQCTRL) & RFCORE_XREG_FREQCTRL_FREQ;
-
-  return (chan - CC2538_RF_CHANNEL_MIN) / CC2538_RF_CHANNEL_SPACING
-         + CC2538_RF_CHANNEL_MIN;
+  return rf_channel;
 }
 /*---------------------------------------------------------------------------*/
 /**
  * \brief Set the current operating channel
  * \param channel The desired channel as a value in [11,26]
- * \return Returns a value in [11,26] representing the current channel
- *         or a negative value if \e channel was out of bounds
  */
-static int8_t
+static void
 set_channel(uint8_t channel)
 {
   uint8_t was_on = 0;
 
-  PRINTF("RF: Set Channel\n");
-
-  if((channel < CC2538_RF_CHANNEL_MIN) || (channel > CC2538_RF_CHANNEL_MAX)) {
-    return CC2538_RF_CHANNEL_SET_ERROR;
-  }
+  LOG_INFO("Set Channel\n");
 
   /* Changes to FREQCTRL take effect after the next recalibration */
 
@@ -195,8 +185,6 @@ set_channel(uint8_t channel)
   }
 
   rf_channel = channel;
-
-  return (int8_t)channel;
 }
 /*---------------------------------------------------------------------------*/
 static radio_value_t
@@ -244,10 +232,11 @@ get_rssi(void)
     on();
   }
 
-  /* Wait on RSSI_VALID */
-  while((REG(RFCORE_XREG_RSSISTAT) & RFCORE_XREG_RSSISTAT_RSSI_VALID) == 0);
-
-  rssi = (int8_t)(REG(RFCORE_XREG_RSSI) & RFCORE_XREG_RSSI_RSSI_VAL) - RSSI_OFFSET;
+  /* Wait for a valid RSSI reading */
+  do {
+    rssi = REG(RFCORE_XREG_RSSI);
+  } while(rssi == RSSI_INVALID);
+  rssi -= RSSI_OFFSET;
 
   /* If we were off, turn back off */
   if(was_off) {
@@ -322,6 +311,16 @@ set_frame_filtering(uint8_t enable)
 }
 /*---------------------------------------------------------------------------*/
 static void
+set_shr_search(int enable)
+{
+  if(enable) {
+    REG(RFCORE_XREG_FRMCTRL0) &= ~RFCORE_XREG_FRMCTRL0_RX_MODE;
+  } else {
+    REG(RFCORE_XREG_FRMCTRL0) |= RFCORE_XREG_FRMCTRL0_RX_MODE;
+  }
+}
+/*---------------------------------------------------------------------------*/
+static void
 mac_timer_init(void)
 {
   CLOCK_STABLE();
@@ -403,7 +402,7 @@ channel_clear(void)
   int cca;
   uint8_t was_off = 0;
 
-  PRINTF("RF: CCA\n");
+  LOG_INFO("CCA\n");
 
   /* If we are off, turn on first */
   if((REG(RFCORE_XREG_FSMSTAT0) & RFCORE_XREG_FSMSTAT0_FSM_FFCTRL_STATE) == 0) {
@@ -431,7 +430,7 @@ channel_clear(void)
 static int
 on(void)
 {
-  PRINTF("RF: On\n");
+  LOG_INFO("On\n");
 
   if(!(rf_flags & RX_ACTIVE)) {
     CC2538_RF_CSP_ISFLUSHRX();
@@ -447,7 +446,7 @@ on(void)
 static int
 off(void)
 {
-  PRINTF("RF: Off\n");
+  LOG_INFO("Off\n");
 
   /* Wait for ongoing TX to complete (e.g. this could be an outgoing ACK) */
   while(REG(RFCORE_XREG_FSMSTAT1) & RFCORE_XREG_FSMSTAT1_TX_ACTIVE);
@@ -470,7 +469,7 @@ off(void)
 static int
 init(void)
 {
-  PRINTF("RF: Init\n");
+  LOG_INFO("Init\n");
 
   if(rf_flags & RF_ON) {
     return 0;
@@ -490,6 +489,7 @@ init(void)
   REG(RFCORE_XREG_TXFILTCFG) = 0x09;    /** TX anti-aliasing filter bandwidth */
   REG(RFCORE_XREG_AGCCTRL1) = 0x15;     /** AGC target value */
   REG(ANA_REGS_IVCTRL) = 0x0B;          /** Bias currents */
+  REG(RFCORE_XREG_FSCAL1) = 0x01;       /** Tune frequency calibration */
 
   /*
    * Defaults:
@@ -513,6 +513,9 @@ init(void)
 
   set_channel(rf_channel);
 
+  /* Enable SHR search */
+  set_shr_search(1);
+
   /* Acknowledge all RF Error interrupts */
   REG(RFCORE_XREG_RFERRM) = RFCORE_XREG_RFERRM_RFERRM;
   NVIC_EnableIRQ(RF_ERR_IRQn);
@@ -545,8 +548,6 @@ init(void)
 
   rf_flags |= RF_ON;
 
-  ENERGEST_ON(ENERGEST_TYPE_LISTEN);
-
   return 1;
 }
 /*---------------------------------------------------------------------------*/
@@ -555,7 +556,7 @@ prepare(const void *payload, unsigned short payload_len)
 {
   uint8_t i;
 
-  PRINTF("RF: Prepare 0x%02x bytes\n", payload_len + CHECKSUM_LEN);
+  LOG_INFO("Prepare 0x%02x bytes\n", payload_len + CHECKSUM_LEN);
 
   /*
    * When we transmit in very quick bursts, make sure previous transmission
@@ -569,12 +570,12 @@ prepare(const void *payload, unsigned short payload_len)
 
   CC2538_RF_CSP_ISFLUSHTX();
 
-  PRINTF("RF: data = ");
+  LOG_INFO("data = ");
   /* Send the phy length byte first */
   REG(RFCORE_SFR_RFDATA) = payload_len + CHECKSUM_LEN;
 
   if(CC2538_RF_CONF_TX_USE_DMA) {
-    PRINTF("<uDMA payload>");
+    LOG_INFO_("<uDMA payload>");
 
     /* Set the transfer source's end address */
     udma_set_channel_src(CC2538_RF_CONF_TX_DMA_CHAN,
@@ -598,10 +599,10 @@ prepare(const void *payload, unsigned short payload_len)
   } else {
     for(i = 0; i < payload_len; i++) {
       REG(RFCORE_SFR_RFDATA) = ((unsigned char *)(payload))[i];
-      PRINTF("%02x", ((unsigned char *)(payload))[i]);
+      LOG_INFO_("%02x", ((unsigned char *)(payload))[i]);
     }
   }
-  PRINTF("\n");
+  LOG_INFO_("\n");
 
   return 0;
 }
@@ -614,7 +615,7 @@ transmit(unsigned short transmit_len)
   rtimer_clock_t t0;
   uint8_t was_off = 0;
 
-  PRINTF("RF: Transmit\n");
+  LOG_INFO("Transmit\n");
 
   if(!(rf_flags & RX_ACTIVE)) {
     t0 = RTIMER_NOW();
@@ -649,7 +650,7 @@ transmit(unsigned short transmit_len)
   }
 
   if(!(REG(RFCORE_XREG_FSMSTAT1) & RFCORE_XREG_FSMSTAT1_TX_ACTIVE)) {
-    PRINTF("RF: TX never active.\n");
+    LOG_ERR("TX never active.\n");
     CC2538_RF_CSP_ISFLUSHTX();
     ret = RADIO_TX_ERR;
   } else {
@@ -679,7 +680,7 @@ read(void *buf, unsigned short bufsize)
   uint8_t i;
   uint8_t len;
 
-  PRINTF("RF: Read\n");
+  LOG_INFO("Read\n");
 
   if((REG(RFCORE_XREG_FSMSTAT1) & RFCORE_XREG_FSMSTAT1_FIFOP) == 0) {
     return 0;
@@ -691,33 +692,33 @@ read(void *buf, unsigned short bufsize)
   /* Check for validity */
   if(len > CC2538_RF_MAX_PACKET_LEN) {
     /* Oops, we must be out of sync. */
-    PRINTF("RF: bad sync\n");
+    LOG_ERR("RF: bad sync\n");
 
     CC2538_RF_CSP_ISFLUSHRX();
     return 0;
   }
 
   if(len <= CC2538_RF_MIN_PACKET_LEN) {
-    PRINTF("RF: too short\n");
+    LOG_ERR("RF: too short\n");
 
     CC2538_RF_CSP_ISFLUSHRX();
     return 0;
   }
 
   if(len - CHECKSUM_LEN > bufsize) {
-    PRINTF("RF: too long\n");
+    LOG_ERR("RF: too long\n");
 
     CC2538_RF_CSP_ISFLUSHRX();
     return 0;
   }
 
   /* If we reach here, chances are the FIFO is holding a valid frame */
-  PRINTF("RF: read (0x%02x bytes) = ", len);
+  LOG_INFO("read (0x%02x bytes) = ", len);
   len -= CHECKSUM_LEN;
 
   /* Don't bother with uDMA for short frames (e.g. ACKs) */
   if(CC2538_RF_CONF_RX_USE_DMA && len > UDMA_RX_SIZE_THRESHOLD) {
-    PRINTF("<uDMA payload>");
+    LOG_INFO_("<uDMA payload>");
 
     /* Set the transfer destination's end address */
     udma_set_channel_dst(CC2538_RF_CONF_RX_DMA_CHAN,
@@ -738,7 +739,7 @@ read(void *buf, unsigned short bufsize)
   } else {
     for(i = 0; i < len; ++i) {
       ((unsigned char *)(buf))[i] = REG(RFCORE_SFR_RFDATA);
-      PRINTF("%02x", ((unsigned char *)(buf))[i]);
+      LOG_INFO_("%02x", ((unsigned char *)(buf))[i]);
     }
   }
 
@@ -746,14 +747,14 @@ read(void *buf, unsigned short bufsize)
   rssi = ((int8_t)REG(RFCORE_SFR_RFDATA)) - RSSI_OFFSET;
   crc_corr = REG(RFCORE_SFR_RFDATA);
 
-  PRINTF("%02x%02x\n", (uint8_t)rssi, crc_corr);
+  LOG_INFO_("%02x%02x\n", (uint8_t)rssi, crc_corr);
 
   /* MS bit CRC OK/Not OK, 7 LS Bits, Correlation value */
   if(crc_corr & CRC_BIT_MASK) {
     packetbuf_set_attr(PACKETBUF_ATTR_RSSI, rssi);
     packetbuf_set_attr(PACKETBUF_ATTR_LINK_QUALITY, crc_corr & LQI_BIT_MASK);
   } else {
-    PRINTF("RF: Bad CRC\n");
+    LOG_ERR("Bad CRC\n");
     CC2538_RF_CSP_ISFLUSHRX();
     return 0;
   }
@@ -775,7 +776,7 @@ read(void *buf, unsigned short bufsize)
 static int
 receiving_packet(void)
 {
-  PRINTF("RF: Receiving\n");
+  LOG_INFO("Receiving\n");
 
   /*
    * SFD high while transmitting and receiving.
@@ -791,7 +792,7 @@ receiving_packet(void)
 static int
 pending_packet(void)
 {
-  PRINTF("RF: Pending\n");
+  LOG_INFO("Pending\n");
 
   return REG(RFCORE_XREG_FSMSTAT1) & RFCORE_XREG_FSMSTAT1_FIFOP;
 }
@@ -862,6 +863,21 @@ get_value(radio_param_t param, radio_value_t *value)
   case RADIO_CONST_TXPOWER_MAX:
     *value = OUTPUT_POWER_MAX;
     return RADIO_RESULT_OK;
+  case RADIO_CONST_PHY_OVERHEAD:
+    *value = (radio_value_t)3; /* 1 len byte, 2 bytes CRC */
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_BYTE_AIR_TIME:
+    *value = (radio_value_t)32; /* 250kbps data rate. One byte = 32us.*/
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_DELAY_BEFORE_TX:
+    *value = (radio_value_t)CC2538_DELAY_BEFORE_TX;
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_DELAY_BEFORE_RX:
+    *value = (radio_value_t)CC2538_DELAY_BEFORE_RX;
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_DELAY_BEFORE_DETECT:
+    *value = (radio_value_t)CC2538_DELAY_BEFORE_DETECT;
+    return RADIO_RESULT_OK;
   default:
     return RADIO_RESULT_NOT_SUPPORTED;
   }
@@ -886,9 +902,7 @@ set_value(radio_param_t param, radio_value_t value)
        value > CC2538_RF_CHANNEL_MAX) {
       return RADIO_RESULT_INVALID_VALUE;
     }
-    if(set_channel(value) == CC2538_RF_CHANNEL_SET_ERROR) {
-      return RADIO_RESULT_ERROR;
-    }
+    set_channel(value);
     return RADIO_RESULT_OK;
   case RADIO_PARAM_PAN_ID:
     set_pan_id(value & 0xffff);
@@ -924,6 +938,9 @@ set_value(radio_param_t param, radio_value_t value)
   case RADIO_PARAM_CCA_THRESHOLD:
     set_cca_threshold(value);
     return RADIO_RESULT_OK;
+  case RADIO_PARAM_SHR_SEARCH:
+    set_shr_search(value);
+    return RADIO_RESULT_OK;
   default:
     return RADIO_RESULT_NOT_SUPPORTED;
   }
@@ -956,6 +973,16 @@ get_object(radio_param_t param, void *dest, size_t size)
     return RADIO_RESULT_OK;
   }
 
+#if MAC_CONF_WITH_TSCH
+  if(param == RADIO_CONST_TSCH_TIMING) {
+    if(size != sizeof(uint16_t *) || !dest) {
+      return RADIO_RESULT_INVALID_VALUE;
+    }
+    *(const uint16_t **)dest = tsch_timeslot_timing_us_10000;
+    return RADIO_RESULT_OK;
+  }
+#endif /* MAC_CONF_WITH_TSCH */
+
   return RADIO_RESULT_NOT_SUPPORTED;
 }
 /*---------------------------------------------------------------------------*/
@@ -1085,7 +1112,7 @@ cc2538_rf_rx_tx_isr(void)
 void
 cc2538_rf_err_isr(void)
 {
-  PRINTF("RF Error: 0x%08lx\n", REG(RFCORE_SFR_RFERRF));
+  LOG_ERR("Error 0x%08lx occurred\n", REG(RFCORE_SFR_RFERRF));
 
   /* If the error is not an RX FIFO overflow, set a flag */
   if(REG(RFCORE_SFR_RFERRF) != RFCORE_SFR_RFERRF_RXOVERF) {
@@ -1097,10 +1124,5 @@ cc2538_rf_err_isr(void)
   process_poll(&cc2538_rf_process);
 }
 /*---------------------------------------------------------------------------*/
-void
-cc2538_rf_set_promiscous_mode(char p)
-{
-  set_frame_filtering(p);
-}
-/*---------------------------------------------------------------------------*/
+
 /** @} */

arch/cpu/cc2538/dev/cc2538-rf.h

@@ -56,7 +56,6 @@
 #define CC2538_RF_CHANNEL_MIN            11
 #define CC2538_RF_CHANNEL_MAX            26
 #define CC2538_RF_CHANNEL_SPACING         5
-#define CC2538_RF_CHANNEL_SET_ERROR      -1
 #define CC2538_RF_MAX_PACKET_LEN        127
 #define CC2538_RF_MIN_PACKET_LEN          4
 #define CC2538_RF_CCA_CLEAR               1
@@ -74,12 +73,6 @@
 #define CC2538_RF_CCA_THRES CC2538_RF_CCA_THRES_USER_GUIDE
 #endif /* CC2538_RF_CONF_CCA_THRES */
 
-#ifdef CC2538_RF_CONF_CHANNEL
-#define CC2538_RF_CHANNEL CC2538_RF_CONF_CHANNEL
-#else
-#define CC2538_RF_CHANNEL 18
-#endif /* CC2538_RF_CONF_CHANNEL */
-
 #ifdef CC2538_RF_CONF_AUTOACK
 #define CC2538_RF_AUTOACK CC2538_RF_CONF_AUTOACK
 #else
@@ -119,7 +112,6 @@
  */
 #define CC2538_RF_CSP_ISFLUSHRX()  do { \
   REG(RFCORE_SFR_RFST) = CC2538_RF_CSP_OP_ISFLUSHRX; \
-  REG(RFCORE_SFR_RFST) = CC2538_RF_CSP_OP_ISFLUSHRX; \
 } while(0)
 
 /**
@@ -127,7 +119,6 @@
  */
 #define CC2538_RF_CSP_ISFLUSHTX()  do { \
   REG(RFCORE_SFR_RFST) = CC2538_RF_CSP_OP_ISFLUSHTX; \
-  REG(RFCORE_SFR_RFST) = CC2538_RF_CSP_OP_ISFLUSHTX; \
 } while(0)
 /*---------------------------------------------------------------------------*/
 /** The NETSTACK data structure for the cc2538 RF driver */
@@ -144,16 +135,6 @@ extern const struct radio_driver cc2538_rf_driver;
  */
 void cc2538_rf_set_addr(uint16_t pan);
 
-/**
- * \brief Turn promiscous mode on or off
- * \param p If promiscous mode should be on (1) or off (0)
- *
- * This function turns promiscous mode on or off. In promiscous mode,
- * every received frame is returned from the RF core. In
- * non-promiscous mode, only broadcast frames or frames with our
- * address as the receive address are returned from the RF core.
- */
-void cc2538_rf_set_promiscous_mode(char p);
 /*---------------------------------------------------------------------------*/
 #endif /* CC2538_RF_H__ */
 

arch/cpu/cc2538/dev/gpio-hal-arch.h

@@ -56,6 +56,8 @@
 #define PIN_TO_NUM(pin) (pin % 8)
 #define PIN_TO_PORT_BASE(pin) GPIO_PORT_TO_BASE(PIN_TO_PORT(pin))
 /*---------------------------------------------------------------------------*/
+#define gpio_hal_arch_init() do { /* Do nothing */ } while(0)
+
 #define gpio_hal_arch_interrupt_enable(p) do { \
   GPIO_ENABLE_INTERRUPT(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \
   NVIC_EnableIRQ(PIN_TO_PORT(p)); \

arch/cpu/cc2538/dev/spi-arch.c

@@ -107,7 +107,7 @@ static const spi_regs_t spi_regs[SSI_INSTANCE_COUNT] = {
 
 typedef struct spi_locks_s {
   mutex_t lock;
-  spi_device_t *owner;
+  const spi_device_t *owner;
 } spi_locks_t;
 
 /* One lock per SPI controller */
@@ -115,40 +115,40 @@ spi_locks_t board_spi_locks_spi[SPI_CONTROLLER_COUNT] = { { MUTEX_STATUS_UNLOCKE
 
 /*---------------------------------------------------------------------------*/
 static void
-spix_wait_tx_ready(spi_device_t *dev)
+spix_wait_tx_ready(const spi_device_t *dev)
 {
   /* Infinite loop until SR_TNF - Transmit FIFO Not Full */
   while(!(REG(spi_regs[dev->spi_controller].base + SSI_SR) & SSI_SR_TNF));
 }
 /*---------------------------------------------------------------------------*/
 static int
-spix_read_buf(spi_device_t *dev)
+spix_read_buf(const spi_device_t *dev)
 {
   return REG(spi_regs[dev->spi_controller].base + SSI_DR);
 }
 /*---------------------------------------------------------------------------*/
 static void
-spix_write_buf(spi_device_t *dev, int data)
+spix_write_buf(const spi_device_t *dev, int data)
 {
   REG(spi_regs[dev->spi_controller].base + SSI_DR) = data;
 }
 /*---------------------------------------------------------------------------*/
 static void
-spix_wait_eotx(spi_device_t *dev)
+spix_wait_eotx(const spi_device_t *dev)
 {
   /* wait until not busy */
   while(REG(spi_regs[dev->spi_controller].base + SSI_SR) & SSI_SR_BSY);
 }
 /*---------------------------------------------------------------------------*/
 static void
-spix_wait_eorx(spi_device_t *dev)
+spix_wait_eorx(const spi_device_t *dev)
 {
   /* wait as long as receive is empty */
   while(!(REG(spi_regs[dev->spi_controller].base + SSI_SR) & SSI_SR_RNE));
 }
 /*---------------------------------------------------------------------------*/
 bool
-spi_arch_has_lock(spi_device_t *dev)
+spi_arch_has_lock(const spi_device_t *dev)
 {
   if(board_spi_locks_spi[dev->spi_controller].owner == dev) {
     return true;
@@ -158,7 +158,7 @@ spi_arch_has_lock(spi_device_t *dev)
 }
 /*---------------------------------------------------------------------------*/
 bool
-spi_arch_is_bus_locked(spi_device_t *dev)
+spi_arch_is_bus_locked(const spi_device_t *dev)
 {
   if(board_spi_locks_spi[dev->spi_controller].lock == MUTEX_STATUS_LOCKED) {
     return true;
@@ -168,7 +168,7 @@ spi_arch_is_bus_locked(spi_device_t *dev)
 }
 /*---------------------------------------------------------------------------*/
 spi_status_t
-spi_arch_lock_and_open(spi_device_t *dev)
+spi_arch_lock_and_open(const spi_device_t *dev)
 {
   const spi_regs_t *regs;
   uint32_t scr;
@@ -265,7 +265,7 @@ spi_arch_lock_and_open(spi_device_t *dev)
 }
 /*---------------------------------------------------------------------------*/
 spi_status_t
-spi_arch_close_and_unlock(spi_device_t *dev)
+spi_arch_close_and_unlock(const spi_device_t *dev)
 {
   if(!spi_arch_has_lock(dev)) {
     return SPI_DEV_STATUS_BUS_NOT_OWNED;
@@ -281,30 +281,9 @@ spi_arch_close_and_unlock(spi_device_t *dev)
   return SPI_DEV_STATUS_OK;
 }
 /*---------------------------------------------------------------------------*/
-spi_status_t
-spi_arch_select(spi_device_t *dev)
-{
-
-  if(!spi_arch_has_lock(dev)) {
-    return SPI_DEV_STATUS_BUS_NOT_OWNED;
-  }
-
-  SPIX_CS_CLR(PIN_TO_PORT(dev->pin_spi_cs), PIN_TO_NUM(dev->pin_spi_cs));
-
-  return SPI_DEV_STATUS_OK;
-}
-/*---------------------------------------------------------------------------*/
-spi_status_t
-spi_arch_deselect(spi_device_t *dev)
-{
-  SPIX_CS_SET(PIN_TO_PORT(dev->pin_spi_cs), PIN_TO_NUM(dev->pin_spi_cs));
-
-  return SPI_DEV_STATUS_OK;
-}
-/*---------------------------------------------------------------------------*/
 /* Assumes that checking dev and bus is not NULL before calling this */
 spi_status_t
-spi_arch_transfer(spi_device_t *dev,
+spi_arch_transfer(const spi_device_t *dev,
                   const uint8_t *write_buf, int wlen,
                   uint8_t *inbuf, int rlen, int ignore_len)
 {

arch/cpu/cc2538/ieee-addr.c

@@ -70,11 +70,8 @@ ieee_addr_cpy_to(uint8_t *dst, uint8_t len)
     if(((uint8_t *)IEEE_ADDR_LOCATION)[3] == oui_ti[0]
        && ((uint8_t *)IEEE_ADDR_LOCATION)[2] == oui_ti[1]
        && ((uint8_t *)IEEE_ADDR_LOCATION)[1] == oui_ti[2]) {
-      for(i = 0; i < len / 2; i++) {
-        dst[i] = ((uint8_t *)IEEE_ADDR_LOCATION)[len / 2 - 1 - i];
-      }
-      for(i = 0; i < len / 2; i++) {
-        dst[i + len / 2] = ((uint8_t *)IEEE_ADDR_LOCATION)[len - 1 - i];
+      for(i = 0; i < len; i++) {
+        dst[len - i - 1] = ((uint8_t *)IEEE_ADDR_LOCATION)[i < 4 ? i + 4 : i - 4];
       }
     } else {
       for(i = 0; i < len; i++) {

arch/cpu/cc26xx-cc13xx/Makefile.cc13xx

@@ -1,7 +1,7 @@
 TI_XXWARE_PATH = lib/cc13xxware
 
-CONTIKI_CPU_SOURCEFILES += smartrf-settings.c prop-mode.c prop-mode-tx-power.c
+CONTIKI_CPU_SOURCEFILES += smartrf-settings.c prop-mode.c prop-mode-tx-power.c cc13xx-50kbps-tsch.c
 
-CFLAGS += -DCPU_FAMILY_CC13XX=1
+CFLAGS += -DCPU_FAMILY_CC13X0=1 -DCPU_FAMILY_CC13XX=1
 
 include $(CONTIKI_CPU)/Makefile.cc26xx-cc13xx

arch/cpu/cc26xx-cc13xx/Makefile.cc26x0r2f

@@ -0,0 +1,5 @@
+TI_XXWARE_PATH = lib/cc2640r2-sdk
+
+CFLAGS += -DCPU_FAMILY_CC26X0R2=1 -DCPU_FAMILY_CC26XXR2=1
+
+include $(CONTIKI_CPU)/Makefile.cc26xx-cc13xx

arch/cpu/cc26xx-cc13xx/Makefile.cc26xx

@@ -1,3 +1,5 @@
 TI_XXWARE_PATH = lib/cc26xxware
 
+CFLAGS += -DCPU_FAMILY_CC26X0=1 -DCPU_FAMILY_CC26XX=1
+
 include $(CONTIKI_CPU)/Makefile.cc26xx-cc13xx

arch/cpu/cc26xx-cc13xx/Makefile.cc26xx-cc13xx

@@ -1,7 +1,14 @@
 CPU_ABS_PATH       = arch/cpu/cc26xx-cc13xx
 TI_XXWARE = $(CONTIKI_CPU)/$(TI_XXWARE_PATH)
 
-### cc26xxware sources under driverlib will be added to the MODULES list
+ifeq (,$(wildcard $(TI_XXWARE)/*))
+    $(warning $(TI_XXWARE) does not exist or is empty.)
+    $(warning Did you run 'git submodule update --init' ?)
+    $(error "")
+endif
+
+### cc26xxware / cc26x0r2fware sources under driverlib will be added to the
+### MODULES list
 TI_XXWARE_SRC = $(CPU_ABS_PATH)/$(TI_XXWARE_PATH)/driverlib
 
 ### The directory with startup sources will be added to the CONTIKI_CPU_DIRS
@@ -38,8 +45,6 @@ CONTIKI_CPU_SOURCEFILES += ble-cc2650.c ble-hal-cc26xx.c ble-addr.c rf-ble-cmd.c
 CONTIKI_CPU_SOURCEFILES += random.c soc-trng.c int-master.c
 CONTIKI_CPU_SOURCEFILES += spi-arch.c
 
-MODULES += os/lib/dbg-io
-
 CONTIKI_SOURCEFILES += $(CONTIKI_CPU_SOURCEFILES)
 
 CPU_START_SOURCEFILES += fault-handlers.c $(TI_XXWARE_STARTUP_SRCS)
@@ -76,8 +81,10 @@ STACK_SIZE = 0
 	@$(SIZE) -A $< | egrep "data|bss" | awk '{s+=$$2} END {s=s+$(STACK_SIZE); f=$(RAM_SIZE)-s; printf "[RAM]   used %6d, free %6d\n",s,f;}'
 	@$(SIZE) -A $< | egrep "text|isr_vector" | awk '{s+=$$2} END {f=$(FLASH_SIZE)-s; printf "[Flash] used %6d, free %6d\n",s,f;}'
 
+include $(CONTIKI)/arch/cpu/arm/cortex-m/cm3/Makefile.cm3
+
 ifeq ($(BOARD_SUPPORTS_BSL),1)
-%.upload: %.bin
+%.upload: $(OUT_BIN)
 ifeq ($(wildcard $(BSL)), )
 	@echo "ERROR: Could not find the cc2538-bsl script. Did you run 'git submodule update --init' ?"
 else
@@ -88,21 +95,5 @@ else
 	@echo "This board cannot be programmed through the ROM bootloader and therefore does not support the .upload target."
 endif
 
-# Check if we are running under Windows
-ifeq ($(HOST_OS),Windows)
-  SERIALDUMP ?= $(CONTIKI)/tools/sky/serialdump-windows
-else
-ifeq ($(HOST_OS),Darwin)
-  SERIALDUMP ?= $(CONTIKI)/tools/sky/serialdump-macos
-else
-  # Else assume Linux
-  SERIALDUMP ?= $(CONTIKI)/tools/sky/serialdump-linux
-endif
-endif
-
-UART_BAUDRATE = 115200
-
-login:
-	$(SERIALDUMP) -b$(UART_BAUDRATE) $(PORT)
-
-include $(CONTIKI)/arch/cpu/arm/cortex-m/cm3/Makefile.cm3
+### For the login etc targets
+BAUDRATE = 115200

arch/cpu/cc26xx-cc13xx/cc13xx-cc26xx-conf.h

@@ -54,14 +54,6 @@
 #define CC2650_FAST_RADIO_STARTUP               (MAC_CONF_WITH_TSCH)
 #endif
 
-#ifdef RF_CHANNEL
-#define RF_CORE_CONF_CHANNEL             RF_CHANNEL
-#endif
-
-#ifndef RF_CORE_CONF_CHANNEL
-#define RF_CORE_CONF_CHANNEL                     25
-#endif
-
 /* Number of Prop Mode RX buffers */
 #ifndef PROP_MODE_CONF_RX_BUF_CNT
 #define PROP_MODE_CONF_RX_BUF_CNT        4
@@ -72,22 +64,33 @@
  * project has specified otherwise. Depending on the final mode, determine a
  * default channel (again, if unspecified) and configure RDC params
  */
-#if CPU_FAMILY_CC13XX
+#if CPU_FAMILY_CC13X0
 #ifndef CC13XX_CONF_PROP_MODE
 #define CC13XX_CONF_PROP_MODE 1
 #endif /* CC13XX_CONF_PROP_MODE */
-#endif /* CPU_FAMILY_CC13XX */
+#endif /* CPU_FAMILY_CC13X0 */
 
 #if CC13XX_CONF_PROP_MODE
+#ifndef NETSTACK_CONF_RADIO
 #define NETSTACK_CONF_RADIO        prop_mode_driver
+#endif /* NETSTACK_CONF_RADIO */
 
-#ifndef RF_CORE_CONF_CHANNEL
-#define RF_CORE_CONF_CHANNEL                      0
-#endif
+/* Channels count from 0 upwards in IEEE 802.15.4g */
+#ifndef IEEE802154_CONF_DEFAULT_CHANNEL
+#define IEEE802154_CONF_DEFAULT_CHANNEL                      0
+#endif /* IEEE802154_CONF_DEFAULT_CHANNEL */
 
+#ifndef CSMA_CONF_ACK_WAIT_TIME
 #define CSMA_CONF_ACK_WAIT_TIME                (RTIMER_SECOND / 400)
+#endif /* CSMA_CONF_ACK_WAIT_TIME */
+
+#ifndef CSMA_CONF_AFTER_ACK_DETECTED_WAIT_TIME
 #define CSMA_CONF_AFTER_ACK_DETECTED_WAIT_TIME (RTIMER_SECOND / 1000)
+#endif /* CSMA_CONF_AFTER_ACK_DETECTED_WAIT_TIME */
+
+#ifndef CSMA_CONF_SEND_SOFT_ACK
 #define CSMA_CONF_SEND_SOFT_ACK              1
+#endif /* CSMA_CONF_SEND_SOFT_ACK */
 
 #else /* CC13XX_CONF_PROP_MODE */
 #ifndef NETSTACK_CONF_RADIO
@@ -196,8 +199,14 @@
  * the chip to enter bootloader mode.
  * @{
  */
-#ifndef ROM_BOOTLOADER_ENABLE
-#define ROM_BOOTLOADER_ENABLE              0
+
+/* Backward compatibility */
+#ifdef ROM_BOOTLOADER_ENABLE
+#define CCXXWARE_CONF_ROM_BOOTLOADER_ENABLE ROM_BOOTLOADER_ENABLE
+#endif
+
+#ifndef CCXXWARE_CONF_ROM_BOOTLOADER_ENABLE
+#define CCXXWARE_CONF_ROM_BOOTLOADER_ENABLE              1
 #endif
 /** @} */
 /*---------------------------------------------------------------------------*/

arch/cpu/cc26xx-cc13xx/cc13xx-cc26xx-def.h

@@ -36,8 +36,43 @@
 /*---------------------------------------------------------------------------*/
 /* TSCH related defines */
 
+/* 2 bytes header, 4 bytes CRC */
+#define CC13XX_RADIO_PHY_OVERHEAD 6
+/* 3 bytes preamble, 3 bytes sync */
+#define CC13XX_RADIO_PHY_HEADER_LEN 6
+/* The default data rate is 50 kbps */
+#define CC13XX_RADIO_BIT_RATE 50000
+
+/* 1 len byte, 2 bytes CRC */
+#define CC26XX_RADIO_PHY_OVERHEAD     3
+/* 4 bytes preamble, 1 byte sync */
+#define CC26XX_RADIO_PHY_HEADER_LEN   5
+/* The fixed data rate is 250 kbps */
+#define CC26XX_RADIO_BIT_RATE  250000
+
+#if CPU_FAMILY_CC13XX
+#define RADIO_PHY_HEADER_LEN CC13XX_RADIO_PHY_HEADER_LEN
+#define RADIO_PHY_OVERHEAD   CC13XX_RADIO_PHY_OVERHEAD
+#define RADIO_BIT_RATE       CC13XX_RADIO_BIT_RATE
+
+/* The TSCH default slot length of 10ms is too short, use custom one instead */
+#ifndef TSCH_CONF_DEFAULT_TIMESLOT_TIMING
+#define TSCH_CONF_DEFAULT_TIMESLOT_TIMING tsch_timing_cc13xx_50kbps
+#endif /* TSCH_CONF_DEFAULT_TIMESLOT_TIMING */
+
+/* Symbol for the custom TSCH timeslot timing template */
+#define TSCH_CONF_ARCH_HDR_PATH "rf-core/cc13xx-50kbps-tsch.h"
+
+#else
+#define RADIO_PHY_HEADER_LEN CC26XX_RADIO_PHY_HEADER_LEN
+#define RADIO_PHY_OVERHEAD   CC26XX_RADIO_PHY_OVERHEAD
+#define RADIO_BIT_RATE       CC26XX_RADIO_BIT_RATE
+#endif
+
+#define RADIO_BYTE_AIR_TIME  (1000000 / (RADIO_BIT_RATE / 8))
+
 /* Delay between GO signal and SFD */
-#define RADIO_DELAY_BEFORE_TX ((unsigned)US_TO_RTIMERTICKS(81))
+#define RADIO_DELAY_BEFORE_TX ((unsigned)US_TO_RTIMERTICKS(RADIO_PHY_HEADER_LEN * RADIO_BYTE_AIR_TIME))
 /* Delay between GO signal and start listening.
  * This value is so small because the radio is constantly on within each timeslot. */
 #define RADIO_DELAY_BEFORE_RX ((unsigned)US_TO_RTIMERTICKS(15))
@@ -52,9 +87,6 @@
 #define RADIO_TO_RTIMER(X)   ((uint32_t)(((uint64_t)(X) * (RTIMER_SECOND / 256)) / (RADIO_TIMER_SECOND / 256)))
 #define USEC_TO_RADIO(X)     ((X) * 4)
 
-/* The PHY header (preamble + SFD, 4+1 bytes) duration is equivalent to 10 symbols */
-#define RADIO_IEEE_802154_PHY_HEADER_DURATION_USEC 160
-
 /* Do not turn off TSCH within a timeslot: not enough time */
 #define TSCH_CONF_RADIO_ON_DURING_TIMESLOT 1
 
@@ -85,6 +117,11 @@
 #define TSCH_CONF_CHANNEL_SCAN_DURATION (CLOCK_SECOND / 10)
 #endif
 
+/* Increase this from the default 100 to improve TSCH association speed on this platform */
+#ifndef TSCH_CONF_ASSOCIATION_POLL_FREQUENCY
+#define TSCH_CONF_ASSOCIATION_POLL_FREQUENCY 1000
+#endif
+
 /* Slightly reduce the TSCH guard time (from 2200 usec to 1800 usec) to make sure
  * the CC26xx radio has sufficient time to start up. */
 #ifndef TSCH_CONF_RX_WAIT

arch/cpu/cc26xx-cc13xx/cc26xx.ld

@@ -76,6 +76,7 @@ SECTIONS
         *(.data*)
         _edata = .;
     } > SRAM AT > FLASH
+    _ldata = LOADADDR(.data);
 
     .ARM.exidx :
     {
@@ -95,6 +96,8 @@ SECTIONS
     /* These symbols are used by the stack check library. */
     _stack = .;
     _stack_origin = ORIGIN(SRAM) + LENGTH(SRAM);
+    _heap = _stack;
+    _eheap = _stack_origin;
 
     .ccfg :
     {

arch/cpu/cc26xx-cc13xx/ccxxware-conf.h

@@ -68,6 +68,26 @@
 #define SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE          0x00
 #endif
 /** @} */
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief ROM bootloader configuration
+ *
+ * Those values are not meant to be modified by the user
+ * @{
+ */
+#if CCXXWARE_CONF_ROM_BOOTLOADER_ENABLE
+#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE      0xC5
+#define SET_CCFG_BL_CONFIG_BL_LEVEL               CCXXWARE_CONF_BL_LEVEL
+#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER          CCXXWARE_CONF_BL_PIN_NUMBER
+#define SET_CCFG_BL_CONFIG_BL_ENABLE              0xC5
+#else
+#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE      0x00
+#define SET_CCFG_BL_CONFIG_BL_LEVEL               0x01
+#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER          IOID_UNUSED
+#define SET_CCFG_BL_CONFIG_BL_ENABLE              0xFF
+#endif
+/** @} */
+/*---------------------------------------------------------------------------*/
 #endif /* CCXXWARE_CONF_H_ */
 /*---------------------------------------------------------------------------*/
 /**

arch/cpu/cc26xx-cc13xx/dev/gpio-hal-arch.c

@@ -39,7 +39,6 @@
 /*---------------------------------------------------------------------------*/
 #include "contiki.h"
 #include "ti-lib.h"
-#include "ti-lib-rom.h"
 #include "dev/gpio-hal.h"
 
 #include <stdint.h>
@@ -53,7 +52,7 @@ gpio_hal_arch_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg)
   gpio_hal_pin_cfg_t tmp;
 
   /* Clear settings that we are about to change, keep everything else */
-  config = ti_lib_rom_ioc_port_configure_get(pin);
+  config = ti_lib_ioc_port_configure_get(pin);
   config &= ~CONFIG_MASK;
 
   tmp = cfg & GPIO_HAL_PIN_CFG_EDGE_BOTH;
@@ -83,7 +82,7 @@ gpio_hal_arch_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg)
     config |= IOC_INT_ENABLE;
   }
 
-  ti_lib_rom_ioc_port_configure_set(pin, IOC_PORT_GPIO, config);
+  ti_lib_ioc_port_configure_set(pin, IOC_PORT_GPIO, config);
 }
 /*---------------------------------------------------------------------------*/
 gpio_hal_pin_cfg_t
@@ -94,7 +93,7 @@ gpio_hal_arch_pin_cfg_get(gpio_hal_pin_t pin)
   uint32_t config;
 
   cfg = 0;
-  config = ti_lib_rom_ioc_port_configure_get(pin);
+  config = ti_lib_ioc_port_configure_get(pin);
 
   /* Pull */
   tmp = config & IOC_IOPULL_M;

arch/cpu/cc26xx-cc13xx/dev/gpio-hal-arch.h

@@ -49,15 +49,16 @@
 /*---------------------------------------------------------------------------*/
 #include "contiki.h"
 #include "ti-lib.h"
-#include "ti-lib-rom.h"
 
 #include <stdint.h>
 /*---------------------------------------------------------------------------*/
-#define gpio_hal_arch_interrupt_enable(p)  interrupt_enable(p)
-#define gpio_hal_arch_interrupt_disable(p) ti_lib_rom_ioc_int_disable(p)
+#define gpio_hal_arch_init()               do { /* Do nothing */ } while(0)
 
-#define gpio_hal_arch_pin_set_input(p)     ti_lib_rom_ioc_pin_type_gpio_input(p)
-#define gpio_hal_arch_pin_set_output(p)    ti_lib_rom_ioc_pin_type_gpio_output(p)
+#define gpio_hal_arch_interrupt_enable(p)  interrupt_enable(p)
+
+#define gpio_hal_arch_interrupt_disable(p) ti_lib_ioc_int_disable(p)
+#define gpio_hal_arch_pin_set_input(p)     ti_lib_ioc_pin_type_gpio_input(p)
+#define gpio_hal_arch_pin_set_output(p)    ti_lib_ioc_pin_type_gpio_output(p)
 
 #define gpio_hal_arch_set_pin(p)           ti_lib_gpio_set_dio(p)
 #define gpio_hal_arch_clear_pin(p)         ti_lib_gpio_clear_dio(p)
@@ -73,7 +74,7 @@ static inline void
 interrupt_enable(gpio_hal_pin_t pin)
 {
   ti_lib_gpio_clear_event_dio(pin);
-  ti_lib_rom_ioc_int_enable(pin);
+  ti_lib_ioc_int_enable(pin);
 }
 /*---------------------------------------------------------------------------*/
 #endif /* GPIO_HAL_ARCH_H_ */

arch/cpu/cc26xx-cc13xx/dev/gpio-interrupt.c

@@ -52,10 +52,10 @@ gpio_interrupt_isr(void)
   /* Read interrupt flags */
   pin_mask = (HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) & GPIO_DIO_ALL_MASK);
 
-  gpio_hal_event_handler(pin_mask);
-
   /* Clear the interrupt flags */
   HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) = pin_mask;
+
+  gpio_hal_event_handler(pin_mask);
 }
 /*---------------------------------------------------------------------------*/
 /** @} */

arch/cpu/cc26xx-cc13xx/dev/soc-rtc.c

@@ -99,7 +99,7 @@ soc_rtc_init(void)
   ti_lib_aon_rtc_channel_enable(AON_RTC_CH1);
   ti_lib_aon_rtc_enable();
 
-  ti_lib_rom_int_enable(INT_AON_RTC_COMB);
+  ti_lib_int_enable(INT_AON_RTC_COMB);
 
   /* Re-enable interrupts */
   if(!interrupts_disabled) {

arch/cpu/cc26xx-cc13xx/dev/soc-trng.c

@@ -71,7 +71,7 @@ static void
 disable_number_ready_interrupt(void)
 {
   ti_lib_trng_int_disable(TRNG_NUMBER_READY);
-  ti_lib_rom_int_disable(INT_TRNG_IRQ);
+  ti_lib_int_disable(INT_TRNG_IRQ);
 }
 /*---------------------------------------------------------------------------*/
 static void
@@ -79,14 +79,14 @@ enable_number_ready_interrupt(void)
 {
   ti_lib_trng_int_clear(TRNG_NUMBER_READY);
   ti_lib_trng_int_enable(TRNG_NUMBER_READY);
-  ti_lib_rom_int_enable(INT_TRNG_IRQ);
+  ti_lib_int_enable(INT_TRNG_IRQ);
 }
 /*---------------------------------------------------------------------------*/
 static bool
 accessible(void)
 {
   /* First, check the PD */
-  if(ti_lib_rom_prcm_power_domain_status(PRCM_DOMAIN_PERIPH)
+  if(ti_lib_prcm_power_domain_status(PRCM_DOMAIN_PERIPH)
      != PRCM_DOMAIN_POWER_ON) {
     return false;
   }
@@ -104,12 +104,12 @@ static void
 power_up(void)
 {
   /* First, make sure the PERIPH PD is on */
-  ti_lib_rom_prcm_power_domain_on(PRCM_DOMAIN_PERIPH);
-  while((ti_lib_rom_prcm_power_domain_status(PRCM_DOMAIN_PERIPH)
+  ti_lib_prcm_power_domain_on(PRCM_DOMAIN_PERIPH);
+  while((ti_lib_prcm_power_domain_status(PRCM_DOMAIN_PERIPH)
          != PRCM_DOMAIN_POWER_ON));
 
   /* Enable clock in active mode */
-  ti_lib_rom_prcm_peripheral_run_enable(PRCM_PERIPH_TRNG);
+  ti_lib_prcm_peripheral_run_enable(PRCM_PERIPH_TRNG);
   ti_lib_prcm_load_set();
   while(!ti_lib_prcm_load_get());
 }
@@ -136,7 +136,7 @@ static uint64_t
 read_number(void)
 {
   uint64_t ran = (uint64_t)HWREG(TRNG_BASE + TRNG_O_OUT1) << 32;
-  ran += ti_lib_rom_trng_number_get(TRNG_LOW_WORD);
+  ran += ti_lib_trng_number_get(TRNG_LOW_WORD);
 
   return ran;
 }
@@ -237,7 +237,7 @@ soc_trng_rand_asynchronous(uint32_t samples, soc_trng_callback_t cb)
   ti_lib_trng_int_clear(TRNG_NUMBER_READY);
 
   /* Enable clock in sleep mode and register with LPM */
-  ti_lib_rom_prcm_peripheral_sleep_enable(PRCM_PERIPH_TRNG);
+  ti_lib_prcm_peripheral_sleep_enable(PRCM_PERIPH_TRNG);
   ti_lib_prcm_load_set();
   while(!ti_lib_prcm_load_get());
 
@@ -271,7 +271,7 @@ PROCESS_THREAD(soc_trng_process, ev, data)
     }
 
     /* Disable clock in sleep mode */
-    ti_lib_rom_prcm_peripheral_sleep_disable(PRCM_PERIPH_TRNG);
+    ti_lib_prcm_peripheral_sleep_disable(PRCM_PERIPH_TRNG);
     ti_lib_prcm_load_set();
     while(!ti_lib_prcm_load_get());
 

arch/cpu/cc26xx-cc13xx/dev/spi-arch.c

@@ -37,7 +37,7 @@
 
 typedef struct spi_locks_s {
   mutex_t lock;
-  spi_device_t *owner;
+  const spi_device_t *owner;
 } spi_locks_t;
 
 /* One lock per SPI controller */
@@ -68,7 +68,7 @@ static const board_spi_controller_t spi_controller[SPI_CONTROLLER_COUNT] = {
 };
 /*---------------------------------------------------------------------------*/
 bool
-spi_arch_has_lock(spi_device_t *dev)
+spi_arch_has_lock(const spi_device_t *dev)
 {
   if(board_spi_locks_spi[dev->spi_controller].owner == dev) {
     return true;
@@ -78,7 +78,7 @@ spi_arch_has_lock(spi_device_t *dev)
 }
 /*---------------------------------------------------------------------------*/
 bool
-spi_arch_is_bus_locked(spi_device_t *dev)
+spi_arch_is_bus_locked(const spi_device_t *dev)
 {
   if(board_spi_locks_spi[dev->spi_controller].lock == MUTEX_STATUS_LOCKED) {
     return true;
@@ -88,7 +88,7 @@ spi_arch_is_bus_locked(spi_device_t *dev)
 }
 /*---------------------------------------------------------------------------*/
 static uint32_t
-get_mode(spi_device_t *dev)
+get_mode(const spi_device_t *dev)
 {
   /* Select the correct SPI mode */
   if(dev->spi_pha == 0 && dev->spi_pol == 0) {
@@ -103,7 +103,7 @@ get_mode(spi_device_t *dev)
 }
 /*---------------------------------------------------------------------------*/
 spi_status_t
-spi_arch_lock_and_open(spi_device_t *dev)
+spi_arch_lock_and_open(const spi_device_t *dev)
 {
   uint32_t c;
 
@@ -123,17 +123,22 @@ spi_arch_lock_and_open(spi_device_t *dev)
          != PRCM_DOMAIN_POWER_ON)) ;
 
   /* Enable clock in active mode */
-  ti_lib_rom_prcm_peripheral_run_enable(spi_controller[dev->spi_controller].prcm_periph);
+  ti_lib_prcm_peripheral_run_enable(spi_controller[dev->spi_controller].prcm_periph);
   ti_lib_prcm_load_set();
   while(!ti_lib_prcm_load_get()) ;
 
   /* SPI configuration */
   ti_lib_ssi_int_disable(spi_controller[dev->spi_controller].ssi_base, SSI_RXOR | SSI_RXFF | SSI_RXTO | SSI_TXFF);
   ti_lib_ssi_int_clear(spi_controller[dev->spi_controller].ssi_base, SSI_RXOR | SSI_RXTO);
-  ti_lib_rom_ssi_config_set_exp_clk(spi_controller[dev->spi_controller].ssi_base, ti_lib_sys_ctrl_clock_get(),
-                                    get_mode(dev), SSI_MODE_MASTER, dev->spi_bit_rate, 8);
-  ti_lib_rom_ioc_pin_type_ssi_master(spi_controller[dev->spi_controller].ssi_base, dev->pin_spi_miso,
-                                     dev->pin_spi_mosi, IOID_UNUSED, dev->pin_spi_sck);
+  
+  ti_lib_ssi_config_set_exp_clk(spi_controller[dev->spi_controller].ssi_base,
+                                ti_lib_sys_ctrl_clock_get(),
+                                get_mode(dev), SSI_MODE_MASTER,
+                                dev->spi_bit_rate, 8);
+  ti_lib_ioc_pin_type_ssi_master(spi_controller[dev->spi_controller].ssi_base,
+                                 dev->pin_spi_miso,
+                                 dev->pin_spi_mosi, IOID_UNUSED,
+                                 dev->pin_spi_sck);
 
   ti_lib_ssi_enable(spi_controller[dev->spi_controller].ssi_base);
 
@@ -144,14 +149,14 @@ spi_arch_lock_and_open(spi_device_t *dev)
 }
 /*---------------------------------------------------------------------------*/
 spi_status_t
-spi_arch_close_and_unlock(spi_device_t *dev)
+spi_arch_close_and_unlock(const spi_device_t *dev)
 {
   if(!spi_arch_has_lock(dev)) {
     return SPI_DEV_STATUS_BUS_NOT_OWNED;
   }
 
   /* Power down SSI */
-  ti_lib_rom_prcm_peripheral_run_disable(spi_controller[dev->spi_controller].prcm_periph);
+  ti_lib_prcm_peripheral_run_disable(spi_controller[dev->spi_controller].prcm_periph);
   ti_lib_prcm_load_set();
   while(!ti_lib_prcm_load_get()) ;
 
@@ -173,7 +178,7 @@ spi_arch_close_and_unlock(spi_device_t *dev)
 }
 /*---------------------------------------------------------------------------*/
 spi_status_t
-spi_arch_transfer(spi_device_t *dev,
+spi_arch_transfer(const spi_device_t *dev,
                   const uint8_t *write_buf, int wlen,
                   uint8_t *inbuf, int rlen, int ignore_len)
 {
@@ -205,33 +210,12 @@ spi_arch_transfer(spi_device_t *dev,
   for(i = 0; i < totlen; i++) {
     c = i < wlen ? write_buf[i] : 0;
     ti_lib_ssi_data_put(spi_controller[dev->spi_controller].ssi_base, (uint8_t)c);
-    ti_lib_rom_ssi_data_get(spi_controller[dev->spi_controller].ssi_base, &c);
+    ti_lib_ssi_data_get(spi_controller[dev->spi_controller].ssi_base, &c);
     if(i < rlen) {
       inbuf[i] = (uint8_t)c;
     }
   }
-
-  while(ti_lib_rom_ssi_data_get_non_blocking(spi_controller[dev->spi_controller].ssi_base, &c)) ;
-
+  while(ti_lib_ssi_data_get_non_blocking(spi_controller[dev->spi_controller].ssi_base, &c)) ;
   return SPI_DEV_STATUS_OK;
 }
 /*---------------------------------------------------------------------------*/
-spi_status_t
-spi_arch_select(spi_device_t *dev)
-{
-
-  if(!spi_arch_has_lock(dev)) {
-    return SPI_DEV_STATUS_BUS_NOT_OWNED;
-  }
-
-  ti_lib_gpio_clear_dio(dev->pin_spi_cs);
-
-  return SPI_DEV_STATUS_OK;
-}
-spi_status_t
-spi_arch_deselect(spi_device_t *dev)
-{
-  ti_lib_gpio_set_dio(dev->pin_spi_cs);
-
-  return SPI_DEV_STATUS_OK;
-}

arch/cpu/cc26xx-cc13xx/lib/cc2640r2-sdk

@@ -0,0 +1 @@
+Subproject commit 0c01cfd363fd421d43baaa52af551a4ce8bf9e2b

arch/cpu/cc26xx-cc13xx/lpm.c

@@ -162,7 +162,9 @@ lpm_shutdown(uint32_t wakeup_pin, uint32_t io_pull, uint32_t wake_on)
   ti_lib_aon_wuc_mcu_power_off_config(MCU_VIRT_PWOFF_DISABLE);
 
   /* Latch the IOs in the padring and enable I/O pad sleep mode */
-  ti_lib_pwr_ctrl_io_freeze_enable();
+  ti_lib_aon_ioc_freeze_enable();
+  HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_SLEEPCTL) = 0;
+  ti_lib_sys_ctrl_aon_sync();
 
   /* Turn off VIMS cache, CRAM and TRAM - possibly not required */
   ti_lib_prcm_cache_retention_disable();

arch/cpu/cc26xx-cc13xx/rf-core/ble-hal/ble-hal-cc26xx.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2017, Graz University of Technology
+ * Copyright (c) 2018, University of Bristol - http://www.bristol.ac.uk/
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,6 +35,7 @@
  *
  * \author
  *    Michael Spoerk <michael.spoerk@tugraz.at>
+ *    Jinyan BAI <onefreebjy@outlook.com>
  */
 /*---------------------------------------------------------------------------*/
 
@@ -63,6 +65,9 @@
 #include <string.h>
 
 #include "rf-core/ble-hal/rf-ble-cmd.h"
+#if RADIO_CONF_BLE5
+#include "rf_patches/rf_patch_cpe_bt5.h"
+#endif
 /*---------------------------------------------------------------------------*/
 #include "sys/log.h"
 #define LOG_MODULE "BLE-RADIO"
@@ -117,9 +122,15 @@ ticks_to_unit(rtimer_clock_t value, uint32_t unit)
   return (uint32_t)temp;
 }
 /*---------------------------------------------------------------------------*/
+#if RADIO_CONF_BLE5
+#define CMD_BUFFER_SIZE         28
+#define PARAM_BUFFER_SIZE       48
+#define OUTPUT_BUFFER_SIZE        24
+#else
 #define CMD_BUFFER_SIZE         24
 #define PARAM_BUFFER_SIZE       36
 #define OUTPUT_BUFFER_SIZE        24
+#endif
 /*---------------------------------------------------------------------------*/
 /* ADVERTISING data structures												 */
 #define ADV_RX_BUFFERS_OVERHEAD     8
@@ -358,12 +369,24 @@ on(void)
   oscillators_request_hf_xosc();
   if(!rf_core_is_accessible()) {
     /* boot the rf core */
-    if(rf_core_boot() != RF_CORE_CMD_OK) {
-      LOG_ERR("ble_controller_reset() could not boot rf-core\n");
-      return BLE_RESULT_ERROR;
-    }
 
-    rf_core_setup_interrupts(0);
+    /*    boot and apply Bluetooth 5 Patch    */
+    if(rf_core_power_up() != RF_CORE_CMD_OK) {
+      LOG_ERR("rf_core_boot: rf_core_power_up() failed\n");
+      rf_core_power_down();
+      return RF_CORE_CMD_ERROR;
+    }
+    
+#if RADIO_CONF_BLE5
+    /*  Apply Bluetooth 5 patch, if applicable  */
+    rf_patch_cpe_bt5();
+#endif
+    if(rf_core_start_rat() != RF_CORE_CMD_OK) {
+      LOG_ERR("rf_core_boot: rf_core_start_rat() failed\n");
+      rf_core_power_down();
+      return RF_CORE_CMD_ERROR;
+    }
+    rf_core_setup_interrupts();
     oscillators_switch_to_hf_xosc();
 
     if(rf_ble_cmd_setup_ble_mode() != RF_BLE_CMD_OK) {
@@ -845,7 +868,11 @@ connection_rx(ble_conn_param_t *param)
 
   while(RX_ENTRY_STATUS(param->rx_queue_current) == DATA_ENTRY_FINISHED) {
     rx_data = RX_ENTRY_DATA_PTR(param->rx_queue_current);
+#if RADIO_CONF_BLE5
+    len = RX_ENTRY_DATA_LENGTH(param->rx_queue_current) - 7 - 2;  /* last 9 bytes are status, timestamp, ... */
+#else
     len = RX_ENTRY_DATA_LENGTH(param->rx_queue_current) - 6 - 2;  /* last 8 bytes are status, timestamp, ... */
+#endif
     channel = (rx_data[len + 3] & 0x3F);
     frame_type = rx_data[0] & 0x03;
     more_data = (rx_data[0] & 0x10) >> 4;

arch/cpu/cc26xx-cc13xx/rf-core/ble-hal/rf-ble-cmd.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2017, Graz University of Technology
+ * Copyright (c) 2018, University of Bristol - http://www.bristol.ac.uk/
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -36,6 +37,7 @@
  *
  * \author
  *    Michael Spoerk <michael.spoerk@tugraz.at>
+ *    Jinyan BAI <onefreebjy@outlook.com>
  */
 /*---------------------------------------------------------------------------*/
 #include "contiki.h"
@@ -57,6 +59,62 @@ static uint16_t tx_power = 0x3161;                /*  0 dBm */
 /*static uint16_t tx_power = 0x0CCB;                / *  -15 dBm * / */
 /*---------------------------------------------------------------------------*/
 /* BLE overrides */
+#if RADIO_CONF_BLE5
+uint32_t ble_overrides_common[] =
+{
+  /* Rx: Set LNA IB trim value based on the selected defaultPhy.mainMode setting. (NOTE: The value 0x8 is a placeholder. The value to use should be set during run-time by radio driver function.) */
+  ADI_HALFREG_OVERRIDE(0,4,0xF,0x8),
+  /* Rx: Set LNA IB offset used for automatic software compensation to 0 */
+  (uint32_t)0x00008883,
+  /* Synth: Use 24 MHz crystal, enable extra PLL filtering */
+  (uint32_t)0x02010403,
+  /* Synth: Set fine top and bottom code to 127 and 0 */
+  HW_REG_OVERRIDE(0x4020, 0x7F00),
+  /* Synth: Configure faster calibration */
+  HW32_ARRAY_OVERRIDE(0x4004, 1),
+  /* Synth: Configure faster calibration */
+  (uint32_t)0x1C0C0618,
+  /* Synth: Configure faster calibration */
+  (uint32_t)0xC00401A1,
+  /* Synth: Configure faster calibration */
+  (uint32_t)0x21010101,
+  /* Synth: Configure faster calibration */
+  (uint32_t)0xC0040141,
+  /* Synth: Configure faster calibration */
+  (uint32_t)0x00214AD3,
+  /* Synth: Decrease synth programming time-out by 90 us (0x0298 RAT ticks = 166 us) */
+  (uint32_t)0x02980243,
+  /* Bluetooth 5: Set correct total clock accuracy for received AuxPtr assuming local sleep clock of 50 ppm */
+  (uint32_t)0x0E490823,
+  /* override_frontend_id.xml */
+  (uint32_t)0xFFFFFFFF,
+};
+
+uint32_t ble_overrides_1Mbps[] =
+{
+  /* Rx: Set LNA IB trim to normal trim value. (NOTE: The value 0x8 is a placeholder. The value to use should be set during run-time by radio driver function.) */
+  ADI_HALFREG_OVERRIDE(0,4,0xF,0x8),
+  /* Rx: Configure AGC to use gain table for improved performance */
+  HW_REG_OVERRIDE(0x6084, 0x05F8),
+  (uint32_t)0xFFFFFFFF,
+};
+
+uint32_t ble_overrides_2Mbps[] =
+{
+  /* Rx: Set LNA IB trim to normal trim value. (NOTE: The value 0x8 is a placeholder. The value to use should be set during run-time by radio driver function.) */
+  ADI_HALFREG_OVERRIDE(0,4,0xF,0x8),
+  (uint32_t)0xFFFFFFFF,
+};
+
+uint32_t ble_overrides_coded[] =
+{
+  /* Rx: Set LNA IB trim to 0xF (maximum) */
+  ADI_HALFREG_OVERRIDE(0,4,0xF,0xF),
+  /* Rx: Override AGC target gain to improve performance */
+  HW_REG_OVERRIDE(0x6088, 0x0018),
+  (uint32_t)0xFFFFFFFF,
+};
+#else
 static uint32_t ble_overrides[] = {
   0x00364038, /* Synth: Set RTRIM (POTAILRESTRIM) to 6 */
   0x000784A3, /* Synth: Set FREF = 3.43 MHz (24 MHz / 7) */
@@ -67,6 +125,7 @@ static uint32_t ble_overrides[] = {
   0x008F88B3, /* GPIO mode: https://e2e.ti.com/support/wireless_connectivity/proprietary_sub_1_ghz_simpliciti/f/156/t/488244?*/
   0xFFFFFFFF, /* End of override list */
 };
+#endif
 /*---------------------------------------------------------------------------*/
 unsigned short
 rf_ble_cmd_send(uint8_t *command)
@@ -97,14 +156,29 @@ rf_ble_cmd_wait(uint8_t *command)
 unsigned short
 rf_ble_cmd_setup_ble_mode(void)
 {
+#if RADIO_CONF_BLE5
+  rfc_CMD_BLE5_RADIO_SETUP_t cmd;
+  
+  /* Create radio setup command */
+  rf_core_init_radio_op((rfc_radioOp_t *)&cmd, sizeof(cmd), CMD_BLE5_RADIO_SETUP);
+  
+  cmd.startTrigger.bEnaCmd = 0;
+  cmd.defaultPhy.mainMode = 1;
+  cmd.defaultPhy.coding = 1;
+  cmd.pRegOverrideCommon = ble_overrides_common;
+  cmd.pRegOverride1Mbps = ble_overrides_1Mbps;
+  cmd.pRegOverride2Mbps = ble_overrides_2Mbps;
+  cmd.pRegOverrideCoded = ble_overrides_coded;
+#else
   rfc_CMD_RADIO_SETUP_t cmd;
 
   /* Create radio setup command */
   rf_core_init_radio_op((rfc_radioOp_t *)&cmd, sizeof(cmd), CMD_RADIO_SETUP);
 
-  cmd.txPower = tx_power;
-  cmd.pRegOverride = ble_overrides;
   cmd.mode = 0;
+  cmd.pRegOverride = ble_overrides;
+#endif
+  cmd.txPower = tx_power;
 
   /* Send Radio setup to RF Core */
   if(rf_ble_cmd_send((uint8_t *)&cmd) != RF_BLE_CMD_OK) {
@@ -116,14 +190,26 @@ rf_ble_cmd_setup_ble_mode(void)
 }
 /*---------------------------------------------------------------------------*/
 /* ADVERTISING functions                                                     */
+/*---------------------------------------------------------------------------*/
 void
 rf_ble_cmd_create_adv_cmd(uint8_t *command, uint8_t channel,
                           uint8_t *param, uint8_t *output)
 {
+#if RADIO_CONF_BLE5
+  rfc_CMD_BLE5_ADV_t *c = (rfc_CMD_BLE5_ADV_t *)command;
+  
+  memset(c, 0x00, sizeof(rfc_CMD_BLE5_ADV_t));
+  
+  c->commandNo = CMD_BLE5_ADV;
+  c->rangeDelay = 0;
+  
+  c->txPower = tx_power;
+#else
   rfc_CMD_BLE_ADV_t *c = (rfc_CMD_BLE_ADV_t *)command;
 
   memset(c, 0x00, sizeof(rfc_CMD_BLE_ADV_t));
   c->commandNo = CMD_BLE_ADV;
+#endif
   c->condition.rule = COND_NEVER;
   c->whitening.bOverride = 0;
   c->channel = channel;
@@ -162,12 +248,113 @@ rf_ble_cmd_create_adv_params(uint8_t *param, dataQueue_t *rx_queue,
   p->endTrigger.triggerType = TRIG_NEVER;
 }
 /*---------------------------------------------------------------------------*/
+/* INITIATOR functions                                                       */
+/*---------------------------------------------------------------------------*/
+void
+rf_ble_cmd_create_initiator_cmd(uint8_t *cmd, uint8_t channel, uint8_t *params,
+                                uint8_t *output, uint32_t start_time)
+{
+#if RADIO_CONF_BLE5
+  rfc_CMD_BLE5_INITIATOR_t *c = (rfc_CMD_BLE5_INITIATOR_t *)cmd;
+  
+  memset(c, 0x00, sizeof(rfc_CMD_BLE5_INITIATOR_t));
+  
+  c->commandNo = CMD_BLE5_INITIATOR;
+  c->condition.rule = COND_NEVER;
+  c->whitening.bOverride = 0;
+  c->channel = channel;
+  c->pParams = (rfc_ble5InitiatorPar_t *)params;
+  c->startTrigger.triggerType = TRIG_ABSTIME;
+  c->startTime = start_time;
+  c->pOutput = (rfc_ble5ScanInitOutput_t *)output;
+  
+  c->txPower = tx_power;
+  c->rangeDelay = 0;
+#else
+  rfc_CMD_BLE_INITIATOR_t *c = (rfc_CMD_BLE_INITIATOR_t *)cmd;
+  
+  memset(c, 0x00, sizeof(rfc_CMD_BLE_INITIATOR_t));
+  
+  c->commandNo = CMD_BLE_INITIATOR;
+  c->condition.rule = COND_NEVER;
+  c->whitening.bOverride = 0;
+  c->channel = channel;
+  c->pParams = (rfc_bleInitiatorPar_t *)params;
+  c->startTrigger.triggerType = TRIG_ABSTIME;
+  c->startTime = start_time;
+  c->pOutput = (rfc_bleInitiatorOutput_t *)output;
+#endif
+}
+/*---------------------------------------------------------------------------*/
+void
+rf_ble_cmd_create_initiator_params(uint8_t *param, dataQueue_t *rx_queue,
+                                   uint32_t initiator_time,
+                                   ble_addr_type_t own_addr_type, uint8_t *own_addr,
+                                   ble_addr_type_t peer_addr_type, uint8_t *peer_addr,
+                                   uint32_t connect_time, uint8_t *conn_req_data)
+{
+#if RADIO_CONF_BLE5
+  rfc_ble5InitiatorPar_t *p = (rfc_ble5InitiatorPar_t *)param;
+  p->backoffPar.bLastSucceeded = 0;
+  p->backoffPar.bLastFailed = 0;
+  p->maxWaitTimeForAuxCh = 0;
+  p->rxStartTime = 0;
+  p->rxListenTime = 0;
+#else
+  rfc_bleInitiatorPar_t *p = (rfc_bleInitiatorPar_t *)param;
+#endif
+  p->pRxQ = rx_queue;
+  p->rxConfig.bAutoFlushIgnored = 1;
+  p->rxConfig.bAutoFlushCrcErr = 0;
+  p->rxConfig.bAutoFlushEmpty = 1;
+  p->rxConfig.bIncludeLenByte = 1;
+  p->rxConfig.bIncludeCrc = 0;
+  p->rxConfig.bAppendRssi = 1;
+  p->rxConfig.bAppendStatus = 1;
+  p->rxConfig.bAppendTimestamp = 1;
+  
+  /*    p->initConfig.bUseWhiteList = 0; */
+  p->initConfig.bUseWhiteList = 1;
+  p->initConfig.bDynamicWinOffset = 0;
+  p->initConfig.deviceAddrType = own_addr_type;
+  p->initConfig.peerAddrType = peer_addr_type;
+  p->initConfig.bStrictLenFilter = 1;
+  
+  p->connectReqLen = 22;
+  p->pConnectReqData = conn_req_data;
+  p->pDeviceAddress = (uint16_t *)own_addr;
+  p->pWhiteList = (rfc_bleWhiteListEntry_t *)peer_addr;
+  p->connectTime = connect_time;
+  p->timeoutTrigger.triggerType = TRIG_REL_START;
+  p->timeoutTime = initiator_time;
+  p->endTrigger.triggerType = TRIG_NEVER;
+}
+/*---------------------------------------------------------------------------*/
 /* CONNECTION slave functions                                                */
 /*---------------------------------------------------------------------------*/
 void
 rf_ble_cmd_create_slave_cmd(uint8_t *cmd, uint8_t channel, uint8_t *params,
                             uint8_t *output, uint32_t start_time)
 {
+#if RADIO_CONF_BLE5
+  rfc_CMD_BLE5_SLAVE_t *c = (rfc_CMD_BLE5_SLAVE_t *)cmd;
+  
+  memset(c, 0x00, sizeof(rfc_CMD_BLE5_SLAVE_t));
+  
+  c->commandNo = CMD_BLE5_SLAVE;
+  c->condition.rule = COND_NEVER;
+  c->whitening.bOverride = 0;
+  c->channel = channel;
+  c->pParams = (rfc_ble5SlavePar_t *)params;
+  c->startTrigger.triggerType = TRIG_ABSTIME;
+  c->startTime = start_time;
+  c->pOutput = (rfc_bleMasterSlaveOutput_t *)output;
+  
+  c->phyMode.mainMode = 1;
+  c->phyMode.coding = 1;
+  c->txPower = tx_power;
+  c->rangeDelay = 0;
+#else
   rfc_CMD_BLE_SLAVE_t *c = (rfc_CMD_BLE_SLAVE_t *)cmd;
 
   memset(c, 0x00, sizeof(rfc_CMD_BLE_SLAVE_t));
@@ -181,6 +368,7 @@ rf_ble_cmd_create_slave_cmd(uint8_t *cmd, uint8_t channel, uint8_t *params,
   c->startTrigger.pastTrig = 0;
   c->startTime = start_time;
   c->pOutput = (rfc_bleMasterSlaveOutput_t *)output;
+#endif
 }
 /*---------------------------------------------------------------------------*/
 void
@@ -190,8 +378,13 @@ rf_ble_cmd_create_slave_params(uint8_t *params, dataQueue_t *rx_queue,
                                uint8_t crc_init_2, uint32_t win_size,
                                uint32_t window_widening, uint8_t first_packet)
 {
+#if RADIO_CONF_BLE5
+  rfc_ble5SlavePar_t *p = (rfc_ble5SlavePar_t *)params;
+  p->maxRxPktLen = 255;
+  p->maxLenLowRate = 0;
+#else
   rfc_bleSlavePar_t *p = (rfc_bleSlavePar_t *)params;
-
+#endif
   p->pRxQ = rx_queue;
   p->pTxQ = tx_queue;
   p->rxConfig.bAutoFlushIgnored = 1;
@@ -230,6 +423,91 @@ rf_ble_cmd_create_slave_params(uint8_t *params, dataQueue_t *rx_queue,
   p->endTrigger.triggerType = TRIG_NEVER;
 }
 /*---------------------------------------------------------------------------*/
+/* CONNECTION master functions                                               */
+/*---------------------------------------------------------------------------*/
+void
+rf_ble_cmd_create_master_cmd(uint8_t *cmd, uint8_t channel, uint8_t *params,
+                             uint8_t *output, uint32_t start_time)
+{
+#if RADIO_CONF_BLE5
+  rfc_CMD_BLE5_MASTER_t *c = (rfc_CMD_BLE5_MASTER_t *)cmd;
+  
+  memset(c, 0x00, sizeof(rfc_CMD_BLE5_MASTER_t));
+  
+  c->commandNo = CMD_BLE5_MASTER;
+  c->condition.rule = COND_NEVER;
+  c->whitening.bOverride = 0;
+  c->channel = channel;
+  c->pParams = (rfc_ble5MasterPar_t *)params;
+  c->startTrigger.triggerType = TRIG_ABSTIME;
+  c->startTime = start_time;
+  c->pOutput = (rfc_bleMasterSlaveOutput_t *)output;
+  
+  c->phyMode.mainMode = 1;
+  c->phyMode.coding = 1;
+  c->txPower = tx_power;
+  c->rangeDelay = 0;
+#else
+  rfc_CMD_BLE_MASTER_t *c = (rfc_CMD_BLE_MASTER_t *)cmd;
+  
+  memset(c, 0x00, sizeof(rfc_CMD_BLE_MASTER_t));
+  
+  c->commandNo = CMD_BLE_MASTER;
+  c->condition.rule = COND_NEVER;
+  c->whitening.bOverride = 0;
+  c->channel = channel;
+  c->pParams = (rfc_bleMasterPar_t *)params;
+  c->startTrigger.triggerType = TRIG_ABSTIME;
+  c->startTime = start_time;
+  c->pOutput = (rfc_bleMasterSlaveOutput_t *)output;
+#endif
+}
+/*---------------------------------------------------------------------------*/
+void
+rf_ble_cmd_create_master_params(uint8_t *params, dataQueue_t *rx_queue,
+                                dataQueue_t *tx_queue, uint32_t access_address,
+                                uint8_t crc_init_0, uint8_t crc_init_1,
+                                uint8_t crc_init_2, uint8_t first_packet)
+{
+#if RADIO_CONF_BLE5
+  rfc_ble5MasterPar_t *p = (rfc_ble5MasterPar_t *)params;
+  p->maxRxPktLen = 255;
+  p->maxLenLowRate = 0;
+#else
+  rfc_bleMasterPar_t *p = (rfc_bleMasterPar_t *)params;
+#endif
+  p->pRxQ = rx_queue;
+  p->pTxQ = tx_queue;
+  p->rxConfig.bAutoFlushIgnored = 1;
+  p->rxConfig.bAutoFlushCrcErr = 1;
+  p->rxConfig.bAutoFlushEmpty = 1;
+  p->rxConfig.bIncludeLenByte = 1;
+  p->rxConfig.bIncludeCrc = 0;
+  p->rxConfig.bAppendRssi = 1;
+  p->rxConfig.bAppendStatus = 1;
+  p->rxConfig.bAppendTimestamp = 1;
+  
+  if(first_packet) {
+    /* set parameters for first packet according to TI Technical Reference Manual */
+    p->seqStat.lastRxSn = 1;
+    p->seqStat.lastTxSn = 1;
+    p->seqStat.nextTxSn = 0;
+    p->seqStat.bFirstPkt = 1;
+    p->seqStat.bAutoEmpty = 0;
+    p->seqStat.bLlCtrlTx = 0;
+    p->seqStat.bLlCtrlAckRx = 0;
+    p->seqStat.bLlCtrlAckPending = 0;
+  }
+  
+  p->maxPkt = 12;
+  p->accessAddress = access_address;
+  p->crcInit0 = crc_init_0;
+  p->crcInit1 = crc_init_1;
+  p->crcInit2 = crc_init_2;
+  p->endTrigger.triggerType = TRIG_REL_START;
+  p->endTime = (uint32_t)15 * 4000;   /* a connection event must end after 10 ms */
+}
+/*---------------------------------------------------------------------------*/
 /* DATA queue functions                                                      */
 /*---------------------------------------------------------------------------*/
 unsigned short

arch/cpu/cc26xx-cc13xx/rf-core/ble-hal/rf-ble-cmd.h

@@ -106,6 +106,45 @@ void rf_ble_cmd_create_adv_params(uint8_t *param, dataQueue_t *rx_queue,
                                   uint8_t scan_resp_data_len, uint8_t *scan_resp_data,
                                   ble_addr_type_t own_addr_type, uint8_t *own_addr);
 
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief Creates a BLE radio command structure that sets up
+ *      BLE initiation event when sent to the radio core
+ * \param cmd     A pointer to command that is created
+ * \param channel The BLE data channel used for the connection event
+ * \param params   A pointer to the radio command parameters
+ * \param output  A pointer to the radio command output
+ * \param start_time
+ *          The time in rf_core_ticks when the connection event will start
+ */
+void rf_ble_cmd_create_initiator_cmd(uint8_t *cmd, uint8_t channel, uint8_t *params,
+                                     uint8_t *output, uint32_t start_time);
+
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief Creates BLE radio command parameters that are used to set up
+ *      BLE initiation event on the radio core
+ * \param param      A pointer to parameter structure that is created
+ * \param rx_queue  A pointer to the RX queue that is used
+ * \param initiator_window
+ *          T
+ * \param own_addr_type
+ *          Either BLE_ADDR_TYPE_PUBLIC or BLE_ADDR_TYPE_RANDOM
+ * \param own_addr A pointer to the device address that is used as own address
+ * \param peer_addr_type
+ *          Either BLE_ADDR_TYPE_PUBLIC or BLE_ADDR_TYPE_RANDOM
+ * \param peer_addr A pointer to the device address that is used as peer address
+ * \param connect_time
+            The first possible start time of the first connection event
+ * \param conn_req_data  A pointer to the connect request data
+ */
+void rf_ble_cmd_create_initiator_params(uint8_t *param, dataQueue_t *rx_queue,
+                                        uint32_t initiator_window,
+                                        ble_addr_type_t own_addr_type, uint8_t *own_addr,
+                                        ble_addr_type_t peer_addr_type, uint8_t *peer_addr,
+                                        uint32_t connect_time,
+                                        uint8_t *conn_req_data);
+
 /*---------------------------------------------------------------------------*/
 /**
  * \brief Creates a BLE radio command structure that sets up a single
@@ -148,6 +187,44 @@ void rf_ble_cmd_create_slave_params(uint8_t *param, dataQueue_t *rx_queue,
                                     uint8_t crc_init_2, uint32_t win_size,
                                     uint32_t window_widening, uint8_t first_packet);
 
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief Creates a BLE radio command structure that sets up
+ *      BLE connection event when sent to the radio core
+ * \param cmd     A pointer to command that is created
+ * \param channel The BLE data channel used for the connection event
+ * \param params   A pointer to the radio command parameters
+ * \param output  A pointer to the radio command output
+ * \param start_time
+ *          The time in rf_core_ticks when the connection event will start
+ */
+void rf_ble_cmd_create_master_cmd(uint8_t *cmd, uint8_t channel, uint8_t *params,
+                                  uint8_t *output, uint32_t start_time);
+
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief Creates BLE radio command parameters that are used to set up
+ *      BLE connection event on the radio core
+ * \param params      A pointer to parameter structure that is created
+ * \param rx_queue  A pointer to the RX queue that is used
+ * \param tx_queue  A pointer to the TX queue that is used
+ * \param access_address
+ *          The access address of the used BLE connection
+ * \param crc_init_0
+ *          Part of the initialization of the CRC checksum
+ * \param crc_init_1
+ *          Part of the initialization of the CRC checksum
+ * \param crc_init_2
+ *          Part of the initialization of the CRC checksum
+ * \param first_packet
+ *          1 for the first packet of the BLE connection so that the
+ *          connection is properly initialized
+ */
+void rf_ble_cmd_create_master_params(uint8_t *params, dataQueue_t *rx_queue,
+                                     dataQueue_t *tx_queue, uint32_t access_address,
+                                     uint8_t crc_init_0, uint8_t crc_init_1,
+                                     uint8_t crc_init_2, uint8_t first_packet);
+
 /*---------------------------------------------------------------------------*/
 /**
  * \brief Adds a data buffer to a BLE transmission queue

arch/cpu/cc26xx-cc13xx/rf-core/cc13xx-50kbps-tsch.c

@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2018, University of Bristol - http://www.bristol.ac.uk/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the Contiki operating system.
+ *
+ */
+
+/**
+ * \file
+ *         IEEE 802.15.4 TSCH timeslot timings for CC13xx chips at 50kbps datarate
+ * \author
+ *         Atis Elsts <atis.elsts@bristol.ac.uk>
+ *
+ */
+
+#include "contiki.h"
+#include "net/mac/tsch/tsch.h"
+
+#define CC13XX_TSCH_DEFAULT_TS_CCA_OFFSET         1800
+#define CC13XX_TSCH_DEFAULT_TS_CCA                128
+#define CC13XX_TSCH_DEFAULT_TS_TX_OFFSET          2500
+#define CC13XX_TSCH_DEFAULT_TS_RX_OFFSET          (CC13XX_TSCH_DEFAULT_TS_TX_OFFSET - (TSCH_CONF_RX_WAIT / 2))
+#define CC13XX_TSCH_DEFAULT_TS_RX_ACK_DELAY       2000
+#define CC13XX_TSCH_DEFAULT_TS_TX_ACK_DELAY       3000
+#define CC13XX_TSCH_DEFAULT_TS_RX_WAIT            TSCH_CONF_RX_WAIT
+#define CC13XX_TSCH_DEFAULT_TS_ACK_WAIT           3000
+#define CC13XX_TSCH_DEFAULT_TS_RX_TX              192
+#define CC13XX_TSCH_DEFAULT_TS_MAX_ACK            10000
+#define CC13XX_TSCH_DEFAULT_TS_MAX_TX             21600
+
+/* Timeslot length: 40000 usec */
+#define CC13XX_TSCH_DEFAULT_TS_TIMESLOT_LENGTH  40000
+
+/* TSCH timeslot timing (microseconds) */
+const uint16_t tsch_timing_cc13xx_50kbps[tsch_ts_elements_count] = {
+  CC13XX_TSCH_DEFAULT_TS_CCA_OFFSET,
+  CC13XX_TSCH_DEFAULT_TS_CCA,
+  CC13XX_TSCH_DEFAULT_TS_TX_OFFSET,
+  CC13XX_TSCH_DEFAULT_TS_RX_OFFSET,
+  CC13XX_TSCH_DEFAULT_TS_RX_ACK_DELAY,
+  CC13XX_TSCH_DEFAULT_TS_TX_ACK_DELAY,
+  CC13XX_TSCH_DEFAULT_TS_RX_WAIT,
+  CC13XX_TSCH_DEFAULT_TS_ACK_WAIT,
+  CC13XX_TSCH_DEFAULT_TS_RX_TX,
+  CC13XX_TSCH_DEFAULT_TS_MAX_ACK,
+  CC13XX_TSCH_DEFAULT_TS_MAX_TX,
+  CC13XX_TSCH_DEFAULT_TS_TIMESLOT_LENGTH,
+};

arch/cpu/cc26xx-cc13xx/rf-core/cc13xx-50kbps-tsch.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2018, University of Bristol - http://www.bristol.ac.uk/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Institute nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * This file is part of the Contiki operating system.
+ *
+ */
+
+#ifndef CC13XX_50KBPS_TSCH_H_
+#define CC13XX_50KBPS_TSCH_H_
+
+#include "contiki.h"
+
+/* TSCH timeslot timing (microseconds) */
+extern const uint16_t tsch_timing_cc13xx_50kbps[];
+
+#endif /* CC13XX_50KBPS_TSCH_H_ */

arch/cpu/cc26xx-cc13xx/rf-core/dot-15-4g.h

@@ -49,20 +49,21 @@
 #include "driverlib/rf_mailbox.h"
 /*---------------------------------------------------------------------------*/
 /* IEEE 802.15.4g frequency band identifiers (Table 68f) */
-#define DOT_15_4G_FREQUENCY_BAND_169  0 /* 169.400–169.475 (Europe) - 169 MHz band */
-#define DOT_15_4G_FREQUENCY_BAND_450  1 /* 450–470 (US FCC Part 22/90) - 450 MHz band */
-#define DOT_15_4G_FREQUENCY_BAND_470  2 /* 470–510 (China) - 470 MHz band */
-#define DOT_15_4G_FREQUENCY_BAND_780  3 /* 779–787 (China) - 780 MHz band */
-#define DOT_15_4G_FREQUENCY_BAND_863  4 /* 863–870 (Europe) - 863 MHz band */
-#define DOT_15_4G_FREQUENCY_BAND_896  5 /* 896–901 (US FCC Part 90) - 896 MHz band */
-#define DOT_15_4G_FREQUENCY_BAND_901  6 /* 901–902 (US FCC Part 24) - 901 MHz band */
-#define DOT_15_4G_FREQUENCY_BAND_915  7 /* 902–928 (US) - 915 MHz band */
-#define DOT_15_4G_FREQUENCY_BAND_917  8 /* 917–923.5 (Korea) - 917 MHz band */
-#define DOT_15_4G_FREQUENCY_BAND_920  9 /* 920–928 (Japan) - 920 MHz band */
-#define DOT_15_4G_FREQUENCY_BAND_928  10 /* 928–960 (US, non-contiguous) - 928 MHz band */
-#define DOT_15_4G_FREQUENCY_BAND_950  11 /* 950–958 (Japan) - 950 MHz band */
-#define DOT_15_4G_FREQUENCY_BAND_1427 12 /* 1427–1518 (US and Canada, non-contiguous) - 1427 MHz band */
-#define DOT_15_4G_FREQUENCY_BAND_2450 13 /* 2400–2483.5 2450 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_169     0 /* 169.400–169.475 (Europe) - 169 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_450     1 /* 450–470 (US FCC Part 22/90) - 450 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_470     2 /* 470–510 (China) - 470 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_780     3 /* 779–787 (China) - 780 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_863     4 /* 863–870 (Europe) - 863 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_896     5 /* 896–901 (US FCC Part 90) - 896 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_901     6 /* 901–902 (US FCC Part 24) - 901 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_915     7 /* 902–928 (US) - 915 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_917     8 /* 917–923.5 (Korea) - 917 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_920     9 /* 920–928 (Japan) - 920 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_928     10 /* 928–960 (US, non-contiguous) - 928 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_950     11 /* 950–958 (Japan) - 950 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_1427    12 /* 1427–1518 (US and Canada, non-contiguous) - 1427 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_2450    13 /* 2400–2483.5 2450 MHz band */
+#define DOT_15_4G_FREQUENCY_BAND_CUSTOM  14 /* For use with custom frequency band settings */
 /*---------------------------------------------------------------------------*/
 /* Default band selection to band 4 - 863MHz */
 #ifdef DOT_15_4G_CONF_FREQUENCY_BAND_ID
@@ -77,6 +78,18 @@
  * bands we only support operating mode #1 (Table 134).
  *
  * DOT_15_4G_CHAN0_FREQUENCY is specified here in KHz
+ *
+ * Custom bands and configuration can be used with DOT_15_4G_FREQUENCY_BAND_CUSTOM.
+ *
+ * Example of custom setup for the 868Mhz sub-band in Europe with 11 channels,
+ * center frequency at 868.050MHz and channel spacing at 100KHz.
+ * These should be put in project-config.h or similar.
+ *
+ * #define DOT_15_4G_FREQUENCY_BAND_ID DOT_15_4G_FREQUENCY_BAND_CUSTOM
+ * #define DOT_15_4G_CHAN0_FREQUENCY        868050
+ * #define DOT_15_4G_CHANNEL_SPACING        100
+ * #define DOT_15_4G_CHANNEL_MAX            11
+ * #define PROP_MODE_CONF_LO_DIVIDER        0x05
  */
 #if DOT_15_4G_FREQUENCY_BAND_ID==DOT_15_4G_FREQUENCY_BAND_470
 #define DOT_15_4G_CHANNEL_MAX        198
@@ -116,6 +129,22 @@
 #define DOT_15_4G_CHAN0_FREQUENCY 951000
 #define PROP_MODE_CONF_LO_DIVIDER   0x05
 
+#elif DOT_15_4G_FREQUENCY_BAND_ID==DOT_15_4G_FREQUENCY_BAND_CUSTOM
+#ifndef DOT_15_4G_CHANNEL_MAX
+#error DOT_15_4G_CHANNEL_MAX must be manually set when using custom frequency band
+#endif
+
+#ifndef DOT_15_4G_CHANNEL_SPACING
+#error DOT_15_4G_CHANNEL_SPACING must be manually set when using custom frequency band
+#endif
+
+#ifndef DOT_15_4G_CHAN0_FREQUENCY
+#error DOT_15_4G_CHAN0_FREQUENCY must be manually set when using custom frequency band
+#endif
+
+#ifndef PROP_MODE_CONF_LO_DIVIDER
+#error PROP_MODE_CONF_LO_DIVIDER must be manually set when using custom frequency band
+#endif
 #else
 #error The selected frequency band is not supported
 #endif

arch/cpu/cc26xx-cc13xx/rf-core/ieee-mode.c

@@ -120,6 +120,8 @@ static uint8_t rf_stats[16] = { 0 };
 /* The size of the RF commands buffer */
 #define RF_CMD_BUFFER_SIZE             128
 /*---------------------------------------------------------------------------*/
+#define RAT_TIMESTAMP_OFFSET_2_4_GHZ   0
+/*---------------------------------------------------------------------------*/
 /**
  * \brief Returns the current status of a running Radio Op command
  * \param a A pointer with the buffer used to initiate the command
@@ -130,55 +132,9 @@ static uint8_t rf_stats[16] = { 0 };
  */
 #define RF_RADIO_OP_GET_STATUS(a) (((rfc_radioOp_t *)a)->status)
 /*---------------------------------------------------------------------------*/
-/* Special value returned by CMD_IEEE_CCA_REQ when an RSSI is not available */
-#define RF_CMD_CCA_REQ_RSSI_UNKNOWN     -128
-
-/* Used for the return value of channel_clear */
-#define RF_CCA_CLEAR                       1
-#define RF_CCA_BUSY                        0
-
-/* Used as an error return value for get_cca_info */
-#define RF_GET_CCA_INFO_ERROR           0xFF
-
-/*
- * Values of the individual bits of the ccaInfo field in CMD_IEEE_CCA_REQ's
- * status struct
- */
-#define RF_CMD_CCA_REQ_CCA_STATE_IDLE      0 /* 00 */
-#define RF_CMD_CCA_REQ_CCA_STATE_BUSY      1 /* 01 */
-#define RF_CMD_CCA_REQ_CCA_STATE_INVALID   2 /* 10 */
-
-#define RF_CMD_CCA_REQ_CCA_CORR_IDLE       (0 << 4)
-#define RF_CMD_CCA_REQ_CCA_CORR_BUSY       (1 << 4)
-#define RF_CMD_CCA_REQ_CCA_CORR_INVALID    (3 << 4)
-#define RF_CMD_CCA_REQ_CCA_CORR_MASK       (3 << 4)
-
-#define RF_CMD_CCA_REQ_CCA_SYNC_BUSY       (1 << 6)
-/*---------------------------------------------------------------------------*/
 #define IEEE_MODE_CHANNEL_MIN            11
 #define IEEE_MODE_CHANNEL_MAX            26
 /*---------------------------------------------------------------------------*/
-/* How long to wait for an ongoing ACK TX to finish before starting frame TX */
-#define TX_WAIT_TIMEOUT       (RTIMER_SECOND >> 11)
-
-/* How long to wait for the RF to enter RX in rf_cmd_ieee_rx */
-#define ENTER_RX_WAIT_TIMEOUT (RTIMER_SECOND >> 10)
-
-/* How long to wait for the RF to react on CMD_ABORT: around 1 msec */
-#define RF_TURN_OFF_WAIT_TIMEOUT (RTIMER_SECOND >> 10)
-
-/* How long to wait for the RF to finish TX of a packet or an ACK */
-#define TX_FINISH_WAIT_TIMEOUT (RTIMER_SECOND >> 7)
-
-#define LIMITED_BUSYWAIT(cond, timeout) do {                         \
-    rtimer_clock_t end_time = RTIMER_NOW() + timeout;                \
-    while(cond) {                                                    \
-      if(!RTIMER_CLOCK_LT(RTIMER_NOW(), end_time)) {                 \
-        break;                                                       \
-      }                                                              \
-    }                                                                \
-  } while(0)
-/*---------------------------------------------------------------------------*/
 /* TX Power dBm lookup table - values from SmartRF Studio */
 typedef struct output_config {
   radio_value_t dbm;
@@ -211,33 +167,6 @@ static const output_config_t output_power[] = {
 /* Default TX Power - position in output_power[] */
 static const output_config_t *tx_power_current = &output_power[0];
 /*---------------------------------------------------------------------------*/
-static volatile int8_t last_rssi = 0;
-static volatile uint8_t last_corr_lqi = 0;
-
-extern int32_t rat_offset;
-
-/*---------------------------------------------------------------------------*/
-/* SFD timestamp in RTIMER ticks */
-static volatile uint32_t last_packet_timestamp = 0;
-/* SFD timestamp in RAT ticks (but 64 bits) */
-static uint64_t last_rat_timestamp64 = 0;
-
-/* For RAT overflow handling */
-static struct ctimer rat_overflow_timer;
-static volatile uint32_t rat_overflow_counter = 0;
-static rtimer_clock_t last_rat_overflow = 0;
-
-/* RAT has 32-bit register, overflows once 18 minutes */
-#define RAT_RANGE  4294967296ull
-/* approximate value */
-#define RAT_OVERFLOW_PERIOD_SECONDS (60 * 18)
-
-/* XXX: don't know what exactly is this, looks like the time to Tx 3 octets */
-#define TIMESTAMP_OFFSET  -(USEC_TO_RADIO(32 * 3) - 1) /* -95.75 usec */
-/*---------------------------------------------------------------------------*/
-/* Are we currently in poll mode? */
-static uint8_t poll_mode = 0;
-
 static rfc_CMD_IEEE_MOD_FILT_t filter_cmd;
 /*---------------------------------------------------------------------------*/
 /*
@@ -256,27 +185,28 @@ static uint8_t cmd_ieee_rx_buf[RF_CMD_BUFFER_SIZE] CC_ALIGN(4);
 #define DATA_ENTRY_LENSZ_BYTE 1
 #define DATA_ENTRY_LENSZ_WORD 2 /* 2 bytes */
 
-#define RX_BUF_SIZE 144
-/* Four receive buffers entries with room for 1 IEEE802.15.4 frame in each */
-static uint8_t rx_buf_0[RX_BUF_SIZE] CC_ALIGN(4);
-static uint8_t rx_buf_1[RX_BUF_SIZE] CC_ALIGN(4);
-static uint8_t rx_buf_2[RX_BUF_SIZE] CC_ALIGN(4);
-static uint8_t rx_buf_3[RX_BUF_SIZE] CC_ALIGN(4);
-
-#define RX_BUF_INCLUDE_CRC 1
-#define RX_BUF_INCLUDE_RSSI 1
-#define RX_BUF_INCLUDE_CORR 1
-#define RX_BUF_INCLUDE_TIMESTAMP 1
-
 /* The size of the metadata (excluding the packet length field) */
 #define RX_BUF_METADATA_SIZE \
-  (2 * RX_BUF_INCLUDE_CRC + RX_BUF_INCLUDE_RSSI + RX_BUF_INCLUDE_CORR + 4 * RX_BUF_INCLUDE_TIMESTAMP)
+  (2 * RF_CORE_RX_BUF_INCLUDE_CRC \
+      + RF_CORE_RX_BUF_INCLUDE_RSSI \
+      + RF_CORE_RX_BUF_INCLUDE_CORR \
+      + 4 * RF_CORE_RX_BUF_INCLUDE_TIMESTAMP)
 
 /* The offset of the packet length in a rx buffer */
 #define RX_BUF_LENGTH_OFFSET sizeof(rfc_dataEntry_t)
 /* The offset of the packet data in a rx buffer */
 #define RX_BUF_DATA_OFFSET (RX_BUF_LENGTH_OFFSET + 1)
 
+#define RX_BUF_SIZE (RX_BUF_DATA_OFFSET \
+      + NETSTACK_RADIO_MAX_PAYLOAD_LEN  \
+      + RX_BUF_METADATA_SIZE)
+
+/* Four receive buffers entries with room for 1 IEEE802.15.4 frame in each */
+static uint8_t rx_buf_0[RX_BUF_SIZE] CC_ALIGN(4);
+static uint8_t rx_buf_1[RX_BUF_SIZE] CC_ALIGN(4);
+static uint8_t rx_buf_2[RX_BUF_SIZE] CC_ALIGN(4);
+static uint8_t rx_buf_3[RX_BUF_SIZE] CC_ALIGN(4);
+
 /* The RX Data Queue */
 static dataQueue_t rx_data_queue = { 0 };
 
@@ -358,8 +288,8 @@ transmitting(void)
     return 0;
   }
 
-  if((cmd.currentRssi == RF_CMD_CCA_REQ_RSSI_UNKNOWN) &&
-     (cmd.ccaInfo.ccaEnergy == RF_CMD_CCA_REQ_CCA_STATE_BUSY)) {
+  if((cmd.currentRssi == RF_CORE_CMD_CCA_REQ_RSSI_UNKNOWN) &&
+     (cmd.ccaInfo.ccaEnergy == RF_CORE_CMD_CCA_REQ_CCA_STATE_BUSY)) {
     return 1;
   }
 
@@ -368,12 +298,12 @@ transmitting(void)
 /*---------------------------------------------------------------------------*/
 /**
  * \brief Returns CCA information
- * \return RF_GET_CCA_INFO_ERROR if the RF was not on
+ * \return RF_CORE_GET_CCA_INFO_ERROR if the RF was not on
  * \return On success, the return value is formatted as per the ccaInfo field
  *         of CMD_IEEE_CCA_REQ
  *
  * It is the caller's responsibility to make sure the RF is on. This function
- * will return RF_GET_CCA_INFO_ERROR if the RF is off
+ * will return RF_CORE_GET_CCA_INFO_ERROR if the RF is off
  *
  * This function will in fact wait for a valid CCA state
  */
@@ -385,20 +315,20 @@ get_cca_info(void)
 
   if(!rf_is_on()) {
     PRINTF("get_cca_info: Not on\n");
-    return RF_GET_CCA_INFO_ERROR;
+    return RF_CORE_GET_CCA_INFO_ERROR;
   }
 
   memset(&cmd, 0x00, sizeof(cmd));
-  cmd.ccaInfo.ccaState = RF_CMD_CCA_REQ_CCA_STATE_INVALID;
+  cmd.ccaInfo.ccaState = RF_CORE_CMD_CCA_REQ_CCA_STATE_INVALID;
 
-  while(cmd.ccaInfo.ccaState == RF_CMD_CCA_REQ_CCA_STATE_INVALID) {
+  while(cmd.ccaInfo.ccaState == RF_CORE_CMD_CCA_REQ_CCA_STATE_INVALID) {
     memset(&cmd, 0x00, sizeof(cmd));
     cmd.commandNo = CMD_IEEE_CCA_REQ;
 
     if(rf_core_send_cmd((uint32_t)&cmd, &cmd_status) == RF_CORE_CMD_ERROR) {
       PRINTF("get_cca_info: CMDSTA=0x%08lx\n", cmd_status);
 
-      return RF_GET_CCA_INFO_ERROR;
+      return RF_CORE_GET_CCA_INFO_ERROR;
     }
   }
 
@@ -425,14 +355,14 @@ get_rssi(void)
     was_off = 1;
     if(on() != RF_CORE_CMD_OK) {
       PRINTF("get_rssi: on() failed\n");
-      return RF_CMD_CCA_REQ_RSSI_UNKNOWN;
+      return RF_CORE_CMD_CCA_REQ_RSSI_UNKNOWN;
     }
   }
 
   memset(&cmd, 0x00, sizeof(cmd));
-  cmd.ccaInfo.ccaEnergy = RF_CMD_CCA_REQ_CCA_STATE_INVALID;
+  cmd.ccaInfo.ccaEnergy = RF_CORE_CMD_CCA_REQ_CCA_STATE_INVALID;
 
-  while(cmd.ccaInfo.ccaEnergy == RF_CMD_CCA_REQ_CCA_STATE_INVALID) {
+  while(cmd.ccaInfo.ccaEnergy == RF_CORE_CMD_CCA_REQ_CCA_STATE_INVALID) {
     memset(&cmd, 0x00, sizeof(cmd));
     cmd.commandNo = CMD_IEEE_CCA_REQ;
 
@@ -440,7 +370,7 @@ get_rssi(void)
       PRINTF("get_rssi: CMDSTA=0x%08lx\n", cmd_status);
 
       /* Make sure to return RSSI unknown */
-      cmd.currentRssi = RF_CMD_CCA_REQ_RSSI_UNKNOWN;
+      cmd.currentRssi = RF_CORE_CMD_CCA_REQ_RSSI_UNKNOWN;
       break;
     }
   }
@@ -558,8 +488,8 @@ rf_cmd_ieee_rx()
     return RF_CORE_CMD_ERROR;
   }
 
-  LIMITED_BUSYWAIT(RF_RADIO_OP_GET_STATUS(cmd_ieee_rx_buf) != RF_CORE_RADIO_OP_STATUS_ACTIVE,
-                   ENTER_RX_WAIT_TIMEOUT);
+  RTIMER_BUSYWAIT_UNTIL(RF_RADIO_OP_GET_STATUS(cmd_ieee_rx_buf) == RF_CORE_RADIO_OP_STATUS_ACTIVE,
+                        RF_CORE_ENTER_RX_TIMEOUT);
 
   /* Wait to enter RX */
   if(RF_RADIO_OP_GET_STATUS(cmd_ieee_rx_buf) != RF_CORE_RADIO_OP_STATUS_ACTIVE) {
@@ -610,16 +540,16 @@ init_rf_params(void)
   cmd->startTime = 0x00000000;
   cmd->startTrigger.triggerType = TRIG_NOW;
   cmd->condition.rule = COND_NEVER;
-  cmd->channel = RF_CORE_CHANNEL;
+  cmd->channel = IEEE802154_DEFAULT_CHANNEL;
 
   cmd->rxConfig.bAutoFlushCrc = 1;
   cmd->rxConfig.bAutoFlushIgn = 0;
   cmd->rxConfig.bIncludePhyHdr = 0;
-  cmd->rxConfig.bIncludeCrc = RX_BUF_INCLUDE_CRC;
-  cmd->rxConfig.bAppendRssi = RX_BUF_INCLUDE_RSSI;
-  cmd->rxConfig.bAppendCorrCrc = RX_BUF_INCLUDE_CORR;
+  cmd->rxConfig.bIncludeCrc = RF_CORE_RX_BUF_INCLUDE_CRC;
+  cmd->rxConfig.bAppendRssi = RF_CORE_RX_BUF_INCLUDE_RSSI;
+  cmd->rxConfig.bAppendCorrCrc = RF_CORE_RX_BUF_INCLUDE_CORR;
   cmd->rxConfig.bAppendSrcInd = 0;
-  cmd->rxConfig.bAppendTimestamp = RX_BUF_INCLUDE_TIMESTAMP;
+  cmd->rxConfig.bAppendTimestamp = RF_CORE_RX_BUF_INCLUDE_TIMESTAMP;
 
   cmd->pRxQ = &rx_data_queue;
   cmd->pOutput = (rfc_ieeeRxOutput_t *)rf_stats;
@@ -714,7 +644,7 @@ rx_off(void)
   }
 
   /* Wait for ongoing ACK TX to finish */
-  LIMITED_BUSYWAIT(transmitting(), TX_FINISH_WAIT_TIMEOUT);
+  RTIMER_BUSYWAIT_UNTIL(!transmitting(), RF_CORE_TX_FINISH_TIMEOUT);
 
   /* Send a CMD_ABORT command to RF Core */
   if(rf_core_send_cmd(CMDR_DIR_CMD(CMD_ABORT), &cmd_status) != RF_CORE_CMD_OK) {
@@ -722,7 +652,7 @@ rx_off(void)
     /* Continue nonetheless */
   }
 
-  LIMITED_BUSYWAIT(rf_is_on(), RF_TURN_OFF_WAIT_TIMEOUT);
+  RTIMER_BUSYWAIT_UNTIL(!rf_is_on(), RF_CORE_TURN_OFF_TIMEOUT);
 
   if(RF_RADIO_OP_GET_STATUS(cmd_ieee_rx_buf) == IEEE_DONE_STOPPED ||
      RF_RADIO_OP_GET_STATUS(cmd_ieee_rx_buf) == IEEE_DONE_ABORT) {
@@ -773,8 +703,8 @@ soft_off(void)
     return;
   }
 
-  LIMITED_BUSYWAIT((cmd->status & RF_CORE_RADIO_OP_MASKED_STATUS) ==
-                   RF_CORE_RADIO_OP_MASKED_STATUS_RUNNING, RF_TURN_OFF_WAIT_TIMEOUT);
+  RTIMER_BUSYWAIT_UNTIL((cmd->status & RF_CORE_RADIO_OP_MASKED_STATUS) !=
+                        RF_CORE_RADIO_OP_MASKED_STATUS_RUNNING, RF_CORE_TURN_OFF_TIMEOUT);
 }
 /*---------------------------------------------------------------------------*/
 static uint8_t
@@ -791,71 +721,10 @@ soft_on(void)
 static const rf_core_primary_mode_t mode_ieee = {
   soft_off,
   soft_on,
+  rf_is_on,
+  RAT_TIMESTAMP_OFFSET_2_4_GHZ
 };
 /*---------------------------------------------------------------------------*/
-static uint8_t
-check_rat_overflow(bool first_time)
-{
-  static uint32_t last_value;
-  uint32_t current_value;
-  uint8_t interrupts_disabled;
-
-  /* Bail out if the RF is not on */
-  if(!rf_is_on()) {
-    return 0;
-  }
-
-  interrupts_disabled = ti_lib_int_master_disable();
-  if(first_time) {
-    last_value = HWREG(RFC_RAT_BASE + RATCNT);
-  } else {
-    current_value = HWREG(RFC_RAT_BASE + RATCNT);
-    if(current_value + RAT_RANGE / 4 < last_value) {
-      /* Overflow detected */
-      last_rat_overflow = RTIMER_NOW();
-      rat_overflow_counter++;
-    }
-    last_value = current_value;
-  }
-  if(!interrupts_disabled) {
-    ti_lib_int_master_enable();
-  }
-  return 1;
-}
-/*---------------------------------------------------------------------------*/
-static void
-handle_rat_overflow(void *unused)
-{
-  uint8_t success;
-  uint8_t was_off = 0;
-
-  if(!rf_is_on()) {
-    was_off = 1;
-    if(on() != RF_CORE_CMD_OK) {
-      PRINTF("overflow: on() failed\n");
-      ctimer_set(&rat_overflow_timer, CLOCK_SECOND,
-                 handle_rat_overflow, NULL);
-      return;
-    }
-  }
-
-  success = check_rat_overflow(false);
-
-  if(was_off) {
-    off();
-  }
-
-  if(success) {
-    /* Retry after half of the interval */
-    ctimer_set(&rat_overflow_timer, RAT_OVERFLOW_PERIOD_SECONDS * CLOCK_SECOND / 2,
-               handle_rat_overflow, NULL);
-  } else {
-    /* Retry sooner */
-    ctimer_set(&rat_overflow_timer, CLOCK_SECOND,
-               handle_rat_overflow, NULL);
-  }
-}
-/*---------------------------------------------------------------------------*/
 static int
 init(void)
 {
@@ -889,9 +758,7 @@ init(void)
 
   rf_core_primary_mode_register(&mode_ieee);
 
-  check_rat_overflow(true);
-  ctimer_set(&rat_overflow_timer, RAT_OVERFLOW_PERIOD_SECONDS * CLOCK_SECOND / 2,
-             handle_rat_overflow, NULL);
+  rf_core_rat_init();
 
   process_start(&rf_core_process, NULL);
   return 1;
@@ -935,7 +802,7 @@ transmit(unsigned short transmit_len)
   do {
     tx_active = transmitting();
   } while(tx_active == 1 &&
-          (RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + TX_WAIT_TIMEOUT)));
+          (RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + RF_CORE_TX_TIMEOUT)));
 
   if(tx_active) {
     PRINTF("transmit: Already TXing and wait timed out\n");
@@ -957,7 +824,7 @@ transmit(unsigned short transmit_len)
   cmd.startTrigger.triggerType = TRIG_NOW;
 
   /* Enable the LAST_FG_COMMAND_DONE interrupt, which will wake us up */
-  rf_core_cmd_done_en(true, poll_mode);
+  rf_core_cmd_done_en(true);
 
   ret = rf_core_send_cmd((uint32_t)&cmd, &cmd_status);
 
@@ -973,7 +840,7 @@ transmit(unsigned short transmit_len)
        *  1) make the `lpm_sleep()` call here unconditional;
        *  2) change the radio ISR priority to allow radio ISR to interrupt rtimer ISR.
        */
-      if(!poll_mode) {
+      if(!rf_core_poll_mode) {
         lpm_sleep();
       }
     }
@@ -1007,7 +874,7 @@ transmit(unsigned short transmit_len)
    * Disable LAST_FG_COMMAND_DONE interrupt. We don't really care about it
    * except when we are transmitting
    */
-  rf_core_cmd_done_dis(poll_mode);
+  rf_core_cmd_done_dis();
 
   if(was_off) {
     off();
@@ -1036,46 +903,6 @@ release_data_entry(void)
   rx_read_entry = entry->pNextEntry;
 }
 /*---------------------------------------------------------------------------*/
-static uint32_t
-calc_last_packet_timestamp(uint32_t rat_timestamp)
-{
-  uint64_t rat_timestamp64;
-  uint32_t adjusted_overflow_counter;
-  uint8_t was_off = 0;
-
-  if(!rf_is_on()) {
-    was_off = 1;
-    on();
-  }
-
-  if(rf_is_on()) {
-    check_rat_overflow(false);
-    if(was_off) {
-      off();
-    }
-  }
-
-  adjusted_overflow_counter = rat_overflow_counter;
-
-  /* if the timestamp is large and the last oveflow was recently,
-     assume that the timestamp refers to the time before the overflow */
-  if(rat_timestamp > (uint32_t)(RAT_RANGE * 3 / 4)) {
-    if(RTIMER_CLOCK_LT(RTIMER_NOW(),
-                       last_rat_overflow + RAT_OVERFLOW_PERIOD_SECONDS * RTIMER_SECOND / 4)) {
-      adjusted_overflow_counter--;
-    }
-  }
-
-  /* add the overflowed time to the timestamp */
-  rat_timestamp64 = rat_timestamp + RAT_RANGE * adjusted_overflow_counter;
-  /* correct timestamp so that it refers to the end of the SFD */
-  rat_timestamp64 += TIMESTAMP_OFFSET;
-
-  last_rat_timestamp64 = rat_timestamp64 - rat_offset;
-
-  return RADIO_TO_RTIMER(rat_timestamp64 - rat_offset);
-}
-/*---------------------------------------------------------------------------*/
 static int
 read_frame(void *buf, unsigned short buf_len)
 {
@@ -1111,20 +938,20 @@ read_frame(void *buf, unsigned short buf_len)
 
   memcpy(buf, (uint8_t *)rx_read_entry + RX_BUF_DATA_OFFSET, len);
 
-  last_rssi = (int8_t)rx_read_entry[RX_BUF_DATA_OFFSET + len + 2];
-  last_corr_lqi = (uint8_t)rx_read_entry[RX_BUF_DATA_OFFSET + len + 3] & STATUS_CORRELATION;
+  rf_core_last_rssi = (int8_t)rx_read_entry[RX_BUF_DATA_OFFSET + len];
+  rf_core_last_corr_lqi = (uint8_t)rx_read_entry[RX_BUF_DATA_OFFSET + len + 1] & STATUS_CORRELATION;
 
   /* get the timestamp */
-  memcpy(&rat_timestamp, (uint8_t *)rx_read_entry + RX_BUF_DATA_OFFSET + len + 4, 4);
+  memcpy(&rat_timestamp, (uint8_t *)rx_read_entry + RX_BUF_DATA_OFFSET + len + 2, 4);
 
-  last_packet_timestamp = calc_last_packet_timestamp(rat_timestamp);
+  rf_core_last_packet_timestamp = rf_core_convert_rat_to_rtimer(rat_timestamp);
 
-  if(!poll_mode) {
+  if(!rf_core_poll_mode) {
     /* Not in poll mode: packetbuf should not be accessed in interrupt context.
      * In poll mode, the last packet RSSI and link quality can be obtained through
      * RADIO_PARAM_LAST_RSSI and RADIO_PARAM_LAST_LINK_QUALITY */
-    packetbuf_set_attr(PACKETBUF_ATTR_RSSI, last_rssi);
-    packetbuf_set_attr(PACKETBUF_ATTR_LINK_QUALITY, last_corr_lqi);
+    packetbuf_set_attr(PACKETBUF_ATTR_RSSI, rf_core_last_rssi);
+    packetbuf_set_attr(PACKETBUF_ATTR_LINK_QUALITY, rf_core_last_corr_lqi);
   }
 
   release_data_entry();
@@ -1137,7 +964,7 @@ channel_clear(void)
 {
   uint8_t was_off = 0;
   uint8_t cca_info;
-  int ret = RF_CCA_CLEAR;
+  int ret = RF_CORE_CCA_CLEAR;
 
   /*
    * If we are in the middle of a BLE operation, we got called by ContikiMAC
@@ -1145,7 +972,7 @@ channel_clear(void)
    */
   if(rf_ble_is_active() == RF_BLE_ACTIVE) {
     PRINTF("channel_clear: Interrupt context but BLE in progress\n");
-    return RF_CCA_CLEAR;
+    return RF_CORE_CCA_CLEAR;
   }
 
   if(rf_is_on()) {
@@ -1157,7 +984,7 @@ channel_clear(void)
      *
      * We could probably even simply return that the channel is clear
      */
-    LIMITED_BUSYWAIT(transmitting(), TX_FINISH_WAIT_TIMEOUT);
+    RTIMER_BUSYWAIT_UNTIL(!transmitting(), RF_CORE_TX_FINISH_TIMEOUT);
   } else {
     was_off = 1;
     if(on() != RF_CORE_CMD_OK) {
@@ -1165,21 +992,21 @@ channel_clear(void)
       if(was_off) {
         off();
       }
-      return RF_CCA_CLEAR;
+      return RF_CORE_CCA_CLEAR;
     }
   }
 
   cca_info = get_cca_info();
 
-  if(cca_info == RF_GET_CCA_INFO_ERROR) {
+  if(cca_info == RF_CORE_GET_CCA_INFO_ERROR) {
     PRINTF("channel_clear: CCA error\n");
-    ret = RF_CCA_CLEAR;
+    ret = RF_CORE_CCA_CLEAR;
   } else {
     /*
      * cca_info bits 1:0 - ccaStatus
      * Return 1 (clear) if idle or invalid.
      */
-    ret = (cca_info & 0x03) != RF_CMD_CCA_REQ_CCA_STATE_BUSY;
+    ret = (cca_info & 0x03) != RF_CORE_CMD_CCA_REQ_CCA_STATE_BUSY;
   }
 
   if(was_off) {
@@ -1218,12 +1045,12 @@ receiving_packet(void)
   cca_info = get_cca_info();
 
   /* If we can't read CCA info, return "not receiving" */
-  if(cca_info == RF_GET_CCA_INFO_ERROR) {
+  if(cca_info == RF_CORE_GET_CCA_INFO_ERROR) {
     return 0;
   }
 
   /* If sync has been seen, return 1 (receiving) */
-  if(cca_info & RF_CMD_CCA_REQ_CCA_SYNC_BUSY) {
+  if(cca_info & RF_CORE_CMD_CCA_REQ_CCA_SYNC_BUSY) {
     return 1;
   }
 
@@ -1241,7 +1068,7 @@ pending_packet(void)
     if(entry->status == DATA_ENTRY_STATUS_FINISHED
         || entry->status == DATA_ENTRY_STATUS_BUSY) {
       rv = 1;
-      if(!poll_mode) {
+      if(!rf_core_poll_mode) {
         process_poll(&rf_core_process);
       }
     }
@@ -1292,7 +1119,7 @@ on(void)
     return RF_CORE_CMD_ERROR;
   }
 
-  rf_core_setup_interrupts(poll_mode);
+  rf_core_setup_interrupts();
 
   if(rf_radio_setup() != RF_CORE_CMD_OK) {
     PRINTF("on: radio_setup() failed\n");
@@ -1314,7 +1141,7 @@ off(void)
     return RF_CORE_CMD_OK;
   }
 
-  LIMITED_BUSYWAIT(transmitting(), TX_FINISH_WAIT_TIMEOUT);
+  RTIMER_BUSYWAIT_UNTIL(!transmitting(), RF_CORE_TX_FINISH_TIMEOUT);
 
   /* stopping the rx explicitly results in lower sleep-mode power usage */
   rx_off();
@@ -1394,7 +1221,7 @@ get_value(radio_param_t param, radio_value_t *value)
     if(cmd->frameFiltOpt.autoAckEn) {
       *value |= RADIO_RX_MODE_AUTOACK;
     }
-    if(poll_mode) {
+    if(rf_core_poll_mode) {
       *value |= RADIO_RX_MODE_POLL_MODE;
     }
 
@@ -1411,7 +1238,7 @@ get_value(radio_param_t param, radio_value_t *value)
   case RADIO_PARAM_RSSI:
     *value = get_rssi();
 
-    if(*value == RF_CMD_CCA_REQ_RSSI_UNKNOWN) {
+    if(*value == RF_CORE_CMD_CCA_REQ_RSSI_UNKNOWN) {
       return RADIO_RESULT_ERROR;
     } else {
       return RADIO_RESULT_OK;
@@ -1429,10 +1256,25 @@ get_value(radio_param_t param, radio_value_t *value)
     *value = OUTPUT_POWER_MAX;
     return RADIO_RESULT_OK;
   case RADIO_PARAM_LAST_RSSI:
-    *value = last_rssi;
+    *value = rf_core_last_rssi;
     return RADIO_RESULT_OK;
   case RADIO_PARAM_LAST_LINK_QUALITY:
-    *value = last_corr_lqi;
+    *value = rf_core_last_corr_lqi;
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_PHY_OVERHEAD:
+    *value = (radio_value_t)RADIO_PHY_OVERHEAD;
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_BYTE_AIR_TIME:
+    *value = (radio_value_t)RADIO_BYTE_AIR_TIME;
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_DELAY_BEFORE_TX:
+    *value = (radio_value_t)RADIO_DELAY_BEFORE_TX;
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_DELAY_BEFORE_RX:
+    *value = (radio_value_t)RADIO_DELAY_BEFORE_RX;
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_DELAY_BEFORE_DETECT:
+    *value = (radio_value_t)RADIO_DELAY_BEFORE_DETECT;
     return RADIO_RESULT_OK;
   default:
     return RADIO_RESULT_NOT_SUPPORTED;
@@ -1498,9 +1340,9 @@ set_value(radio_param_t param, radio_value_t value)
     cmd->frameFiltOpt.bPanCoord = 0;
     cmd->frameFiltOpt.bStrictLenFilter = 0;
 
-    old_poll_mode = poll_mode;
-    poll_mode = (value & RADIO_RX_MODE_POLL_MODE) != 0;
-    if(poll_mode == old_poll_mode) {
+    old_poll_mode = rf_core_poll_mode;
+    rf_core_poll_mode = (value & RADIO_RX_MODE_POLL_MODE) != 0;
+    if(rf_core_poll_mode == old_poll_mode) {
       uint32_t cmd_status;
 
       /* do not turn the radio on and off, just send an update command */
@@ -1552,7 +1394,7 @@ set_value(radio_param_t param, radio_value_t value)
   /* Restart the radio timer (RAT).
      This causes resynchronization between RAT and RTC: useful for TSCH. */
   if(rf_core_restart_rat() == RF_CORE_CMD_OK) {
-    check_rat_overflow(false);
+    rf_core_check_rat_overflow();
   }
 
   if(rx_on() != RF_CORE_CMD_OK) {
@@ -1590,7 +1432,7 @@ get_object(radio_param_t param, void *dest, size_t size)
     if(size != sizeof(rtimer_clock_t) || !dest) {
       return RADIO_RESULT_INVALID_VALUE;
     }
-    *(rtimer_clock_t *)dest = last_packet_timestamp;
+    *(rtimer_clock_t *)dest = rf_core_last_packet_timestamp;
 
     return RADIO_RESULT_OK;
   }

arch/cpu/cc26xx-cc13xx/rf-core/prop-mode.c

@@ -45,6 +45,7 @@
 #include "net/netstack.h"
 #include "sys/energest.h"
 #include "sys/clock.h"
+#include "sys/critical.h"
 #include "sys/rtimer.h"
 #include "sys/cc.h"
 #include "lpm.h"
@@ -114,24 +115,6 @@
  */
 #define RF_RADIO_OP_GET_STATUS(a) GET_FIELD_V(a, radioOp, status)
 /*---------------------------------------------------------------------------*/
-/* Special value returned by CMD_IEEE_CCA_REQ when an RSSI is not available */
-#define RF_CMD_CCA_REQ_RSSI_UNKNOWN     -128
-
-/* Used for the return value of channel_clear */
-#define RF_CCA_CLEAR                       1
-#define RF_CCA_BUSY                        0
-
-/* Used as an error return value for get_cca_info */
-#define RF_GET_CCA_INFO_ERROR           0xFF
-
-/*
- * Values of the individual bits of the ccaInfo field in CMD_IEEE_CCA_REQ's
- * status struct
- */
-#define RF_CMD_CCA_REQ_CCA_STATE_IDLE      0 /* 00 */
-#define RF_CMD_CCA_REQ_CCA_STATE_BUSY      1 /* 01 */
-#define RF_CMD_CCA_REQ_CCA_STATE_INVALID   2 /* 10 */
-
 #ifdef PROP_MODE_CONF_RSSI_THRESHOLD
 #define PROP_MODE_RSSI_THRESHOLD PROP_MODE_CONF_RSSI_THRESHOLD
 #else
@@ -140,6 +123,8 @@
 
 static int8_t rssi_threshold = PROP_MODE_RSSI_THRESHOLD;
 /*---------------------------------------------------------------------------*/
+static volatile uint8_t is_receiving_packet;
+/*---------------------------------------------------------------------------*/
 static int on(void);
 static int off(void);
 
@@ -169,12 +154,6 @@ static rfc_propRxOutput_t rx_stats;
 #define DOT_4G_PHR_DW_BIT 0
 #endif
 /*---------------------------------------------------------------------------*/
-/* How long to wait for an ongoing ACK TX to finish before starting frame TX */
-#define TX_WAIT_TIMEOUT       (RTIMER_SECOND >> 11)
-
-/* How long to wait for the RF to enter RX in rf_cmd_ieee_rx */
-#define ENTER_RX_WAIT_TIMEOUT (RTIMER_SECOND >> 10)
-/*---------------------------------------------------------------------------*/
 /* TX power table for the 431-527MHz band */
 #ifdef PROP_MODE_CONF_TX_POWER_431_527
 #define PROP_MODE_TX_POWER_431_527 PROP_MODE_CONF_TX_POWER_431_527
@@ -221,12 +200,29 @@ static const prop_mode_tx_power_config_t *tx_power_current = &TX_POWER_DRIVER[1]
 #define DATA_ENTRY_LENSZ_BYTE 1
 #define DATA_ENTRY_LENSZ_WORD 2 /* 2 bytes */
 
+/* The size of the metadata (excluding the packet length field) */
+#define RX_BUF_METADATA_SIZE \
+  (CRC_LEN * RF_CORE_RX_BUF_INCLUDE_CRC \
+      + RF_CORE_RX_BUF_INCLUDE_RSSI \
+      + RF_CORE_RX_BUF_INCLUDE_CORR \
+      + 4 * RF_CORE_RX_BUF_INCLUDE_TIMESTAMP)
+
+/* The offset of the packet length in a rx buffer */
+#define RX_BUF_LENGTH_OFFSET sizeof(rfc_dataEntry_t)
+/* The offset of the packet data in a rx buffer */
+#define RX_BUF_DATA_OFFSET (RX_BUF_LENGTH_OFFSET + DOT_4G_PHR_LEN)
+
+#define ALIGN_TO_4(size)	(((size) + 3) & ~3)
+
+#define RX_BUF_SIZE ALIGN_TO_4(RX_BUF_DATA_OFFSET          \
+      + NETSTACK_RADIO_MAX_PAYLOAD_LEN   \
+      + RX_BUF_METADATA_SIZE)
+
 /*
  * RX buffers.
  * PROP_MODE_RX_BUF_CNT buffers of RX_BUF_SIZE bytes each. The start of each
  * buffer must be 4-byte aligned, therefore RX_BUF_SIZE must divide by 4
  */
-#define RX_BUF_SIZE 140
 static uint8_t rx_buf[PROP_MODE_RX_BUF_CNT][RX_BUF_SIZE] CC_ALIGN(4);
 
 /* The RX Data Queue */
@@ -235,6 +231,12 @@ static dataQueue_t rx_data_queue = { 0 };
 /* Receive entry pointer to keep track of read items */
 volatile static uint8_t *rx_read_entry;
 /*---------------------------------------------------------------------------*/
+/*
+ * Increasing this number causes unicast Tx immediately after broadcast Rx to have
+ * negative synchronization errors ("dr" in TSCH logs); decreasing it: the opposite.
+ */
+#define RAT_TIMESTAMP_OFFSET_SUB_GHZ USEC_TO_RADIO(160 * 6 - 240)
+/*---------------------------------------------------------------------------*/
 /* The outgoing frame buffer */
 #define TX_BUF_PAYLOAD_LEN 180
 #define TX_BUF_HDR_LEN       2
@@ -271,13 +273,13 @@ get_rssi(void)
     was_off = 1;
     if(on() != RF_CORE_CMD_OK) {
       PRINTF("get_rssi: on() failed\n");
-      return RF_CMD_CCA_REQ_RSSI_UNKNOWN;
+      return RF_CORE_CMD_CCA_REQ_RSSI_UNKNOWN;
     }
   }
 
-  rssi = RF_CMD_CCA_REQ_RSSI_UNKNOWN;
+  rssi = RF_CORE_CMD_CCA_REQ_RSSI_UNKNOWN;
 
-  while((rssi == RF_CMD_CCA_REQ_RSSI_UNKNOWN || rssi == 0) && ++attempts < 10) {
+  while((rssi == RF_CORE_CMD_CCA_REQ_RSSI_UNKNOWN || rssi == 0) && ++attempts < 10) {
     memset(&cmd, 0x00, sizeof(cmd));
     cmd.commandNo = CMD_GET_RSSI;
 
@@ -419,13 +421,17 @@ static uint8_t
 rf_cmd_prop_rx()
 {
   uint32_t cmd_status;
-  rtimer_clock_t t0;
   volatile rfc_CMD_PROP_RX_ADV_t *cmd_rx_adv;
   int ret;
 
   cmd_rx_adv = (rfc_CMD_PROP_RX_ADV_t *)&smartrf_settings_cmd_prop_rx_adv;
   cmd_rx_adv->status = RF_CORE_RADIO_OP_STATUS_IDLE;
 
+  cmd_rx_adv->rxConf.bIncludeCrc = RF_CORE_RX_BUF_INCLUDE_CRC;
+  cmd_rx_adv->rxConf.bAppendRssi = RF_CORE_RX_BUF_INCLUDE_RSSI;
+  cmd_rx_adv->rxConf.bAppendTimestamp = RF_CORE_RX_BUF_INCLUDE_TIMESTAMP;
+  cmd_rx_adv->rxConf.bAppendStatus = RF_CORE_RX_BUF_INCLUDE_CORR;
+
   /*
    * Set the max Packet length. This is for the payload only, therefore
    * 2047 - length offset
@@ -440,10 +446,8 @@ rf_cmd_prop_rx()
     return RF_CORE_CMD_ERROR;
   }
 
-  t0 = RTIMER_NOW();
-
-  while(cmd_rx_adv->status != RF_CORE_RADIO_OP_STATUS_ACTIVE &&
-        (RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + ENTER_RX_WAIT_TIMEOUT)));
+  RTIMER_BUSYWAIT_UNTIL(cmd_rx_adv->status == RF_CORE_RADIO_OP_STATUS_ACTIVE,
+                        RF_CORE_ENTER_RX_TIMEOUT);
 
   /* Wait to enter RX */
   if(cmd_rx_adv->status != RF_CORE_RADIO_OP_STATUS_ACTIVE) {
@@ -505,13 +509,16 @@ rx_off_prop(void)
     return RF_CORE_CMD_OK;
   }
 
+  /* Wait for ongoing ACK TX to finish */
+  RTIMER_BUSYWAIT_UNTIL(!transmitting(), RF_CORE_TX_FINISH_TIMEOUT);
+
   /* Send a CMD_ABORT command to RF Core */
   if(rf_core_send_cmd(CMDR_DIR_CMD(CMD_ABORT), &cmd_status) != RF_CORE_CMD_OK) {
     PRINTF("rx_off_prop: CMD_ABORT status=0x%08lx\n", cmd_status);
     /* Continue nonetheless */
   }
 
-  while(rf_is_on());
+  RTIMER_BUSYWAIT_UNTIL(!rf_is_on(), RF_CORE_TURN_OFF_TIMEOUT);
 
   if(smartrf_settings_cmd_prop_rx_adv.status == PROP_DONE_STOPPED ||
      smartrf_settings_cmd_prop_rx_adv.status == PROP_DONE_ABORT) {
@@ -582,8 +589,8 @@ soft_off_prop(void)
     return;
   }
 
-  while((cmd->status & RF_CORE_RADIO_OP_MASKED_STATUS) ==
-        RF_CORE_RADIO_OP_MASKED_STATUS_RUNNING);
+  RTIMER_BUSYWAIT_UNTIL((cmd->status & RF_CORE_RADIO_OP_MASKED_STATUS) !=
+                         RF_CORE_RADIO_OP_MASKED_STATUS_RUNNING, RF_CORE_TURN_OFF_TIMEOUT);
 }
 /*---------------------------------------------------------------------------*/
 static uint8_t
@@ -605,6 +612,8 @@ soft_on_prop(void)
 static const rf_core_primary_mode_t mode_prop = {
   soft_off_prop,
   soft_on_prop,
+  rf_is_on,
+  RAT_TIMESTAMP_OFFSET_SUB_GHZ
 };
 /*---------------------------------------------------------------------------*/
 static int
@@ -629,17 +638,22 @@ init(void)
   smartrf_settings_cmd_prop_rx_adv.pQueue = &rx_data_queue;
   smartrf_settings_cmd_prop_rx_adv.pOutput = (uint8_t *)&rx_stats;
 
-  set_channel(RF_CORE_CHANNEL);
+  set_channel(IEEE802154_DEFAULT_CHANNEL);
 
   if(on() != RF_CORE_CMD_OK) {
     PRINTF("init: on() failed\n");
     return RF_CORE_CMD_ERROR;
   }
 
+  /* Enable the "sync word seen" interrupt */
+  ti_lib_rfc_hw_int_enable(RFC_DBELL_RFHWIEN_MDMSOFT);
+
   ENERGEST_ON(ENERGEST_TYPE_LISTEN);
 
   rf_core_primary_mode_register(&mode_prop);
 
+  rf_core_rat_init();
+
   process_start(&rf_core_process, NULL);
 
   return 1;
@@ -700,7 +714,7 @@ transmit(unsigned short transmit_len)
   rx_off_prop();
 
   /* Enable the LAST_COMMAND_DONE interrupt to wake us up */
-  rf_core_cmd_done_en(false, false);
+  rf_core_cmd_done_en(false);
 
   ret = rf_core_send_cmd((uint32_t)cmd_tx_adv, &cmd_status);
 
@@ -713,7 +727,14 @@ transmit(unsigned short transmit_len)
     /* Idle away while the command is running */
     while((cmd_tx_adv->status & RF_CORE_RADIO_OP_MASKED_STATUS)
           == RF_CORE_RADIO_OP_MASKED_STATUS_RUNNING) {
-      lpm_sleep();
+      /* Note: for now sleeping while Tx'ing in polling mode is disabled.
+       * To enable it:
+       *  1) make the `lpm_sleep()` call here unconditional;
+       *  2) change the radio ISR priority to allow radio ISR to interrupt rtimer ISR.
+       */
+      if(!rf_core_poll_mode) {
+        lpm_sleep();
+      }
     }
 
     if(cmd_tx_adv->status == RF_CORE_RADIO_OP_STATUS_PROP_DONE_OK) {
@@ -742,7 +763,7 @@ transmit(unsigned short transmit_len)
    * Disable LAST_FG_COMMAND_DONE interrupt. We don't really care about it
    * except when we are transmitting
    */
-  rf_core_cmd_done_dis(false);
+  rf_core_cmd_done_dis();
 
   /* Workaround. Set status to IDLE */
   cmd_tx_adv->status = RF_CORE_RADIO_OP_STATUS_IDLE;
@@ -763,38 +784,98 @@ send(const void *payload, unsigned short payload_len)
   return transmit(payload_len);
 }
 /*---------------------------------------------------------------------------*/
+static void
+release_data_entry(void)
+{
+  rfc_dataEntryGeneral_t *entry = (rfc_dataEntryGeneral_t *)rx_read_entry;
+  uint8_t *data_ptr = &entry->data;
+  int_master_status_t interrupt_status;
+
+  /* Clear the length field (2 bytes) */
+  data_ptr[0] = 0;
+  data_ptr[1] = 0;
+
+  /* Set status to 0 "Pending" in element */
+  entry->status = DATA_ENTRY_STATUS_PENDING;
+  rx_read_entry = entry->pNextEntry;
+
+  interrupt_status = critical_enter();
+  if(rf_core_rx_is_full) {
+    rf_core_rx_is_full = false;
+    PRINTF("RXQ was full, re-enabling radio!\n");
+    rx_on_prop();
+  }
+  critical_exit(interrupt_status);
+
+}
+/*---------------------------------------------------------------------------*/
 static int
 read_frame(void *buf, unsigned short buf_len)
 {
   rfc_dataEntryGeneral_t *entry = (rfc_dataEntryGeneral_t *)rx_read_entry;
   uint8_t *data_ptr = &entry->data;
   int len = 0;
+  uint32_t rat_timestamp;
 
-  if(entry->status == DATA_ENTRY_STATUS_FINISHED) {
+  /* wait for entry to become finished */
+  rtimer_clock_t t0 = RTIMER_NOW();
+  while(entry->status == DATA_ENTRY_STATUS_BUSY
+      && RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (RTIMER_SECOND / 50)));
 
-    /*
-     * First 2 bytes in the data entry are the length.
-     * Our data entry consists of: Payload + RSSI (1 byte) + Status (1 byte)
-     * This length includes all of those.
-     */
-    len = (*(uint16_t *)data_ptr);
-    data_ptr += 2;
-    len -= 2;
+  /* Make sure the flag is reset */
+  is_receiving_packet = 0;
 
-    if(len > 0) {
-      if(len <= buf_len) {
-        memcpy(buf, data_ptr, len);
-      }
-
-      packetbuf_set_attr(PACKETBUF_ATTR_RSSI, (int8_t)data_ptr[len]);
-      packetbuf_set_attr(PACKETBUF_ATTR_LINK_QUALITY, 0x7F);
-    }
-
-    /* Move read entry pointer to next entry */
-    rx_read_entry = entry->pNextEntry;
-    entry->status = DATA_ENTRY_STATUS_PENDING;
+  if(entry->status != DATA_ENTRY_STATUS_FINISHED) {
+    /* No available data */
+    return 0;
   }
 
+  /*
+   * First 2 bytes in the data entry are the length.
+   * Our data entry consists of:
+   *   Payload + RSSI (1 byte) + Timestamp (4 bytes) + Status (1 byte)
+   * This length includes all of those.
+   */
+  len = (*(uint16_t *)data_ptr);
+
+  if(len <= RX_BUF_METADATA_SIZE) {
+    PRINTF("RF: too short!");
+
+    release_data_entry();
+    return 0;
+  }
+
+  data_ptr += 2;
+  len -= RX_BUF_METADATA_SIZE;
+
+  if(len > buf_len) {
+    PRINTF("RF: too long\n");
+
+    release_data_entry();
+    return 0;
+  }
+
+  memcpy(buf, data_ptr, len);
+
+  /* get the RSSI and status */
+  rf_core_last_rssi = (int8_t)data_ptr[len];
+  rf_core_last_corr_lqi = data_ptr[len + 5];
+
+  /* get the timestamp */
+  memcpy(&rat_timestamp, data_ptr + len + 1, 4);
+
+  rf_core_last_packet_timestamp = rf_core_convert_rat_to_rtimer(rat_timestamp);
+
+  if(!rf_core_poll_mode) {
+    /* Not in poll mode: packetbuf should not be accessed in interrupt context.
+     * In poll mode, the last packet RSSI and link quality can be obtained through
+     * RADIO_PARAM_LAST_RSSI and RADIO_PARAM_LAST_LINK_QUALITY */
+    packetbuf_set_attr(PACKETBUF_ATTR_RSSI, rf_core_last_rssi);
+    packetbuf_set_attr(PACKETBUF_ATTR_LINK_QUALITY, rf_core_last_corr_lqi);
+  }
+
+  release_data_entry();
+
   return len;
 }
 /*---------------------------------------------------------------------------*/
@@ -803,14 +884,14 @@ channel_clear(void)
 {
   uint8_t was_off = 0;
   uint32_t cmd_status;
-  int8_t rssi = RF_CMD_CCA_REQ_RSSI_UNKNOWN;
+  int8_t rssi = RF_CORE_CMD_CCA_REQ_RSSI_UNKNOWN;
 
   /*
    * If we are in the middle of a BLE operation, we got called by ContikiMAC
    * from within an interrupt context. Indicate a clear channel
    */
   if(rf_ble_is_active() == RF_BLE_ACTIVE) {
-    return RF_CCA_CLEAR;
+    return RF_CORE_CCA_CLEAR;
   }
 
   if(!rf_core_is_accessible()) {
@@ -820,16 +901,16 @@ channel_clear(void)
       if(was_off) {
         off();
       }
-      return RF_CCA_CLEAR;
+      return RF_CORE_CCA_CLEAR;
     }
   } else {
     if(transmitting()) {
       PRINTF("channel_clear: called while in TX\n");
-      return RF_CCA_CLEAR;
+      return RF_CORE_CCA_CLEAR;
     }
   }
 
-  while(rssi == RF_CMD_CCA_REQ_RSSI_UNKNOWN || rssi == 0) {
+  while(rssi == RF_CORE_CMD_CCA_REQ_RSSI_UNKNOWN || rssi == 0) {
     if(rf_core_send_cmd(CMDR_DIR_CMD(CMD_GET_RSSI), &cmd_status)
        != RF_CORE_CMD_OK) {
       break;
@@ -843,10 +924,10 @@ channel_clear(void)
   }
 
   if(rssi >= rssi_threshold) {
-    return RF_CCA_BUSY;
+    return RF_CORE_CCA_BUSY;
   }
 
-  return RF_CCA_CLEAR;
+  return RF_CORE_CCA_CLEAR;
 }
 /*---------------------------------------------------------------------------*/
 static int
@@ -856,11 +937,23 @@ receiving_packet(void)
     return 0;
   }
 
-  if(channel_clear() == RF_CCA_CLEAR) {
-    return 0;
+  if(!is_receiving_packet) {
+    /* Look for the modem synchronization word detection interrupt flag.
+     * This flag is raised when the synchronization word is received.
+     */
+    if(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) & RFC_DBELL_RFHWIFG_MDMSOFT) {
+      is_receiving_packet = 1;
+    }
+  } else {
+    /* After the start of the packet: reset the Rx flag once the channel gets clear */
+    is_receiving_packet = (channel_clear() == RF_CORE_CCA_BUSY);
+    if(!is_receiving_packet) {
+      /* Clear the modem sync flag */
+      ti_lib_rfc_hw_int_clear(RFC_DBELL_RFHWIFG_MDMSOFT);
+    }
   }
 
-  return 1;
+  return is_receiving_packet;
 }
 /*---------------------------------------------------------------------------*/
 static int
@@ -871,9 +964,12 @@ pending_packet(void)
 
   /* Go through all RX buffers and check their status */
   do {
-    if(entry->status == DATA_ENTRY_STATUS_FINISHED) {
-      rv += 1;
-      process_poll(&rf_core_process);
+    if(entry->status == DATA_ENTRY_STATUS_FINISHED
+        || entry->status == DATA_ENTRY_STATUS_BUSY) {
+      rv = 1;
+      if(!rf_core_poll_mode) {
+        process_poll(&rf_core_process);
+      }
     }
 
     entry = (rfc_dataEntry_t *)entry->pNextEntry;
@@ -894,18 +990,18 @@ on(void)
     return RF_CORE_CMD_OK;
   }
 
-  /*
-   * Request the HF XOSC as the source for the HF clock. Needed before we can
-   * use the FS. This will only request, it will _not_ perform the switch.
-   */
-  oscillators_request_hf_xosc();
-
   if(rf_is_on()) {
     PRINTF("on: We were on. PD=%u, RX=0x%04x \n", rf_core_is_accessible(),
            smartrf_settings_cmd_prop_rx_adv.status);
     return RF_CORE_CMD_OK;
   }
 
+  /*
+   * Request the HF XOSC as the source for the HF clock. Needed before we can
+   * use the FS. This will only request, it will _not_ perform the switch.
+   */
+  oscillators_request_hf_xosc();
+
   if(!rf_core_is_accessible()) {
     if(rf_core_power_up() != RF_CORE_CMD_OK) {
       PRINTF("on: rf_core_power_up() failed\n");
@@ -948,7 +1044,7 @@ on(void)
     }
   }
 
-  rf_core_setup_interrupts(false);
+  rf_core_setup_interrupts();
 
   init_rx_buffers();
 
@@ -975,6 +1071,9 @@ on(void)
 static int
 off(void)
 {
+  int i;
+  rfc_dataEntry_t *entry;
+
   /*
    * If we are in the middle of a BLE operation, we got called by ContikiMAC
    * from within an interrupt context. Abort, but pretend everything is OK.
@@ -988,15 +1087,39 @@ off(void)
 
   ENERGEST_OFF(ENERGEST_TYPE_LISTEN);
 
+#if !CC2650_FAST_RADIO_STARTUP
   /* Switch HF clock source to the RCOSC to preserve power */
   oscillators_switch_to_hf_rc();
+#endif
 
   /* We pulled the plug, so we need to restore the status manually */
   smartrf_settings_cmd_prop_rx_adv.status = RF_CORE_RADIO_OP_STATUS_IDLE;
 
+  /*
+   * Just in case there was an ongoing RX (which started after we begun the
+   * shutdown sequence), we don't want to leave the buffer in state == ongoing
+   */
+  for(i = 0; i < PROP_MODE_RX_BUF_CNT; i++) {
+    entry = (rfc_dataEntry_t *)rx_buf[i];
+    if(entry->status == DATA_ENTRY_STATUS_BUSY) {
+       entry->status = DATA_ENTRY_STATUS_PENDING;
+    }
+  }
+
   return RF_CORE_CMD_OK;
 }
 /*---------------------------------------------------------------------------*/
+/* Enable or disable CCA before sending */
+static radio_result_t
+set_send_on_cca(uint8_t enable)
+{
+  if(enable) {
+    /* this driver does not have support for CCA on Tx */
+    return RADIO_RESULT_NOT_SUPPORTED;
+  }
+  return RADIO_RESULT_OK;
+}
+/*---------------------------------------------------------------------------*/
 static radio_result_t
 get_value(radio_param_t param, radio_value_t *value)
 {
@@ -1012,6 +1135,15 @@ get_value(radio_param_t param, radio_value_t *value)
   case RADIO_PARAM_CHANNEL:
     *value = (radio_value_t)get_channel();
     return RADIO_RESULT_OK;
+  case RADIO_PARAM_RX_MODE:
+    *value = 0;
+    if(rf_core_poll_mode) {
+      *value |= RADIO_RX_MODE_POLL_MODE;
+    }
+    return RADIO_RESULT_OK;
+  case RADIO_PARAM_TX_MODE:
+    *value = 0;
+    return RADIO_RESULT_OK;
   case RADIO_PARAM_TXPOWER:
     *value = get_tx_power();
     return RADIO_RESULT_OK;
@@ -1021,7 +1153,7 @@ get_value(radio_param_t param, radio_value_t *value)
   case RADIO_PARAM_RSSI:
     *value = get_rssi();
 
-    if(*value == RF_CMD_CCA_REQ_RSSI_UNKNOWN) {
+    if(*value == RF_CORE_CMD_CCA_REQ_RSSI_UNKNOWN) {
       return RADIO_RESULT_ERROR;
     } else {
       return RADIO_RESULT_OK;
@@ -1038,6 +1170,28 @@ get_value(radio_param_t param, radio_value_t *value)
   case RADIO_CONST_TXPOWER_MAX:
     *value = OUTPUT_POWER_MAX;
     return RADIO_RESULT_OK;
+  case RADIO_PARAM_LAST_RSSI:
+    *value = rf_core_last_rssi;
+    return RADIO_RESULT_OK;
+  case RADIO_PARAM_LAST_LINK_QUALITY:
+    *value = rf_core_last_corr_lqi;
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_PHY_OVERHEAD:
+    /* 2 header bytes, 2 or 4 bytes CRC */
+    *value = (radio_value_t)(DOT_4G_PHR_LEN + CRC_LEN);
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_BYTE_AIR_TIME:
+    *value = (radio_value_t)RADIO_BYTE_AIR_TIME;
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_DELAY_BEFORE_TX:
+    *value = (radio_value_t)RADIO_DELAY_BEFORE_TX;
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_DELAY_BEFORE_RX:
+    *value = (radio_value_t)RADIO_DELAY_BEFORE_RX;
+    return RADIO_RESULT_OK;
+  case RADIO_CONST_DELAY_BEFORE_DETECT:
+    *value = (radio_value_t)RADIO_DELAY_BEFORE_DETECT;
+    return RADIO_RESULT_OK;
   default:
     return RADIO_RESULT_NOT_SUPPORTED;
   }
@@ -1046,8 +1200,8 @@ get_value(radio_param_t param, radio_value_t *value)
 static radio_result_t
 set_value(radio_param_t param, radio_value_t value)
 {
-  uint8_t was_off = 0;
   radio_result_t rv = RADIO_RESULT_OK;
+  uint8_t old_poll_mode;
 
   switch(param) {
   case RADIO_PARAM_POWER_MODE:
@@ -1077,6 +1231,25 @@ set_value(radio_param_t param, radio_value_t value)
 
     set_channel((uint8_t)value);
     break;
+
+  case RADIO_PARAM_RX_MODE:
+    if(value & ~(RADIO_RX_MODE_POLL_MODE)) {
+      return RADIO_RESULT_INVALID_VALUE;
+    }
+
+    old_poll_mode = rf_core_poll_mode;
+    rf_core_poll_mode = (value & RADIO_RX_MODE_POLL_MODE) != 0;
+    if(rf_core_poll_mode == old_poll_mode) {
+      return RADIO_RESULT_OK;
+    }
+    break;
+
+  case RADIO_PARAM_TX_MODE:
+    if(value & ~(RADIO_TX_MODE_SEND_ON_CCA)) {
+      return RADIO_RESULT_INVALID_VALUE;
+    }
+    return set_send_on_cca((value & RADIO_TX_MODE_SEND_ON_CCA) != 0);
+
   case RADIO_PARAM_TXPOWER:
     if(value < TX_POWER_DRIVER[get_tx_power_array_last_element()].dbm ||
        value > OUTPUT_POWER_MAX) {
@@ -1093,8 +1266,7 @@ set_value(radio_param_t param, radio_value_t value)
     }
 
     return RADIO_RESULT_OK;
-  case RADIO_PARAM_RX_MODE:
-    return RADIO_RESULT_OK;
+
   case RADIO_PARAM_CCA_THRESHOLD:
     rssi_threshold = (int8_t)value;
     break;
@@ -1102,28 +1274,29 @@ set_value(radio_param_t param, radio_value_t value)
     return RADIO_RESULT_NOT_SUPPORTED;
   }
 
-  /* If we reach here we had no errors. Apply new settings */
+  /* If off, the new configuration will be applied the next time radio is started */
   if(!rf_is_on()) {
-    was_off = 1;
-    if(on() != RF_CORE_CMD_OK) {
-      PRINTF("set_value: on() failed (2)\n");
-      return RADIO_RESULT_ERROR;
-    }
+    return RADIO_RESULT_OK;
   }
 
+  /* If we reach here we had no errors. Apply new settings */
   if(rx_off_prop() != RF_CORE_CMD_OK) {
     PRINTF("set_value: rx_off_prop() failed\n");
     rv = RADIO_RESULT_ERROR;
   }
 
-  if(soft_on_prop() != RF_CORE_CMD_OK) {
-    PRINTF("set_value: rx_on_prop() failed\n");
-    rv = RADIO_RESULT_ERROR;
+  /* Restart the radio timer (RAT).
+     This causes resynchronization between RAT and RTC: useful for TSCH. */
+  if(rf_core_restart_rat() != RF_CORE_CMD_OK) {
+    PRINTF("set_value: rf_core_restart_rat() failed\n");
+    /* do not set the error */
+  } else {
+    rf_core_check_rat_overflow();
   }
 
-  /* If we were off, turn back off */
-  if(was_off) {
-    off();
+  if(soft_on_prop() != RF_CORE_CMD_OK) {
+    PRINTF("set_value: soft_on_prop() failed\n");
+    rv = RADIO_RESULT_ERROR;
   }
 
   return rv;
@@ -1132,6 +1305,15 @@ set_value(radio_param_t param, radio_value_t value)
 static radio_result_t
 get_object(radio_param_t param, void *dest, size_t size)
 {
+  if(param == RADIO_PARAM_LAST_PACKET_TIMESTAMP) {
+    if(size != sizeof(rtimer_clock_t) || !dest) {
+      return RADIO_RESULT_INVALID_VALUE;
+    }
+    *(rtimer_clock_t *)dest = rf_core_last_packet_timestamp;
+
+    return RADIO_RESULT_OK;
+  }
+
   return RADIO_RESULT_NOT_SUPPORTED;
 }
 /*---------------------------------------------------------------------------*/

arch/cpu/cc26xx-cc13xx/rf-core/rf-core.c

@@ -76,7 +76,7 @@
 /*---------------------------------------------------------------------------*/
 /* RF interrupts */
 #define RX_FRAME_IRQ IRQ_RX_ENTRY_DONE
-#define ERROR_IRQ    IRQ_INTERNAL_ERROR
+#define ERROR_IRQ    (IRQ_INTERNAL_ERROR | IRQ_RX_BUF_FULL)
 #define RX_NOK_IRQ   IRQ_RX_NOK
 
 /* Those IRQs are enabled all the time */
@@ -99,9 +99,37 @@ static rfc_radioOp_t *last_radio_op = NULL;
 /* A struct holding pointers to the primary mode's abort() and restore() */
 static const rf_core_primary_mode_t *primary_mode = NULL;
 /*---------------------------------------------------------------------------*/
+/* RAT has 32-bit register, overflows once 18 minutes */
+#define RAT_RANGE  4294967296ull
+/* approximate value */
+#define RAT_OVERFLOW_PERIOD_SECONDS (60 * 18)
+
+/* how often to check for the overflow, as a minimum */
+#define RAT_OVERFLOW_TIMER_INTERVAL (CLOCK_SECOND * RAT_OVERFLOW_PERIOD_SECONDS / 3)
+
 /* Radio timer (RAT) offset as compared to the rtimer counter (RTC) */
-int32_t rat_offset = 0;
-static bool rat_offset_known = false;
+static int32_t rat_offset;
+static bool rat_offset_known;
+
+/* Value during the last read of the RAT register */
+static uint32_t rat_last_value;
+
+/* For RAT overflow handling */
+static struct ctimer rat_overflow_timer;
+static volatile uint32_t rat_overflow_counter;
+static rtimer_clock_t rat_last_overflow;
+
+static void rat_overflow_check_timer_cb(void *);
+/*---------------------------------------------------------------------------*/
+volatile int8_t rf_core_last_rssi = RF_CORE_CMD_CCA_REQ_RSSI_UNKNOWN;
+volatile uint8_t rf_core_last_corr_lqi = 0;
+volatile uint32_t rf_core_last_packet_timestamp = 0;
+/*---------------------------------------------------------------------------*/
+/* Are we currently in poll mode? */
+uint8_t rf_core_poll_mode = 0;
+/*---------------------------------------------------------------------------*/
+/* Buffer full flag */
+volatile bool rf_core_rx_is_full = false;
 /*---------------------------------------------------------------------------*/
 PROCESS(rf_core_process, "CC13xx / CC26xx RF driver");
 /*---------------------------------------------------------------------------*/
@@ -396,6 +424,11 @@ rf_core_set_modesel()
   } else if(chip_type == CHIP_TYPE_CC1350) {
     HWREG(PRCM_BASE + PRCM_O_RFCMODESEL) = PRCM_RFCMODESEL_CURR_MODE5;
     rv = RF_CORE_CMD_OK;
+#if CPU_FAMILY_CC26X0R2
+  } else if(chip_type == CHIP_TYPE_CC2640R2) {
+    HWREG(PRCM_BASE + PRCM_O_RFCMODESEL) = PRCM_RFCMODESEL_CURR_MODE1;
+    rv = RF_CORE_CMD_OK;
+#endif
   }
 
   return rv;
@@ -443,10 +476,10 @@ rf_core_restart_rat(void)
 }
 /*---------------------------------------------------------------------------*/
 void
-rf_core_setup_interrupts(bool poll_mode)
+rf_core_setup_interrupts(void)
 {
   bool interrupts_disabled;
-  const uint32_t enabled_irqs = poll_mode ? ENABLED_IRQS_POLL_MODE : ENABLED_IRQS;
+  const uint32_t enabled_irqs = rf_core_poll_mode ? ENABLED_IRQS_POLL_MODE : ENABLED_IRQS;
 
   /* We are already turned on by the caller, so this should not happen */
   if(!rf_core_is_accessible()) {
@@ -477,19 +510,23 @@ rf_core_setup_interrupts(bool poll_mode)
 }
 /*---------------------------------------------------------------------------*/
 void
-rf_core_cmd_done_en(bool fg, bool poll_mode)
+rf_core_cmd_done_en(bool fg)
 {
-  uint32_t irq = fg ? IRQ_LAST_FG_COMMAND_DONE : IRQ_LAST_COMMAND_DONE;
-  const uint32_t enabled_irqs = poll_mode ? ENABLED_IRQS_POLL_MODE : ENABLED_IRQS;
+  uint32_t irq = 0;
+  const uint32_t enabled_irqs = rf_core_poll_mode ? ENABLED_IRQS_POLL_MODE : ENABLED_IRQS;
+
+  if(!rf_core_poll_mode) {
+    irq = fg ? IRQ_LAST_FG_COMMAND_DONE : IRQ_LAST_COMMAND_DONE;
+  }
 
   HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = enabled_irqs;
   HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIEN) = enabled_irqs | irq;
 }
 /*---------------------------------------------------------------------------*/
 void
-rf_core_cmd_done_dis(bool poll_mode)
+rf_core_cmd_done_dis(void)
 {
-  const uint32_t enabled_irqs = poll_mode ? ENABLED_IRQS_POLL_MODE : ENABLED_IRQS;
+  const uint32_t enabled_irqs = rf_core_poll_mode ? ENABLED_IRQS_POLL_MODE : ENABLED_IRQS;
   HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIEN) = enabled_irqs;
 }
 /*---------------------------------------------------------------------------*/
@@ -536,6 +573,123 @@ rf_core_primary_mode_restore()
   return RF_CORE_CMD_ERROR;
 }
 /*---------------------------------------------------------------------------*/
+uint8_t
+rf_core_rat_init(void)
+{
+  rat_last_value = HWREG(RFC_RAT_BASE + RATCNT);
+
+  ctimer_set(&rat_overflow_timer, RAT_OVERFLOW_TIMER_INTERVAL,
+             rat_overflow_check_timer_cb, NULL);
+
+  return 1;
+}
+/*---------------------------------------------------------------------------*/
+uint8_t
+rf_core_check_rat_overflow(void)
+{
+  uint32_t rat_current_value;
+  uint8_t interrupts_disabled;
+
+  /* Bail out if the RF is not on */
+  if(primary_mode == NULL || !primary_mode->is_on()) {
+    return 0;
+  }
+
+  interrupts_disabled = ti_lib_int_master_disable();
+
+  rat_current_value = HWREG(RFC_RAT_BASE + RATCNT);
+  if(rat_current_value + RAT_RANGE / 4 < rat_last_value) {
+    /* Overflow detected */
+    rat_last_overflow = RTIMER_NOW();
+    rat_overflow_counter++;
+  }
+  rat_last_value = rat_current_value;
+
+  if(!interrupts_disabled) {
+    ti_lib_int_master_enable();
+  }
+
+  return 1;
+}
+/*---------------------------------------------------------------------------*/
+static void
+rat_overflow_check_timer_cb(void *unused)
+{
+  uint8_t success = 0;
+  uint8_t was_off = 0;
+
+  if(primary_mode != NULL) {
+
+    if(!primary_mode->is_on()) {
+      was_off = 1;
+      if(NETSTACK_RADIO.on() != RF_CORE_CMD_OK) {
+        PRINTF("overflow: on() failed\n");
+        ctimer_set(&rat_overflow_timer, CLOCK_SECOND,
+                   rat_overflow_check_timer_cb, NULL);
+        return;
+      }
+    }
+
+    success = rf_core_check_rat_overflow();
+
+    if(was_off) {
+      NETSTACK_RADIO.off();
+    }
+  }
+
+  if(success) {
+    /* Retry after half of the interval */
+    ctimer_set(&rat_overflow_timer, RAT_OVERFLOW_TIMER_INTERVAL,
+               rat_overflow_check_timer_cb, NULL);
+  } else {
+    /* Retry sooner */
+    ctimer_set(&rat_overflow_timer, CLOCK_SECOND,
+               rat_overflow_check_timer_cb, NULL);
+  }
+}
+/*---------------------------------------------------------------------------*/
+uint32_t
+rf_core_convert_rat_to_rtimer(uint32_t rat_timestamp)
+{
+  uint64_t rat_timestamp64;
+  uint32_t adjusted_overflow_counter;
+  uint8_t was_off = 0;
+
+  if(primary_mode == NULL) {
+    PRINTF("rf_core_convert_rat_to_rtimer: not initialized\n");
+    return 0;
+  }
+
+  if(!primary_mode->is_on()) {
+    was_off = 1;
+    NETSTACK_RADIO.on();
+  }
+
+  rf_core_check_rat_overflow();
+
+  if(was_off) {
+    NETSTACK_RADIO.off();
+  }
+
+  adjusted_overflow_counter = rat_overflow_counter;
+
+  /* if the timestamp is large and the last oveflow was recently,
+     assume that the timestamp refers to the time before the overflow */
+  if(rat_timestamp > (uint32_t)(RAT_RANGE * 3 / 4)) {
+    if(RTIMER_CLOCK_LT(RTIMER_NOW(),
+                       rat_last_overflow + RAT_OVERFLOW_PERIOD_SECONDS * RTIMER_SECOND / 4)) {
+      adjusted_overflow_counter--;
+    }
+  }
+
+  /* add the overflowed time to the timestamp */
+  rat_timestamp64 = rat_timestamp + RAT_RANGE * adjusted_overflow_counter;
+  /* correct timestamp so that it refers to the end of the SFD */
+  rat_timestamp64 += primary_mode->sfd_timestamp_offset;
+
+  return RADIO_TO_RTIMER(rat_timestamp64 - rat_offset);
+}
+/*---------------------------------------------------------------------------*/
 PROCESS_THREAD(rf_core_process, ev, data)
 {
   int len;
@@ -575,6 +729,16 @@ cc26xx_rf_cpe1_isr(void)
     }
   }
 
+  if(HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) & IRQ_RX_BUF_FULL) {
+    PRINTF("\nRF: BUF_FULL\n\n");
+    /* set a flag that the buffer is full*/
+    rf_core_rx_is_full = true;
+    /* make sure read_frame() will be called to make space in RX buffer */
+    process_poll(&rf_core_process);
+    /* Clear the IRQ_RX_BUF_FULL interrupt flag by writing zero to bit */
+    HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = ~(IRQ_RX_BUF_FULL);
+  }
+
   /* Clear INTERNAL_ERROR interrupt flag */
   HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = 0x7FFFFFFF;
 }

arch/cpu/cc26xx-cc13xx/rf-core/rf-core.h

@@ -57,13 +57,6 @@
 #include <stdint.h>
 #include <stdbool.h>
 /*---------------------------------------------------------------------------*/
-/* The channel to use in IEEE or prop mode. */
-#ifdef RF_CORE_CONF_CHANNEL
-#define RF_CORE_CHANNEL RF_CORE_CONF_CHANNEL
-#else
-#define RF_CORE_CHANNEL 25
-#endif /* RF_CORE_CONF_IEEE_MODE_CHANNEL */
-/*---------------------------------------------------------------------------*/
 #define RF_CORE_FRONT_END_MODE_DIFFERENTIAL   0
 #define RF_CORE_FRONT_END_MODE_SINGLE_RFP     1
 #define RF_CORE_FRONT_END_MODE_SINGLE_RFN     2
@@ -140,6 +133,17 @@ typedef struct rf_core_primary_mode_s {
    * \return RF_CORE_CMD_OK or RF_CORE_CMD_ERROR
    */
   uint8_t (*restore)(void);
+
+  /**
+   * \brief A pointer to a function that checks if the radio is on
+   * \return 1 or 0
+   */
+  uint8_t (*is_on)(void);
+
+  /**
+   * \brief Offset of the end of SFD when compared to the radio HW-generated timestamp
+   */
+   int16_t sfd_timestamp_offset;
 } rf_core_primary_mode_t;
 /*---------------------------------------------------------------------------*/
 /* RF Command status constants - Correspond to values in the CMDSTA register */
@@ -269,10 +273,66 @@ typedef struct rf_core_primary_mode_s {
 /*---------------------------------------------------------------------------*/
 /* Radio timer register */
 #define RATCNT  0x00000004
+/*---------------------------------------------------------------------------*/
+/* Special value returned by CMD_IEEE_CCA_REQ when an RSSI is not available */
+#define RF_CORE_CMD_CCA_REQ_RSSI_UNKNOWN     -128
+
+/* Used for the return value of channel_clear */
+#define RF_CORE_CCA_CLEAR                       1
+#define RF_CORE_CCA_BUSY                        0
+
+/* Used as an error return value for get_cca_info */
+#define RF_CORE_GET_CCA_INFO_ERROR           0xFF
+
+/*
+ * Values of the individual bits of the ccaInfo field in CMD_IEEE_CCA_REQ's
+ * status struct
+ */
+#define RF_CORE_CMD_CCA_REQ_CCA_STATE_IDLE      0 /* 00 */
+#define RF_CORE_CMD_CCA_REQ_CCA_STATE_BUSY      1 /* 01 */
+#define RF_CORE_CMD_CCA_REQ_CCA_STATE_INVALID   2 /* 10 */
+
+#define RF_CORE_CMD_CCA_REQ_CCA_CORR_IDLE       (0 << 4)
+#define RF_CORE_CMD_CCA_REQ_CCA_CORR_BUSY       (1 << 4)
+#define RF_CORE_CMD_CCA_REQ_CCA_CORR_INVALID    (3 << 4)
+#define RF_CORE_CMD_CCA_REQ_CCA_CORR_MASK       (3 << 4)
+
+#define RF_CORE_CMD_CCA_REQ_CCA_SYNC_BUSY       (1 << 6)
+/*---------------------------------------------------------------------------*/
+#define RF_CORE_RX_BUF_INCLUDE_CRC 0
+#define RF_CORE_RX_BUF_INCLUDE_RSSI 1
+#define RF_CORE_RX_BUF_INCLUDE_CORR 1
+#define RF_CORE_RX_BUF_INCLUDE_TIMESTAMP 1
+/*---------------------------------------------------------------------------*/
+/* How long to wait for an ongoing ACK TX to finish before starting frame TX */
+#define RF_CORE_TX_TIMEOUT       (RTIMER_SECOND >> 11)
+
+/* How long to wait for the RF to enter RX in rf_cmd_ieee_rx */
+#define RF_CORE_ENTER_RX_TIMEOUT (RTIMER_SECOND >> 10)
+
+/* How long to wait for the RF to react on CMD_ABORT: around 1 msec */
+#define RF_CORE_TURN_OFF_TIMEOUT (RTIMER_SECOND >> 10)
+
+/* How long to wait for the RF to finish TX of a packet or an ACK */
+#define RF_CORE_TX_FINISH_TIMEOUT (RTIMER_SECOND >> 7)
+
 /*---------------------------------------------------------------------------*/
 /* Make the main driver process visible to mode drivers */
 PROCESS_NAME(rf_core_process);
 /*---------------------------------------------------------------------------*/
+/* Buffer full flag */
+extern volatile bool rf_core_rx_is_full;
+/*---------------------------------------------------------------------------*/
+/* RSSI of the last read frame */
+extern volatile int8_t rf_core_last_rssi;
+/* Correlation/LQI of the last read frame */
+extern volatile uint8_t rf_core_last_corr_lqi;
+/* SFD timestamp of the last read frame, in rtimer ticks */
+extern volatile uint32_t rf_core_last_packet_timestamp;
+/*---------------------------------------------------------------------------*/
+/* Are we currently in poll mode? */
+extern uint8_t rf_core_poll_mode;
+/*---------------------------------------------------------------------------*/
 /**
  * \brief Check whether the RF core is accessible
  * \retval RF_CORE_ACCESSIBLE The core is powered and ready for access
@@ -387,20 +447,19 @@ uint8_t rf_core_boot(void);
 /**
  * \brief Setup RF core interrupts
  */
-void rf_core_setup_interrupts(bool poll_mode);
+void rf_core_setup_interrupts(void);
 
 /**
  * \brief Enable interrupt on command done.
  * \param fg set true to enable irq on foreground command done and false for
  * background commands or if not in ieee mode.
- * \param poll_mode true if the driver is in poll mode
  *
  * This is used within TX routines in order to be able to sleep the CM3 and
  * wake up after TX has finished
  *
  * \sa rf_core_cmd_done_dis()
  */
-void rf_core_cmd_done_en(bool fg, bool poll_mode);
+void rf_core_cmd_done_en(bool fg);
 
 /**
  * \brief Disable the LAST_CMD_DONE and LAST_FG_CMD_DONE interrupts.
@@ -409,7 +468,7 @@ void rf_core_cmd_done_en(bool fg, bool poll_mode);
  *
  * \sa rf_core_cmd_done_en()
  */
-void rf_core_cmd_done_dis(bool poll_mode);
+void rf_core_cmd_done_dis(void);
 
 /**
  * \brief Returns a pointer to the most recent proto-dependent Radio Op
@@ -471,6 +530,22 @@ void rf_core_primary_mode_abort(void);
  * \brief Abort the currently running primary radio op
  */
 uint8_t rf_core_primary_mode_restore(void);
+
+/**
+ * \brief Initialize the RAT to RTC conversion machinery
+ */
+uint8_t rf_core_rat_init(void);
+
+/**
+ * \brief Check if RAT overflow has occured and increment the overflow counter if so
+ */
+uint8_t rf_core_check_rat_overflow(void);
+
+/**
+ * \brief Convert from RAT timestamp to rtimer ticks
+ */
+uint32_t rf_core_convert_rat_to_rtimer(uint32_t rat_timestamp);
+
 /*---------------------------------------------------------------------------*/
 #endif /* RF_CORE_H_ */
 /*---------------------------------------------------------------------------*/

arch/cpu/cc26xx-cc13xx/ti-lib-rom.h

@@ -1,193 +0,0 @@
-/*
- * Copyright (c) 2016, Texas Instruments Incorporated - http://www.ti.com/
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the copyright holder nor the names of its
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
- * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
- * OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/*---------------------------------------------------------------------------*/
-/**
- * \addtogroup cc26xx-ti-lib
- * @{
- *
- * \file
- * Header file with CC13xxware/CC26xxware ROM API.
- */
-/*---------------------------------------------------------------------------*/
-#ifndef TI_LIB_ROM_H_
-#define TI_LIB_ROM_H_
-/*---------------------------------------------------------------------------*/
-/* rom.h */
-#include "driverlib/rom.h"
-
-/* AON API */
-#define ti_lib_rom_aon_event_mcu_wake_up_set          ROM_AONEventMcuWakeUpSet
-#define ti_lib_rom_aon_event_mcu_wake_up_get          ROM_AONEventMcuWakeUpGet
-#define ti_lib_rom_aon_event_aux_wake_up_set          ROM_AONEventAuxWakeUpSet
-#define ti_lib_rom_aon_event_aux_wake_up_get          ROM_AONEventAuxWakeUpGet
-#define ti_lib_rom_aon_event_mcu_set                  ROM_AONEventMcuSet
-#define ti_lib_rom_aon_event_mcu_get                  ROM_AONEventMcuGet
-
-/* AON_WUC API */
-#define ti_lib_rom_aon_wuc_aux_reset                  ROM_AONWUCAuxReset
-#define ti_lib_rom_aon_wuc_recharge_ctrl_config_set   ROM_AONWUCRechargeCtrlConfigSet
-#define ti_lib_rom_aon_wuc_osc_config                 ROM_AONWUCOscConfig
-
-/* AUX_TDC API */
-#define ti_lib_rom_aux_tdc_config_set                 ROM_AUXTDCConfigSet
-#define ti_lib_rom_aux_tdc_measurement_done           ROM_AUXTDCMeasurementDone
-
-/* AUX_WUC API */
-#define ti_lib_rom_aux_wuc_clock_enable               ROM_AUXWUCClockEnable
-#define ti_lib_rom_aux_wuc_clock_disable              ROM_AUXWUCClockDisable
-#define ti_lib_rom_aux_wuc_clock_status               ROM_AUXWUCClockStatus
-#define ti_lib_rom_aux_wuc_power_ctrl                 ROM_AUXWUCPowerCtrl
-
-/* FLASH API */
-#define ti_lib_rom_flash_power_mode_get               ROM_FlashPowerModeGet
-#define ti_lib_rom_flash_protection_set               ROM_FlashProtectionSet
-#define ti_lib_rom_flash_protection_get               ROM_FlashProtectionGet
-#define ti_lib_rom_flash_protection_save              ROM_FlashProtectionSave
-#define ti_lib_rom_flash_efuse_read_row               ROM_FlashEfuseReadRow
-#define ti_lib_rom_flash_disable_sectors_for_write    ROM_FlashDisableSectorsForWrite
-
-/* I2C API */
-#define ti_lib_rom_i2c_master_init_exp_clk            ROM_I2CMasterInitExpClk
-#define ti_lib_rom_i2c_master_err                     ROM_I2CMasterErr
-
-/* INTERRUPT API */
-#define ti_lib_rom_int_priority_grouping_set          ROM_IntPriorityGroupingSet
-#define ti_lib_rom_int_priority_grouping_get          ROM_IntPriorityGroupingGet
-#define ti_lib_rom_int_priority_set                   ROM_IntPrioritySet
-#define ti_lib_rom_int_priority_get                   ROM_IntPriorityGet
-#define ti_lib_rom_int_enable                         ROM_IntEnable
-#define ti_lib_rom_int_disable                        ROM_IntDisable
-#define ti_lib_rom_int_pend_set                       ROM_IntPendSet
-#define ti_lib_rom_int_pend_get                       ROM_IntPendGet
-#define ti_lib_rom_int_pend_clear                     ROM_IntPendClear
-
-/* IOC API */
-#define ti_lib_rom_ioc_port_configure_set             ROM_IOCPortConfigureSet
-#define ti_lib_rom_ioc_port_configure_get             ROM_IOCPortConfigureGet
-#define ti_lib_rom_ioc_io_shutdown_set                ROM_IOCIOShutdownSet
-#define ti_lib_rom_ioc_io_mode_set                    ROM_IOCIOModeSet
-#define ti_lib_rom_ioc_io_int_set                     ROM_IOCIOIntSet
-#define ti_lib_rom_ioc_io_port_pull_set               ROM_IOCIOPortPullSet
-#define ti_lib_rom_ioc_io_hyst_set                    ROM_IOCIOHystSet
-#define ti_lib_rom_ioc_io_input_set                   ROM_IOCIOInputSet
-#define ti_lib_rom_ioc_io_slew_ctrl_set               ROM_IOCIOSlewCtrlSet
-#define ti_lib_rom_ioc_io_drv_strength_set            ROM_IOCIODrvStrengthSet
-#define ti_lib_rom_ioc_io_port_id_set                 ROM_IOCIOPortIdSet
-#define ti_lib_rom_ioc_int_enable                     ROM_IOCIntEnable
-#define ti_lib_rom_ioc_int_disable                    ROM_IOCIntDisable
-#define ti_lib_rom_ioc_pin_type_gpio_input            ROM_IOCPinTypeGpioInput
-#define ti_lib_rom_ioc_pin_type_gpio_output           ROM_IOCPinTypeGpioOutput
-#define ti_lib_rom_ioc_pin_type_uart                  ROM_IOCPinTypeUart
-#define ti_lib_rom_ioc_pin_type_ssi_master            ROM_IOCPinTypeSsiMaster
-#define ti_lib_rom_ioc_pin_type_ssi_slave             ROM_IOCPinTypeSsiSlave
-#define ti_lib_rom_ioc_pin_type_i2c                   ROM_IOCPinTypeI2c
-#define ti_lib_rom_ioc_pin_type_aux                   ROM_IOCPinTypeAux
-
-/* PRCM API */
-#define ti_lib_rom_prcm_inf_clock_configure_set       ROM_PRCMInfClockConfigureSet
-#define ti_lib_rom_prcm_inf_clock_configure_get       ROM_PRCMInfClockConfigureGet
-#define ti_lib_rom_prcm_audio_clock_config_set        ROM_PRCMAudioClockConfigSet
-#define ti_lib_rom_prcm_power_domain_on               ROM_PRCMPowerDomainOn
-#define ti_lib_rom_prcm_power_domain_off              ROM_PRCMPowerDomainOff
-#define ti_lib_rom_prcm_peripheral_run_enable         ROM_PRCMPeripheralRunEnable
-#define ti_lib_rom_prcm_peripheral_run_disable        ROM_PRCMPeripheralRunDisable
-#define ti_lib_rom_prcm_peripheral_sleep_enable       ROM_PRCMPeripheralSleepEnable
-#define ti_lib_rom_prcm_peripheral_sleep_disable      ROM_PRCMPeripheralSleepDisable
-#define ti_lib_rom_prcm_peripheral_deep_sleep_enable  ROM_PRCMPeripheralDeepSleepEnable
-#define ti_lib_rom_prcm_peripheral_deep_sleep_disable ROM_PRCMPeripheralDeepSleepDisable
-#define ti_lib_rom_prcm_power_domain_status           ROM_PRCMPowerDomainStatus
-#define ti_lib_rom_prcm_deep_sleep                    ROM_PRCMDeepSleep
-
-/* SMPH API */
-#define ti_lib_rom_smph_acquire                       ROM_SMPHAcquire
-
-/* SSI API */
-#define ti_lib_rom_ssi_config_set_exp_clk             ROM_SSIConfigSetExpClk
-#define ti_lib_rom_ssi_data_put                       ROM_SSIDataPut
-#define ti_lib_rom_ssi_data_put_non_blocking          ROM_SSIDataPutNonBlocking
-#define ti_lib_rom_ssi_data_get                       ROM_SSIDataGet
-#define ti_lib_rom_ssi_data_get_non_blocking          ROM_SSIDataGetNonBlocking
-
-/* TIMER API */
-#define ti_lib_rom_timer_configure                    ROM_TimerConfigure
-#define ti_lib_rom_timer_level_control                ROM_TimerLevelControl
-#define ti_lib_rom_timer_stall_control                ROM_TimerStallControl
-#define ti_lib_rom_timer_wait_on_trigger_control      ROM_TimerWaitOnTriggerControl
-
-/* TRNG API */
-#define ti_lib_rom_trng_number_get                    ROM_TRNGNumberGet
-
-/* UART API */
-#define ti_lib_rom_uart_fifo_level_get                ROM_UARTFIFOLevelGet
-#define ti_lib_rom_uart_config_set_exp_clk            ROM_UARTConfigSetExpClk
-#define ti_lib_rom_uart_config_get_exp_clk            ROM_UARTConfigGetExpClk
-#define ti_lib_rom_uart_disable                       ROM_UARTDisable
-#define ti_lib_rom_uart_char_get_non_blocking         ROM_UARTCharGetNonBlocking
-#define ti_lib_rom_uart_char_get                      ROM_UARTCharGet
-#define ti_lib_rom_uart_char_put_non_blocking         ROM_UARTCharPutNonBlocking
-#define ti_lib_rom_uart_char_put                      ROM_UARTCharPut
-
-/* UDMA API */
-#define ti_lib_rom_udma_channel_attribute_enable      ROM_uDMAChannelAttributeEnable
-#define ti_lib_rom_udma_channel_attribute_disable     ROM_uDMAChannelAttributeDisable
-#define ti_lib_rom_udma_channel_attribute_get         ROM_uDMAChannelAttributeGet
-#define ti_lib_rom_udma_channel_control_set           ROM_uDMAChannelControlSet
-#define ti_lib_rom_udma_channel_transfer_set          ROM_uDMAChannelTransferSet
-#define ti_lib_rom_udma_channel_scatter_gather_set    ROM_uDMAChannelScatterGatherSet
-#define ti_lib_rom_udma_channel_size_get              ROM_uDMAChannelSizeGet
-#define ti_lib_rom_udma_channel_mode_get              ROM_uDMAChannelModeGet
-
-/* VIMS API */
-#define ti_lib_rom_vims_configure                     ROM_VIMSConfigure
-#define ti_lib_rom_vims_mode_set                      ROM_VIMSModeSet
-
-/* HAPI */
-#define ti_lib_hapi_crc32(a, b, c)              HapiCrc32(a, b, c)
-#define ti_lib_hapi_get_flash_size()            HapiGetFlashSize()
-#define ti_lib_hapi_get_chip_id()               HapiGetChipId()
-#define ti_lib_hapi_sector_erase(a)             HapiSectorErase(a)
-#define ti_lib_hapi_program_flash(a, b, c)      HapiProgramFlash(a, b, c)
-#define ti_lib_hapi_reset_device()              HapiResetDevice()
-#define ti_lib_hapi_fletcher32(a, b, c)         HapiFletcher32(a, b, c)
-#define ti_lib_hapi_min_value(a, b)             HapiMinValue(a,b)
-#define ti_lib_hapi_max_value(a, b)             HapiMaxValue(a,b)
-#define ti_lib_hapi_mean_value(a, b)            HapiMeanValue(a,b)
-#define ti_lib_hapi_stand_deviation_value(a, b) HapiStandDeviationValue(a,b)
-#define ti_lib_hapi_hf_source_safe_switch()     HapiHFSourceSafeSwitch()
-#define ti_lib_hapi_select_comp_a_input(a)      HapiSelectCompAInput(a)
-#define ti_lib_hapi_select_comp_a_ref(a)        HapiSelectCompARef(a)
-#define ti_lib_hapi_select_adc_comp_b_input(a)  HapiSelectADCCompBInput(a)
-#define ti_lib_hapi_select_comp_b_ref(a)        HapiSelectCompBRef(a)
-/*---------------------------------------------------------------------------*/
-#endif /* TI_LIB_ROM_H_ */
-/*---------------------------------------------------------------------------*/
-/**
- * @}
- */

arch/cpu/cc26xx-cc13xx/ti-lib.h

@@ -52,9 +52,6 @@
 #ifndef TI_LIB_H_
 #define TI_LIB_H_
 /*---------------------------------------------------------------------------*/
-/* Include ROM API */
-#include "ti-lib-rom.h"
-/*---------------------------------------------------------------------------*/
 /* aon_batmon.h */
 #include "driverlib/aon_batmon.h"
 
@@ -200,8 +197,16 @@
 #define ti_lib_chipinfo_get_device_id_hw_rev_code(...) ChipInfo_GetDeviceIdHwRevCode(__VA_ARGS__)
 #define ti_lib_chipinfo_get_chip_type(...)             ChipInfo_GetChipType(__VA_ARGS__)
 #define ti_lib_chipinfo_get_chip_family(...)           ChipInfo_GetChipFamily(__VA_ARGS__)
+
+#if CPU_FAMILY_CC26X0R2
+#define ti_lib_chipinfo_chip_family_is_cc26xx(...)     ChipInfo_ChipFamilyIs_CC26x0(__VA_ARGS__)
+#define ti_lib_chipinfo_chip_family_is_cc13xx(...)     ChipInfo_ChipFamilyIs_CC13x0(__VA_ARGS__)
+#define ti_lib_chipinfo_chip_family_is_cc26x0r2(...)   ChipInfo_ChipFamilyIs_CC26x0R2(__VA_ARGS__)
+#else
 #define ti_lib_chipinfo_chip_family_is_cc26xx(...)     ChipInfo_ChipFamilyIsCC26xx(__VA_ARGS__)
 #define ti_lib_chipinfo_chip_family_is_cc13xx(...)     ChipInfo_ChipFamilyIsCC13xx(__VA_ARGS__)
+#endif /* CPU_FAMILY_CC26X0R2 */
+
 #define ti_lib_chipinfo_get_hw_revision(...)           ChipInfo_GetHwRevision(__VA_ARGS__)
 #define ti_lib_chipinfo_hw_revision_is_1_0(...)        ChipInfo_HwRevisionIs_1_0(__VA_ARGS__)
 #define ti_lib_chipinfo_hw_revision_is_gteq_2_0(...)   ChipInfo_HwRevisionIs_GTEQ_2_0(__VA_ARGS__)
@@ -388,14 +393,15 @@
 #define ti_lib_pwr_ctrl_source_get(...)         PowerCtrlSourceGet(__VA_ARGS__)
 #define ti_lib_pwr_ctrl_reset_source_get(...)   PowerCtrlResetSourceGet(__VA_ARGS__)
 #define ti_lib_pwr_ctrl_reset_source_clear(...) PowerCtrlResetSourceClear(__VA_ARGS__)
-#define ti_lib_pwr_ctrl_io_freeze_enable(...)   PowerCtrlIOFreezeEnable(__VA_ARGS__)
-#define ti_lib_pwr_ctrl_io_freeze_disable(...)  PowerCtrlIOFreezeDisable(__VA_ARGS__)
 /*---------------------------------------------------------------------------*/
 /* rfc.h */
 #include "driverlib/rfc.h"
 
 #define ti_lib_rfc_rtrim(...)                    RFCRTrim(__VA_ARGS__)
 #define ti_lib_rfc_adi3vco_ldo_voltage_mode(...) RFCAdi3VcoLdoVoltageMode(__VA_ARGS__)
+#define ti_lib_rfc_hw_int_enable(...)            RFCHwIntEnable(__VA_ARGS__)
+#define ti_lib_rfc_hw_int_disable(...)           RFCHwIntDisable(__VA_ARGS__)
+#define ti_lib_rfc_hw_int_clear(...)             RFCHwIntClear(__VA_ARGS__)
 /*---------------------------------------------------------------------------*/
 /* sys_ctrl.h */
 #include "driverlib/sys_ctrl.h"
@@ -408,7 +414,14 @@
 #define ti_lib_sys_ctrl_aon_sync(...)                         SysCtrlAonSync(__VA_ARGS__)
 #define ti_lib_sys_ctrl_aon_update(...)                       SysCtrlAonUpdate(__VA_ARGS__)
 #define ti_lib_sys_ctrl_set_recharge_before_power_down(...)   SysCtrlSetRechargeBeforePowerDown(__VA_ARGS__)
-#define ti_lib_sys_ctrl_adjust_recharge_after_power_down(...) SysCtrlAdjustRechargeAfterPowerDown(__VA_ARGS__)
+
+#if CPU_FAMILY_CC26X0R2
+/* May need to change to XOSC_IN_LOW_POWER_MODE */
+#define ti_lib_sys_ctrl_adjust_recharge_after_power_down()    SysCtrlAdjustRechargeAfterPowerDown(XOSC_IN_HIGH_POWER_MODE)
+#else
+#define ti_lib_sys_ctrl_adjust_recharge_after_power_down()    SysCtrlAdjustRechargeAfterPowerDown()
+#endif /* CPU_FAMILY_CC26X0R2 */
+
 #define ti_lib_sys_ctrl_dcdc_voltage_conditional_control(...) SysCtrl_DCDC_VoltageConditionalControl(__VA_ARGS__)
 #define ti_lib_sys_ctrl_reset_source_get(...)                 SysCtrlResetSourceGet(__VA_ARGS__)
 #define ti_lib_sys_ctrl_system_reset(...)                     SysCtrlSystemReset(__VA_ARGS__)

arch/cpu/msp430/msp430-def.h

@@ -79,6 +79,9 @@ typedef long off_t;
 /* Our clock resolution, this is the same as Unix HZ. */
 #define CLOCK_CONF_SECOND 128UL
 
+/* Use 16-bit rtimer (default in Contiki-NG is 32) */
+#define RTIMER_CONF_CLOCK_SIZE 2
+
 typedef int spl_t;
 spl_t   splhigh_(void);
 

arch/cpu/msp430/rtimer-arch.h

@@ -42,11 +42,7 @@
 
 #include "sys/rtimer.h"
 
-#ifdef RTIMER_CONF_SECOND
-#define RTIMER_ARCH_SECOND RTIMER_CONF_SECOND
-#else
 #define RTIMER_ARCH_SECOND (4096U*8)
-#endif
 
 /* Do the math in 32bits to save precision.
  * Round to nearest integer rather than truncate. */

arch/cpu/native/Makefile.native

@@ -20,8 +20,33 @@ endif
 CFLAGSNO = -Wall -g -I/usr/local/include $(CFLAGSWERROR)
 CFLAGS  += $(CFLAGSNO)
 
+### Are we building with code size optimisations?
+SMALL ?= 0
+
+# The optimizations on native platform cannot be enabled in GCC (not Clang) versions less than 7.2
+GCC_IS_CLANG := $(shell gcc --version 2> /dev/null | grep clang)
+ifneq ($(GCC_IS_CLANG),)
+  NATIVE_CAN_OPTIIMIZE = 1
+else
+  GCC_VERSION := $(shell gcc -dumpfullversion -dumpversion | cut -b1-3)
+  ifeq ($(shell expr $(GCC_VERSION) \>= 7.2), 1)
+  	NATIVE_CAN_OPTIIMIZE = 1
+  else
+  	NATIVE_CAN_OPTIIMIZE = 0
+  endif
+endif
+
+ifeq ($(NATIVE_CAN_OPTIIMIZE),1)
+  ifeq ($(SMALL),1)
+    CFLAGS += -Os
+  else
+    CFLAGS += -O2
+  endif
+endif
+
 ifeq ($(HOST_OS),Darwin)
 AROPTS = -rc
+LDFLAGS_WERROR := -Wl,-fatal_warnings
 LDFLAGS += -Wl,-flat_namespace,-map,$(CONTIKI_NG_PROJECT_MAP)
 CFLAGS += -DHAVE_SNPRINTF=1 -U__ASSERT_USE_STDERR
 else

arch/cpu/native/dev/gpio-hal-arch.c

@@ -43,6 +43,12 @@ static gpio_hal_pin_cfg_t pin_cfg[GPIO_HAL_PIN_COUNT];
 static uint8_t pin_state[GPIO_HAL_PIN_COUNT];
 /*---------------------------------------------------------------------------*/
 void
+gpio_hal_arch_init(void)
+{
+  /* Do nothing */
+}
+/*---------------------------------------------------------------------------*/
+void
 gpio_hal_arch_interrupt_enable(gpio_hal_pin_t pin)
 {
   if(pin >= GPIO_HAL_PIN_COUNT) {

arch/cpu/nrf52832/Makefile.nrf52832

@@ -25,9 +25,9 @@ ifneq ($(NRF52_WITHOUT_SOFTDEVICE),1)
     NRF52_SOFTDEVICE := $(shell find $(NRF52_SDK_ROOT) -name *iot*_softdevice.hex | head -n 1)
   endif
   $(info SoftDevice: $(NRF52_SOFTDEVICE))
-  LINKER_SCRIPT := $(CONTIKI_CPU)/ld/nrf52-$(NRF52_DK_REVISION)-sd.ld
+  LDSCRIPT := $(CONTIKI_CPU)/ld/nrf52-$(NRF52_DK_REVISION)-sd.ld
 else
-  LINKER_SCRIPT := $(CONTIKI_CPU)/ld/nrf52.ld
+  LDSCRIPT := $(CONTIKI_CPU)/ld/nrf52.ld
 endif
 
 OUTPUT_FILENAME := $(CONTIKI_PROJECT)
@@ -140,7 +140,7 @@ CFLAGS += -mfloat-abi=hard -mfpu=fpv4-sp-d16
 
 # keep every function in separate section. This will allow linker to dump unused functions
 LDFLAGS += -Xlinker -Map=$(CONTIKI_NG_PROJECT_MAP)
-LDFLAGS += -mabi=aapcs -L $(TEMPLATE_PATH) -T$(LINKER_SCRIPT)
+LDFLAGS += -mabi=aapcs -L $(TEMPLATE_PATH)
 LDFLAGS += -mfloat-abi=hard -mfpu=fpv4-sp-d16
 # let linker to dump unused sections
 LDFLAGS += -Wl,--gc-sections
@@ -172,11 +172,11 @@ vpath %.s $(ASM_PATHS)
 
 OBJECTS = $(C_OBJECTS) $(ASM_OBJECTS)
 
-CLEAN += nrf52832.a
+NRFLIB = $(BUILD_DIR_BOARD)/nrf52832.a
 
-TARGET_LIBS= nrf52832.a $(NRF52_SDK_ROOT)/components/iot/ble_6lowpan/lib/ble_6lowpan.a
+TARGET_LIBS = $(NRFLIB) $(NRF52_SDK_ROOT)/components/iot/ble_6lowpan/lib/ble_6lowpan.a
 
-nrf52832.a: $(OBJECTS)
+$(NRFLIB): $(OBJECTS)
 	$(TRACE_AR)
 	$(Q)$(AR) $(AROPTS) $@ $^
 

arch/cpu/nrf52832/ld/nrf52-pca10036-sd.ld

@@ -14,3 +14,5 @@ INCLUDE "nrf5x_common.ld"
 /* These symbols are used by the stack check library. */
 _stack = end;
 _stack_origin = ORIGIN(RAM) + LENGTH(RAM);
+_heap = _stack;
+_eheap = _stack_origin;

arch/cpu/nrf52832/ld/nrf52-pca10040-sd.ld

@@ -14,3 +14,5 @@ INCLUDE "nrf5x_common.ld"
 /* These symbols are used by the stack check library. */
 _stack = end;
 _stack_origin = ORIGIN(RAM) + LENGTH(RAM);
+_heap = _stack;
+_eheap = _stack_origin;

arch/cpu/nrf52832/ld/nrf52.ld

@@ -14,3 +14,5 @@ INCLUDE "nrf5x_common.ld"
 /* These symbols are used by the stack check library. */
 _stack = end;
 _stack_origin = ORIGIN(RAM) + LENGTH(RAM);
+_heap = _stack;
+_eheap = _stack_origin;

arch/cpu/simplelink-cc13xx-cc26xx/Makefile.cc13xx-cc26xx

@@ -0,0 +1,149 @@
+################################################################################
+### CC13xx/CC26xx CPU makefile
+
+CC13x2_CC26x2_PRE_RTM ?= 1
+
+# Core SDK is placed as a submodule under arch/cpu/cc13xx-cc26xx/lib.
+# Do a sanity check that Core SDK submodule has been initialized.
+ifndef CORE_SDK
+ CORE_SDK := $(CONTIKI_CPU)/lib/coresdk_cc13xx_cc26xx
+ CORE_SDK_INIT := $(shell [ -f $(CORE_SDK)/.git ] && echo 1)
+
+ ifneq ($(CORE_SDK_INIT),1)
+  $(error The Core SDK submodule is not available. Please run 'git submodule update --init --recursive')
+ endif
+# Note that Core SDK can be overriden with a user-specified SimpleLink SDK.
+# As long as the SimpleLink SDK matches the device in use and is of a reasonable
+# newer version, then it should be no different than using Core SDK.
+else
+ # Do a sanity check the path exists.
+ CORE_SDK_VALID := $(shell [ -d $(CORE_SDK) ] && echo 1)
+
+ ifneq ($(CORE_SDK_VALID),1)
+  $(error User-specified CORE_SDK is not a valid path.)
+ endif
+endif
+
+################################################################################
+### Device Family
+
+# CC13x2/CC26x2 has to differentiate both pre-RTM and RTM devices. As of now,
+# pre-RTM is suffixed with _v1 while RTM is suffixed with _v2. This will be
+# removed when CC13x2/CC26x2 RTMs. For now, provide a switch to choose
+# either pre-RTM or RTM.
+# Also note that the devices name is cc13x2_cc26x2 for all CC13x2/CC26x2
+# devices, while the library name is individual for each device family.
+ifeq ($(SUBFAMILY),cc13x2-cc26x2)
+ ifeq ($(CC13x2_CC26x2_PRE_RTM),1)
+  SDK_DEVICES_NAME := cc13x2_cc26x2_v1
+  SDK_LIB_NAME := $(DEVICE_FAMILY_LC)_v1
+ else
+  SDK_DEVICES_NAME := cc13x2_cc26x2_v2
+  SDK_LIB_NAME := $(DEVICE_FAMILY_LC)_v2
+ endif
+# CC13x0/CC26x0 does not have this, with both its devices name and library
+# name the same as its own device family name.
+else
+ SDK_DEVICES_NAME := $(DEVICE_FAMILY_LC)
+ SDK_LIB_NAME := $(DEVICE_FAMILY_LC)
+endif
+
+################################################################################
+### CC13xx/CC26xx CPU files
+
+# Both ccfg-conf.c and startup_cc13xx_cc26xx_gcc.c is located locally in
+# the arch/cpu/cc13xx-cc26xx folder.
+CPU_START_SOURCEFILES += ccfg-conf.c startup_cc13xx_cc26xx_gcc.c
+
+# CPU-dependent source files
+CONTIKI_CPU_SOURCEFILES += rtimer-arch.c    clock-arch.c
+CONTIKI_CPU_SOURCEFILES += watchdog-arch.c  dbg-arch.c
+CONTIKI_CPU_SOURCEFILES += uart0-arch.c     slip-arch.c
+CONTIKI_CPU_SOURCEFILES += gpio-hal-arch.c  int-master-arch.c
+CONTIKI_CPU_SOURCEFILES += random.c         trng-arch.c
+CONTIKI_CPU_SOURCEFILES += spi-arch.c
+
+# RF source files
+CONTIKI_CPU_SOURCEFILES += sched.c          data-queue.c
+CONTIKI_CPU_SOURCEFILES += ieee-addr.c      ble-addr.c
+CONTIKI_CPU_SOURCEFILES += ble-beacond.c
+
+ifeq ($(SUPPORTS_PROP_MODE),1)
+ CONTIKI_CPU_SOURCEFILES += prop-mode.c prop-settings.c prop-tx-power.c
+endif
+
+ifeq ($(SUPPORTS_IEEE_MODE),1)
+ CONTIKI_CPU_SOURCEFILES += ieee-mode.c ieee-settings.c ieee-tx-power.c
+endif
+
+ifeq ($(SUPPORTS_BLE_BEACON),1)
+ CONTIKI_CPU_SOURCEFILES += ble-settings.c ble-tx-power.c
+endif
+
+################################################################################
+### Modules and paths
+
+# Core SDK paths
+SDK_NORTOS  := $(CORE_SDK)/kernel/nortos
+SDK_SOURCE  := $(CORE_SDK)/source
+SDK_DRIVERS := $(CORE_SDK)/source/ti/drivers
+SDK_DEVICES := $(CORE_SDK)/source/ti/devices/$(SDK_DEVICES_NAME)
+
+EXTERNALDIRS += $(SDK_SOURCE) $(SDK_NORTOS)
+
+# CPU-dependent directories
+CONTIKI_CPU_DIRS += . dev $(SUBFAMILY)
+CONTIKI_CPU_DIRS += rf rf-settings rf-settings/$(DEVICE_FAMILY_LC)
+
+CONTIKI_SOURCEFILES += $(CONTIKI_CPU_SOURCEFILES) $(DEBUG_IO_SOURCEFILES)
+
+################################################################################
+### Compiler configuration
+
+# A weird behaviour of GCC garbage collector has been observed, where
+# unitialized global variables with global linkage (aka non-static) put in the
+# COMMON section weren't analyzed by the garbage collector at all. No idea why.
+# The solution is to disable the common section, which subsequently places all
+# unitialized global variables with global linkage in the .bss section,
+# allowing the GC to analyze the variables. This is especially an issue with
+# Board.h files, as they rely heavily on global variables placed in COMMON to
+# be garbage collected if unused.
+CFLAGS += -fno-common
+
+################################################################################
+### Linker configuration
+
+# Linker flags
+LDFLAGS += --entry resetISR
+LDFLAGS += --specs=nano.specs
+LDFLAGS += -nostartfiles
+LDFLAGS += -static
+
+# Linker script
+LDSCRIPT := $(CONTIKI_CPU)/$(SUBFAMILY)/$(SUBFAMILY).lds
+
+# Globally linked libraries
+TARGET_LIBFILES += -lc -lgcc -lnosys -lm
+
+################################################################################
+### Specialized build targets
+
+.PHONY: FORCE
+FORCE:
+
+# Always re-build ieee-addr.o in case the command line passes a new NODEID
+$(OBJECTDIR)/ieee-addr.o: ieee-addr.c FORCE | $(OBJECTDIR)
+	$(TRACE_CC)
+	$(Q)$(CC) $(CFLAGS) -c $< -o $@
+
+# Always re-build ccfg-conf.c so any changes to CCFG configuration
+# always applies
+$(OBJECTDIR)/ccfg-conf.o: ccfg-conf.c FORCE | $(OBJECTDIR)
+	$(TRACE_CC)
+	$(Q)$(CC) $(CFLAGS) -c $< -o $@
+
+################################################################################
+### Sub-family Makefile
+
+# Include the Sub-family Makefile specific for the specified device
+include $(CONTIKI_CPU)/$(SUBFAMILY)/Makefile.$(SUBFAMILY)

arch/cpu/simplelink-cc13xx-cc26xx/cc13x0-cc26x0/Makefile.cc13x0-cc26x0

@@ -0,0 +1,11 @@
+################################################################################
+### CC13x0/CC26x0 CPU makefile
+
+# Simplelink SDK pre-compiled libraries
+TARGET_LIBFILES += $(SDK_NORTOS)/lib/nortos_$(SDK_LIB_NAME).am3g
+TARGET_LIBFILES += $(SDK_DRIVERS)/rf/lib/rf_multiMode_$(SDK_LIB_NAME).am3g
+TARGET_LIBFILES += $(SDK_DRIVERS)/lib/drivers_$(SDK_LIB_NAME).am3g
+TARGET_LIBFILES += $(SDK_DEVICES)/driverlib/bin/gcc/driverlib.lib
+
+# CC13x0/CC26x0 is a Cortex-M3 architecture
+include $(CONTIKI)/arch/cpu/arm/cortex-m/cm3/Makefile.cm3

arch/cpu/simplelink-cc13xx-cc26xx/cc13x0-cc26x0/cc13x0-cc26x0-cm3.h

@@ -0,0 +1,128 @@
+/*
+ * Template:
+ * Copyright (c) 2012 ARM LIMITED
+ * All rights reserved.
+ *
+ * CC13xx-CC26xx:
+ * Copyright (c) 2017, George Oikonomou - http://www.spd.gr
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*---------------------------------------------------------------------------*/
+/**
+ * \addtogroup cc26xx
+ * @{
+ *
+ * \defgroup cc26xx-cm3 CC13xx/CC26xx CMSIS
+ *
+ * CC13xx/CC26xx Cortex-M3 CMSIS definitions
+ * @{
+ *
+ * \file
+ * CMSIS Cortex-M3 core peripheral access layer header file for CC13xx/CC26xx
+ */
+/*---------------------------------------------------------------------------*/
+#ifndef CC13XX_CC26XX_CM3_H_
+#define CC13XX_CC26XX_CM3_H_
+/*---------------------------------------------------------------------------*/
+/**
+ * \name Interrupt Number Definition
+ * @{
+ */
+typedef enum cc13xx_cc26xx_cm3_irq_e {
+  /* Cortex-M3 Processor Exceptions */
+  CC13XX_CC26XX_CM3_EXCEPTION_RESET = -15,            /**<  1 Reset */
+  CC13XX_CC26XX_CM3_EXCEPTION_NMI = -14,              /**<  2 NMI */
+  CC13XX_CC26XX_CM3_EXCEPTION_HARD_FAULT = -13,       /**<  3 Hard fault */
+  CC13XX_CC26XX_CM3_EXCEPTION_MPU_FAULT = -12,        /**<  4 MPU fault */
+  CC13XX_CC26XX_CM3_EXCEPTION_BUS_FAULT = -11,        /**<  5 Bus fault */
+  CC13XX_CC26XX_CM3_EXCEPTION_USAGE_FAULT = -10,      /**<  6 Usage fault */
+  CC13XX_CC26XX_CM3_EXCEPTION_SV_CALL = -5,           /**< 11 SVCall */
+  CC13XX_CC26XX_CM3_EXCEPTION_DEBUG_MON = -4,         /**< 12 Debug monitor */
+  CC13XX_CC26XX_CM3_EXCEPTION_PEND_SV = -2,           /**< 14 PendSV */
+  CC13XX_CC26XX_CM3_EXCEPTION_SYS_TICK = -1,          /**< 15 SysTick */
+
+  /* CC13xx/CC26xx interrupts */
+  CC13XX_CC26XX_CM3_IRQ_EDGE_DETECT = 0,              /**< 16 AON edge detect */
+  CC13XX_CC26XX_CM3_EXCEPTION_I2C = 1,                /**< 17 I2C */
+  CC13XX_CC26XX_CM3_EXCEPTION_RF_CPE1 = 2,            /**< 18 RF Command and Packet Engine 1 */
+  CC13XX_CC26XX_CM3_EXCEPTION_AON_SPI_SLAVE = 3,      /**< 19 AON SpiSplave Rx, Tx and CS */
+  CC13XX_CC26XX_CM3_EXCEPTION_AON_RTC = 4,            /**< 20 AON RTC */
+  CC13XX_CC26XX_CM3_EXCEPTION_UART0 = 5,              /**< 21 UART0 Rx and Tx */
+  CC13XX_CC26XX_CM3_EXCEPTION_AON_AUX_SWEV0 = 6,      /**< 22 Sensor Controller software event 0, through AON domain*/
+  CC13XX_CC26XX_CM3_EXCEPTION_SSI0 = 7,               /**< 23 SSI0 Rx and Tx */
+  CC13XX_CC26XX_CM3_EXCEPTION_SSI1 = 8,               /**< 24 SSI1 Rx and Tx */
+  CC13XX_CC26XX_CM3_EXCEPTION_RF_CPE0 = 9,            /**< 25 RF Command and Packet Engine 0 */
+  CC13XX_CC26XX_CM3_EXCEPTION_RF_HW = 10,             /**< 26 RF Core Hardware */
+  CC13XX_CC26XX_CM3_EXCEPTION_RF_CMD_ACK = 11,        /**< 27 RF Core Command Acknowledge */
+  CC13XX_CC26XX_CM3_EXCEPTION_I2S = 12,               /**< 28 I2S */
+  CC13XX_CC26XX_CM3_EXCEPTION_AON_AUX_SWEV1 = 13,     /**< 29 Sensor Controller software event 1, through AON domain*/
+  CC13XX_CC26XX_CM3_EXCEPTION_WATCHDOG = 14,          /**< 30 Watchdog timer */
+  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_0A = 15,        /**< 31 Timer 0 subtimer A */
+  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_0B = 16,        /**< 32 Timer 0 subtimer B */
+  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_1A = 17,        /**< 33 Timer 1 subtimer A */
+  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_1B = 18,        /**< 34 Timer 1 subtimer B */
+  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_2A = 19,        /**< 35 Timer 2 subtimer A */
+  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_2B = 20,        /**< 36 Timer 2 subtimer B */
+  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_3A = 21,        /**< 37 Timer 3 subtimer A */
+  CC13XX_CC26XX_CM3_EXCEPTION_GPTIMER_3B = 22,        /**< 38 Timer 3 subtimer B */
+  CC13XX_CC26XX_CM3_EXCEPTION_CRYPTO = 23,            /**< 39 Crypto Core Result available */
+  CC13XX_CC26XX_CM3_EXCEPTION_UDMA = 24,              /**< 40 uDMA Software */
+  CC13XX_CC26XX_CM3_EXCEPTION_UDMA_ERR = 25,          /**< 41 uDMA Error */
+  CC13XX_CC26XX_CM3_EXCEPTION_FLASH_CTRL = 26,        /**< 42 Flash controller */
+  CC13XX_CC26XX_CM3_EXCEPTION_SW0 = 27,               /**< 43 Software Event 0 */
+  CC13XX_CC26XX_CM3_EXCEPTION_AUX_COM_EVENT = 28,     /**< 44 AUX combined event, directly to MCU domain*/
+  CC13XX_CC26XX_CM3_EXCEPTION_AON_PRG0 = 29,          /**< 45 AON programmable 0 */
+  CC13XX_CC26XX_CM3_EXCEPTION_PROG = 30,              /**< 46 Dynamic Programmable interrupt (default source: PRCM)*/
+  CC13XX_CC26XX_CM3_EXCEPTION_AUX_COMPA = 31,         /**< 47 AUX Comparator A */
+  CC13XX_CC26XX_CM3_EXCEPTION_AUX_ADC = 32,           /**< 48 AUX ADC IRQ */
+  CC13XX_CC26XX_CM3_EXCEPTION_TRNG = 33,              /**< 49 TRNG event */
+} cc13xx_cc26xx_cm3_irq_t;
+
+typedef cc13xx_cc26xx_cm3_irq_t IRQn_Type;
+
+#define SysTick_IRQn CC13XX_CC26XX_CM3_EXCEPTION_SYS_TICK
+/** @} */
+/*---------------------------------------------------------------------------*/
+/** \name Processor and Core Peripheral Section
+ * @{
+ */
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT           1       /**< MPU present or not */
+#define __NVIC_PRIO_BITS        3       /**< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig  0       /**< Set to 1 if different SysTick Config is used */
+/** @} */
+/*---------------------------------------------------------------------------*/
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+/*---------------------------------------------------------------------------*/
+#endif /* CC13XX_CC26XX_CM3_H_ */
+/*---------------------------------------------------------------------------*/
+/**
+ * @}
+ * @}
+ */

arch/cpu/simplelink-cc13xx-cc26xx/cc13x0-cc26x0/cc13x0-cc26x0.icf

@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2017, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+define symbol STACK_SIZE       = 0x800; /* 2048 bytes */
+define symbol HEAP_SIZE        = 0x100; /* 256 bytes */
+
+define symbol __intvec_start__ = 0x00000000;
+
+/*-Memory Regions-*/
+define symbol ROM_start__      = 0x00000000;
+define symbol ROM_end__        = 0x0001FFFF;
+define symbol RAM_start__      = 0x20000000;
+define symbol RAM_end__        = 0x20004FFF;
+
+/* Define a memory region that covers the entire 4 GB addressable space */
+define memory mem with size = 4G;
+
+/* Define a region for the on-chip flash */
+define region FLASH_region   = mem:[from ROM_start__ to ROM_end__];
+
+/* Define a region for the on-chip SRAM */
+define region RAM_region     = mem:[from RAM_start__ to RAM_end__];
+
+/* Place the interrupt vectors at the start of flash */
+place at address mem:__intvec_start__ { readonly section .intvec };
+keep { section .intvec };
+
+/* Place the CCA area at the end of flash */
+place at end of FLASH_region { readonly section .ccfg };
+keep { section .ccfg };
+
+/* Place remaining 'read only' in Flash */
+place in FLASH_region { readonly };
+
+/* Place all read/write items into RAM */
+place in RAM_region { readwrite };
+initialize by copy { readwrite };
+
+/*
+ * Define CSTACK block to contain .stack section. This enables the IAR IDE
+ * to properly show the stack content during debug. Place stack at end of
+ * retention RAM, do not initialize (initializing the stack will destroy the
+ * return address from the initialization code, causing the processor to branch
+ * to zero and fault)
+ */
+define block CSTACK with alignment = 8, size = STACK_SIZE { section .stack };
+place at end of RAM_region { block CSTACK };
+do not initialize { section .stack, section .noinit };
+
+/* Export stack top symbol. Used by startup file */
+define exported symbol STACK_TOP = RAM_end__ + 1;
+
+/* Primary Heap configuration */
+define block HEAP with alignment = 8, size = HEAP_SIZE { };
+
+/* Place heap just before CSTACK */
+place in RAM_region { block HEAP };

arch/cpu/simplelink-cc13xx-cc26xx/cc13x0-cc26x0/cc13x0-cc26x0.lds

@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2017-2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+MIN_STACKSIZE = 0x600;  /* 1536 bytes */
+HEAPSIZE      = 0x100;  /* 256 bytes */
+
+MEMORY
+{
+    FLASH (RX)      : ORIGIN = 0x00000000, LENGTH = 0x0001ffa8
+    /*
+     * Customer Configuration Area and Bootloader Backdoor configuration in
+     * flash, 40 bytes
+     */
+    FLASH_CCFG (RX) : ORIGIN = 0x0001ffa8, LENGTH = 0x00000058
+    SRAM (RWX)      : ORIGIN = 0x20000000, LENGTH = 0x00005000
+    GPRAM (RWX)     : ORIGIN = 0x11000000, LENGTH = 0x00002000
+}
+
+REGION_ALIAS("REGION_TEXT",      FLASH);
+REGION_ALIAS("REGION_BSS",       SRAM);
+REGION_ALIAS("REGION_DATA",      SRAM);
+REGION_ALIAS("REGION_STACK",     SRAM);
+REGION_ALIAS("REGION_HEAP",      SRAM);
+REGION_ALIAS("REGION_ARM_EXIDX", FLASH);
+REGION_ALIAS("REGION_ARM_EXTAB", FLASH);
+
+SECTIONS {
+
+    PROVIDE (_resetVecs_base_addr = DEFINED(_resetVecs_base_addr)
+                                  ? _resetVecs_base_addr
+                                  : 0x0);
+
+    .resetVecs (_resetVecs_base_addr) : AT (_resetVecs_base_addr) {
+        KEEP (*(.resetVecs))
+    } > REGION_TEXT
+
+    .ramVecs (NOLOAD) : ALIGN(1024) {
+        KEEP (*(.ramVecs))
+    } > REGION_DATA
+
+    /*
+     * UDMACC26XX_CONFIG_BASE below must match UDMACC26XX_CONFIG_BASE defined
+     * by ti/drivers/dma/UDMACC26XX.h
+     * The user is allowed to change UDMACC26XX_CONFIG_BASE to move it away from
+     * the default address 0x2000_0400, but remember it must be 1024 bytes aligned.
+     */
+    UDMACC26XX_CONFIG_BASE = 0x20000400;
+
+    /*
+     * Define absolute addresses for the DMA channels.
+     * DMA channels must always be allocated at a fixed offset from the DMA base address.
+     * CTEA := Control Table Entry Address
+     * --------- DO NOT MODIFY -----------
+     */
+    DMA_SPI0_RX_CTEA   = (UDMACC26XX_CONFIG_BASE + 0x30);
+    DMA_SPI0_TX_CTEA   = (UDMACC26XX_CONFIG_BASE + 0x40);
+    DMA_ADC_PRI_CTEA   = (UDMACC26XX_CONFIG_BASE + 0x70);
+    DMA_GPT0A_PRI_CTEA = (UDMACC26XX_CONFIG_BASE + 0x90);
+    DMA_SPI1_RX_CTEA   = (UDMACC26XX_CONFIG_BASE + 0x100);
+    DMA_SPI1_TX_CTEA   = (UDMACC26XX_CONFIG_BASE + 0x110);
+    DMA_ADC_ALT_CTEA   = (UDMACC26XX_CONFIG_BASE + 0x270);
+    DMA_GPT0A_ALT_CTEA = (UDMACC26XX_CONFIG_BASE + 0x290);
+
+    /*
+     * Allocate SPI0, SPI1, ADC, and GPTimer0 DMA descriptors at absolute addresses.
+     * --------- DO NOT MODIFY -----------
+     */
+    UDMACC26XX_dmaSpi0RxControlTableEntry_is_placed = 0;
+    .dmaSpi0RxControlTableEntry DMA_SPI0_RX_CTEA : AT (DMA_SPI0_RX_CTEA) {
+        *(.dmaSpi0RxControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaSpi0TxControlTableEntry_is_placed = 0;
+    .dmaSpi0TxControlTableEntry DMA_SPI0_TX_CTEA : AT (DMA_SPI0_TX_CTEA) {
+        *(.dmaSpi0TxControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaADCPriControlTableEntry_is_placed = 0;
+    .dmaADCPriControlTableEntry DMA_ADC_PRI_CTEA : AT (DMA_ADC_PRI_CTEA) {
+        *(.dmaADCPriControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaGPT0APriControlTableEntry_is_placed = 0;
+    .dmaGPT0APriControlTableEntry DMA_GPT0A_PRI_CTEA : AT (DMA_GPT0A_PRI_CTEA) {
+        *(.dmaGPT0APriControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaSpi1RxControlTableEntry_is_placed = 0;
+    .dmaSpi1RxControlTableEntry DMA_SPI1_RX_CTEA : AT (DMA_SPI1_RX_CTEA) {
+        *(.dmaSpi1RxControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaSpi1TxControlTableEntry_is_placed = 0;
+    .dmaSpi1TxControlTableEntry DMA_SPI1_TX_CTEA : AT (DMA_SPI1_TX_CTEA) {
+        *(.dmaSpi1TxControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaADCAltControlTableEntry_is_placed = 0;
+    .dmaADCAltControlTableEntry DMA_ADC_ALT_CTEA : AT (DMA_ADC_ALT_CTEA) {
+        *(.dmaADCAltControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaGPT0AAltControlTableEntry_is_placed = 0;
+    .dmaGPT0AAltControlTableEntry DMA_GPT0A_ALT_CTEA : AT (DMA_GPT0A_ALT_CTEA) {
+        *(.dmaGPT0AAltControlTableEntry)
+    } > REGION_DATA
+
+    .text : {
+        CREATE_OBJECT_SYMBOLS
+        *(.text)
+        *(.text.*)
+        . = ALIGN(0x4);
+        KEEP (*(.ctors))
+        . = ALIGN(0x4);
+        KEEP (*(.dtors))
+        . = ALIGN(0x4);
+        __init_array_start = .;
+        KEEP (*(.init_array*))
+        __init_array_end = .;
+        *(.init)
+        *(.fini*)
+    } > REGION_TEXT AT> REGION_TEXT
+
+    PROVIDE(__etext = .);
+    PROVIDE(_etext  = .);
+    PROVIDE(etext   = .);
+
+    .rodata : {
+        *(.rodata)
+        *(.rodata.*)
+    } > REGION_TEXT AT> REGION_TEXT
+
+    .data : ALIGN(0x4) {
+        __data_load__  = LOADADDR(.data);
+        __data_start__ = .;
+        *(.data)
+        *(.data.*)
+        . = ALIGN (0x4);
+        __data_end__ = .;
+    } > REGION_DATA AT> REGION_TEXT
+
+    .ARM.exidx : {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
+
+    .ARM.extab : {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
+
+    .nvs (NOLOAD) : ALIGN(0x1000) {
+        *(.nvs)
+    } > REGION_TEXT
+
+    .ccfg : {
+        KEEP(*(.ccfg))
+    } > FLASH_CCFG AT> FLASH_CCFG
+
+    .bss : {
+        __bss_start__ = .;
+        *(.shbss)
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+        . = ALIGN(0x4);
+        __bss_end__ = .;
+    } > REGION_BSS AT> REGION_BSS
+
+    /* Start of heap must be 4 byte aligned */
+    .heap (NOLOAD) : ALIGN(0x4) {
+        PROVIDE(__heap_start__ = .);
+        PROVIDE(_heap          = __heap_start__);
+        PROVIDE(end            = __heap_start__);
+        PROVIDE(_end           = __heap_start__);
+        PROVIDE(__end          = __heap_start__);
+
+        . += HEAPSIZE;
+        KEEP(*(.heap))
+
+        PROVIDE(__heap_end__ = .);
+        PROVIDE(_eheap       = __heap_end__);
+        PROVIDE(__HeapLimit  = __heap_end__);
+    } > REGION_HEAP AT> REGION_HEAP
+
+    PROVIDE(__stack_size = ORIGIN(SRAM) + LENGTH(SRAM) - ALIGN(0x8));
+
+    /* Start of stack must be 8 byte aligned */
+    .stack (NOLOAD) : {
+        PROVIDE(_stack        = ALIGN(0x8));
+        PROVIDE(__stack       = _stack);
+
+        PROVIDE(_stack_end    = ORIGIN(SRAM) + LENGTH(SRAM));
+        PROVIDE(__stack_end   = _stack_end);
+        PROVIDE(_stack_origin = _stack_end);
+
+        /* Note that the stack check library requires the symbols */
+        /* "_stack" and "_stack_origin" to be defined. */
+
+        /* Assert that we have enough stack */
+        ASSERT(__stack_size >= MIN_STACKSIZE, "Error: No room left for the stack");
+    } > REGION_STACK AT> REGION_STACK
+}

arch/cpu/simplelink-cc13xx-cc26xx/cc13x0-cc26x0/driverlib/rf_ieee_cmd.h

@@ -0,0 +1,629 @@
+/******************************************************************************
+*  Filename:       rf_ieee_cmd.h
+*  Revised:        2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018)
+*  Revision:       18170
+*
+*  Description:    CC13x2/CC26x2 API for IEEE 802.15.4 commands
+*
+*  Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+*  All rights reserved.
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions are met:
+*
+*  1) Redistributions of source code must retain the above copyright notice,
+*     this list of conditions and the following disclaimer.
+*
+*  2) Redistributions in binary form must reproduce the above copyright notice,
+*     this list of conditions and the following disclaimer in the documentation
+*     and/or other materials provided with the distribution.
+*
+*  3) Neither the name of the ORGANIZATION nor the names of its contributors may
+*     be used to endorse or promote products derived from this software without
+*     specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+*  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+*  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+*  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+*  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+*  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+*  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+*  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+*  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+*  POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __IEEE_CMD_H
+#define __IEEE_CMD_H
+
+#ifndef __RFC_STRUCT
+#define __RFC_STRUCT
+#endif
+
+#ifndef __RFC_STRUCT_ATTR
+#if defined(__GNUC__)
+#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4)))
+#elif defined(__TI_ARM__)
+#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4)))
+#else
+#define __RFC_STRUCT_ATTR
+#endif
+#endif
+
+//! \addtogroup rfc
+//! @{
+
+//! \addtogroup ieee_cmd
+//! @{
+
+#include <stdint.h>
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(driverlib/rf_mailbox.h)
+#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h)
+
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_s rfc_CMD_IEEE_RX_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s rfc_CMD_IEEE_ED_SCAN_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_TX_s rfc_CMD_IEEE_TX_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s rfc_CMD_IEEE_CSMA_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s rfc_CMD_IEEE_RX_ACK_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s rfc_CMD_IEEE_ABORT_BG_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s rfc_CMD_IEEE_MOD_CCA_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s rfc_CMD_IEEE_MOD_FILT_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s rfc_CMD_IEEE_MOD_SRC_MATCH_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s rfc_CMD_IEEE_ABORT_FG_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s rfc_CMD_IEEE_STOP_FG_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s rfc_CMD_IEEE_CCA_REQ_t;
+typedef struct __RFC_STRUCT rfc_ieeeRxOutput_s rfc_ieeeRxOutput_t;
+typedef struct __RFC_STRUCT rfc_shortAddrEntry_s rfc_shortAddrEntry_t;
+typedef struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s rfc_ieeeRxCorrCrc_t;
+
+//! \addtogroup CMD_IEEE_RX
+//! @{
+#define CMD_IEEE_RX                                             0x2801
+//! IEEE 802.15.4 Receive Command
+struct __RFC_STRUCT rfc_CMD_IEEE_RX_s {
+   uint16_t commandNo;                  //!<        The command ID number 0x2801
+   uint16_t status;                     //!< \brief An integer telling the status of the command. This value is
+                                        //!<        updated by the radio CPU during operation and may be read by the
+                                        //!<        system CPU at any time.
+   rfc_radioOp_t *pNextOp;              //!<        Pointer to the next operation to run after this operation is done
+   ratmr_t startTime;                   //!<        Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+   struct {
+      uint8_t triggerType:4;            //!<        The type of trigger
+      uint8_t bEnaCmd:1;                //!< \brief 0: No alternative trigger command<br>
+                                        //!<        1: CMD_TRIGGER can be used as an alternative trigger
+      uint8_t triggerNo:2;              //!<        The trigger number of the CMD_TRIGGER command that triggers this action
+      uint8_t pastTrig:1;               //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+                                        //!<        1: A trigger in the past is triggered as soon as possible
+   } startTrigger;                      //!<        Identification of the trigger that starts the operation
+   struct {
+      uint8_t rule:4;                   //!<        Condition for running next command: Rule for how to proceed
+      uint8_t nSkip:4;                  //!<        Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+   } condition;
+   uint8_t channel;                     //!< \brief Channel to tune to in the start of the operation<br>
+                                        //!<        0: Use existing channel<br>
+                                        //!<        11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 &times; (channel - 11)) MHz<br>
+                                        //!<        60--207: Frequency is  (2300 + channel) MHz<br>
+                                        //!<        Others: <i>Reserved</i>
+   struct {
+      uint8_t bAutoFlushCrc:1;          //!<        If 1, automatically remove packets with CRC error from Rx queue
+      uint8_t bAutoFlushIgn:1;          //!<        If 1, automatically remove packets that can be ignored according to frame filtering from Rx queue
+      uint8_t bIncludePhyHdr:1;         //!<        If 1, include the received PHY header field in the stored packet; otherwise discard it
+      uint8_t bIncludeCrc:1;            //!<        If 1, include the received CRC field in the stored packet; otherwise discard it
+      uint8_t bAppendRssi:1;            //!<        If 1, append an RSSI byte to the packet in the Rx queue
+      uint8_t bAppendCorrCrc:1;         //!<        If 1, append a correlation value and CRC result byte to the packet in the Rx queue
+      uint8_t bAppendSrcInd:1;          //!<        If 1, append an index from the source matching algorithm
+      uint8_t bAppendTimestamp:1;       //!<        If 1, append a timestamp to the packet in the Rx queue
+   } rxConfig;
+   dataQueue_t* pRxQ;                   //!<        Pointer to receive queue
+   rfc_ieeeRxOutput_t *pOutput;         //!<        Pointer to output structure (NULL: Do not store results)
+   struct {
+      uint16_t frameFiltEn:1;           //!< \brief 0: Disable frame filtering<br>
+                                        //!<        1: Enable frame filtering
+      uint16_t frameFiltStop:1;         //!< \brief 0: Receive all packets to the end<br>
+                                        //!<        1: Stop receiving frame once frame filtering has caused the frame to be rejected.
+      uint16_t autoAckEn:1;             //!< \brief 0: Disable auto ACK<br>
+                                        //!<        1: Enable auto ACK.
+      uint16_t slottedAckEn:1;          //!< \brief 0: Non-slotted ACK<br>
+                                        //!<        1: Slotted ACK.
+      uint16_t autoPendEn:1;            //!< \brief 0: Auto-pend disabled<br>
+                                        //!<        1: Auto-pend enabled
+      uint16_t defaultPend:1;           //!<        The value of the pending data bit in auto ACK packets that are not subject to auto-pend
+      uint16_t bPendDataReqOnly:1;      //!< \brief 0: Use auto-pend for any packet<br>
+                                        //!<        1: Use auto-pend for data request packets only
+      uint16_t bPanCoord:1;             //!< \brief 0: Device is not PAN coordinator<br>
+                                        //!<        1: Device is PAN coordinator
+      uint16_t maxFrameVersion:2;       //!<        Reject frames where the frame version field in the FCF is greater than this value
+      uint16_t fcfReservedMask:3;       //!<        Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero
+      uint16_t modifyFtFilter:2;        //!< \brief Treatment of MSB of frame type field before frame-type filtering:<br>
+                                        //!<        0: No modification<br>
+                                        //!<        1: Invert MSB<br>
+                                        //!<        2: Set MSB to 0<br>
+                                        //!<        3: Set MSB to 1
+      uint16_t bStrictLenFilter:1;      //!< \brief 0: Accept acknowledgement frames of any length >= 5<br>
+                                        //!<        1: Accept only acknowledgement frames of length 5
+   } frameFiltOpt;                      //!<        Frame filtering options
+   struct {
+      uint8_t bAcceptFt0Beacon:1;       //!< \brief Treatment of frames with frame type 000 (beacon):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+      uint8_t bAcceptFt1Data:1;         //!< \brief Treatment of frames with frame type 001 (data):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+      uint8_t bAcceptFt2Ack:1;          //!< \brief Treatment of frames with frame type 010 (ACK):<br>
+                                        //!<        0: Reject, unless running ACK receive command<br>
+                                        //!<        1: Always accept
+      uint8_t bAcceptFt3MacCmd:1;       //!< \brief Treatment of frames with frame type 011 (MAC command):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+      uint8_t bAcceptFt4Reserved:1;     //!< \brief Treatment of frames with frame type 100 (reserved):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+      uint8_t bAcceptFt5Reserved:1;     //!< \brief Treatment of frames with frame type 101 (reserved):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+      uint8_t bAcceptFt6Reserved:1;     //!< \brief Treatment of frames with frame type 110 (reserved):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+      uint8_t bAcceptFt7Reserved:1;     //!< \brief Treatment of frames with frame type 111 (reserved):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+   } frameTypes;                        //!<        Frame types to receive in frame filtering
+   struct {
+      uint8_t ccaEnEnergy:1;            //!<        Enable energy scan as CCA source
+      uint8_t ccaEnCorr:1;              //!<        Enable correlator based carrier sense as CCA source
+      uint8_t ccaEnSync:1;              //!<        Enable sync found based carrier sense as CCA source
+      uint8_t ccaCorrOp:1;              //!< \brief Operator to use between energy based and correlator based CCA<br>
+                                        //!<        0: Report busy channel if either ccaEnergy or ccaCorr are busy<br>
+                                        //!<        1: Report busy channel if both ccaEnergy and ccaCorr are busy
+      uint8_t ccaSyncOp:1;              //!< \brief Operator to use between sync found based CCA and the others<br>
+                                        //!<        0: Always report busy channel if ccaSync is busy<br>
+                                        //!<        1: Always report idle channel if ccaSync is idle
+      uint8_t ccaCorrThr:2;             //!<        Threshold for number of correlation peaks in correlator based carrier sense
+   } ccaOpt;                            //!<        CCA options
+   int8_t ccaRssiThr;                   //!<        RSSI threshold for CCA
+   uint8_t __dummy0;
+   uint8_t numExtEntries;               //!<        Number of extended address entries
+   uint8_t numShortEntries;             //!<        Number of short address entries
+   uint32_t* pExtEntryList;             //!<        Pointer to list of extended address entries
+   uint32_t* pShortEntryList;           //!<        Pointer to list of short address entries
+   uint64_t localExtAddr;               //!<        The extended address of the local device
+   uint16_t localShortAddr;             //!<        The short address of the local device
+   uint16_t localPanID;                 //!<        The PAN ID of the local device
+   uint16_t __dummy1;
+   uint8_t __dummy2;
+   struct {
+      uint8_t triggerType:4;            //!<        The type of trigger
+      uint8_t bEnaCmd:1;                //!< \brief 0: No alternative trigger command<br>
+                                        //!<        1: CMD_TRIGGER can be used as an alternative trigger
+      uint8_t triggerNo:2;              //!<        The trigger number of the CMD_TRIGGER command that triggers this action
+      uint8_t pastTrig:1;               //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+                                        //!<        1: A trigger in the past is triggered as soon as possible
+   } endTrigger;                        //!<        Trigger that causes the device to end the Rx operation
+   ratmr_t endTime;                     //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the Rx
+                                        //!<        operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_ED_SCAN
+//! @{
+#define CMD_IEEE_ED_SCAN                                        0x2802
+//! IEEE 802.15.4 Energy Detect Scan Command
+struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s {
+   uint16_t commandNo;                  //!<        The command ID number 0x2802
+   uint16_t status;                     //!< \brief An integer telling the status of the command. This value is
+                                        //!<        updated by the radio CPU during operation and may be read by the
+                                        //!<        system CPU at any time.
+   rfc_radioOp_t *pNextOp;              //!<        Pointer to the next operation to run after this operation is done
+   ratmr_t startTime;                   //!<        Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+   struct {
+      uint8_t triggerType:4;            //!<        The type of trigger
+      uint8_t bEnaCmd:1;                //!< \brief 0: No alternative trigger command<br>
+                                        //!<        1: CMD_TRIGGER can be used as an alternative trigger
+      uint8_t triggerNo:2;              //!<        The trigger number of the CMD_TRIGGER command that triggers this action
+      uint8_t pastTrig:1;               //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+                                        //!<        1: A trigger in the past is triggered as soon as possible
+   } startTrigger;                      //!<        Identification of the trigger that starts the operation
+   struct {
+      uint8_t rule:4;                   //!<        Condition for running next command: Rule for how to proceed
+      uint8_t nSkip:4;                  //!<        Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+   } condition;
+   uint8_t channel;                     //!< \brief Channel to tune to in the start of the operation<br>
+                                        //!<        0: Use existing channel<br>
+                                        //!<        11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 &times; (channel - 11)) MHz<br>
+                                        //!<        60--207: Frequency is  (2300 + channel) MHz<br>
+                                        //!<        Others: <i>Reserved</i>
+   struct {
+      uint8_t ccaEnEnergy:1;            //!<        Enable energy scan as CCA source
+      uint8_t ccaEnCorr:1;              //!<        Enable correlator based carrier sense as CCA source
+      uint8_t ccaEnSync:1;              //!<        Enable sync found based carrier sense as CCA source
+      uint8_t ccaCorrOp:1;              //!< \brief Operator to use between energy based and correlator based CCA<br>
+                                        //!<        0: Report busy channel if either ccaEnergy or ccaCorr are busy<br>
+                                        //!<        1: Report busy channel if both ccaEnergy and ccaCorr are busy
+      uint8_t ccaSyncOp:1;              //!< \brief Operator to use between sync found based CCA and the others<br>
+                                        //!<        0: Always report busy channel if ccaSync is busy<br>
+                                        //!<        1: Always report idle channel if ccaSync is idle
+      uint8_t ccaCorrThr:2;             //!<        Threshold for number of correlation peaks in correlator based carrier sense
+   } ccaOpt;                            //!<        CCA options
+   int8_t ccaRssiThr;                   //!<        RSSI threshold for CCA
+   uint8_t __dummy0;
+   int8_t maxRssi;                      //!<        The maximum RSSI recorded during the ED scan
+   struct {
+      uint8_t triggerType:4;            //!<        The type of trigger
+      uint8_t bEnaCmd:1;                //!< \brief 0: No alternative trigger command<br>
+                                        //!<        1: CMD_TRIGGER can be used as an alternative trigger
+      uint8_t triggerNo:2;              //!<        The trigger number of the CMD_TRIGGER command that triggers this action
+      uint8_t pastTrig:1;               //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+                                        //!<        1: A trigger in the past is triggered as soon as possible
+   } endTrigger;                        //!<        Trigger that causes the device to end the Rx operation
+   ratmr_t endTime;                     //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the Rx
+                                        //!<        operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_TX
+//! @{
+#define CMD_IEEE_TX                                             0x2C01
+//! IEEE 802.15.4 Transmit Command
+struct __RFC_STRUCT rfc_CMD_IEEE_TX_s {
+   uint16_t commandNo;                  //!<        The command ID number 0x2C01
+   uint16_t status;                     //!< \brief An integer telling the status of the command. This value is
+                                        //!<        updated by the radio CPU during operation and may be read by the
+                                        //!<        system CPU at any time.
+   rfc_radioOp_t *pNextOp;              //!<        Pointer to the next operation to run after this operation is done
+   ratmr_t startTime;                   //!<        Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+   struct {
+      uint8_t triggerType:4;            //!<        The type of trigger
+      uint8_t bEnaCmd:1;                //!< \brief 0: No alternative trigger command<br>
+                                        //!<        1: CMD_TRIGGER can be used as an alternative trigger
+      uint8_t triggerNo:2;              //!<        The trigger number of the CMD_TRIGGER command that triggers this action
+      uint8_t pastTrig:1;               //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+                                        //!<        1: A trigger in the past is triggered as soon as possible
+   } startTrigger;                      //!<        Identification of the trigger that starts the operation
+   struct {
+      uint8_t rule:4;                   //!<        Condition for running next command: Rule for how to proceed
+      uint8_t nSkip:4;                  //!<        Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+   } condition;
+   struct {
+      uint8_t bIncludePhyHdr:1;         //!< \brief 0: Find PHY header automatically<br>
+                                        //!<        1: Insert PHY header from the buffer
+      uint8_t bIncludeCrc:1;            //!< \brief 0: Append automatically calculated CRC<br>
+                                        //!<        1: Insert FCS (CRC) from the buffer
+      uint8_t :1;
+      uint8_t payloadLenMsb:5;          //!< \brief Most significant bits of payload length. Should only be non-zero to create long
+                                        //!<        non-standard packets for test purposes
+   } txOpt;
+   uint8_t payloadLen;                  //!<        Number of bytes in the payload
+   uint8_t* pPayload;                   //!<        Pointer to payload buffer of size <code>payloadLen</code>
+   ratmr_t timeStamp;                   //!<        Time stamp of transmitted frame
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_CSMA
+//! @{
+#define CMD_IEEE_CSMA                                           0x2C02
+//! IEEE 802.15.4 CSMA-CA Command
+struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s {
+   uint16_t commandNo;                  //!<        The command ID number 0x2C02
+   uint16_t status;                     //!< \brief An integer telling the status of the command. This value is
+                                        //!<        updated by the radio CPU during operation and may be read by the
+                                        //!<        system CPU at any time.
+   rfc_radioOp_t *pNextOp;              //!<        Pointer to the next operation to run after this operation is done
+   ratmr_t startTime;                   //!<        Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+   struct {
+      uint8_t triggerType:4;            //!<        The type of trigger
+      uint8_t bEnaCmd:1;                //!< \brief 0: No alternative trigger command<br>
+                                        //!<        1: CMD_TRIGGER can be used as an alternative trigger
+      uint8_t triggerNo:2;              //!<        The trigger number of the CMD_TRIGGER command that triggers this action
+      uint8_t pastTrig:1;               //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+                                        //!<        1: A trigger in the past is triggered as soon as possible
+   } startTrigger;                      //!<        Identification of the trigger that starts the operation
+   struct {
+      uint8_t rule:4;                   //!<        Condition for running next command: Rule for how to proceed
+      uint8_t nSkip:4;                  //!<        Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+   } condition;
+   uint16_t randomState;                //!<        The state of the pseudo-random generator
+   uint8_t macMaxBE;                    //!<        The IEEE 802.15.4 MAC parameter <i>macMaxBE</i>
+   uint8_t macMaxCSMABackoffs;          //!<        The IEEE 802.15.4 MAC parameter <i>macMaxCSMABackoffs</i>
+   struct {
+      uint8_t initCW:5;                 //!<        The initialization value for the CW parameter
+      uint8_t bSlotted:1;               //!< \brief 0:  non-slotted CSMA<br>
+                                        //!<        1: slotted CSMA
+      uint8_t rxOffMode:2;              //!< \brief 0: RX stays on during CSMA backoffs<br>
+                                        //!<        1: The CSMA-CA algorithm will suspend the receiver if no frame is being received<br>
+                                        //!<        2: The CSMA-CA algorithm will suspend the receiver if no frame is being received,
+                                        //!<        or after finishing it (including auto ACK) otherwise<br>
+                                        //!<        3: The CSMA-CA algorithm will suspend the receiver immediately during back-offs
+   } csmaConfig;
+   uint8_t NB;                          //!<        The NB parameter from the IEEE 802.15.4 CSMA-CA algorithm
+   uint8_t BE;                          //!<        The BE parameter from the IEEE 802.15.4 CSMA-CA algorithm
+   uint8_t remainingPeriods;            //!<        The number of remaining periods from a paused backoff countdown
+   int8_t lastRssi;                     //!<        RSSI measured at the last CCA operation
+   struct {
+      uint8_t triggerType:4;            //!<        The type of trigger
+      uint8_t bEnaCmd:1;                //!< \brief 0: No alternative trigger command<br>
+                                        //!<        1: CMD_TRIGGER can be used as an alternative trigger
+      uint8_t triggerNo:2;              //!<        The trigger number of the CMD_TRIGGER command that triggers this action
+      uint8_t pastTrig:1;               //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+                                        //!<        1: A trigger in the past is triggered as soon as possible
+   } endTrigger;                        //!<        Trigger that causes the device to end the CSMA-CA operation
+   ratmr_t lastTimeStamp;               //!<        Time of the last CCA operation
+   ratmr_t endTime;                     //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the
+                                        //!<        CSMA-CA operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_RX_ACK
+//! @{
+#define CMD_IEEE_RX_ACK                                         0x2C03
+//! IEEE 802.15.4 Receive Acknowledgement Command
+struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s {
+   uint16_t commandNo;                  //!<        The command ID number 0x2C03
+   uint16_t status;                     //!< \brief An integer telling the status of the command. This value is
+                                        //!<        updated by the radio CPU during operation and may be read by the
+                                        //!<        system CPU at any time.
+   rfc_radioOp_t *pNextOp;              //!<        Pointer to the next operation to run after this operation is done
+   ratmr_t startTime;                   //!<        Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+   struct {
+      uint8_t triggerType:4;            //!<        The type of trigger
+      uint8_t bEnaCmd:1;                //!< \brief 0: No alternative trigger command<br>
+                                        //!<        1: CMD_TRIGGER can be used as an alternative trigger
+      uint8_t triggerNo:2;              //!<        The trigger number of the CMD_TRIGGER command that triggers this action
+      uint8_t pastTrig:1;               //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+                                        //!<        1: A trigger in the past is triggered as soon as possible
+   } startTrigger;                      //!<        Identification of the trigger that starts the operation
+   struct {
+      uint8_t rule:4;                   //!<        Condition for running next command: Rule for how to proceed
+      uint8_t nSkip:4;                  //!<        Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+   } condition;
+   uint8_t seqNo;                       //!<        Sequence number to expect
+   struct {
+      uint8_t triggerType:4;            //!<        The type of trigger
+      uint8_t bEnaCmd:1;                //!< \brief 0: No alternative trigger command<br>
+                                        //!<        1: CMD_TRIGGER can be used as an alternative trigger
+      uint8_t triggerNo:2;              //!<        The trigger number of the CMD_TRIGGER command that triggers this action
+      uint8_t pastTrig:1;               //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+                                        //!<        1: A trigger in the past is triggered as soon as possible
+   } endTrigger;                        //!<        Trigger that causes the device to give up acknowledgement reception
+   ratmr_t endTime;                     //!< \brief Time used together with <code>endTrigger</code> that causes the device to give up
+                                        //!<        acknowledgement reception
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_ABORT_BG
+//! @{
+#define CMD_IEEE_ABORT_BG                                       0x2C04
+//! IEEE 802.15.4 Abort Background Level Command
+struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s {
+   uint16_t commandNo;                  //!<        The command ID number 0x2C04
+   uint16_t status;                     //!< \brief An integer telling the status of the command. This value is
+                                        //!<        updated by the radio CPU during operation and may be read by the
+                                        //!<        system CPU at any time.
+   rfc_radioOp_t *pNextOp;              //!<        Pointer to the next operation to run after this operation is done
+   ratmr_t startTime;                   //!<        Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+   struct {
+      uint8_t triggerType:4;            //!<        The type of trigger
+      uint8_t bEnaCmd:1;                //!< \brief 0: No alternative trigger command<br>
+                                        //!<        1: CMD_TRIGGER can be used as an alternative trigger
+      uint8_t triggerNo:2;              //!<        The trigger number of the CMD_TRIGGER command that triggers this action
+      uint8_t pastTrig:1;               //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+                                        //!<        1: A trigger in the past is triggered as soon as possible
+   } startTrigger;                      //!<        Identification of the trigger that starts the operation
+   struct {
+      uint8_t rule:4;                   //!<        Condition for running next command: Rule for how to proceed
+      uint8_t nSkip:4;                  //!<        Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+   } condition;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_MOD_CCA
+//! @{
+#define CMD_IEEE_MOD_CCA                                        0x2001
+//! IEEE 802.15.4 Modify CCA Parameter Command
+struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s {
+   uint16_t commandNo;                  //!<        The command ID number 0x2001
+   struct {
+      uint8_t ccaEnEnergy:1;            //!<        Enable energy scan as CCA source
+      uint8_t ccaEnCorr:1;              //!<        Enable correlator based carrier sense as CCA source
+      uint8_t ccaEnSync:1;              //!<        Enable sync found based carrier sense as CCA source
+      uint8_t ccaCorrOp:1;              //!< \brief Operator to use between energy based and correlator based CCA<br>
+                                        //!<        0: Report busy channel if either ccaEnergy or ccaCorr are busy<br>
+                                        //!<        1: Report busy channel if both ccaEnergy and ccaCorr are busy
+      uint8_t ccaSyncOp:1;              //!< \brief Operator to use between sync found based CCA and the others<br>
+                                        //!<        0: Always report busy channel if ccaSync is busy<br>
+                                        //!<        1: Always report idle channel if ccaSync is idle
+      uint8_t ccaCorrThr:2;             //!<        Threshold for number of correlation peaks in correlator based carrier sense
+   } newCcaOpt;                         //!<        New value of <code>ccaOpt</code> for the running background level operation
+   int8_t newCcaRssiThr;                //!<        New value of <code>ccaRssiThr</code> for the running background level operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_MOD_FILT
+//! @{
+#define CMD_IEEE_MOD_FILT                                       0x2002
+//! IEEE 802.15.4 Modify Frame Filtering Parameter Command
+struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s {
+   uint16_t commandNo;                  //!<        The command ID number 0x2002
+   struct {
+      uint16_t frameFiltEn:1;           //!< \brief 0: Disable frame filtering<br>
+                                        //!<        1: Enable frame filtering
+      uint16_t frameFiltStop:1;         //!< \brief 0: Receive all packets to the end<br>
+                                        //!<        1: Stop receiving frame once frame filtering has caused the frame to be rejected.
+      uint16_t autoAckEn:1;             //!< \brief 0: Disable auto ACK<br>
+                                        //!<        1: Enable auto ACK.
+      uint16_t slottedAckEn:1;          //!< \brief 0: Non-slotted ACK<br>
+                                        //!<        1: Slotted ACK.
+      uint16_t autoPendEn:1;            //!< \brief 0: Auto-pend disabled<br>
+                                        //!<        1: Auto-pend enabled
+      uint16_t defaultPend:1;           //!<        The value of the pending data bit in auto ACK packets that are not subject to auto-pend
+      uint16_t bPendDataReqOnly:1;      //!< \brief 0: Use auto-pend for any packet<br>
+                                        //!<        1: Use auto-pend for data request packets only
+      uint16_t bPanCoord:1;             //!< \brief 0: Device is not PAN coordinator<br>
+                                        //!<        1: Device is PAN coordinator
+      uint16_t maxFrameVersion:2;       //!<        Reject frames where the frame version field in the FCF is greater than this value
+      uint16_t fcfReservedMask:3;       //!<        Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero
+      uint16_t modifyFtFilter:2;        //!< \brief Treatment of MSB of frame type field before frame-type filtering:<br>
+                                        //!<        0: No modification<br>
+                                        //!<        1: Invert MSB<br>
+                                        //!<        2: Set MSB to 0<br>
+                                        //!<        3: Set MSB to 1
+      uint16_t bStrictLenFilter:1;      //!< \brief 0: Accept acknowledgement frames of any length >= 5<br>
+                                        //!<        1: Accept only acknowledgement frames of length 5
+   } newFrameFiltOpt;                   //!<        New value of <code>frameFiltOpt</code> for the running background level operation
+   struct {
+      uint8_t bAcceptFt0Beacon:1;       //!< \brief Treatment of frames with frame type 000 (beacon):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+      uint8_t bAcceptFt1Data:1;         //!< \brief Treatment of frames with frame type 001 (data):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+      uint8_t bAcceptFt2Ack:1;          //!< \brief Treatment of frames with frame type 010 (ACK):<br>
+                                        //!<        0: Reject, unless running ACK receive command<br>
+                                        //!<        1: Always accept
+      uint8_t bAcceptFt3MacCmd:1;       //!< \brief Treatment of frames with frame type 011 (MAC command):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+      uint8_t bAcceptFt4Reserved:1;     //!< \brief Treatment of frames with frame type 100 (reserved):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+      uint8_t bAcceptFt5Reserved:1;     //!< \brief Treatment of frames with frame type 101 (reserved):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+      uint8_t bAcceptFt6Reserved:1;     //!< \brief Treatment of frames with frame type 110 (reserved):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+      uint8_t bAcceptFt7Reserved:1;     //!< \brief Treatment of frames with frame type 111 (reserved):<br>
+                                        //!<        0: Reject<br>
+                                        //!<        1: Accept
+   } newFrameTypes;                     //!<        New value of <code>frameTypes</code> for the running background level operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_MOD_SRC_MATCH
+//! @{
+#define CMD_IEEE_MOD_SRC_MATCH                                  0x2003
+//! IEEE 802.15.4 Enable/Disable Source Matching Entry Command
+struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s {
+   uint16_t commandNo;                  //!<        The command ID number 0x2003
+   struct {
+      uint8_t bEnable:1;                //!< \brief 0: Disable entry<br>
+                                        //!<        1: Enable entry
+      uint8_t srcPend:1;                //!<        New value of the pending bit for the entry
+      uint8_t entryType:1;              //!< \brief 0: Short address<br>
+                                        //!<        1: Extended address
+   } options;
+   uint8_t entryNo;                     //!<        Index of entry to enable or disable
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_ABORT_FG
+//! @{
+#define CMD_IEEE_ABORT_FG                                       0x2401
+//! IEEE 802.15.4 Abort Foreground Level Command
+struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s {
+   uint16_t commandNo;                  //!<        The command ID number 0x2401
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_STOP_FG
+//! @{
+#define CMD_IEEE_STOP_FG                                        0x2402
+//! IEEE 802.15.4 Gracefully Stop Foreground Level Command
+struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s {
+   uint16_t commandNo;                  //!<        The command ID number 0x2402
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_CCA_REQ
+//! @{
+#define CMD_IEEE_CCA_REQ                                        0x2403
+//! IEEE 802.15.4 CCA and RSSI Information Request Command
+struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s {
+   uint16_t commandNo;                  //!<        The command ID number 0x2403
+   int8_t currentRssi;                  //!<        The RSSI currently observed on the channel
+   int8_t maxRssi;                      //!<        The maximum RSSI observed on the channel since Rx was started
+   struct {
+      uint8_t ccaState:2;               //!< \brief Value of the current CCA state<br>
+                                        //!<        0: Idle<br>
+                                        //!<        1: Busy<br>
+                                        //!<        2: Invalid
+      uint8_t ccaEnergy:2;              //!< \brief Value of the current energy detect CCA state<br>
+                                        //!<        0: Idle<br>
+                                        //!<        1: Busy<br>
+                                        //!<        2: Invalid
+      uint8_t ccaCorr:2;                //!< \brief Value of the current correlator based carrier sense CCA state<br>
+                                        //!<        0: Idle<br>
+                                        //!<        1: Busy<br>
+                                        //!<        2: Invalid
+      uint8_t ccaSync:1;                //!< \brief Value of the current sync found based carrier sense CCA state<br>
+                                        //!<        0: Idle<br>
+                                        //!<        1: Busy
+   } ccaInfo;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ieeeRxOutput
+//! @{
+//! Output structure for CMD_IEEE_RX
+
+struct __RFC_STRUCT rfc_ieeeRxOutput_s {
+   uint8_t nTxAck;                      //!<        Total number of transmitted ACK frames
+   uint8_t nRxBeacon;                   //!<        Number of received beacon frames
+   uint8_t nRxData;                     //!<        Number of received data frames
+   uint8_t nRxAck;                      //!<        Number of received acknowledgement frames
+   uint8_t nRxMacCmd;                   //!<        Number of received MAC command frames
+   uint8_t nRxReserved;                 //!<        Number of received frames with reserved frame type
+   uint8_t nRxNok;                      //!<        Number of received frames with CRC error
+   uint8_t nRxIgnored;                  //!<        Number of frames received that are to be ignored
+   uint8_t nRxBufFull;                  //!<        Number of received frames discarded because the Rx buffer was full
+   int8_t lastRssi;                     //!<        RSSI of last received frame
+   int8_t maxRssi;                      //!<        Highest RSSI observed in the operation
+   uint8_t __dummy0;
+   ratmr_t beaconTimeStamp;             //!<        Time stamp of last received beacon frame
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup shortAddrEntry
+//! @{
+//! Structure for short address entries
+
+struct __RFC_STRUCT rfc_shortAddrEntry_s {
+   uint16_t shortAddr;                  //!<        Short address
+   uint16_t panId;                      //!<        PAN ID
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ieeeRxCorrCrc
+//! @{
+//! Receive status byte that may be appended to message in receive buffer
+
+struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s {
+   struct {
+      uint8_t corr:6;                   //!<        The correlation value
+      uint8_t bIgnore:1;                //!<        1 if the packet should be rejected by frame filtering, 0 otherwise
+      uint8_t bCrcErr:1;                //!<        1 if the packet was received with CRC error, 0 otherwise
+   } status;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! @}
+//! @}
+#endif

arch/cpu/simplelink-cc13xx-cc26xx/cc13x0-cc26x0/driverlib/rf_ieee_mailbox.h

@@ -0,0 +1,74 @@
+/******************************************************************************
+*  Filename:       rf_ieee_mailbox.h
+*  Revised:        2018-01-23 19:51:42 +0100 (Tue, 23 Jan 2018)
+*  Revision:       18189
+*
+*  Description:    Definitions for IEEE 802.15.4 interface
+*
+*  Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+*  All rights reserved.
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions are met:
+*
+*  1) Redistributions of source code must retain the above copyright notice,
+*     this list of conditions and the following disclaimer.
+*
+*  2) Redistributions in binary form must reproduce the above copyright notice,
+*     this list of conditions and the following disclaimer in the documentation
+*     and/or other materials provided with the distribution.
+*
+*  3) Neither the name of the ORGANIZATION nor the names of its contributors may
+*     be used to endorse or promote products derived from this software without
+*     specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+*  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+*  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+*  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+*  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+*  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+*  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+*  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+*  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+*  POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef _IEEE_MAILBOX_H
+#define _IEEE_MAILBOX_H
+
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(driverlib/rf_mailbox.h)
+
+/// \name Radio operation status
+///@{
+/// \name Operation not finished
+///@{
+#define IEEE_SUSPENDED          0x2001  ///< Operation suspended
+///@}
+/// \name Operation finished normally
+///@{
+#define IEEE_DONE_OK            0x2400  ///< Operation ended normally
+#define IEEE_DONE_BUSY          0x2401  ///< CSMA-CA operation ended with failure
+#define IEEE_DONE_STOPPED       0x2402  ///< Operation stopped after stop command
+#define IEEE_DONE_ACK           0x2403  ///< ACK packet received with pending data bit cleared
+#define IEEE_DONE_ACKPEND       0x2404  ///< ACK packet received with pending data bit set
+#define IEEE_DONE_TIMEOUT       0x2405  ///< Operation ended due to timeout
+#define IEEE_DONE_BGEND         0x2406  ///< FG operation ended because necessary background level
+                                        ///< operation ended
+#define IEEE_DONE_ABORT         0x2407  ///< Operation aborted by command
+///@}
+/// \name Operation finished with error
+///@{
+#define IEEE_ERROR_PAR          0x2800  ///< Illegal parameter
+#define IEEE_ERROR_NO_SETUP     0x2801  ///< Operation using Rx or Tx attempted when not in 15.4 mode
+#define IEEE_ERROR_NO_FS        0x2802  ///< Operation using Rx or Tx attempted without frequency synth configured
+#define IEEE_ERROR_SYNTH_PROG   0x2803  ///< Synthesizer programming failed to complete on time
+#define IEEE_ERROR_RXOVF        0x2804  ///< Receiver overflowed during operation
+#define IEEE_ERROR_TXUNF        0x2805  ///< Transmitter underflowed during operation
+///@}
+///@}
+
+#endif

arch/cpu/simplelink-cc13xx-cc26xx/cc13x0-cc26x0/rf_patches/rf_patch_cpe_ieee.h

@@ -0,0 +1,269 @@
+/******************************************************************************
+*  Filename:       rf_patch_cpe_ieee.h
+*  Revised:        $Date$
+*  Revision:       $Revision$
+*
+*  Description:    RF Core patch file for CC26xx IEEE 802.15.4 PHY
+*
+*  Copyright (c) 2015, Texas Instruments Incorporated
+*  All rights reserved.
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions are met:
+*
+*  1) Redistributions of source code must retain the above copyright notice,
+*     this list of conditions and the following disclaimer.
+*
+*  2) Redistributions in binary form must reproduce the above copyright notice,
+*     this list of conditions and the following disclaimer in the documentation
+*     and/or other materials provided with the distribution.
+*
+*  3) Neither the name of the ORGANIZATION nor the names of its contributors may
+*     be used to endorse or promote products derived from this software without
+*     specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+*  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+*  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+*  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+*  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+*  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+*  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+*  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+*  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+*  POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef _RF_PATCH_CPE_IEEE_H
+#define _RF_PATCH_CPE_IEEE_H
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <string.h>
+
+#ifndef CPE_PATCH_TYPE
+#define CPE_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef SYS_PATCH_TYPE
+#define SYS_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef PATCH_FUN_SPEC
+#define PATCH_FUN_SPEC static inline
+#endif
+
+#ifndef _APPLY_PATCH_TAB
+#define _APPLY_PATCH_TAB
+#endif
+
+
+CPE_PATCH_TYPE patchImageIeee[] = {
+   0x210004ef,
+   0x21000419,
+   0x21000519,
+   0x21000599,
+   0x210004b1,
+   0x22024823,
+   0x421a7dc3,
+   0xd0034472,
+   0x1dc04678,
+   0xb5f84686,
+   0x4c1f4710,
+   0x200834ae,
+   0x490347a0,
+   0x60082008,
+   0x3cec6008,
+   0xbdf847a0,
+   0x40045004,
+   0x4c17b5f0,
+   0x18612140,
+   0x280278c8,
+   0x4809d005,
+   0x60012100,
+   0x47884908,
+   0x6e25bdf0,
+   0x60354e07,
+   0x43280760,
+   0x68276620,
+   0x480e6024,
+   0x60274780,
+   0xbdf06035,
+   0x4004112c,
+   0x000065a5,
+   0x40044028,
+   0x4c07b510,
+   0x29007da1,
+   0x2101d105,
+   0x024875a1,
+   0x393e4904,
+   0x68204788,
+   0xd0002800,
+   0xbd104780,
+   0x21000254,
+   0x0000398b,
+   0x6a034807,
+   0x46784907,
+   0x46861dc0,
+   0x4788b5f8,
+   0x009b089b,
+   0x6a014802,
+   0xd10007c9,
+   0xbdf86203,
+   0x40045040,
+   0x0000f1ab,
+   0x6a00480b,
+   0xd00407c0,
+   0x2201480a,
+   0x43117801,
+   0x48097001,
+   0x72c84700,
+   0xd006280d,
+   0x00802285,
+   0x18800252,
+   0x60486840,
+   0x48044770,
+   0x0000e7fb,
+   0x40045040,
+   0x21000268,
+   0x0000ff39,
+   0x210004d9,
+   0x4e1ab5f8,
+   0x6b314605,
+   0x09cc4819,
+   0x2d0001e4,
+   0x4918d011,
+   0x29027809,
+   0x7b00d00f,
+   0xb6724304,
+   0x4f152001,
+   0x47b80240,
+   0x38204811,
+   0x09c18800,
+   0xd00407c9,
+   0x7ac0e016,
+   0x7b40e7f0,
+   0x490fe7ee,
+   0x61cc6334,
+   0x07c00a40,
+   0x2001d00c,
+   0x6af10380,
+   0xd0012d00,
+   0xe0004301,
+   0x46084381,
+   0x490762f1,
+   0x63483940,
+   0x47b82000,
+   0xbdf8b662,
+   0x21000280,
+   0x21000088,
+   0x21000296,
+   0x00003cdf,
+   0x40044040,
+   0x28004907,
+   0x2004d000,
+   0xb6724a06,
+   0x07c97809,
+   0x5810d001,
+   0x2080e000,
+   0xb240b662,
+   0x00004770,
+   0x2100026b,
+   0x40046058,
+};
+#define _NWORD_PATCHIMAGE_IEEE 111
+
+#define _NWORD_PATCHSYS_IEEE 0
+
+#define _IRQ_PATCH_0 0x21000449
+#define _IRQ_PATCH_1 0x21000489
+
+
+#ifndef _IEEE_SYSRAM_START
+#define _IEEE_SYSRAM_START 0x20000000
+#endif
+
+#ifndef _IEEE_CPERAM_START
+#define _IEEE_CPERAM_START 0x21000000
+#endif
+
+#define _IEEE_SYS_PATCH_FIXED_ADDR 0x20000000
+
+#define _IEEE_PARSER_PATCH_TAB_OFFSET 0x0334
+#define _IEEE_PATCH_TAB_OFFSET 0x033C
+#define _IEEE_IRQPATCH_OFFSET 0x03AC
+#define _IEEE_PATCH_VEC_OFFSET 0x0404
+
+PATCH_FUN_SPEC void enterIeeeCpePatch(void)
+{
+   uint32_t *pPatchVec = (uint32_t *) (_IEEE_CPERAM_START + _IEEE_PATCH_VEC_OFFSET);
+
+#if (_NWORD_PATCHIMAGE_IEEE > 0)
+   memcpy(pPatchVec, patchImageIeee, sizeof(patchImageIeee));
+#endif
+}
+
+PATCH_FUN_SPEC void enterIeeeSysPatch(void)
+{
+}
+
+PATCH_FUN_SPEC void configureIeeePatch(void)
+{
+   uint8_t *pPatchTab = (uint8_t *) (_IEEE_CPERAM_START + _IEEE_PATCH_TAB_OFFSET);
+   uint32_t *pIrqPatch = (uint32_t *) (_IEEE_CPERAM_START + _IEEE_IRQPATCH_OFFSET);
+
+
+   pPatchTab[5] = 0;
+   pPatchTab[52] = 1;
+   pPatchTab[103] = 2;
+   pPatchTab[60] = 3;
+   pPatchTab[38] = 4;
+
+   pIrqPatch[1] = _IRQ_PATCH_0;
+   pIrqPatch[9] = _IRQ_PATCH_1;
+}
+
+PATCH_FUN_SPEC void applyIeeePatch(void)
+{
+   enterIeeeSysPatch();
+   enterIeeeCpePatch();
+   configureIeeePatch();
+}
+
+PATCH_FUN_SPEC void refreshIeeePatch(void)
+{
+   enterIeeeCpePatch();
+   configureIeeePatch();
+}
+
+PATCH_FUN_SPEC void rf_patch_cpe_ieee(void)
+{
+   applyIeeePatch();
+}
+
+#undef _IRQ_PATCH_0
+#undef _IRQ_PATCH_1
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //  _RF_PATCH_CPE_IEEE_H
+

arch/cpu/simplelink-cc13xx-cc26xx/cc13x2-cc26x2/Makefile.cc13x2-cc26x2

@@ -0,0 +1,11 @@
+################################################################################
+### CC13x2/CC26x2 CPU makefile
+
+# Simplelink SDK pre-compiled libraries
+TARGET_LIBFILES += $(SDK_NORTOS)/lib/nortos_$(SDK_LIB_NAME).am4fg
+TARGET_LIBFILES += $(SDK_DRIVERS)/rf/lib/rf_multiMode_$(SDK_LIB_NAME).am4fg
+TARGET_LIBFILES += $(SDK_DRIVERS)/lib/drivers_$(SDK_LIB_NAME).am4fg
+TARGET_LIBFILES += $(SDK_DEVICES)/driverlib/bin/gcc/driverlib.lib
+
+# CC13x2/CC26x2 is a Cortex-M4 architecture
+include $(CONTIKI)/arch/cpu/arm/cortex-m/cm4/Makefile.cm4

arch/cpu/simplelink-cc13xx-cc26xx/cc13x2-cc26x2/cc13x2-cc26x2-cm4.h

@@ -0,0 +1,128 @@
+/*
+ * Template:
+ * Copyright (c) 2012 ARM LIMITED
+ * All rights reserved.
+ *
+ * CC13xx-CC26xx:
+ * Copyright (c) 2017, George Oikonomou - http://www.spd.gr
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*---------------------------------------------------------------------------*/
+/**
+ * \addtogroup cc26xx
+ * @{
+ *
+ * \defgroup cc26xx-cm4 CC13xx/CC26xx CMSIS
+ *
+ * CC13xx/CC26xx Cortex-M4 CMSIS definitions
+ * @{
+ *
+ * \file
+ * CMSIS Cortex-M4 core peripheral access layer header file for CC13xx/CC26xx
+ */
+/*---------------------------------------------------------------------------*/
+#ifndef CC13XX_CC26XX_CM4_H_
+#define CC13XX_CC26XX_CM4_H_
+/*---------------------------------------------------------------------------*/
+/**
+ * \name Interrupt Number Definition
+ * @{
+ */
+typedef enum cc13xx_cc26xx_cm4_irq_e {
+  /* Cortex-M4 Processor Exceptions */
+  CC13XX_CC26XX_CM4_EXCEPTION_RESET = -15,            /**<  1 Reset */
+  CC13XX_CC26XX_CM4_EXCEPTION_NMI = -14,              /**<  2 NMI */
+  CC13XX_CC26XX_CM4_EXCEPTION_HARD_FAULT = -13,       /**<  3 Hard fault */
+  CC13XX_CC26XX_CM4_EXCEPTION_MPU_FAULT = -12,        /**<  4 MPU fault */
+  CC13XX_CC26XX_CM4_EXCEPTION_BUS_FAULT = -11,        /**<  5 Bus fault */
+  CC13XX_CC26XX_CM4_EXCEPTION_USAGE_FAULT = -10,      /**<  6 Usage fault */
+  CC13XX_CC26XX_CM4_EXCEPTION_SV_CALL = -5,           /**< 11 SVCall */
+  CC13XX_CC26XX_CM4_EXCEPTION_DEBUG_MON = -4,         /**< 12 Debug monitor */
+  CC13XX_CC26XX_CM4_EXCEPTION_PEND_SV = -2,           /**< 14 PendSV */
+  CC13XX_CC26XX_CM4_EXCEPTION_SYS_TICK = -1,          /**< 15 SysTick */
+
+  /* CC13xx/CC26xx interrupts */
+  CC13XX_CC26XX_CM4_IRQ_EDGE_DETECT = 0,              /**< 16 AON edge detect */
+  CC13XX_CC26XX_CM4_EXCEPTION_I2C = 1,                /**< 17 I2C */
+  CC13XX_CC26XX_CM4_EXCEPTION_RF_CPE1 = 2,            /**< 18 RF Command and Packet Engine 1 */
+  CC13XX_CC26XX_CM4_EXCEPTION_AON_SPI_SLAVE = 3,      /**< 19 AON SpiSplave Rx, Tx and CS */
+  CC13XX_CC26XX_CM4_EXCEPTION_AON_RTC = 4,            /**< 20 AON RTC */
+  CC13XX_CC26XX_CM4_EXCEPTION_UART0 = 5,              /**< 21 UART0 Rx and Tx */
+  CC13XX_CC26XX_CM4_EXCEPTION_AON_AUX_SWEV0 = 6,      /**< 22 Sensor Controller software event 0, through AON domain*/
+  CC13XX_CC26XX_CM4_EXCEPTION_SSI0 = 7,               /**< 23 SSI0 Rx and Tx */
+  CC13XX_CC26XX_CM4_EXCEPTION_SSI1 = 8,               /**< 24 SSI1 Rx and Tx */
+  CC13XX_CC26XX_CM4_EXCEPTION_RF_CPE0 = 9,            /**< 25 RF Command and Packet Engine 0 */
+  CC13XX_CC26XX_CM4_EXCEPTION_RF_HW = 10,             /**< 26 RF Core Hardware */
+  CC13XX_CC26XX_CM4_EXCEPTION_RF_CMD_ACK = 11,        /**< 27 RF Core Command Acknowledge */
+  CC13XX_CC26XX_CM4_EXCEPTION_I2S = 12,               /**< 28 I2S */
+  CC13XX_CC26XX_CM4_EXCEPTION_AON_AUX_SWEV1 = 13,     /**< 29 Sensor Controller software event 1, through AON domain*/
+  CC13XX_CC26XX_CM4_EXCEPTION_WATCHDOG = 14,          /**< 30 Watchdog timer */
+  CC13XX_CC26XX_CM4_EXCEPTION_GPTIMER_0A = 15,        /**< 31 Timer 0 subtimer A */
+  CC13XX_CC26XX_CM4_EXCEPTION_GPTIMER_0B = 16,        /**< 32 Timer 0 subtimer B */
+  CC13XX_CC26XX_CM4_EXCEPTION_GPTIMER_1A = 17,        /**< 33 Timer 1 subtimer A */
+  CC13XX_CC26XX_CM4_EXCEPTION_GPTIMER_1B = 18,        /**< 34 Timer 1 subtimer B */
+  CC13XX_CC26XX_CM4_EXCEPTION_GPTIMER_2A = 19,        /**< 35 Timer 2 subtimer A */
+  CC13XX_CC26XX_CM4_EXCEPTION_GPTIMER_2B = 20,        /**< 36 Timer 2 subtimer B */
+  CC13XX_CC26XX_CM4_EXCEPTION_GPTIMER_3A = 21,        /**< 37 Timer 3 subtimer A */
+  CC13XX_CC26XX_CM4_EXCEPTION_GPTIMER_3B = 22,        /**< 38 Timer 3 subtimer B */
+  CC13XX_CC26XX_CM4_EXCEPTION_CRYPTO = 23,            /**< 39 Crypto Core Result available */
+  CC13XX_CC26XX_CM4_EXCEPTION_UDMA = 24,              /**< 40 uDMA Software */
+  CC13XX_CC26XX_CM4_EXCEPTION_UDMA_ERR = 25,          /**< 41 uDMA Error */
+  CC13XX_CC26XX_CM4_EXCEPTION_FLASH_CTRL = 26,        /**< 42 Flash controller */
+  CC13XX_CC26XX_CM4_EXCEPTION_SW0 = 27,               /**< 43 Software Event 0 */
+  CC13XX_CC26XX_CM4_EXCEPTION_AUX_COM_EVENT = 28,     /**< 44 AUX combined event, directly to MCU domain*/
+  CC13XX_CC26XX_CM4_EXCEPTION_AON_PRG0 = 29,          /**< 45 AON programmable 0 */
+  CC13XX_CC26XX_CM4_EXCEPTION_PROG = 30,              /**< 46 Dynamic Programmable interrupt (default source: PRCM)*/
+  CC13XX_CC26XX_CM4_EXCEPTION_AUX_COMPA = 31,         /**< 47 AUX Comparator A */
+  CC13XX_CC26XX_CM4_EXCEPTION_AUX_ADC = 32,           /**< 48 AUX ADC IRQ */
+  CC13XX_CC26XX_CM4_EXCEPTION_TRNG = 33,              /**< 49 TRNG event */
+} cc13xx_cc26xx_cm4_irq_t;
+
+typedef cc13xx_cc26xx_cm4_irq_t IRQn_Type;
+
+#define SysTick_IRQn CC13XX_CC26XX_CM4_EXCEPTION_SYS_TICK
+/** @} */
+/*---------------------------------------------------------------------------*/
+/** \name Processor and Core Peripheral Section
+ * @{
+ */
+/* Configuration of the Cortex-M4 Processor and Core Peripherals */
+#define __MPU_PRESENT           1       /**< MPU present or not */
+#define __NVIC_PRIO_BITS        3       /**< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig  0       /**< Set to 1 if different SysTick Config is used */
+/** @} */
+/*---------------------------------------------------------------------------*/
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+/*---------------------------------------------------------------------------*/
+#endif /* CC13XX_CC26XX_CM4_H_ */
+/*---------------------------------------------------------------------------*/
+/**
+ * @}
+ * @}
+ */

arch/cpu/simplelink-cc13xx-cc26xx/cc13x2-cc26x2/cc13x2-cc26x2.icf

@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2017, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+define symbol STACK_SIZE       = 0x800; /* 2048 bytes */
+define symbol HEAP_SIZE        = 0x100; /* 256 bytes */
+
+define symbol __intvec_start__ = 0x00000000;
+
+/*-Memory Regions-*/
+define symbol ROM_start__      = 0x00000000;
+define symbol ROM_end__        = 0x00057FFF;
+define symbol RAM_start__      = 0x20000000;
+define symbol RAM_end__        = 0x20013FFF;
+define symbol GPRAM_start__    = 0x11000000;
+define symbol GPRAM_end__      = 0x11001FFF;
+
+/* Define a memory region that covers the entire 4 GB addressable space */
+define memory mem with size = 4G;
+
+/* Define a region for the on-chip flash */
+define region FLASH_region   = mem:[from ROM_start__ to ROM_end__];
+
+/* Define a region for the on-chip SRAM */
+define region RAM_region     = mem:[from RAM_start__ to RAM_end__];
+
+/* Define a region for the on-chip GPRAM */
+define region GPRAM_region     = mem:[from GPRAM_start__ to GPRAM_end__];
+
+/* Place the interrupt vectors at the start of flash */
+place at address mem:__intvec_start__ { readonly section .intvec };
+keep { section .intvec };
+
+/* Place the CCA area at the end of flash */
+place at end of FLASH_region { readonly section .ccfg };
+keep { section .ccfg };
+
+/* Place remaining 'read only' in Flash */
+place in FLASH_region { readonly };
+
+/* Place all read/write items into RAM */
+place in RAM_region { readwrite };
+initialize by copy { readwrite };
+
+/*
+ * Define CSTACK block to contain .stack section. This enables the IAR IDE
+ * to properly show the stack content during debug. Place stack at end of
+ * retention RAM, do not initialize (initializing the stack will destroy the
+ * return address from the initialization code, causing the processor to branch
+ * to zero and fault)
+ */
+define block CSTACK with alignment = 8, size = STACK_SIZE { section .stack };
+place at end of RAM_region { block CSTACK };
+do not initialize { section .stack, section .noinit };
+
+/* Export stack top symbol. Used by startup file */
+define exported symbol STACK_TOP = RAM_end__ + 1;
+
+/* Primary Heap configuration */
+define block HEAP with alignment = 8, size = HEAP_SIZE { };
+
+/* Place heap just before CSTACK */
+place in RAM_region { block HEAP };

arch/cpu/simplelink-cc13xx-cc26xx/cc13x2-cc26x2/cc13x2-cc26x2.lds

@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2017-2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+MIN_STACKSIZE = 0x600;  /* 1536 bytes */
+HEAPSIZE      = 0x100;  /* 256 bytes */
+
+MEMORY
+{
+    FLASH (RX)      : ORIGIN = 0x00000000, LENGTH = 0x00057fa8
+    /*
+     * Customer Configuration Area and Bootloader Backdoor configuration in
+     * flash, 40 bytes
+     */
+    FLASH_CCFG (RX) : ORIGIN = 0x00057fa8, LENGTH = 0x00000058
+    SRAM (RWX)      : ORIGIN = 0x20000000, LENGTH = 0x00014000
+    GPRAM (RWX)     : ORIGIN = 0x11000000, LENGTH = 0x00002000
+}
+
+REGION_ALIAS("REGION_TEXT",      FLASH);
+REGION_ALIAS("REGION_BSS",       SRAM);
+REGION_ALIAS("REGION_DATA",      SRAM);
+REGION_ALIAS("REGION_STACK",     SRAM);
+REGION_ALIAS("REGION_HEAP",      SRAM);
+REGION_ALIAS("REGION_ARM_EXIDX", FLASH);
+REGION_ALIAS("REGION_ARM_EXTAB", FLASH);
+
+SECTIONS {
+
+    PROVIDE (_resetVecs_base_addr = DEFINED(_resetVecs_base_addr)
+                                  ? _resetVecs_base_addr
+                                  : 0x0);
+
+    .resetVecs (_resetVecs_base_addr) : AT (_resetVecs_base_addr) {
+        KEEP (*(.resetVecs))
+    } > REGION_TEXT
+
+    .ramVecs (NOLOAD) : ALIGN(1024) {
+        KEEP (*(.ramVecs))
+    } > REGION_DATA
+
+    /*
+     * UDMACC26XX_CONFIG_BASE below must match UDMACC26XX_CONFIG_BASE defined
+     * by ti/drivers/dma/UDMACC26XX.h
+     * The user is allowed to change UDMACC26XX_CONFIG_BASE to move it away from
+     * the default address 0x2000_1800, but remember it must be 1024 bytes aligned.
+     */
+    UDMACC26XX_CONFIG_BASE = 0x20001800;
+
+    /*
+     * Define absolute addresses for the DMA channels.
+     * DMA channels must always be allocated at a fixed offset from the DMA base address.
+     * CTEA := Control Table Entry Address
+     * --------- DO NOT MODIFY -----------
+     */
+    DMA_SPI0_RX_CTEA   = (UDMACC26XX_CONFIG_BASE + 0x30);
+    DMA_SPI0_TX_CTEA   = (UDMACC26XX_CONFIG_BASE + 0x40);
+    DMA_ADC_PRI_CTEA   = (UDMACC26XX_CONFIG_BASE + 0x70);
+    DMA_GPT0A_PRI_CTEA = (UDMACC26XX_CONFIG_BASE + 0x90);
+    DMA_SPI1_RX_CTEA   = (UDMACC26XX_CONFIG_BASE + 0x100);
+    DMA_SPI1_TX_CTEA   = (UDMACC26XX_CONFIG_BASE + 0x110);
+    DMA_ADC_ALT_CTEA   = (UDMACC26XX_CONFIG_BASE + 0x270);
+    DMA_GPT0A_ALT_CTEA = (UDMACC26XX_CONFIG_BASE + 0x290);
+
+    /*
+     * Allocate SPI0, SPI1, ADC, and GPTimer0 DMA descriptors at absolute addresses.
+     * --------- DO NOT MODIFY -----------
+     */
+    UDMACC26XX_dmaSpi0RxControlTableEntry_is_placed = 0;
+    .dmaSpi0RxControlTableEntry DMA_SPI0_RX_CTEA : AT (DMA_SPI0_RX_CTEA) {
+        *(.dmaSpi0RxControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaSpi0TxControlTableEntry_is_placed = 0;
+    .dmaSpi0TxControlTableEntry DMA_SPI0_TX_CTEA : AT (DMA_SPI0_TX_CTEA) {
+        *(.dmaSpi0TxControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaADCPriControlTableEntry_is_placed = 0;
+    .dmaADCPriControlTableEntry DMA_ADC_PRI_CTEA : AT (DMA_ADC_PRI_CTEA) {
+        *(.dmaADCPriControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaGPT0APriControlTableEntry_is_placed = 0;
+    .dmaGPT0APriControlTableEntry DMA_GPT0A_PRI_CTEA : AT (DMA_GPT0A_PRI_CTEA) {
+        *(.dmaGPT0APriControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaSpi1RxControlTableEntry_is_placed = 0;
+    .dmaSpi1RxControlTableEntry DMA_SPI1_RX_CTEA : AT (DMA_SPI1_RX_CTEA) {
+        *(.dmaSpi1RxControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaSpi1TxControlTableEntry_is_placed = 0;
+    .dmaSpi1TxControlTableEntry DMA_SPI1_TX_CTEA : AT (DMA_SPI1_TX_CTEA) {
+        *(.dmaSpi1TxControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaADCAltControlTableEntry_is_placed = 0;
+    .dmaADCAltControlTableEntry DMA_ADC_ALT_CTEA : AT (DMA_ADC_ALT_CTEA) {
+        *(.dmaADCAltControlTableEntry)
+    } > REGION_DATA
+
+    UDMACC26XX_dmaGPT0AAltControlTableEntry_is_placed = 0;
+    .dmaGPT0AAltControlTableEntry DMA_GPT0A_ALT_CTEA : AT (DMA_GPT0A_ALT_CTEA) {
+        *(.dmaGPT0AAltControlTableEntry)
+    } > REGION_DATA
+
+    .text : {
+        CREATE_OBJECT_SYMBOLS
+        *(.text)
+        *(.text.*)
+        . = ALIGN(0x4);
+        KEEP (*(.ctors))
+        . = ALIGN(0x4);
+        KEEP (*(.dtors))
+        . = ALIGN(0x4);
+        __init_array_start = .;
+        KEEP (*(.init_array*))
+        __init_array_end = .;
+        *(.init)
+        *(.fini*)
+    } > REGION_TEXT AT> REGION_TEXT
+
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+
+    .rodata : {
+        *(.rodata)
+        *(.rodata.*)
+    } > REGION_TEXT AT> REGION_TEXT
+
+    .data : ALIGN(0x4) {
+        __data_load__ = LOADADDR(.data);
+        __data_start__ = .;
+        *(.data)
+        *(.data.*)
+        . = ALIGN (0x4);
+        __data_end__ = .;
+    } > REGION_DATA AT> REGION_TEXT
+
+    .ARM.exidx : {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
+
+    .ARM.extab : {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
+
+    .nvs (NOLOAD) : ALIGN(0x2000) {
+        *(.nvs)
+    } > REGION_TEXT
+
+    .ccfg : {
+        KEEP(*(.ccfg))
+    } > FLASH_CCFG AT> FLASH_CCFG
+
+    .bss : {
+        __bss_start__ = .;
+        *(.shbss)
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+        . = ALIGN(0x4);
+        __bss_end__ = .;
+    } > REGION_BSS AT> REGION_BSS
+
+    /* Start of heap must be 4 byte aligned */
+    .heap (NOLOAD) : ALIGN(0x4) {
+        PROVIDE(__heap_start__ = .);
+        PROVIDE(_heap          = __heap_start__);
+        PROVIDE(end            = __heap_start__);
+        PROVIDE(_end           = __heap_start__);
+        PROVIDE(__end          = __heap_start__);
+
+        . += HEAPSIZE;
+        KEEP(*(.heap))
+
+        PROVIDE(__heap_end__ = .);
+        PROVIDE(_eheap       = __heap_end__);
+        PROVIDE(__HeapLimit  = __heap_end__);
+    } > REGION_HEAP AT> REGION_HEAP
+
+    PROVIDE(__stack_size = ORIGIN(SRAM) + LENGTH(SRAM) - ALIGN(0x8));
+
+    /* Start of stack must be 8 byte aligned */
+    .stack (NOLOAD) : {
+        PROVIDE(_stack        = ALIGN(0x8));
+        PROVIDE(__stack       = _stack);
+
+        PROVIDE(_stack_end    = ORIGIN(SRAM) + LENGTH(SRAM));
+        PROVIDE(__stack_end   = _stack_end);
+        PROVIDE(_stack_origin = _stack_end);
+
+        /* Note that the stack check library requires the symbols */
+        /* "_stack" and "_stack_origin" to be defined. */
+
+        /* Assert that we have enough stack */
+        ASSERT(__stack_size >= MIN_STACKSIZE, "Error: No room left for the stack");
+    } > REGION_STACK AT> REGION_STACK
+}

arch/cpu/simplelink-cc13xx-cc26xx/cc13xx-cc26xx-conf.h

@@ -0,0 +1,472 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \file
+ *        Header with configuration defines common to the CC13xx/CC26xx
+ *        platform.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#ifndef CC13XX_CC26XX_CONF_H_
+#define CC13XX_CC26XX_CONF_H_
+/*---------------------------------------------------------------------------*/
+#include "cc13xx-cc26xx-def.h"
+
+#include "rf/rf.h"
+/*---------------------------------------------------------------------------*/
+/**
+ * \name Board Configuration.
+ *
+ * @{
+ */
+
+/* Configure that a board has sensors for the dev/sensors.h API. */
+#ifndef BOARD_CONF_HAS_SENSORS
+#define BOARD_CONF_HAS_SENSORS              0
+#endif
+
+/* Enable/disable the dev/sensors.h API for the given board. */
+#ifndef BOARD_CONF_SENSORS_DISABLE
+#define BOARD_CONF_SENSORS_DISABLE          0
+#endif
+/*---------------------------------------------------------------------------*/
+/**
+ * \name GPIO HAL configuration.
+ *
+ * @{
+ */
+#define GPIO_HAL_CONF_ARCH_SW_TOGGLE        0
+#define GPIO_HAL_CONF_ARCH_HDR_PATH         "dev/gpio-hal-arch.h"
+/** @} */
+/*---------------------------------------------------------------------------*/
+/**
+ * \name Watchdog Configuration.
+ *
+ * @{
+ */
+#ifndef WATCHDOG_CONF_DISABLE
+#define WATCHDOG_CONF_DISABLE               0
+#endif
+
+#ifndef WATCHDOG_CONF_TIMER_TOP
+#define WATCHDOG_CONF_TIMER_TOP             0xFFFFF
+#endif
+/** @} */
+/*---------------------------------------------------------------------------*/
+/**
+ * \name RF configuration.
+ *
+ * @{
+ */
+
+/*
+ * Set the inactivity timeout period for the RF driver. This determines how
+ * long the RF driver will wait when inactive until turning off the RF Core.
+ * Specified in microseconds.
+ */
+#ifndef RF_CONF_INACTIVITY_TIMEOUT
+#define RF_CONF_INACTIVITY_TIMEOUT      2000    /**< 2 ms */
+#endif
+
+/*
+ * Configure TX power to either default PA or High PA, defaults to
+ * default PA.
+ */
+#ifndef RF_CONF_TXPOWER_HIGH_PA
+#define RF_CONF_TXPOWER_HIGH_PA         0
+#endif
+
+#if (RF_CONF_TXPOWER_HIGH_PA) && !(SUPPORTS_HIGH_PA)
+#error "Device does not support High PA"
+#endif
+
+/*
+ * CC13xx only: Configure TX power to use boot mode, allowing to gain
+ * up to 14 dBm with the default PA. This will, however, increase power
+ * consumption.
+ */
+#ifndef RF_CONF_TXPOWER_BOOST_MODE
+#define RF_CONF_TXPOWER_BOOST_MODE      0
+#endif
+
+/*
+ * Configure RF mode. That is, whether to run on Sub-1 GHz (Prop-mode) or
+ * 2.4 GHz (IEEE-mode).
+ */
+#ifdef RF_CONF_MODE
+/* Sanity check a valid configuration is provided. */
+#if !(RF_CONF_MODE & RF_MODE_BM)
+#error "Invalid RF_CONF_MODE provided"
+#endif
+
+#define RF_MODE                      RF_CONF_MODE
+#endif /* RF_CONF_MODE */
+
+/* Number of RX buffers. */
+#ifndef RF_CONF_RX_BUF_CNT
+#define RF_CONF_RX_BUF_CNT           4
+#endif
+
+/* Size of each RX buffer in bytes. */
+#ifndef RF_CONF_RX_BUF_SIZE
+#define RF_CONF_RX_BUF_SIZE          144
+#endif
+
+/* Enable/disable BLE beacon. */
+#ifndef RF_CONF_BLE_BEACON_ENABLE
+#define RF_CONF_BLE_BEACON_ENABLE    0
+#endif
+
+#if (RF_CONF_BLE_BEACON_ENABLE) && !(SUPPORTS_BLE_BEACON)
+#error "Device does not support BLE for BLE beacon"
+#endif
+
+/*----- CC13xx Device Line --------------------------------------------------*/
+/* CC13xx supports both IEEE and Prop mode, depending on which device. */
+#if defined(DEVICE_LINE_CC13XX)
+
+/* Default to Prop-mode for CC13xx devices if not configured. */
+#ifndef RF_MODE
+#define RF_MODE                      RF_MODE_SUB_1_GHZ
+#endif
+
+/*----- CC13xx Prop-mode ----------------------------------------------------*/
+#if (RF_MODE == RF_MODE_SUB_1_GHZ) && (SUPPORTS_PROP_MODE)
+
+/* Netstack configuration. */
+#define NETSTACK_CONF_RADIO         prop_mode_driver
+
+/* CSMA configuration. */
+#define CSMA_CONF_ACK_WAIT_TIME                (RTIMER_SECOND / 300)
+#define CSMA_CONF_AFTER_ACK_DETECTED_WAIT_TIME (RTIMER_SECOND / 1000)
+#define CSMA_CONF_SEND_SOFT_ACK      1
+
+/*----- CC13xx IEEE-mode ----------------------------------------------------*/
+#elif (RF_MODE == RF_MODE_2_4_GHZ) && (SUPPORTS_IEEE_MODE)
+
+/* Netstack configuration. */
+#define NETSTACK_CONF_RADIO         ieee_mode_driver
+
+/* CSMA configuration. */
+#define CSMA_CONF_SEND_SOFT_ACK     0
+
+#else
+/*----- CC13xx Unsupported Mode ---------------------------------------------*/
+#error "Invalid RF mode configuration of CC13xx device"
+#endif /* CC13xx RF Mode configuration */
+
+/*----- CC26xx Device Line --------------------------------------------------*/
+/* CC26xx only supports IEEE mode */
+#elif defined(DEVICE_LINE_CC26XX)
+
+/* Default to IEEE-mode for CC26xx devices if not configured */
+#ifndef RF_MODE
+#define RF_MODE                      RF_MODE_2_4_GHZ
+#endif
+
+/*----- CC26xx IEEE-mode ----------------------------------------------------*/
+#if (RF_MODE == RF_MODE_2_4_GHZ) && (SUPPORTS_IEEE_MODE)
+
+/* Netstack configuration */
+#define NETSTACK_CONF_RADIO         ieee_mode_driver
+
+/* CSMA configuration */
+#define CSMA_CONF_SEND_SOFT_ACK     0
+
+/* Frequncy band configuration */
+#undef DOT_15_4G_FREQ_BAND_ID
+#define DOT_15_4G_CONF_FREQ_BAND_ID   DOT_15_4G_FREQ_BAND_2450
+
+#else
+/*----- CC26xx Unsupported Mode ---------------------------------------------*/
+#error "IEEE-mode only supported by CC26xx devices"
+#endif /* CC26xx RF Mode configuration */
+
+/*----- Unsupported device line ---------------------------------------------*/
+#else
+#error "Unsupported Device Line defined"
+#endif /* Unsupported device line */
+
+/** @} */
+/*---------------------------------------------------------------------------*/
+/**
+ * \name  IEEE address configuration. Used to generate our link-local and
+ *        global IPv6 addresses.
+ * @{
+ */
+
+/**
+ * \brief  Location of the IEEE address.
+ *         0 => Read from InfoPage.
+ *         1 => Use a hardcoded address, configured by IEEE_ADDR_CONF_ADDRESS.
+ */
+#ifndef IEEE_ADDR_CONF_HARDCODED
+#define IEEE_ADDR_CONF_HARDCODED            0
+#endif
+
+/**
+ * \brief  The hardcoded IEEE address to be used when IEEE_ADDR_CONF_HARDCODED
+ *         is defined as 1. Must be a byte array of size 8.
+ */
+#ifndef IEEE_ADDR_CONF_ADDRESS
+#define IEEE_ADDR_CONF_ADDRESS              { 0x00, 0x12, 0x4B, 0x00, 0x89, 0xAB, 0xCD, 0xEF }
+#endif
+/** @} */
+/*---------------------------------------------------------------------------*/
+/**
+ * \name  IEEE-mode configuration.
+ *
+ * @{
+ */
+
+/**
+ * \brief  Configuration to enable/disable auto ACKs in IEEE-mode.
+ *         0 => ACK generated by software
+ *         1 => ACK generated by the radio.
+ */
+#ifndef IEEE_MODE_CONF_AUTOACK
+#define IEEE_MODE_CONF_AUTOACK              1
+#endif
+
+/**
+ * \brief  Configuration to enable/disable frame filtering in IEEE-mode.
+ *         0 => Disable promiscous mode.
+ *         1 => Enable promiscous mode.
+ */
+#ifndef IEEE_MODE_CONF_PROMISCOUS
+#define IEEE_MODE_CONF_PROMISCOUS           0
+#endif
+
+/**
+ * \brief  Configuration to set the RSSI threshold in dBm in IEEE-mode.
+ *         Defaults to -90 dBm.
+ */
+#ifndef IEEE_MODE_CONF_CCA_RSSI_THRESHOLD
+#define IEEE_MODE_CONF_CCA_RSSI_THRESHOLD   0xA6
+#endif
+/** @} */
+/*---------------------------------------------------------------------------*/
+/**
+ * \name  Prop-mode configuration.
+ *
+ * @{
+ */
+
+/**
+ * \brief  Configuration to set whitener in Prop-mode.
+ *         0 => No whitener
+ *         1 => Whitener.
+ */
+#ifndef PROP_MODE_CONF_DW
+#define PROP_MODE_CONF_DW                   0
+#endif
+
+/**
+ * \brief  Use 16-bit or 32-bit CRC in Prop-mode.
+ *         0 => 32-bit CRC.
+ *         1 => 16-bit CRC.
+ */
+#ifndef PROP_MODE_CONF_USE_CRC16
+#define PROP_MODE_CONF_USE_CRC16            0
+#endif
+
+/**
+ * \brief  Configuration to set the RSSI threshold in dBm in Prop-mode.
+ *         Defaults to -90 dBm.
+ */
+#ifndef PROP_MODE_CONF_CCA_RSSI_THRESHOLD
+#define PROP_MODE_CONF_CCA_RSSI_THRESHOLD   0xA6
+#endif
+/** @} */
+/*---------------------------------------------------------------------------*/
+/**
+ * \name  TI Drivers Configuration.
+ *
+ * @{
+ */
+
+/**
+ * \brief  Enable or disable UART driver.
+ */
+#ifndef TI_UART_CONF_ENABLE
+#define TI_UART_CONF_ENABLE                 1
+#endif
+
+/**
+ * \brief  Enable or disable UART0 peripheral.
+ */
+#ifndef TI_UART_CONF_UART0_ENABLE
+#define TI_UART_CONF_UART0_ENABLE           TI_UART_CONF_ENABLE
+#endif
+
+/**
+ * \brief  Enable or disable UART1 peripheral.
+ */
+#ifndef TI_UART_CONF_UART1_ENABLE
+#define TI_UART_CONF_UART1_ENABLE           0
+#endif
+
+/**
+ * \brief  UART driver baud rate configuration.
+ */
+#ifndef TI_UART_CONF_BAUD_RATE
+#define TI_UART_CONF_BAUD_RATE              115200
+#endif
+
+/**
+ * \brief  Enable or disable SPI driver.
+ */
+#ifndef TI_SPI_CONF_ENABLE
+#define TI_SPI_CONF_ENABLE                  1
+#endif
+
+/**
+ * \brief  Enable or disable SPI0 peripheral.
+ */
+#ifndef TI_SPI_CONF_SPI0_ENABLE
+#define TI_SPI_CONF_SPI0_ENABLE             TI_SPI_CONF_ENABLE
+#endif
+
+/**
+ * \brief  Enable or disable SPI1 peripheral.
+ */
+#ifndef TI_SPI_CONF_SPI1_ENABLE
+#define TI_SPI_CONF_SPI1_ENABLE             0
+#endif
+
+/**
+ * \brief  Enable or disable I2C driver.
+ */
+#ifndef TI_I2C_CONF_ENABLE
+#define TI_I2C_CONF_ENABLE                  1
+#endif
+
+/**
+ * \brief  Enable or disable I2C0 peripheral.
+ */
+#ifndef TI_I2C_CONF_I2C0_ENABLE
+#define TI_I2C_CONF_I2C0_ENABLE             TI_I2C_CONF_ENABLE
+#endif
+
+/**
+ * \brief  Enable or disable Non-Volatile Storage (NVS) driver.
+ */
+#ifndef TI_NVS_CONF_ENABLE
+#define TI_NVS_CONF_ENABLE                  0
+#endif
+
+/**
+ * \brief  Enable or disable internal flash storage.
+ */
+#ifndef TI_NVS_CONF_NVS_INTERNAL_ENABLE
+#define TI_NVS_CONF_NVS_INTERNAL_ENABLE     TI_NVS_CONF_ENABLE
+#endif
+
+/**
+ * \brief  Enable or disable external flash storage.
+ */
+#ifndef TI_NVS_CONF_NVS_EXTERNAL_ENABLE
+#define TI_NVS_CONF_NVS_EXTERNAL_ENABLE     TI_NVS_CONF_ENABLE
+#endif
+
+/**
+ * \brief  Enable or disable SD driver.
+ */
+#ifndef TI_SD_CONF_ENABLE
+#define TI_SD_CONF_ENABLE                   0
+#endif
+/** @} */
+/*---------------------------------------------------------------------------*/
+/**
+ * \name SPI HAL configuration.
+ *
+ * CC13x0/CC26x0 has one SPI interface, while CC13x2/CC26x2 has two
+ * SPI interfaces. Some additional checks has to be made for the
+ * SPI_CONF_CONTROLLER_COUNT configuration, as this relies on whether the
+ * available SPI interfaces are enabled or not, as well as if the SPI driver
+ * is enabled at all.
+ *
+ * @{
+ */
+#if TI_SPI_CONF_ENABLE
+/*
+ * The SPI driver is enabled. Therefore, the number of SPI interfaces depends
+ * on which Device family parent the device falls under and if any of its
+ * corresponding SPI interfaces are enabled or not.
+ */
+
+#define SPI0_IS_ENABLED                     ((TI_SPI_CONF_SPI0_ENABLE) ? 1 : 0)
+#define SPI1_IS_ENABLED                     ((TI_SPI_CONF_SPI1_ENABLE) ? 1 : 0)
+
+#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0)
+
+/* CC13x0/CC26x0 only has one SPI interface: SPI0. */
+#define SPI_CONF_CONTROLLER_COUNT           (SPI0_IS_ENABLED)
+
+#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2)
+
+/* CC13x0/CC26x0 only has two SPI interface: SPI0 and SPI1. */
+#define SPI_CONF_CONTROLLER_COUNT           (SPI0_IS_ENABLED + SPI1_IS_ENABLED)
+
+#endif /* DeviceFamily_PARENT */
+
+#else /* TI_SPI_CONF_ENABLE */
+/*
+ * If the SPI driver is disabled then there are 0 available
+ * SPI interfaces. */
+#define SPI_CONF_CONTROLLER_COUNT           0
+#endif /* TI_SPI_CONF_ENABLE */
+/** @} */
+/*---------------------------------------------------------------------------*/
+/**
+ * \name Slip configuration
+ *
+ * @{
+ */
+#ifndef SLIP_ARCH_CONF_ENABLED
+/*
+ * Determine whether we need SLIP
+ * This will keep working while UIP_FALLBACK_INTERFACE and CMD_CONF_OUTPUT
+ * keep using SLIP
+ */
+#if defined(UIP_FALLBACK_INTERFACE) || defined(CMD_CONF_OUTPUT)
+#define SLIP_ARCH_CONF_ENABLED              1
+#endif
+
+#endif /* SLIP_ARCH_CONF_ENABLED */
+/** @} */
+/*---------------------------------------------------------------------------*/
+#endif /* CC13XX_CC26XX_CONF_H_ */
+/*---------------------------------------------------------------------------*/
+/** @} */

arch/cpu/simplelink-cc13xx-cc26xx/cc13xx-cc26xx-def.h

@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \file
+ *        Header with configuration defines for the Contiki system.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#ifndef CC13XX_CC26XX_DEF_H_
+#define CC13XX_CC26XX_DEF_H_
+/*---------------------------------------------------------------------------*/
+#include <ti/devices/DeviceFamily.h>
+/*---------------------------------------------------------------------------*/
+#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0)
+#include <cm3/cm3-def.h>
+#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2)
+#include <cm4/cm4-def.h>
+#endif
+/*---------------------------------------------------------------------------*/
+#include <stddef.h>
+#include <stdint.h>
+/*---------------------------------------------------------------------------*/
+#define RTIMER_ARCH_SECOND               65536
+/*---------------------------------------------------------------------------*/
+#define INT_MASTER_CONF_STATUS_DATATYPE  uintptr_t
+/*---------------------------------------------------------------------------*/
+/* TSCH related defines */
+
+/* 1 len byte, 2 bytes CRC */
+#define RADIO_PHY_OVERHEAD         3
+/* 250kbps data rate. One byte = 32us */
+#define RADIO_BYTE_AIR_TIME       32
+/* Delay between GO signal and SFD */
+#define RADIO_DELAY_BEFORE_TX       ((unsigned)US_TO_RTIMERTICKS(81))
+/* Delay between GO signal and start listening.
+ * This value is so small because the radio is constantly on within each timeslot. */
+#define RADIO_DELAY_BEFORE_RX       ((unsigned)US_TO_RTIMERTICKS(15))
+/* Delay between the SFD finishes arriving and it is detected in software. */
+#define RADIO_DELAY_BEFORE_DETECT   ((unsigned)US_TO_RTIMERTICKS(352))
+
+/* Timer conversion; radio is running at 4 MHz */
+#define RAT_SECOND            4000000u
+#define RAT_TO_RTIMER(x)      ((uint32_t)(((uint64_t)(x)*(RTIMER_SECOND / 256)) / (RAT_SECOND / 256)))
+#define USEC_TO_RAT(x)        ((x) * 4)
+
+#if (RTIMER_SECOND % 256) || (RAT_SECOND % 256)
+#error RAT_TO_RTIMER macro must be fixed!
+#endif
+
+/* The PHY header (preamble + SFD, 4+1 bytes) duration is equivalent to 10 symbols */
+#define RADIO_IEEE_802154_PHY_HEADER_DURATION_USEC 160
+
+/* Do not turn off TSCH within a timeslot: not enough time */
+#define TSCH_CONF_RADIO_ON_DURING_TIMESLOT 1
+
+/* Disable TSCH frame filtering */
+#define TSCH_CONF_HW_FRAME_FILTERING  0
+
+/* Use hardware timestamps */
+#ifndef TSCH_CONF_RESYNC_WITH_SFD_TIMESTAMPS
+#define TSCH_CONF_RESYNC_WITH_SFD_TIMESTAMPS 1
+#define TSCH_CONF_TIMESYNC_REMOVE_JITTER 0
+#endif
+
+#ifndef TSCH_CONF_BASE_DRIFT_PPM
+/*
+ * The drift compared to "true" 10ms slots.
+ * Enable adaptive sync to enable compensation for this.
+ * Slot length 10000 usec
+ *             328 ticks
+ * Tick duration 30.517578125 usec
+ * Real slot duration 10009.765625 usec
+ * Target - real duration = -9.765625 usec
+ * TSCH_CONF_BASE_DRIFT_PPM -977
+ */
+#define TSCH_CONF_BASE_DRIFT_PPM -977
+#endif
+
+/* 10 times per second */
+#ifndef TSCH_CONF_CHANNEL_SCAN_DURATION
+#define TSCH_CONF_CHANNEL_SCAN_DURATION (CLOCK_SECOND / 10)
+#endif
+
+/* Slightly reduce the TSCH guard time (from 2200 usec to 1800 usec) to make sure
+ * the CC26xx radio has sufficient time to start up. */
+#ifndef TSCH_CONF_RX_WAIT
+#define TSCH_CONF_RX_WAIT 1800
+#endif
+/*---------------------------------------------------------------------------*/
+/* Path to CMSIS header */
+#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0)
+#define CMSIS_CONF_HEADER_PATH              "cc13x0-cc26x0-cm3.h"
+#elif (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2)
+#define CMSIS_CONF_HEADER_PATH              "cc13x2-cc26x2-cm4.h"
+#endif
+/*---------------------------------------------------------------------------*/
+/* Path to headers with implementation of mutexes and memory barriers */
+#define MUTEX_CONF_ARCH_HEADER_PATH          "mutex-cortex.h"
+#define MEMORY_BARRIER_CONF_ARCH_HEADER_PATH "memory-barrier-cortex.h"
+/*---------------------------------------------------------------------------*/
+#endif /* CC13XX_CC26XX_DEF_H_ */
+/*---------------------------------------------------------------------------*/
+/** @} */

arch/cpu/simplelink-cc13xx-cc26xx/ccfg-conf.c

@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \defgroup cc13xx-cc26xx-ccfg Customer Configuration (CCFG)
+ *
+ * @{
+ *
+ * \file
+ *        Configuration of CCFG.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki-conf.h"
+/*---------------------------------------------------------------------------*/
+/**
+ * \name JTAG interface configuration
+ *
+ * Enable/Disable the JTAG DAP and TAP interfaces on the chip.
+ * Setting this to 0 will disable access to the debug interface
+ * to secure deployed images.
+ * @{
+ */
+#if CCFG_CONF_JTAG_INTERFACE_DISABLE
+#define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE        0x00
+#define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE       0x00
+#define SET_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE      0x00
+#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE      0x00
+#define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE    0x00
+#define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE    0x00
+#define SET_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE       0x00
+#endif /* CCFG_CONF_JTAG_INTERFACE_DISABLE */
+/** @} */
+/*---------------------------------------------------------------------------*/
+/**
+ * \name TX Power Boost Mode
+ *
+ * CC13xx only: Enable/Disable boost mode, which enables maximum +14 dBm
+ * output power with the default PA front-end configuration.
+ * @{
+ */
+#if defined(DEVICE_LINE_CC13XX) && (RF_CONF_TXPOWER_BOOST_MODE)
+#define CCFG_FORCE_VDDR_HH                           1
+#endif
+/** @} */
+/*---------------------------------------------------------------------------*/
+/**
+ * \name ROM Bootloader configuration
+ *
+ * Enable/Disable the ROM bootloader in your image, if the board supports it.
+ * Look in Board.h to choose the DIO and corresponding level that will cause
+ * the chip to enter bootloader mode.
+ * @{
+ */
+#ifndef CCFG_CONF_ROM_BOOTLOADER_ENABLE
+#define CCFG_CONF_ROM_BOOTLOADER_ENABLE               0
+#endif
+
+#if CCFG_CONF_ROM_BOOTLOADER_ENABLE
+#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE         0xC5
+#define SET_CCFG_BL_CONFIG_BL_LEVEL                  0x00
+#if defined(CCFG_CONF_BL_PIN_NUMBER)
+#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER            CCFG_CONF_BL_PIN_NUMBER
+#endif
+#define SET_CCFG_BL_CONFIG_BL_ENABLE                 0xC5
+#endif /* CCFG_CONF_ROM_BOOTLOADER_ENABLE */
+/** @} */
+/*---------------------------------------------------------------------------*/
+/**
+ * \name Include the device-specific CCFG file from the SDK.
+ *
+ * @{
+ */
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(startup_files/ccfg.c)
+/** @} */
+/*---------------------------------------------------------------------------*/
+/**
+ * @}
+ * @}
+ */

arch/cpu/simplelink-cc13xx-cc26xx/dev/clock-arch.c

@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \defgroup cc13xx-cc26xx-clock CC13xx/CC26xx clock library
+ *
+ * @{
+ * \file
+ *        Implementation of the clock libary for CC13xx/CC26xx.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+#include "sys/etimer.h"
+/*---------------------------------------------------------------------------*/
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(driverlib/aon_rtc.h)
+#include DeviceFamily_constructPath(driverlib/cpu.h)
+#include DeviceFamily_constructPath(driverlib/interrupt.h)
+#include DeviceFamily_constructPath(driverlib/prcm.h)
+#include DeviceFamily_constructPath(driverlib/timer.h)
+
+#include <ti/drivers/dpl/ClockP.h>
+#include <ti/drivers/dpl/HwiP.h>
+#include <ti/drivers/power/PowerCC26XX.h>
+/*---------------------------------------------------------------------------*/
+static volatile clock_time_t count;
+static ClockP_Struct etimer_clock;
+/*---------------------------------------------------------------------------*/
+static void
+clock_update_cb(void)
+{
+  const uintptr_t key = HwiP_disable();
+  count += 1;
+  HwiP_restore(key);
+
+  /* Notify the etimer system. */
+  if(etimer_pending()) {
+    etimer_request_poll();
+  }
+}
+/*---------------------------------------------------------------------------*/
+static inline clock_time_t
+get_count(void)
+{
+  clock_time_t count_read;
+
+  const uintptr_t key = HwiP_disable();
+  count_read = count;
+  HwiP_restore(key);
+
+  return count_read;
+}
+/*---------------------------------------------------------------------------*/
+void
+clock_init(void)
+{
+  /* ClockP_getSystemTickPeriod() returns ticks per us. */
+  const uint32_t clockp_ticks_second =
+    (uint32_t)(1000 * 1000) / (CLOCK_SECOND) / ClockP_getSystemTickPeriod();
+
+  count = 0;
+
+  ClockP_Params params;
+  ClockP_Params_init(&params);
+
+  params.period = clockp_ticks_second;
+  params.startFlag = true;
+
+  ClockP_construct(&etimer_clock, (ClockP_Fxn)clock_update_cb,
+                   clockp_ticks_second, &params);
+}
+/*---------------------------------------------------------------------------*/
+clock_time_t
+clock_time(void)
+{
+  return get_count();
+}
+/*---------------------------------------------------------------------------*/
+unsigned long
+clock_seconds(void)
+{
+  return (unsigned long)get_count() / CLOCK_SECOND;
+}
+/*---------------------------------------------------------------------------*/
+void
+clock_wait(clock_time_t i)
+{
+  clock_time_t start;
+
+  start = clock_time();
+  while(clock_time() - start < i);
+}
+/*---------------------------------------------------------------------------*/
+void
+clock_delay_usec(uint16_t usec)
+{
+  ClockP_usleep(usec);
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief  Obsolete delay function but we implement it here since some code
+ *         still uses it.
+ */
+void
+clock_delay(unsigned int i)
+{
+  clock_delay_usec(i);
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * @}
+ * @}
+ */

arch/cpu/simplelink-cc13xx-cc26xx/dev/dbg-arch.c

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-platform
+ * @{
+ *
+ * \file
+ *        Implementation of the dbg module for CC13xx/CC26xx, used by stdio.
+ *        The dbg module is implemented by writing to UART0.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+#include "sys/cc.h"
+/*---------------------------------------------------------------------------*/
+#include "uart0-arch.h"
+/*---------------------------------------------------------------------------*/
+#include <stdio.h>
+#include <stddef.h>
+#include <string.h>
+/*---------------------------------------------------------------------------*/
+int
+dbg_putchar(int c)
+{
+  unsigned char ch;
+  int num_bytes;
+
+  ch = (unsigned char)c;
+
+  num_bytes = (int)uart0_write(&ch, 1);
+  return (num_bytes > 0)
+         ? num_bytes
+         : 0;
+}
+/*---------------------------------------------------------------------------*/
+unsigned int
+dbg_send_bytes(const unsigned char *seq, unsigned int len)
+{
+  size_t seq_len;
+  size_t max_len;
+  int num_bytes;
+
+  seq_len = strlen((const char *)seq);
+  max_len = MIN(seq_len, (size_t)len);
+
+  if(max_len == 0) {
+    return 0;
+  }
+
+  num_bytes = (int)uart0_write(seq, max_len);
+  return (num_bytes > 0)
+         ? num_bytes
+         : 0;
+}
+/*---------------------------------------------------------------------------*/
+/** @} */

arch/cpu/simplelink-cc13xx-cc26xx/dev/gpio-hal-arch.c

@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-gpio-hal
+ * @{
+ *
+ * \file
+ *        Implementation of the GPIO HAL module for CC13xx/CC26xx. The GPIO
+ *        HAL module is implemented by using the PINCC26XX module, except
+ *        for multi-dio functions which use the GPIO driverlib module.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+#include "dev/gpio-hal.h"
+/*---------------------------------------------------------------------------*/
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(driverlib/gpio.h)
+
+#include <ti/drivers/PIN.h>
+#include <ti/drivers/pin/PINCC26XX.h>
+/*---------------------------------------------------------------------------*/
+#include <stdint.h>
+/*---------------------------------------------------------------------------*/
+static PIN_Config pin_config[] = { PIN_TERMINATE };
+static PIN_State pin_state;
+static PIN_Handle pin_handle;
+/*---------------------------------------------------------------------------*/
+static void
+from_hal_cfg(gpio_hal_pin_cfg_t cfg, PIN_Config *pin_cfg, PIN_Config *pin_mask)
+{
+  /* Pulling config */
+  *pin_mask |= PIN_BM_PULLING;
+
+  switch(cfg & GPIO_HAL_PIN_CFG_PULL_MASK) {
+  default: /* Default to no pullup/pulldown */
+  case GPIO_HAL_PIN_CFG_PULL_NONE: *pin_cfg |= PIN_NOPULL;   break;
+  case GPIO_HAL_PIN_CFG_PULL_UP:   *pin_cfg |= PIN_PULLUP;   break;
+  case GPIO_HAL_PIN_CFG_PULL_DOWN: *pin_cfg |= PIN_PULLDOWN; break;
+  }
+
+  /* Hysteresis config */
+  *pin_mask |= PIN_BM_HYSTERESIS;
+
+  if(cfg & GPIO_HAL_PIN_CFG_HYSTERESIS) {
+    *pin_cfg |= PIN_HYSTERESIS;
+  }
+
+  /* Interrupt config */
+  *pin_mask |= PIN_BM_IRQ;
+
+  if((cfg & GPIO_HAL_PIN_CFG_INT_MASK) == GPIO_HAL_PIN_CFG_INT_ENABLE) {
+    /* Interrupt edge config */
+    switch(cfg & GPIO_HAL_PIN_CFG_EDGE_BOTH) {
+    case GPIO_HAL_PIN_CFG_EDGE_NONE:    *pin_cfg |= PIN_IRQ_DIS;       break;
+    case GPIO_HAL_PIN_CFG_EDGE_FALLING: *pin_cfg |= PIN_IRQ_NEGEDGE;   break;
+    case GPIO_HAL_PIN_CFG_EDGE_RISING:  *pin_cfg |= PIN_IRQ_POSEDGE;   break;
+    case GPIO_HAL_PIN_CFG_EDGE_BOTH:    *pin_cfg |= PIN_IRQ_BOTHEDGES; break;
+    }
+  } else {
+    *pin_cfg |= PIN_IRQ_DIS;
+  }
+}
+/*---------------------------------------------------------------------------*/
+static void
+to_hal_cfg(PIN_Config pin_cfg, gpio_hal_pin_cfg_t *cfg)
+{
+  /* Input config */
+  if(pin_cfg & PIN_BM_INPUT_MODE) {
+    /* Hysteresis config */
+    if((pin_cfg & PIN_BM_HYSTERESIS) == PIN_HYSTERESIS) {
+      *cfg |= GPIO_HAL_PIN_CFG_HYSTERESIS;
+    }
+
+    /* Pulling config */
+    switch(pin_cfg & PIN_BM_PULLING) {
+    case PIN_NOPULL:   *cfg |= GPIO_HAL_PIN_CFG_PULL_NONE; break;
+    case PIN_PULLUP:   *cfg |= GPIO_HAL_PIN_CFG_PULL_UP;   break;
+    case PIN_PULLDOWN: *cfg |= GPIO_HAL_PIN_CFG_PULL_DOWN; break;
+    }
+  }
+
+  /* Interrupt config */
+  if(pin_cfg & PIN_BM_IRQ) {
+    /* Interrupt edge config */
+    switch(pin_cfg & PIN_BM_IRQ) {
+    case PIN_IRQ_DIS:       *cfg |= GPIO_HAL_PIN_CFG_EDGE_NONE;
+                            *cfg |= GPIO_HAL_PIN_CFG_INT_DISABLE;
+                            break;
+    case PIN_IRQ_NEGEDGE:   *cfg |= GPIO_HAL_PIN_CFG_EDGE_FALLING;
+                            *cfg |= GPIO_HAL_PIN_CFG_INT_ENABLE;
+                            break;
+    case PIN_IRQ_POSEDGE:   *cfg |= GPIO_HAL_PIN_CFG_EDGE_RISING;
+                            *cfg |= GPIO_HAL_PIN_CFG_INT_ENABLE;
+                            break;
+    case PIN_IRQ_BOTHEDGES: *cfg |= GPIO_HAL_PIN_CFG_EDGE_BOTH;
+                            *cfg |= GPIO_HAL_PIN_CFG_INT_ENABLE;
+                            break;
+    }
+  }
+}
+/*---------------------------------------------------------------------------*/
+static void
+gpio_int_cb(PIN_Handle handle, PIN_Id pin_id)
+{
+  /* Unused args */
+  (void)handle;
+
+  /* Notify the GPIO HAL driver */
+  gpio_hal_event_handler(gpio_hal_pin_to_mask(pin_id));
+}
+/*---------------------------------------------------------------------------*/
+void
+gpio_hal_arch_init(void)
+{
+  /* No error checking */
+  pin_handle = PIN_open(&pin_state, pin_config);
+  PIN_registerIntCb(pin_handle, gpio_int_cb);
+}
+/*---------------------------------------------------------------------------*/
+void
+gpio_hal_arch_interrupt_enable(gpio_hal_pin_t pin)
+{
+  PIN_Config pin_cfg;
+  PIN_Config irq_cfg;
+
+  pin_cfg = PIN_getConfig(pin);
+  PIN_add(pin_handle, pin_cfg);
+
+  irq_cfg = pin_cfg & PIN_BM_IRQ;
+  PIN_setInterrupt(pin_handle, pin | irq_cfg);
+}
+/*---------------------------------------------------------------------------*/
+void
+gpio_hal_arch_interrupt_disable(gpio_hal_pin_t pin)
+{
+  PIN_add(pin_handle, PIN_getConfig(pin));
+
+  PIN_setInterrupt(pin_handle, pin | PIN_IRQ_DIS);
+}
+/*---------------------------------------------------------------------------*/
+void
+gpio_hal_arch_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg)
+{
+  PIN_add(pin_handle, PIN_getConfig(pin));
+
+  /* Clear settings that we are about to change, keep everything else. */
+  PIN_Config pin_cfg = 0;
+  PIN_Config pin_mask = 0;
+
+  from_hal_cfg(cfg, &pin_cfg, &pin_mask);
+
+  PIN_setConfig(pin_handle, pin_mask, pin | pin_cfg);
+}
+/*---------------------------------------------------------------------------*/
+gpio_hal_pin_cfg_t
+gpio_hal_arch_pin_cfg_get(gpio_hal_pin_t pin)
+{
+  PIN_Config pin_cfg = PIN_getConfig(pin);
+  gpio_hal_pin_cfg_t cfg = 0;
+
+  to_hal_cfg(pin_cfg, &cfg);
+
+  return cfg;
+}
+/*---------------------------------------------------------------------------*/
+gpio_hal_pin_mask_t
+gpio_hal_arch_read_pins(gpio_hal_pin_mask_t pins)
+{
+  /* For pins configured as output we need to read DOUT31_0 */
+  gpio_hal_pin_mask_t oe_pins = GPIO_getOutputEnableMultiDio(pins);
+
+  pins &= ~oe_pins;
+
+  return (HWREG(GPIO_BASE + GPIO_O_DOUT31_0) & oe_pins) |
+         GPIO_readMultiDio(pins);
+}
+/*---------------------------------------------------------------------------*/
+uint8_t
+gpio_hal_arch_read_pin(gpio_hal_pin_t pin)
+{
+  return (GPIO_getOutputEnableDio(pin))
+         ? PINCC26XX_getOutputValue(pin)
+         : PINCC26XX_getInputValue(pin);
+}
+/*---------------------------------------------------------------------------*/
+/** @} */

arch/cpu/simplelink-cc13xx-cc26xx/dev/gpio-hal-arch.h

@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \defgroup cc13xx-cc26xx-gpio-hal CC13xx/CC26xx GPIO HAL implementation
+ *
+ * @{
+ *
+ * \file
+ *        Header file for the CC13xx/CC26xx GPIO HAL functions.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ * \note
+ *        Do not include this header directly.
+ */
+/*---------------------------------------------------------------------------*/
+#ifndef GPIO_HAL_ARCH_H_
+#define GPIO_HAL_ARCH_H_
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+/*---------------------------------------------------------------------------*/
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(driverlib/gpio.h)
+
+#include <ti/drivers/pin/PINCC26XX.h>
+/*---------------------------------------------------------------------------*/
+#define gpio_hal_arch_pin_set_input(p)        PINCC26XX_setOutputEnable(p, false)
+#define gpio_hal_arch_pin_set_output(p)       PINCC26XX_setOutputEnable(p, true)
+
+#define gpio_hal_arch_set_pin(p)              PINCC26XX_setOutputValue(p, 1)
+#define gpio_hal_arch_clear_pin(p)            PINCC26XX_setOutputValue(p, 0)
+#define gpio_hal_arch_toggle_pin(p)           PINCC26XX_setOutputValue(p, \
+                                                PINCC26XX_getOutputValue(p) \
+                                                  ? 0 : 1)
+#define gpio_hal_arch_write_pin(p, v)         PINCC26XX_setOutputValue(p, v)
+
+#define gpio_hal_arch_set_pins(p)             GPIO_setMultiDio(p)
+#define gpio_hal_arch_clear_pins(p)           GPIO_clearMultiDio(p)
+#define gpio_hal_arch_toggle_pins(p)          GPIO_toggleMultiDio(p)
+#define gpio_hal_arch_write_pins(p, v)        GPIO_writeMultiDio(p, v)
+/*---------------------------------------------------------------------------*/
+#endif /* GPIO_HAL_ARCH_H_ */
+/*---------------------------------------------------------------------------*/
+/**
+ * @}
+ * @}
+ */

arch/cpu/simplelink-cc13xx-cc26xx/dev/int-master-arch.c

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \defgroup cc13xx-cc26xx-int-master CC13xx/CC26xx master interrupt manipulation
+ *
+ * Master interrupt manipulation routines for CC13xx/CC26xx.
+ *
+ * @{
+ *
+ * \file
+ *        Master interrupt manipulation implementation for CC13xx/CC26xx.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+#include "sys/int-master.h"
+/*---------------------------------------------------------------------------*/
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(driverlib/cpu.h)
+
+#include <ti/drivers/dpl/HwiP.h>
+/*---------------------------------------------------------------------------*/
+#include <stddef.h>
+#include <stdbool.h>
+/*---------------------------------------------------------------------------*/
+void
+int_master_enable(void)
+{
+  HwiP_enable();
+}
+/*---------------------------------------------------------------------------*/
+int_master_status_t
+int_master_read_and_disable(void)
+{
+  return (int_master_status_t)HwiP_disable();
+}
+/*---------------------------------------------------------------------------*/
+void
+int_master_status_set(int_master_status_t status)
+{
+  HwiP_restore((uintptr_t)status);
+}
+/*---------------------------------------------------------------------------*/
+bool
+int_master_is_enabled(void)
+{
+  return CPUprimask() ? false : true;
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * @}
+ * @}
+ */

arch/cpu/simplelink-cc13xx-cc26xx/dev/random.c

@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ /**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \defgroup cc13xx-cc26xx-prng Pseudo Random Number Generator (PRNG) for CC13xx/CC26xx.
+ * @{
+ *
+ * Implementation based on Bob Jenkins' small noncryptographic PRNG.
+ * - http://burtleburtle.net/bob/rand/smallprng.html
+ *
+ * This file overrides os/lib/random.c. Note that the file name must
+ * match the original file for the override to work.
+ *
+ * \file
+ *        Implementation of Pseudo Random Number Generator for CC13xx/CC26xx.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#include <contiki.h>
+/*---------------------------------------------------------------------------*/
+#include <stdint.h>
+/*---------------------------------------------------------------------------*/
+typedef struct {
+  uint32_t a;
+  uint32_t b;
+  uint32_t c;
+  uint32_t d;
+} ranctx_t;
+
+static ranctx_t ranctx;
+/*---------------------------------------------------------------------------*/
+#define rot32(x, k) (((x) << (k)) | ((x) >> (32 - (k))))
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief   Generates a new random number using the PRNG.
+ * \return  The random number.
+ */
+unsigned short
+random_rand(void)
+{
+  uint32_t e;
+
+  e        = ranctx.a - rot32(ranctx.b, 27);
+  ranctx.a = ranctx.b ^ rot32(ranctx.c, 17);
+  ranctx.b = ranctx.c + ranctx.d;
+  ranctx.c = ranctx.d + e;
+  ranctx.d = e        + ranctx.a;
+
+  return (unsigned short)ranctx.d;
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief       Initialize the PRNG.
+ * \param seed  Seed for the PRNG.
+ */
+void
+random_init(unsigned short seed)
+{
+  uint32_t i;
+
+  ranctx.a = 0xf1ea5eed;
+  ranctx.b = ranctx.c = ranctx.d = (uint32_t)seed;
+  for(i = 0; i < 20; ++i) {
+    (void)random_rand();
+  }
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * @}
+ * @}
+ */

arch/cpu/simplelink-cc13xx-cc26xx/dev/rtimer-arch.c

@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-rtimer
+ * @{
+ *
+ * \file
+ *        Implementation of the rtimer driver for CC13xx/CC26xx.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+/*---------------------------------------------------------------------------*/
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(driverlib/aon_event.h)
+#include DeviceFamily_constructPath(driverlib/aon_rtc.h)
+#include DeviceFamily_constructPath(driverlib/interrupt.h)
+
+#include <ti/drivers/dpl/ClockP.h>
+#include <ti/drivers/dpl/HwiP.h>
+/*---------------------------------------------------------------------------*/
+#include <stddef.h>
+#include <stdint.h>
+/*---------------------------------------------------------------------------*/
+#define HWIP_RTC_CH     AON_RTC_CH0
+#define RTIMER_RTC_CH   AON_RTC_CH1
+/*---------------------------------------------------------------------------*/
+typedef void (*isr_fxn_t)(void);
+typedef void (*hwi_dispatch_fxn_t)(void);
+
+static hwi_dispatch_fxn_t hwi_dispatch_fxn;
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief  Stub function used when creating the dummy clock object.
+ */
+static void
+rtimer_clock_stub(uintptr_t unused)
+{
+  (void)unused;
+  /* do nothing */
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief  The Man-in-the-Middle ISR hook for the HWI dispatch ISR. This
+ *         will be the ISR dispatched when INT_AON_RTC_COMB is triggered,
+ *         and will either dispatch the interrupt to the rtimer driver or
+ *         the HWI driver, depening on which event triggered the interrupt.
+ */
+static void
+rtimer_isr_hook(void)
+{
+  if(AONRTCEventGet(RTIMER_RTC_CH)) {
+    AONRTCEventClear(RTIMER_RTC_CH);
+    AONRTCChannelDisable(RTIMER_RTC_CH);
+
+    rtimer_run_next();
+  }
+  /*
+   * HWI Dispatch clears the interrupt. If HWI wasn't triggered, clear
+   * the interrupt manually.
+   */
+  if(AONRTCEventGet(HWIP_RTC_CH)) {
+    hwi_dispatch_fxn();
+  } else {
+    IntPendClear(INT_AON_RTC_COMB);
+  }
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief TODO
+ */
+void
+rtimer_arch_init(void)
+{
+  uintptr_t key;
+  ClockP_Struct clk_object;
+  ClockP_Params clk_params;
+  volatile isr_fxn_t *ramvec_table;
+
+  key = HwiP_disable();
+
+  /*
+   * Create a dummy clock to guarantee the RAM vector table is initialized.
+   *
+   * Creating a dummy clock will trigger initialization of TimerP, which
+   * subsequently initializes the driverlib/interrupt.h module. It is the
+   * interrupt module that initializes the RAM vector table.
+   *
+   * It is safe to destruct the Clock object immediately afterwards.
+   */
+  ClockP_Params_init(&clk_params);
+  ClockP_construct(&clk_object, rtimer_clock_stub, 0, &clk_params);
+  ClockP_destruct(&clk_object);
+
+  /* Try to access the RAM vector table. */
+  ramvec_table = (isr_fxn_t *)HWREG(NVIC_VTABLE);
+  if(!ramvec_table) {
+    /*
+     * Unable to find the RAM vector table is a serious fault.
+     * Spin-lock forever.
+     */
+    for(;;) { /* hang */ }
+  }
+
+  /*
+   * The HWI Dispatch ISR is located at interrupt number INT_AON_RTC_COMB
+   * in the RAM vector table. Fetch and store it.
+   */
+  hwi_dispatch_fxn = (hwi_dispatch_fxn_t)ramvec_table[INT_AON_RTC_COMB];
+  if(!hwi_dispatch_fxn) {
+    /*
+     * Unable to find the HWI dispatch ISR in the RAM vector table is
+     * a serious fault. Spin-lock forever.
+     */
+    for(;;) { /* hang */ }
+  }
+
+  /*
+   * Override the INT_AON_RTC_COMB interrupt number with our own ISR hook,
+   * which will act as a man-in-the-middle ISR for the HWI dispatch.
+   */
+  IntRegister(INT_AON_RTC_COMB, rtimer_isr_hook);
+
+  AONEventMcuWakeUpSet(AON_EVENT_MCU_WU1, AON_EVENT_RTC_CH1);
+  AONRTCCombinedEventConfig(HWIP_RTC_CH | RTIMER_RTC_CH);
+
+  HwiP_restore(key);
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief    Schedules an rtimer task to be triggered at time \p t.
+ * \param t  The time when the task will need executed.
+ *
+ *           \p t is an absolute time, in other words the task will be
+ *           executed AT time \p t, not IN \p t rtimer ticks.
+ *
+ *           This function schedules a one-shot event with the AON RTC.
+ *
+ *           This functions converts \p t to a value suitable for the AON RTC.
+ */
+void
+rtimer_arch_schedule(rtimer_clock_t t)
+{
+  /* Convert the rtimer tick value to a value suitable for the AON RTC */
+  AONRTCCompareValueSet(RTIMER_RTC_CH, (uint32_t)t);
+  AONRTCChannelEnable(RTIMER_RTC_CH);
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief   Returns the current real-time clock time.
+ * \return  The current rtimer time in ticks.
+ *
+ *          The value is read from the AON RTC counter and converted to a
+ *          number of rtimer ticks.
+ */
+rtimer_clock_t
+rtimer_arch_now()
+{
+  return (rtimer_clock_t)AONRTCCurrentCompareValueGet();
+}
+/*---------------------------------------------------------------------------*/
+/** @} */

arch/cpu/simplelink-cc13xx-cc26xx/dev/rtimer-arch.h

@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \defgroup cc13xx-cc26xx-rtimer The CC13xx/CC26xx rtimer
+ *
+ * Implementation of the rtimer module for CC13xx/CC26xx. This header
+ * is included by os/sys/rtimer.h.
+ *
+ * RTIMER_ARCH_SECOND is defined in cc13xx-cc26xx-def.h.
+ * @{
+ *
+ * \file
+ *        Header file of the rtimer driver for CC13xx/CC26xx.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#ifndef RTIMER_ARCH_H_
+#define RTIMER_ARCH_H_
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+/*---------------------------------------------------------------------------*/
+rtimer_clock_t rtimer_arch_now(void);
+/*---------------------------------------------------------------------------*/
+/*
+ * HW oscillator frequency is 32 kHz, not 64 kHz. And, RTIMER_NOW() never
+ * returns an odd value; US_TO_RTIMERTICKS always rounds to the nearest
+ * even number.
+ */
+#define US_TO_RTIMERTICKS(us)   ( \
+  (((us) >= 0) \
+    ? (((int32_t)(us) * (RTIMER_ARCH_SECOND / 2) + 500000) / 1000000L) \
+    : (((int32_t)(us) * (RTIMER_ARCH_SECOND / 2) - 500000) / 1000000L) \
+  ) * 2)
+
+#define RTIMERTICKS_TO_US(rt)   ( \
+  ((rt) >= 0) \
+    ? (((int32_t)(rt) * 1000000L + (RTIMER_ARCH_SECOND / 2)) / RTIMER_ARCH_SECOND) \
+    : (((int32_t)(rt) * 1000000L - (RTIMER_ARCH_SECOND / 2)) / RTIMER_ARCH_SECOND) \
+  )
+
+/*
+ * A 64-bit version because the 32-bit one cannot handle T >= 4295 ticks.
+ * Intended only for positive values of T.
+ */
+#define RTIMERTICKS_TO_US_64(rt)  ( \
+  (uint32_t)( \
+    ((uint64_t)(rt) * 1000000 + (RTIMER_ARCH_SECOND / 2)) / RTIMER_ARCH_SECOND \
+  ))
+/*---------------------------------------------------------------------------*/
+#endif /* RTIMER_ARCH_H_ */
+/*---------------------------------------------------------------------------*/
+/**
+ * @}
+ * @}
+ */

arch/cpu/simplelink-cc13xx-cc26xx/dev/slip-arch.c

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \defgroup cc13xx-cc26xx-slip-arch SLIP for CC13xx/CC26xx.
+ * @{
+ *
+ * \file
+ *        Implementation of SLIP driver for CC13xx/CC26xx.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+#include "dev/slip.h"
+/*---------------------------------------------------------------------------*/
+#include "uart0-arch.h"
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief    Write a single byte over SLIP.
+ * \param c  The byte to write.
+ */
+void
+slip_arch_writeb(unsigned char c)
+{
+  uart0_write(&c, 1);
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief  Initialize the SLIP driver.
+ */
+void
+slip_arch_init(void)
+{
+  /*
+   * Set an input handler. In doing so, the driver will make sure that UART
+   * RX stays operational during deep sleep.
+   */
+  uart0_init();
+  uart0_set_callback(slip_input_byte);
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * @}
+ * @}
+ */

arch/cpu/simplelink-cc13xx-cc26xx/dev/spi-arch.c

@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \defgroup cc13xx-cc26xx-spi CC13xx/CC26xx SPI HAL
+ *
+ * @{
+ * \file
+ *        Implementation of the SPI HAL driver for CC13xx/CC26xx.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+#include "sys/cc.h"
+#include "dev/spi.h"
+/*---------------------------------------------------------------------------*/
+#include <ti/drivers/SPI.h>
+#include <ti/drivers/dpl/HwiP.h>
+#include <ti/drivers/pin/PINCC26XX.h>
+/*---------------------------------------------------------------------------*/
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+/*---------------------------------------------------------------------------*/
+typedef struct {
+  SPI_Handle handle;
+  const spi_device_t *owner;
+} spi_arch_t;
+/*---------------------------------------------------------------------------*/
+#if (SPI_CONTROLLER_COUNT > 0)
+static spi_arch_t spi_arches[SPI_CONTROLLER_COUNT];
+#else
+static spi_arch_t *spi_arches = NULL;
+#endif
+/*---------------------------------------------------------------------------*/
+static inline spi_arch_t *
+get_handle(uint8_t spi_controller)
+{
+  if(spi_controller < SPI_CONTROLLER_COUNT) {
+    return &spi_arches[spi_controller];
+  } else {
+    return NULL;
+  }
+}
+/*---------------------------------------------------------------------------*/
+static SPI_FrameFormat
+convert_frame_format(uint8_t pol, uint8_t pha)
+{
+  pol = (pol) ? 1 : 0;
+  pha = (pha) ? 1 : 0;
+  /*
+   * Convert pol/pha to a single byte on the following format:
+   *   xxxA xxxB
+   * where A is the polarity bit and B is the phase bit.
+   * Note that any other value deviating from this format will
+   * default to the SPI_POL1_PHA1 format.
+   */
+  uint8_t pol_pha = (pol << 4) | (pha << 0);
+  switch(pol_pha) {
+  case 0x00: return SPI_POL0_PHA0;
+  case 0x01: return SPI_POL0_PHA1;
+  case 0x10: return SPI_POL1_PHA0;
+  default: /* fallthrough */
+  case 0x11: return SPI_POL1_PHA1;
+  }
+}
+/*---------------------------------------------------------------------------*/
+bool
+spi_arch_has_lock(const spi_device_t *dev)
+{
+  /*
+   * The SPI device is the owner if the SPI controller returns a valid
+   * SPI arch object and the SPI device is owner of that object.
+   */
+  spi_arch_t *spi_arch = get_handle(dev->spi_controller);
+  return (spi_arch != NULL) && (spi_arch->owner == dev);
+}
+/*---------------------------------------------------------------------------*/
+bool
+spi_arch_is_bus_locked(const spi_device_t *dev)
+{
+  /*
+   * The SPI controller is locked by any device if the SPI controller returns
+   * a valid SPI arch object and the SPI handle of that object is valid.
+   */
+  spi_arch_t *spi_arch = get_handle(dev->spi_controller);
+  return (spi_arch != NULL) && (spi_arch->handle != NULL);
+}
+/*---------------------------------------------------------------------------*/
+spi_status_t
+spi_arch_lock_and_open(const spi_device_t *dev)
+{
+  uint_least8_t spi_index;
+  spi_arch_t *spi_arch;
+  SPI_Params spi_params;
+
+  const uintptr_t hwi_key = HwiP_disable();
+
+  spi_index = dev->spi_controller;
+  spi_arch = get_handle(spi_index);
+
+  /* Ensure the provided SPI index is valid. */
+  if(spi_arch == NULL) {
+    HwiP_restore(hwi_key);
+    return SPI_DEV_STATUS_EINVAL;
+  }
+
+  /* Ensure the corresponding SPI interface is not already locked. */
+  if(spi_arch_is_bus_locked(dev)) {
+    HwiP_restore(hwi_key);
+    return SPI_DEV_STATUS_BUS_LOCKED;
+  }
+
+  SPI_Params_init(&spi_params);
+
+  spi_params.transferMode = SPI_MODE_BLOCKING;
+  spi_params.mode = SPI_MASTER;
+  spi_params.bitRate = dev->spi_bit_rate;
+  spi_params.dataSize = 8;
+  spi_params.frameFormat = convert_frame_format(dev->spi_pol, dev->spi_pha);
+
+  /*
+   * Try to open the SPI driver. Accessing the SPI driver also ensures
+   * atomic access to the SPI interface.
+   */
+  spi_arch->handle = SPI_open(spi_index, &spi_params);
+
+  if(spi_arch->handle == NULL) {
+    HwiP_restore(hwi_key);
+    return SPI_DEV_STATUS_BUS_LOCKED;
+  }
+
+  spi_arch->owner = dev;
+
+  HwiP_restore(hwi_key);
+  return SPI_DEV_STATUS_OK;
+}
+/*---------------------------------------------------------------------------*/
+spi_status_t
+spi_arch_close_and_unlock(const spi_device_t *dev)
+{
+  spi_arch_t *spi_arch;
+
+  const uintptr_t hwi_key = HwiP_disable();
+
+  /* Ensure the provided SPI index is valid. */
+  spi_arch = get_handle(dev->spi_controller);
+  if(spi_arch == NULL) {
+    HwiP_restore(hwi_key);
+    return SPI_DEV_STATUS_EINVAL;
+  }
+
+  /* Ensure the corresponding SPI device owns the SPI controller. */
+  if(!spi_arch_has_lock(dev)) {
+    HwiP_restore(hwi_key);
+    return SPI_DEV_STATUS_BUS_NOT_OWNED;
+  }
+
+  SPI_close(spi_arch->handle);
+
+  spi_arch->handle = NULL;
+  spi_arch->owner = NULL;
+
+  HwiP_restore(hwi_key);
+  return SPI_DEV_STATUS_OK;
+}
+/*---------------------------------------------------------------------------*/
+spi_status_t
+spi_arch_transfer(const spi_device_t *dev,
+                  const uint8_t *write_buf, int wlen,
+                  uint8_t *inbuf, int rlen, int ignore_len)
+{
+  spi_arch_t *spi_arch;
+  size_t totlen;
+  SPI_Transaction spi_transaction;
+  bool transfer_ok;
+
+  /* Ensure the provided SPI index is valid. */
+  spi_arch = get_handle(dev->spi_controller);
+  if(spi_arch == NULL) {
+    return SPI_DEV_STATUS_EINVAL;
+  }
+
+  if(!spi_arch_has_lock(dev)) {
+    return SPI_DEV_STATUS_BUS_NOT_OWNED;
+  }
+
+  totlen = MAX((size_t)(rlen + ignore_len), (size_t)wlen);
+
+  if(totlen == 0) {
+    /* Nothing to do */
+    return SPI_DEV_STATUS_OK;
+  }
+
+  spi_transaction.count = totlen;
+  spi_transaction.txBuf = (void *)write_buf;
+  spi_transaction.rxBuf = (void *)inbuf;
+
+  transfer_ok = SPI_transfer(spi_arch->handle, &spi_transaction);
+
+  if(!transfer_ok) {
+    return SPI_DEV_STATUS_TRANSFER_ERR;
+  }
+
+  return SPI_DEV_STATUS_OK;
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * @}
+ * @}
+ */

arch/cpu/simplelink-cc13xx-cc26xx/dev/startup_cc13xx_cc26xx_gcc.c

@@ -0,0 +1,311 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \file
+ *        Startup file for GCC for CC13xx/CC26xx.
+ */
+/*---------------------------------------------------------------------------*/
+/* Check if compiler is GNU Compiler. */
+#if !(defined(__GNUC__))
+#error "startup_cc13xx_cc26xx_gcc.c: Unsupported compiler!"
+#endif
+/*---------------------------------------------------------------------------*/
+#include <string.h>
+
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(inc/hw_types.h)
+#include DeviceFamily_constructPath(driverlib/interrupt.h)
+#include DeviceFamily_constructPath(driverlib/setup.h)
+/*---------------------------------------------------------------------------*/
+/* Forward declaration of the default fault handlers. */
+void resetISR(void);
+static void nmiISR(void);
+static void faultISR(void);
+static void defaultHandler(void);
+static void busFaultHandler(void);
+/*---------------------------------------------------------------------------*/
+/*
+ * External declaration for the reset handler that is to be called when the
+ * processor is started.
+ */
+extern void _c_int00(void);
+
+/* The entry point for the application. */
+extern int main(void);
+/*---------------------------------------------------------------------------*/
+/* Linker variable that marks the top of stack. */
+extern unsigned long _stack_end;
+
+/*
+ * The vector table. Note that the proper constructs must be placed on this to
+ * ensure that it ends up at physical address 0x0000.0000.
+ */
+__attribute__((section(".resetVecs"))) __attribute__((used))
+static void(*const resetVectors[16])(void) =
+{
+  (void(*)(void))((uint32_t)&_stack_end),
+  /* The initial stack pointer */
+  resetISR,                            /* The reset handler */
+  nmiISR,                              /* The NMI handler */
+  faultISR,                            /* The hard fault handler */
+  defaultHandler,                      /* The MPU fault handler */
+  busFaultHandler,                     /* The bus fault handler */
+  defaultHandler,                      /* The usage fault handler */
+  0,                                   /* Reserved */
+  0,                                   /* Reserved */
+  0,                                   /* Reserved */
+  0,                                   /* Reserved */
+  defaultHandler,                      /* SVCall handler */
+  defaultHandler,                      /* Debug monitor handler */
+  0,                                   /* Reserved */
+  defaultHandler,                      /* The PendSV handler */
+  defaultHandler                       /* The SysTick handler */
+};
+/*---------------------------------------------------------------------------*/
+/*
+ * The following are arrays of pointers to constructor functions that need to
+ * be called during startup to initialize global objects.
+ */
+extern void (*__init_array_start[])(void);
+extern void (*__init_array_end[])(void);
+
+/* The following global variable is required for C++ support. */
+void *__dso_handle = (void *)&__dso_handle;
+/*---------------------------------------------------------------------------*/
+/*
+ * The following are constructs created by the linker, indicating where the
+ * the "data" and "bss" segments reside in memory. The initializers for the
+ * for the "data" segment resides immediately following the "text" segment.
+ */
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __data_load__;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+/*---------------------------------------------------------------------------*/
+/*
+ * \brief  Entry point of the startup code.
+ *
+ * Initialize the .data and .bss sections, and call main.
+ */
+void
+localProgramStart(void)
+{
+  uint32_t *bs;
+  uint32_t *be;
+  uint32_t *dl;
+  uint32_t *ds;
+  uint32_t *de;
+  uint32_t count;
+  uint32_t i;
+
+  IntMasterDisable();
+
+  /* Final trim of device */
+  SetupTrimDevice();
+
+  /* initiailize .bss to zero */
+  bs = &__bss_start__;
+  be = &__bss_end__;
+  while(bs < be) {
+    *bs = 0;
+    bs++;
+  }
+
+  /* relocate the .data section */
+  dl = &__data_load__;
+  ds = &__data_start__;
+  de = &__data_end__;
+  if(dl != ds) {
+    while(ds < de) {
+      *ds = *dl;
+      dl++;
+      ds++;
+    }
+  }
+
+  /* Run any constructors */
+  count = (uint32_t)(__init_array_end - __init_array_start);
+  for(i = 0; i < count; i++) {
+    __init_array_start[i]();
+  }
+
+  /* Call the application's entry point. */
+  main();
+
+  /* If we ever return signal Error */
+  faultISR();
+}
+/*---------------------------------------------------------------------------*/
+/*
+ * \brief  Reset ISR.
+ *
+ * This is the code that gets called when the processor first starts execution
+ * following a reset event. Only the absolutely necessary set is performed,
+ * after which the application supplied entry() routine is called.  Any fancy
+ * actions (such as making decisions based on the reset cause register, and
+ * resetting the bits in that register) are left solely in the hands of the
+ * application.
+ */
+void __attribute__((naked))
+resetISR(void)
+{
+  __asm__ __volatile__
+  (
+    "movw r0, #:lower16:resetVectors  \n"
+    "movt r0, #:upper16:resetVectors  \n"
+    "ldr r0, [r0]                     \n"
+    "mov sp, r0                       \n"
+    "bx %0                            \n"
+    : /* output */
+    : /* input */
+    "r"(localProgramStart)
+  );
+}
+/*---------------------------------------------------------------------------*/
+/*
+ * \brief  Non-Maskable Interrupt (NMI) ISR.
+ *
+ * This is the code that gets called when the processor receives a NMI. This
+ * simply enters an infinite loop, preserving the system state for examination
+ * by a debugger.
+ */
+static void
+nmiISR(void)
+{
+  /* Enter an infinite loop. */
+  for(;;) { /* hang */ }
+}
+/*---------------------------------------------------------------------------*/
+/*
+ * \brief     Debug stack pointer.
+ * \param sp  Stack pointer.
+ *
+ * Provide a view into the CPU state from the provided stack pointer.
+ */
+static void
+debugHardfault(uint32_t *sp)
+{
+  volatile uint32_t r0;  /**< R0 register */
+  volatile uint32_t r1;  /**< R1 register */
+  volatile uint32_t r2;  /**< R2 register */
+  volatile uint32_t r3;  /**< R3 register */
+  volatile uint32_t r12; /**< R12 register */
+  volatile uint32_t lr;  /**< LR register */
+  volatile uint32_t pc;  /**< PC register */
+  volatile uint32_t psr; /**< PSR register */
+
+  (void)(r0  = sp[0]);
+  (void)(r1  = sp[1]);
+  (void)(r2  = sp[2]);
+  (void)(r3  = sp[3]);
+  (void)(r12 = sp[4]);
+  (void)(lr  = sp[5]);
+  (void)(pc  = sp[6]);
+  (void)(psr = sp[7]);
+
+  /* Enter an infinite loop. */
+  for(;;) { /* hang */ }
+}
+/*---------------------------------------------------------------------------*/
+/*
+ * \brief  CPU Fault ISR.
+ *
+ * This is the code that gets called when the processor receives a fault
+ * interrupt. Setup a call to debugStackPointer with the current stack pointer.
+ * The stack pointer in this case would be the CPU state which caused the CPU
+ * fault.
+ */
+static void
+faultISR(void)
+{
+  __asm__ __volatile__
+  (
+    "tst lr, #4        \n"
+    "ite eq            \n"
+    "mrseq r0, msp     \n"
+    "mrsne r0, psp     \n"
+    "bx %0             \n"
+    : /* output */
+    : /* input */
+    "r"(debugHardfault)
+  );
+}
+/*---------------------------------------------------------------------------*/
+/* Dummy variable */
+volatile int x__;
+
+/*
+ * \brief  Bus Fault Handler.
+ *
+ * This is the code that gets called when the processor receives an unexpected
+ * interrupt. This simply enters an infinite loop, preserving the system state
+ * for examination by a debugger.
+ */
+static void
+busFaultHandler(void)
+{
+  x__ = 0;
+
+  /* Enter an infinite loop. */
+  for(;;) { /* hang */ }
+}
+/*---------------------------------------------------------------------------*/
+/*
+ * \brief  Default Handler.
+ *
+ * This is the code that gets called when the processor receives an unexpected
+ * interrupt.  This simply enters an infinite loop, preserving the system state
+ * for examination by a debugger.
+ */
+static void
+defaultHandler(void)
+{
+  /* Enter an infinite loop. */
+  for(;;) { /* hang */ }
+}
+/*---------------------------------------------------------------------------*/
+/*
+ * \brief  Finalize object function.
+ *
+ * This function is called by __libc_fini_array which gets called when exit()
+ * is called. In order to support exit(), an empty _fini() stub function is
+ * required.
+ */
+void
+_fini(void)
+{
+  /* Function body left empty intentionally */
+}
+/*---------------------------------------------------------------------------*/
+/** @} */

arch/cpu/simplelink-cc13xx-cc26xx/dev/startup_cc13xx_cc26xx_iar.c

@@ -0,0 +1,318 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \file
+ *        Startup file for IAR for CC13xx/CC26xx.
+ */
+/*---------------------------------------------------------------------------*/
+/* Check if compiler is IAR. */
+#if !(defined(__IAR_SYSTEMS_ICC__))
+#error "startup_cc13xx_cc26xx_iar.c: Unsupported compiler!"
+#endif
+/*---------------------------------------------------------------------------*/
+/* We need intrinsic functions for IAR (if used in source code). */
+#include <intrinsics.h>
+
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(inc/hw_types.h)
+#include DeviceFamily_constructPath(driverlib/setup.h)
+#include DeviceFamily_constructPath(driverlib/interrupt.h)
+/*---------------------------------------------------------------------------*/
+/* Forward declaration of the reset ISR and the default fault handlers. */
+static void nmiISR(void);
+static void faultISR(void);
+static void intDefaultHandler(void);
+extern int  main(void);
+
+extern void MPUFaultIntHandler(void);
+extern void BusFaultIntHandler(void);
+extern void UsageFaultIntHandler(void);
+extern void SVCallIntHandler(void);
+extern void DebugMonIntHandler(void);
+extern void PendSVIntHandler(void);
+extern void SysTickIntHandler(void);
+extern void GPIOIntHandler(void);
+extern void I2CIntHandler(void);
+extern void RFCCPE1IntHandler(void);
+extern void AONRTCIntHandler(void);
+extern void UART0IntHandler(void);
+extern void AUXSWEvent0IntHandler(void);
+extern void SSI0IntHandler(void);
+extern void SSI1IntHandler(void);
+extern void RFCCPE0IntHandler(void);
+extern void RFCHardwareIntHandler(void);
+extern void RFCCmdAckIntHandler(void);
+extern void I2SIntHandler(void);
+extern void AUXSWEvent1IntHandler(void);
+extern void WatchdogIntHandler(void);
+extern void Timer0AIntHandler(void);
+extern void Timer0BIntHandler(void);
+extern void Timer1AIntHandler(void);
+extern void Timer1BIntHandler(void);
+extern void Timer2AIntHandler(void);
+extern void Timer2BIntHandler(void);
+extern void Timer3AIntHandler(void);
+extern void Timer3BIntHandler(void);
+extern void CryptoIntHandler(void);
+extern void uDMAIntHandler(void);
+extern void uDMAErrIntHandler(void);
+extern void FlashIntHandler(void);
+extern void SWEvent0IntHandler(void);
+extern void AUXCombEventIntHandler(void);
+extern void AONProgIntHandler(void);
+extern void DynProgIntHandler(void);
+extern void AUXCompAIntHandler(void);
+extern void AUXADCIntHandler(void);
+extern void TRNGIntHandler(void);
+
+/* Default interrupt handlers */
+#pragma weak MPUFaultIntHandler     = intDefaultHandler
+#pragma weak BusFaultIntHandler     = intDefaultHandler
+#pragma weak UsageFaultIntHandler   = intDefaultHandler
+#pragma weak SVCallIntHandler       = intDefaultHandler
+#pragma weak DebugMonIntHandler     = intDefaultHandler
+#pragma weak PendSVIntHandler       = intDefaultHandler
+#pragma weak SysTickIntHandler      = intDefaultHandler
+#pragma weak GPIOIntHandler         = intDefaultHandler
+#pragma weak I2CIntHandler          = intDefaultHandler
+#pragma weak RFCCPE1IntHandler      = intDefaultHandler
+#pragma weak AONRTCIntHandler       = intDefaultHandler
+#pragma weak UART0IntHandler        = intDefaultHandler
+#pragma weak AUXSWEvent0IntHandler  = intDefaultHandler
+#pragma weak SSI0IntHandler         = intDefaultHandler
+#pragma weak SSI1IntHandler         = intDefaultHandler
+#pragma weak RFCCPE0IntHandler      = intDefaultHandler
+#pragma weak RFCHardwareIntHandler  = intDefaultHandler
+#pragma weak RFCCmdAckIntHandler    = intDefaultHandler
+#pragma weak I2SIntHandler          = intDefaultHandler
+#pragma weak AUXSWEvent1IntHandler  = intDefaultHandler
+#pragma weak WatchdogIntHandler     = intDefaultHandler
+#pragma weak Timer0AIntHandler      = intDefaultHandler
+#pragma weak Timer0BIntHandler      = intDefaultHandler
+#pragma weak Timer1AIntHandler      = intDefaultHandler
+#pragma weak Timer1BIntHandler      = intDefaultHandler
+#pragma weak Timer2AIntHandler      = intDefaultHandler
+#pragma weak Timer2BIntHandler      = intDefaultHandler
+#pragma weak Timer3AIntHandler      = intDefaultHandler
+#pragma weak Timer3BIntHandler      = intDefaultHandler
+#pragma weak CryptoIntHandler       = intDefaultHandler
+#pragma weak uDMAIntHandler         = intDefaultHandler
+#pragma weak uDMAErrIntHandler      = intDefaultHandler
+#pragma weak FlashIntHandler        = intDefaultHandler
+#pragma weak SWEvent0IntHandler     = intDefaultHandler
+#pragma weak AUXCombEventIntHandler = intDefaultHandler
+#pragma weak AONProgIntHandler      = intDefaultHandler
+#pragma weak DynProgIntHandler      = intDefaultHandler
+#pragma weak AUXCompAIntHandler     = intDefaultHandler
+#pragma weak AUXADCIntHandler       = intDefaultHandler
+#pragma weak TRNGIntHandler         = intDefaultHandler
+/*---------------------------------------------------------------------------*/
+/* The entry point for the application startup code. */
+extern void __iar_program_start(void);
+
+/* Get stack start (highest address) symbol from linker file. */
+extern const void *STACK_TOP;
+/*---------------------------------------------------------------------------*/
+/*
+ * It is required to place something in the CSTACK segment to get the stack
+ * check feature in IAR to work as expected
+ */
+__root static void *dummy_stack @ ".stack";
+
+/*
+ * The vector table. Note that the proper constructs must be placed on this to
+ * ensure that it ends up at physical address 0x0000.0000 or at the start of
+ * the program if located at a start address other than 0.
+ */
+__root void(*const __vector_table[])(void) @ ".intvec" =
+{
+  (void (*)(void)) & STACK_TOP,           /*  0 The initial stack pointer */
+  __iar_program_start,                    /*  1 The reset handler */
+  nmiISR,                                 /*  2 The NMI handler */
+  faultISR,                               /*  3 The hard fault handler */
+  MPUFaultIntHandler,                     /*  4 The MPU fault handler */
+  BusFaultIntHandler,                     /*  5 The bus fault handler */
+  UsageFaultIntHandler,                   /*  6 The usage fault handler */
+  0,                                      /*  7 Reserved */
+  0,                                      /*  8 Reserved */
+  0,                                      /*  9 Reserved */
+  0,                                      /* 10 Reserved */
+  SVCallIntHandler,                       /* 11 SVCall handler */
+  DebugMonIntHandler,                     /* 12 Debug monitor handler */
+  0,                                      /* 13 Reserved */
+  PendSVIntHandler,                       /* 14 The PendSV handler */
+  SysTickIntHandler,                      /* 15 The SysTick handler */
+  /* --- External interrupts --- */
+  GPIOIntHandler,                         /* 16 AON edge detect */
+  I2CIntHandler,                          /* 17 I2C */
+  RFCCPE1IntHandler,                      /* 18 RF Core Command & Packet Engine 1 */
+  intDefaultHandler,                      /* 19 Reserved */
+  AONRTCIntHandler,                       /* 20 AON RTC */
+  UART0IntHandler,                        /* 21 UART0 Rx and Tx */
+  AUXSWEvent0IntHandler,                  /* 22 AUX software event 0 */
+  SSI0IntHandler,                         /* 23 SSI0 Rx and Tx */
+  SSI1IntHandler,                         /* 24 SSI1 Rx and Tx */
+  RFCCPE0IntHandler,                      /* 25 RF Core Command & Packet Engine 0 */
+  RFCHardwareIntHandler,                  /* 26 RF Core Hardware */
+  RFCCmdAckIntHandler,                    /* 27 RF Core Command Acknowledge */
+  I2SIntHandler,                          /* 28 I2S */
+  AUXSWEvent1IntHandler,                  /* 29 AUX software event 1 */
+  WatchdogIntHandler,                     /* 30 Watchdog timer */
+  Timer0AIntHandler,                      /* 31 Timer 0 subtimer A */
+  Timer0BIntHandler,                      /* 32 Timer 0 subtimer B */
+  Timer1AIntHandler,                      /* 33 Timer 1 subtimer A */
+  Timer1BIntHandler,                      /* 34 Timer 1 subtimer B */
+  Timer2AIntHandler,                      /* 35 Timer 2 subtimer A */
+  Timer2BIntHandler,                      /* 36 Timer 2 subtimer B */
+  Timer3AIntHandler,                      /* 37 Timer 3 subtimer A */
+  Timer3BIntHandler,                      /* 38 Timer 3 subtimer B */
+  CryptoIntHandler,                       /* 39 Crypto Core Result available */
+  uDMAIntHandler,                         /* 40 uDMA Software */
+  uDMAErrIntHandler,                      /* 41 uDMA Error */
+  FlashIntHandler,                        /* 42 Flash controller */
+  SWEvent0IntHandler,                     /* 43 Software Event 0 */
+  AUXCombEventIntHandler,                 /* 44 AUX combined event */
+  AONProgIntHandler,                      /* 45 AON programmable 0 */
+  DynProgIntHandler,                      /* 46 Dynamic Programmable interrupt */
+                                          /*    source (Default: PRCM) */
+  AUXCompAIntHandler,                     /* 47 AUX Comparator A */
+  AUXADCIntHandler,                       /* 48 AUX ADC new sample or ADC DMA */
+                                          /*    done, ADC underflow, ADC overflow */
+  TRNGIntHandler                          /* 49 TRNG event */
+}
+/*---------------------------------------------------------------------------*/
+/*
+ * \brief   Setup trim device.
+ * \return  Return value determines whether to omit seg_init or not.
+ *       0 => omit seg_init
+ *       1 => run seg_init
+ *
+ * This function is called by __iar_program_start() early in the boot sequence.
+ * Copy the first 16 vectors from the read-only/reset table to the runtime
+ * RAM table. Fill the remaining vectors with a stub. This vector table will
+ * be updated at runtime.
+ */
+int
+__low_level_init(void)
+{
+  IntMasterDisable();
+
+  /* Final trim of device */
+  SetupTrimDevice();
+
+  /* Run seg_init */
+  return 1;
+}
+/*---------------------------------------------------------------------------*/
+/*
+ * \brief  Non-Maskable Interrupt (NMI) ISR.
+ *
+ * This is the code that gets called when the processor receives a NMI. This
+ * simply enters an infinite loop, preserving the system state for examination
+ * by a debugger.
+ */
+static void
+nmiISR(void)
+{
+  /* Enter an infinite loop. */
+  for(;;) { /* hang */ }
+}
+/*---------------------------------------------------------------------------*/
+/*
+ * \brief     Debug stack pointer.
+ * \param sp  Stack pointer.
+ *
+ * Provide a view into the CPU state from the provided stack pointer.
+ */
+void
+debugStackPointer(uint32_t *sp)
+{
+  volatile uint32_t r0;  /**< R0 register */
+  volatile uint32_t r1;  /**< R1 register */
+  volatile uint32_t r2;  /**< R2 register */
+  volatile uint32_t r3;  /**< R3 register */
+  volatile uint32_t r12; /**< R12 register */
+  volatile uint32_t lr;  /**< LR register */
+  volatile uint32_t pc;  /**< PC register */
+  volatile uint32_t psr; /**< PSR register */
+
+  /* Cast to void to disable warnings of unused variables */
+  (void)(r0  = sp[0]);
+  (void)(r1  = sp[1]);
+  (void)(r2  = sp[2]);
+  (void)(r3  = sp[3]);
+  (void)(r12 = sp[4]);
+  (void)(lr  = sp[5]);
+  (void)(pc  = sp[6]);
+  (void)(psr = sp[7]);
+
+  /* Enter an infinite loop. */
+  for(;;) { /* hang */ }
+}
+/*---------------------------------------------------------------------------*/
+/*
+ * \brief  CPU Fault ISR.
+ *
+ * This is the code that gets called when the processor receives a fault
+ * interrupt. Setup a call to debugStackPointer with the current stack pointer.
+ * The stack pointer in this case would be the CPU state which caused the CPU
+ * fault.
+ */
+static void
+faultISR(void)
+{
+  __asm__ __volatile__
+  (
+    "tst lr, #4           \n"
+    "ite eq               \n"
+    "mrseq r0, msp        \n"
+    "mrsne r0, psp        \n"
+    "b debugStackPointer  \n"
+  );
+}
+/*---------------------------------------------------------------------------*/
+/*
+ * \brief  Interrupt Default Handler.
+ *
+ * This is the code that gets called when the processor receives an unexpected
+ * interrupt. This simply enters an infinite loop, preserving the system state
+ * for examination by a debugger.
+ */
+static void
+intDefaultHandler(void)
+{
+  /* Enter an infinite loop. */
+  for(;;) { /* hang */ }
+}
+/*---------------------------------------------------------------------------*/
+/** @} */

arch/cpu/simplelink-cc13xx-cc26xx/dev/trng-arch.c

@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-trng
+ * @{
+ *
+ * \file
+ *        Implementation of True Random Number Generator for CC13xx/CC26xx.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+
+#include "trng-arch.h"
+/*---------------------------------------------------------------------------*/
+#include <ti/drivers/TRNG.h>
+#include <ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h>
+/*---------------------------------------------------------------------------*/
+/*
+ * Very dirty workaround because the pre-compiled TI drivers library for
+ * CC13x0/CC26x0 is missing the CryptoKey object file. This can be removed
+ * when the pre-compiled library includes the missing object file.
+ */
+#include <ti/devices/DeviceFamily.h>
+#if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X0_CC26X0)
+#include <ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintextCC26XX.c>
+#endif
+/*---------------------------------------------------------------------------*/
+#include <stdint.h>
+#include <stdbool.h>
+/*---------------------------------------------------------------------------*/
+bool
+trng_rand(uint8_t *entropy_buf, size_t entropy_len, uint32_t timeout_us)
+{
+  TRNG_Params trng_params;
+  TRNG_Handle trng_handle;
+  CryptoKey entropy_key;
+  int_fast16_t result;
+
+  TRNG_Params_init(&trng_params);
+  trng_params.returnBehavior = TRNG_RETURN_BEHAVIOR_BLOCKING;
+  if(timeout_us != TRNG_WAIT_FOREVER) {
+    trng_params.timeout = timeout_us;
+  }
+
+  trng_handle = TRNG_open(0, &trng_params);
+  if(!trng_handle) {
+    return false;
+  }
+
+  CryptoKeyPlaintext_initBlankKey(&entropy_key, entropy_buf, entropy_len);
+
+  result = TRNG_generateEntropy(trng_handle, &entropy_key);
+
+  TRNG_close(trng_handle);
+
+  return result == TRNG_STATUS_SUCCESS;
+}
+/*---------------------------------------------------------------------------*/
+/** @} */

arch/cpu/simplelink-cc13xx-cc26xx/dev/trng-arch.h

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \defgroup cc13xx-cc26xx-trng True Random Number Generator for CC13xx/CC26xx.
+ * @{
+ *
+ * \file
+ *        Header file of True Random Number Generator for CC13xx/CC26xx.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#ifndef TRNG_ARCH_H_
+#define TRNG_ARCH_H_
+/*---------------------------------------------------------------------------*/
+#include <contiki.h>
+/*---------------------------------------------------------------------------*/
+#include <stdbool.h>
+#include <stdint.h>
+/*---------------------------------------------------------------------------*/
+#define TRNG_WAIT_FOREVER       (~(uint32_t)0)
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief              Generates a stream of entropy from which you can create
+ *                     a true random number from. This is a blocking function
+ *                     call with a specified timeout.
+ * \param entropy_buf  Buffer to store a stream of entropy.
+ * \param entropy_len  Length of the entropy buffer.
+ * \param timeout_us   How long to wait until timing out the operation. A
+ *                     timeout of TRNG_WAIT_FOREVER blocks forever.
+ * \return             true if successful; else, false.
+ */
+bool trng_rand(uint8_t *entropy_buf, size_t entropy_len, uint32_t timeout_us);
+/*---------------------------------------------------------------------------*/
+#endif /* TRNG_ARCH_H_ */
+/*---------------------------------------------------------------------------*/
+/**
+ * @}
+ * @}
+ */

arch/cpu/simplelink-cc13xx-cc26xx/dev/uart0-arch.c

@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-uart
+ * @{
+ *
+ * \file
+ *        Implementation of UART driver for CC13xx/CC26xx.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+/*---------------------------------------------------------------------------*/
+#include "uart0-arch.h"
+/*---------------------------------------------------------------------------*/
+#include <Board.h>
+
+#include <ti/drivers/UART.h>
+/*---------------------------------------------------------------------------*/
+#include <stdint.h>
+#include <stdbool.h>
+/*---------------------------------------------------------------------------*/
+static UART_Handle uart_handle;
+
+static volatile uart0_input_fxn_t curr_input_cb;
+static unsigned char char_buf;
+
+static bool initialized;
+/*---------------------------------------------------------------------------*/
+static void
+uart0_cb(UART_Handle handle, void *buf, size_t count)
+{
+  /* Simply return if the current callback is NULL. */
+  if(!curr_input_cb) {
+    return;
+  }
+
+  /*
+   * Save the current callback function locally, as it might be overwritten
+   * after calling the callback.
+   */
+  const uart0_input_fxn_t curr_cb = curr_input_cb;
+  curr_cb(char_buf);
+  /*
+   * If curr_input_cb didn't change after the call, do another read.
+   * Else, the uart0_set_callback was called with a different callback pointer
+   * and triggered an another read.
+   */
+  if(curr_cb == curr_input_cb) {
+    UART_read(uart_handle, &char_buf, 1);
+  }
+}
+/*---------------------------------------------------------------------------*/
+void
+uart0_init(void)
+{
+  if(initialized) {
+    return;
+  }
+
+  UART_Params uart_params;
+  UART_Params_init(&uart_params);
+
+  uart_params.baudRate = TI_UART_CONF_BAUD_RATE;
+  uart_params.readMode = UART_MODE_CALLBACK;
+  uart_params.writeMode = UART_MODE_BLOCKING;
+  uart_params.readCallback = uart0_cb;
+  uart_params.readDataMode = UART_DATA_TEXT;
+  uart_params.readReturnMode = UART_RETURN_NEWLINE;
+
+  /* No error handling. */
+  uart_handle = UART_open(Board_UART0, &uart_params);
+
+  initialized = true;
+}
+/*---------------------------------------------------------------------------*/
+int_fast32_t
+uart0_write(const void *buf, size_t buf_size)
+{
+  if(!initialized) {
+    return UART_STATUS_ERROR;
+  }
+  return UART_write(uart_handle, buf, buf_size);
+}
+/*---------------------------------------------------------------------------*/
+int_fast32_t
+uart0_write_byte(uint8_t byte)
+{
+  if(!initialized) {
+    return UART_STATUS_ERROR;
+  }
+  return UART_write(uart_handle, &byte, 1);
+}
+/*---------------------------------------------------------------------------*/
+int_fast32_t
+uart0_set_callback(uart0_input_fxn_t input_cb)
+{
+  if(!initialized) {
+    return UART_STATUS_ERROR;
+  }
+
+  if(curr_input_cb == input_cb) {
+    return UART_STATUS_SUCCESS;
+  }
+
+  curr_input_cb = input_cb;
+  if(input_cb) {
+    return UART_read(uart_handle, &char_buf, 1);
+  } else {
+    UART_readCancel(uart_handle);
+    return UART_STATUS_SUCCESS;
+  }
+}
+/*---------------------------------------------------------------------------*/
+/** @} */

arch/cpu/simplelink-cc13xx-cc26xx/dev/uart0-arch.h

@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \defgroup cc13xx-cc26xx-uart UART for CC13xx/CC26xx.
+ *
+ * This particular driver utilizes the UART0 peripheral specifically.
+ *
+ * Driver for the CC13xx/CC26xx UART controller.
+ * @{
+ *
+ * \file
+ *        Header file of UART driver for CC13xx/CC26xx.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+#ifndef UART0_ARCH_H_
+#define UART0_ARCH_H_
+/*---------------------------------------------------------------------------*/
+#include <stddef.h>
+#include <stdint.h>
+/*---------------------------------------------------------------------------*/
+typedef int (*uart0_input_fxn_t)(unsigned char);
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief  Initializes the UART driver.
+ */
+void uart0_init(void);
+
+/**
+ * \brief           Writes data from a memory buffer to the UART interface.
+ * \param buf       A pointer to the data buffer.
+ * \param buf_size  Size of the data buffer.
+ * \return          Number of bytes that has been written to the UART. If an
+ *                  error occurs, a negative value is returned.
+ */
+int_fast32_t uart0_write(const void *buf, size_t buf_size);
+
+/**
+ * \brief           Writes a single byte to the UART interface.
+ * \param byte      Byte to write.
+ * \return          Number of bytes that has been written to the UART. If an
+ *                  error occurs, a negative value is returned.
+ */
+int_fast32_t uart0_write_byte(uint8_t byte);
+
+/**
+ * \brief           Set the callback function for when bytes are received
+ *                  on UART0.
+ * \param input_cb  Pointer to the callback function. A valid pointer
+ *                  subscribes for UART0 callbacks when bytes are received,
+ *                  while a NULL pointer unsubscribes.
+ * \return          0 for success, negative value for errors.
+ */
+int_fast32_t uart0_set_callback(uart0_input_fxn_t input_cb);
+/*---------------------------------------------------------------------------*/
+#endif /* UART0_ARCH_H_ */
+/**
+ * @}
+ * @}
+ */

arch/cpu/simplelink-cc13xx-cc26xx/dev/watchdog-arch.c

@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ /**
+ * \addtogroup cc13xx-cc26xx-cpu
+ * @{
+ *
+ * \defgroup cc13xx-cc26xx-watchdog CC13xx/CC26xx watchdog timer driver
+ *
+ * Driver for the CC13xx/CC26xx Watchdog Timer
+ *
+ * This file is not called watchdog.c because the filename is in use by
+ * TI CC26xxware/CC13xxware
+ * @{
+ *
+ * \file
+ * Implementation of the CC13xx/CC26xx watchdog driver.
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+#include "dev/watchdog.h"
+/*---------------------------------------------------------------------------*/
+#include <Board.h>
+
+#include <ti/drivers/Watchdog.h>
+/*---------------------------------------------------------------------------*/
+#include <stdbool.h>
+#include <stdint.h>
+/*---------------------------------------------------------------------------*/
+#define WATCHDOG_DISABLE    WATCHDOG_CONF_DISABLE
+#define WATCHDOG_TIMER_TOP  WATCHDOG_CONF_TIMER_TOP
+/*---------------------------------------------------------------------------*/
+static Watchdog_Handle wdt_handle;
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief  Initialises the Watchdog module.
+ *
+ *         Simply sets the reload counter to a default value. The WDT is not
+ *         started yet. To start it, watchdog_start() must be called.
+ */
+void
+watchdog_init(void)
+{
+  if(WATCHDOG_DISABLE) {
+    return;
+  }
+
+  Watchdog_init();
+
+  Watchdog_Params wdt_params;
+  Watchdog_Params_init(&wdt_params);
+
+  wdt_params.resetMode = Watchdog_RESET_ON;
+  wdt_params.debugStallMode = Watchdog_DEBUG_STALL_ON;
+
+  wdt_handle = Watchdog_open(Board_WATCHDOG0, &wdt_params);
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief  Start the Watchdog.
+ */
+void
+watchdog_start(void)
+{
+  if(WATCHDOG_DISABLE) {
+    return;
+  }
+
+  watchdog_periodic();
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief  Refresh (feed) the Watchdog.
+ */
+void
+watchdog_periodic(void)
+{
+  if(WATCHDOG_DISABLE) {
+    return;
+  }
+
+  Watchdog_setReload(wdt_handle, WATCHDOG_TIMER_TOP);
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief  Stop the Watchdog such that it won't timeout and cause a
+ *         system reset.
+ */
+void
+watchdog_stop(void)
+{
+  if(WATCHDOG_DISABLE) {
+    return;
+  }
+
+  Watchdog_clear(wdt_handle);
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief  Manually trigger a Watchdog timeout.
+ */
+void
+watchdog_reboot(void)
+{
+  if(WATCHDOG_DISABLE) {
+    return;
+  }
+
+  watchdog_start();
+
+  /* Busy loop until watchdog times out */
+  for (;;) { /* hang */ }
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * @}
+ * @}
+ */

arch/cpu/simplelink-cc13xx-cc26xx/doxygen-group.txt

@@ -0,0 +1,16 @@
+/**
+ * \defgroup cc13xx-cc26xx-cpu The TI SimpleLink CC13xx and CC26xx SoC
+ *
+ * This group documents the TI CC13xx and CC26xx CPUs. The two CPU families are
+ * very similar, with the main difference being related to radio capability.
+ *
+ * Documentation in this group should be considered to be applicable to both
+ * families, unless explicitly stated otherwise.
+ *
+ * \ingroup cpu
+ */
+
+/**
+ * \defgroup cc13xx-cc26xx-platform TI SimpleLink CC13xx/CC26xx platform
+ * \ingroup platform
+ */

arch/cpu/simplelink-cc13xx-cc26xx/lib/coresdk_cc13xx_cc26xx

@@ -0,0 +1 @@
+Subproject commit b83faf3be2cb7468dc836a6fbd9d804638263252

arch/cpu/simplelink-cc13xx-cc26xx/rf-settings/cc13x0/ble-settings.c

@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*---------------------------------------------------------------------------*/
+/*
+ * Parameter summary
+ * Adv. Address: 010203040506
+ * Adv. Data: 255
+ * BLE Channel: 17
+ * Frequency: 2440 MHz
+ * PDU Payload length: 30
+ * TX Power: 9 dBm (requires define CCFG_FORCE_VDDR_HH = 1 in ccfg.c,
+ *                  see CC13xx/CC26xx Technical Reference Manual)
+ * Whitening: true
+ */
+/*---------------------------------------------------------------------------*/
+#include "sys/cc.h"
+/*---------------------------------------------------------------------------*/
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(driverlib/rf_mailbox.h)
+#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h)
+#include DeviceFamily_constructPath(driverlib/rf_ble_cmd.h)
+#include DeviceFamily_constructPath(rf_patches/rf_patch_cpe_ble.h)
+#include DeviceFamily_constructPath(rf_patches/rf_patch_rfe_ble.h)
+
+#include <ti/drivers/rf/RF.h>
+/*---------------------------------------------------------------------------*/
+#include "ble-settings.h"
+/*---------------------------------------------------------------------------*/
+/* TI-RTOS RF Mode Object */
+RF_Mode rf_ble_mode =
+{
+  .rfMode = RF_MODE_BLE,
+  .cpePatchFxn = &rf_patch_cpe_ble,
+  .mcePatchFxn = 0,
+  .rfePatchFxn = &rf_patch_rfe_ble,
+};
+/*---------------------------------------------------------------------------*/
+/* Overrides for CMD_RADIO_SETUP */
+uint32_t rf_ble_overrides[] CC_ALIGN(4) =
+{
+                                     /* override_use_patch_ble_1mbps.xml */
+  MCE_RFE_OVERRIDE(0,0,0,1,0,0),     /* PHY: Use MCE ROM, RFE RAM patch */
+                                     /* override_synth_ble_1mbps.xml */
+  HW_REG_OVERRIDE(0x4038,0x0034),    /* Synth: Set recommended RTRIM to 4 */
+  (uint32_t)0x000784A3,              /* Synth: Set Fref to 3.43 MHz */
+  HW_REG_OVERRIDE(0x4020,0x7F00),    /* Synth: Configure fine calibration setting */
+  HW_REG_OVERRIDE(0x4064,0x0040),    /* Synth: Configure fine calibration setting */
+  (uint32_t)0xB1070503,              /* Synth: Configure fine calibration setting */
+  (uint32_t)0x05330523,              /* Synth: Configure fine calibration setting */
+  (uint32_t)0xA47E0583,              /* Synth: Set loop bandwidth after lock to 80 kHz */
+  (uint32_t)0xEAE00603,              /* Synth: Set loop bandwidth after lock to 80 kHz */
+  (uint32_t)0x00010623,              /* Synth: Set loop bandwidth after lock to 80 kHz */
+  HW32_ARRAY_OVERRIDE(0x405C,1),     /* Synth: Configure PLL bias */
+  (uint32_t)0x18000000,              /* Synth: Configure PLL bias */
+                                     /* Synth: Configure VCO LDO */
+  ADI_REG_OVERRIDE(1,4,0x9F),        /* (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference) */
+  ADI_HALFREG_OVERRIDE(1,7,0x4,0x4), /* Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1) */
+                                     /* override_phy_ble_1mbps.xml */
+  (uint32_t)0x013800C3,              /* Tx: Configure symbol shape for BLE frequency deviation requirements */
+  HW_REG_OVERRIDE(0x6088, 0x0045),   /* Rx: Configure AGC reference level */
+  HW_REG_OVERRIDE(0x6084, 0x05FD),   /* Rx: Configure AGC gain level */
+  (uint32_t)0x00038883,              /* Rx: Configure LNA bias current trim offset */
+                                     /* override_frontend_xd.xml */
+  (uint32_t)0x00F388A3,              /* Rx: Set RSSI offset to adjust reported RSSI by +13 dB */
+                                     /* TX power override */
+  ADI_REG_OVERRIDE(0,12,0xF8),       /* Tx: Set PA trim to max (in ADI0, set PACTL0=0xF8) */
+  (uint32_t)0xFFFFFFFF,
+};
+/*---------------------------------------------------------------------------*/
+/* CMD_RADIO_SETUP: Radio Setup Command for Pre-Defined Schemes */
+rfc_CMD_RADIO_SETUP_t rf_ble_cmd_radio_setup =
+{
+  .commandNo = CMD_RADIO_SETUP,
+  .status = IDLE,
+  .pNextOp = 0,
+  .startTime = 0x00000000,
+  .startTrigger.triggerType = TRIG_NOW,
+  .startTrigger.bEnaCmd = 0x0,
+  .startTrigger.triggerNo = 0x0,
+  .startTrigger.pastTrig = 0x0,
+  .condition.rule = COND_NEVER,
+  .condition.nSkip = 0x0,
+  .mode = 0x00,
+  .loDivider = 0x00,
+  .config.frontEndMode = 0x0,
+  .config.biasMode = 0x0,
+  .config.analogCfgMode = 0x0,
+  .config.bNoFsPowerUp = 0x0,
+  .txPower = 0x3D3F,
+  .pRegOverride = rf_ble_overrides,
+};
+/*---------------------------------------------------------------------------*/
+/* Structure for CMD_BLE_ADV_NC.pParams */
+rfc_bleAdvPar_t rf_ble_adv_par =
+{
+  .pRxQ = 0,
+  .rxConfig.bAutoFlushIgnored = 0x0,
+  .rxConfig.bAutoFlushCrcErr = 0x0,
+  .rxConfig.bAutoFlushEmpty = 0x0,
+  .rxConfig.bIncludeLenByte = 0x0,
+  .rxConfig.bIncludeCrc = 0x0,
+  .rxConfig.bAppendRssi = 0x0,
+  .rxConfig.bAppendStatus = 0x0,
+  .rxConfig.bAppendTimestamp = 0x0,
+  .advConfig.advFilterPolicy = 0x0,
+  .advConfig.deviceAddrType = 0x0,
+  .advConfig.peerAddrType = 0x0,
+  .advConfig.bStrictLenFilter = 0x0,
+  .advConfig.rpaMode = 0x0,
+  .advLen = 0x18,
+  .scanRspLen = 0x00,
+  .pAdvData = 0,
+  .pScanRspData = 0,
+  .pDeviceAddress = 0,
+  .pWhiteList = 0,
+  .__dummy0 = 0x0000,
+  .__dummy1 = 0x00,
+  .endTrigger.triggerType = TRIG_NEVER,
+  .endTrigger.bEnaCmd = 0x0,
+  .endTrigger.triggerNo = 0x0,
+  .endTrigger.pastTrig = 0x0,
+  .endTime = 0x00000000,
+};
+/*---------------------------------------------------------------------------*/
+/* CMD_BLE_ADV_NC: BLE Non-Connectable Advertiser Command */
+rfc_CMD_BLE_ADV_NC_t rf_ble_cmd_ble_adv_nc =
+{
+  .commandNo = CMD_BLE_ADV_NC,
+  .status = IDLE,
+  .pNextOp = 0,
+  .startTime = 0x00000000,
+  .startTrigger.triggerType = TRIG_NOW,
+  .startTrigger.bEnaCmd = 0x0,
+  .startTrigger.triggerNo = 0x0,
+  .startTrigger.pastTrig = 0x0,
+  .condition.rule = COND_NEVER,
+  .condition.nSkip = 0x0,
+  .channel = 0x8C,
+  .whitening.init = 0x51,
+  .whitening.bOverride = 0x1,
+  .pParams = &rf_ble_adv_par,
+  .pOutput = 0,
+};
+/*---------------------------------------------------------------------------*/

arch/cpu/simplelink-cc13xx-cc26xx/rf-settings/cc13x0/ble-settings.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*---------------------------------------------------------------------------*/
+#ifndef BLE_SETTINGS_H_
+#define BLE_SETTINGS_H_
+/*---------------------------------------------------------------------------*/
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(driverlib/rf_mailbox.h)
+#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h)
+#include DeviceFamily_constructPath(driverlib/rf_ble_cmd.h)
+
+#include <ti/drivers/rf/RF.h>
+/*---------------------------------------------------------------------------*/
+/* TI-RTOS RF Mode Object */
+extern RF_Mode               rf_ble_mode;
+/*---------------------------------------------------------------------------*/
+/* RF Core API commands */
+extern rfc_CMD_RADIO_SETUP_t rf_ble_cmd_radio_setup;
+extern rfc_bleAdvPar_t       rf_ble_adv_par;
+extern rfc_CMD_BLE_ADV_NC_t  rf_ble_cmd_ble_adv_nc;
+/*---------------------------------------------------------------------------*/
+/* RF Core API Overrides */
+extern uint32_t              rf_ble_overrides[];
+/*---------------------------------------------------------------------------*/
+#endif /* BLE_SETTINGS_H_ */
+/*---------------------------------------------------------------------------*/

arch/cpu/simplelink-cc13xx-cc26xx/rf-settings/cc13x0/ble-tx-power.c

@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-rf-tx-power
+ * @{
+ *
+ * \file
+ *        Source file for BLE Beacon TX power tables for CC13x0.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+/*---------------------------------------------------------------------------*/
+#include "rf/tx-power.h"
+/*---------------------------------------------------------------------------*/
+/*
+ * TX Power table for CC1350
+ * The RF_TxPowerTable_DEFAULT_PA_ENTRY macro is defined in RF.h and requires the following arguments:
+ * RF_TxPowerTable_DEFAULT_PA_ENTRY(bias, gain, boost coefficient)
+ * See the Technical Reference Manual for further details about the "txPower" Command field.
+ * The PA settings require the CCFG_FORCE_VDDR_HH = 0 unless stated otherwise.
+ */
+tx_power_table_t rf_ble_tx_power_table_cc1350[] =
+{
+  { -21, RF_TxPowerTable_DEFAULT_PA_ENTRY( 8, 3, 1,  6) },
+  { -18, RF_TxPowerTable_DEFAULT_PA_ENTRY(11, 3, 1,  6) },
+  { -15, RF_TxPowerTable_DEFAULT_PA_ENTRY(14, 3, 1, 10) },
+  { -12, RF_TxPowerTable_DEFAULT_PA_ENTRY(20, 3, 1, 12) },
+  {  -9, RF_TxPowerTable_DEFAULT_PA_ENTRY(26, 3, 1, 14) },
+  {  -6, RF_TxPowerTable_DEFAULT_PA_ENTRY(35, 3, 1, 18) },
+  {  -3, RF_TxPowerTable_DEFAULT_PA_ENTRY(47, 3, 1, 22) },
+  {   0, RF_TxPowerTable_DEFAULT_PA_ENTRY(29, 0, 1, 45) },
+  {   1, RF_TxPowerTable_DEFAULT_PA_ENTRY(33, 0, 1, 49) },
+  {   2, RF_TxPowerTable_DEFAULT_PA_ENTRY(38, 0, 1, 55) },
+  {   3, RF_TxPowerTable_DEFAULT_PA_ENTRY(44, 0, 1, 63) },
+  {   4, RF_TxPowerTable_DEFAULT_PA_ENTRY(52, 0, 1, 59) },
+  {   5, RF_TxPowerTable_DEFAULT_PA_ENTRY(60, 0, 1, 47) },
+#if RF_TXPOWER_BOOST_MODE
+  /* This setting requires CCFG_FORCE_VDDR_HH = 1. */
+  {   6, RF_TxPowerTable_DEFAULT_PA_ENTRY(38, 0, 1, 49) },
+  /* This setting requires CCFG_FORCE_VDDR_HH = 1. */
+  {   7, RF_TxPowerTable_DEFAULT_PA_ENTRY(46, 0, 1, 59) },
+  /* This setting requires CCFG_FORCE_VDDR_HH = 1. */
+  {   8, RF_TxPowerTable_DEFAULT_PA_ENTRY(55, 0, 1, 51) },
+  /* This setting requires CCFG_FORCE_VDDR_HH = 1. */
+  {   9, RF_TxPowerTable_DEFAULT_PA_ENTRY(63, 0, 1, 30) },
+#endif
+  RF_TxPowerTable_TERMINATION_ENTRY
+};
+/*---------------------------------------------------------------------------*/
+tx_power_table_t rf_ble_tx_power_table_empty[] =
+{
+  RF_TxPowerTable_TERMINATION_ENTRY
+};
+/*---------------------------------------------------------------------------*/
+/* TX power table, based on which board is used. */
+#if defined(DEVICE_CC1350) || defined(DEVICE_CC1350_4)
+#define TX_POWER_TABLE  rf_ble_tx_power_table_cc1350
+
+#else
+#define TX_POWER_TABLE  rf_ble_tx_power_table_empty
+#endif
+
+/*
+ * Define symbols for both the TX power table and its size. The TX power
+ * table size is with one less entry by excluding the termination entry.
+ */
+tx_power_table_t *const ble_tx_power_table = TX_POWER_TABLE;
+const size_t ble_tx_power_table_size = (sizeof(TX_POWER_TABLE) / sizeof(TX_POWER_TABLE[0])) - 1;
+/*---------------------------------------------------------------------------*/

arch/cpu/simplelink-cc13xx-cc26xx/rf-settings/cc13x0/ieee-settings.c

@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*---------------------------------------------------------------------------*/
+/*
+ * Parameter summary
+ * IEEE Channel: 11
+ * Frequency: 2405 MHz
+ * SFD: 0
+ * Packet Data: 255
+ * Preamble (32 bit): 01010101...
+ * TX Power: 5 dBm (requires define CCFG_FORCE_VDDR_HH = 0 in ccfg.c,
+ *                  see CC13xx/CC26xx Technical Reference Manual)
+ */
+/*---------------------------------------------------------------------------*/
+#include "sys/cc.h"
+/*---------------------------------------------------------------------------*/
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(driverlib/rf_mailbox.h)
+#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h)
+/*
+ * rf_ieee_cmd.h must be included "locally" from the arch/cpu directory,
+ * as it isn't defined in CC13x0 driverlib.
+ */
+#include "driverlib/rf_ieee_cmd.h"
+
+#include <ti/drivers/rf/RF.h>
+/*---------------------------------------------------------------------------*/
+#include "ieee-settings.h"
+/*---------------------------------------------------------------------------*/
+/* TI-RTOS RF Mode Object */
+RF_Mode rf_ieee_mode =
+{
+  .rfMode = RF_MODE_IEEE_15_4,
+  .cpePatchFxn = 0,
+  .mcePatchFxn = 0,
+  .rfePatchFxn = 0,
+};
+/*---------------------------------------------------------------------------*/
+/*
+ * CMD_RADIO_SETUP must be configured with default TX power value
+ * in the .txPower field.
+ */
+#define DEFAULT_TX_POWER    0x9330 /* 5 dBm */
+/*---------------------------------------------------------------------------*/
+/* Overrides for CMD_RADIO_SETUP */
+uint32_t rf_ieee_overrides[] CC_ALIGN(4) =
+{
+                                  /* override_synth_ieee_15_4.xml */
+  HW_REG_OVERRIDE(0x4038,0x0035), /* Synth: Set recommended RTRIM to 5 */
+  (uint32_t)0x000784A3,           /* Synth: Set Fref to 3.43 MHz */
+  (uint32_t)0xA47E0583,           /* Synth: Set loop bandwidth after lock to 80 kHz */
+  (uint32_t)0xEAE00603,           /* Synth: Set loop bandwidth after lock to 80 kHz */
+  (uint32_t)0x00010623,           /* Synth: Set loop bandwidth after lock to 80 kHz */
+  HW32_ARRAY_OVERRIDE(0x405C,1),  /* Synth: Configure PLL bias */
+  (uint32_t)0x1801F800,           /* Synth: Configure PLL bias */
+  HW32_ARRAY_OVERRIDE(0x402C,1),  /* Synth: Configure PLL latency */
+  (uint32_t)0x00608402,           /* Synth: Configure PLL latency */
+  (uint32_t)0x02010403,           /* Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering */
+  HW32_ARRAY_OVERRIDE(0x4034,1),  /* Synth: Configure extra PLL filtering */
+  (uint32_t)0x177F0408,           /* Synth: Configure extra PLL filtering */
+  (uint32_t)0x38000463,           /* Synth: Configure extra PLL filtering */
+                                  /* override_phy_ieee_15_4.xml */
+  (uint32_t)0x05000243,           /* Synth: Increase synth programming timeout */
+  (uint32_t)0x002082C3,           /* Rx: Adjust Rx FIFO threshold to avoid overflow */
+                                  /* override_frontend_id.xml */
+  (uint32_t)0x000288A3,           /* Rx: Set RSSI offset to adjust reported RSSI by -2 dB */
+  (uint32_t)0x000F8883,           /* Rx: Configure LNA bias current trim offset */
+  HW_REG_OVERRIDE(0x50DC,0x002B), /* Rx: Adjust AGC DC filter */
+  (uint32_t)0xFFFFFFFF,
+};
+/*---------------------------------------------------------------------------*/
+/* CMD_RADIO_SETUP: Radio Setup Command for Pre-Defined Schemes */
+rfc_CMD_RADIO_SETUP_t rf_cmd_ieee_radio_setup =
+{
+  .commandNo = CMD_RADIO_SETUP,
+  .status = IDLE,
+  .pNextOp = 0,
+  .startTime = 0x00000000,
+  .startTrigger.triggerType = TRIG_NOW,
+  .startTrigger.bEnaCmd = 0x0,
+  .startTrigger.triggerNo = 0x0,
+  .startTrigger.pastTrig = 0x0,
+  .condition.rule = COND_NEVER,
+  .condition.nSkip = 0x0,
+  .mode = 0x01,
+  .config.frontEndMode = 0x0,
+  .config.biasMode = 0x0,
+  .config.analogCfgMode = 0x0,
+  .config.bNoFsPowerUp = 0x0,
+  .txPower = DEFAULT_TX_POWER, /* 5 dBm default */
+  .pRegOverride = rf_ieee_overrides,
+};
+/*---------------------------------------------------------------------------*/
+/* CMD_FS: Frequency Synthesizer Programming Command */
+rfc_CMD_FS_t rf_cmd_ieee_fs =
+{
+  .commandNo = CMD_FS,
+  .status = IDLE,
+  .pNextOp = 0,
+  .startTime = 0x00000000,
+  .startTrigger.triggerType = TRIG_NOW,
+  .startTrigger.bEnaCmd = 0x0,
+  .startTrigger.triggerNo = 0x0,
+  .startTrigger.pastTrig = 0x0,
+  .condition.rule = COND_NEVER,
+  .condition.nSkip = 0x0,
+  .frequency = 0x0965, /* set by driver */
+  .fractFreq = 0x0000, /* set by driver */
+  .synthConf.bTxMode = 0x1,
+  .synthConf.refFreq = 0x0,
+  .__dummy0 = 0x00,
+  .__dummy1 = 0x00,
+  .__dummy2 = 0x00,
+  .__dummy3 = 0x0000,
+};
+/*---------------------------------------------------------------------------*/
+/* CMD_IEEE_TX: IEEE 802.15.4 Transmit Command */
+rfc_CMD_IEEE_TX_t rf_cmd_ieee_tx =
+{
+  .commandNo = CMD_IEEE_TX,
+  .status = IDLE,
+  .pNextOp = 0,
+  .startTime = 0x00000000,
+  .startTrigger.triggerType = TRIG_NOW,
+  .startTrigger.bEnaCmd = 0x0,
+  .startTrigger.triggerNo = 0x0,
+  .startTrigger.pastTrig = 0x0,
+  .condition.rule = COND_NEVER,
+  .condition.nSkip = 0x0,
+  .txOpt.bIncludePhyHdr = 0x0,
+  .txOpt.bIncludeCrc = 0x0,
+  .txOpt.payloadLenMsb = 0x0,
+  .payloadLen = 0x0, /* set by driver */
+  .pPayload = 0, /* set by driver */
+  .timeStamp = 0x00000000,
+};
+/*---------------------------------------------------------------------------*/
+/* CMD_IEEE_RX: IEEE 802.15.4 Receive Command */
+rfc_CMD_IEEE_RX_t rf_cmd_ieee_rx =
+{
+  .commandNo = CMD_IEEE_RX,
+  .status = IDLE,
+  .pNextOp = 0,
+  .startTime = 0x00000000,
+  .startTrigger.triggerType = TRIG_NOW,
+  .startTrigger.bEnaCmd = 0x0,
+  .startTrigger.triggerNo = 0x0,
+  .startTrigger.pastTrig = 0x0,
+  .condition.rule = COND_NEVER,
+  .condition.nSkip = 0x0,
+  .channel = 0x00, /* set by driver */
+  .rxConfig.bAutoFlushCrc = 0x1,
+  .rxConfig.bAutoFlushIgn = 0x1,
+  .rxConfig.bIncludePhyHdr = 0x0,
+  .rxConfig.bIncludeCrc = 0x1,
+  .rxConfig.bAppendRssi = 0x1,
+  .rxConfig.bAppendCorrCrc = 0x1,
+  .rxConfig.bAppendSrcInd = 0x0,
+  .rxConfig.bAppendTimestamp = 0x1,
+  .pRxQ = 0, /* set by driver */
+  .pOutput = 0, /* set by driver */
+  .frameFiltOpt.frameFiltEn = 0x0, /* set by driver */
+  .frameFiltOpt.frameFiltStop = 0x1,
+  .frameFiltOpt.autoAckEn = 0x0, /* set by driver */
+  .frameFiltOpt.slottedAckEn = 0x0,
+  .frameFiltOpt.autoPendEn = 0x0,
+  .frameFiltOpt.defaultPend = 0x0,
+  .frameFiltOpt.bPendDataReqOnly = 0x0,
+  .frameFiltOpt.bPanCoord = 0x0,
+  .frameFiltOpt.maxFrameVersion = 0x2,
+  .frameFiltOpt.fcfReservedMask = 0x0,
+  .frameFiltOpt.modifyFtFilter = 0x0,
+  .frameFiltOpt.bStrictLenFilter = 0x0,
+  .frameTypes.bAcceptFt0Beacon = 0x1,
+  .frameTypes.bAcceptFt1Data = 0x1,
+  .frameTypes.bAcceptFt2Ack = 0x1,
+  .frameTypes.bAcceptFt3MacCmd = 0x1,
+  .frameTypes.bAcceptFt4Reserved = 0x1,
+  .frameTypes.bAcceptFt5Reserved = 0x1,
+  .frameTypes.bAcceptFt6Reserved = 0x1,
+  .frameTypes.bAcceptFt7Reserved = 0x1,
+  .ccaOpt.ccaEnEnergy = 0x1,
+  .ccaOpt.ccaEnCorr = 0x1,
+  .ccaOpt.ccaEnSync = 0x1,
+  .ccaOpt.ccaCorrOp = 0x1,
+  .ccaOpt.ccaSyncOp = 0x0,
+  .ccaOpt.ccaCorrThr = 0x3,
+  .ccaRssiThr = 0x0, /* set by driver */
+  .__dummy0 = 0x00,
+  .numExtEntries = 0x00,
+  .numShortEntries = 0x00,
+  .pExtEntryList = 0,
+  .pShortEntryList = 0,
+  .localExtAddr = 0x0, /* set by driver */
+  .localShortAddr = 0x0, /* set by driver */
+  .localPanID = 0x0000,
+  .__dummy1 = 0x000000,
+  .endTrigger.triggerType = TRIG_NEVER,
+  .endTrigger.bEnaCmd = 0x0,
+  .endTrigger.triggerNo = 0x0,
+  .endTrigger.pastTrig = 0x0,
+  .endTime = 0x00000000,
+};
+/*---------------------------------------------------------------------------*/
+/* CMD_IEEE_RX_ACK: IEEE 802.15.4 Receive ACK Command */
+rfc_CMD_IEEE_RX_ACK_t rf_cmd_ieee_rx_ack =
+{
+  .commandNo = CMD_IEEE_RX_ACK,
+  .status = IDLE,
+  .pNextOp = 0,
+  .startTime = 0x00000000,
+  .startTrigger.triggerType = TRIG_NOW,
+  .startTrigger.bEnaCmd = 0x0,
+  .startTrigger.triggerNo = 0x0,
+  .startTrigger.pastTrig = 0x0,
+  .condition.rule = COND_NEVER,
+  .condition.nSkip = 0x0,
+  .seqNo = 0x0,
+  .endTrigger.triggerType = TRIG_NEVER,
+  .endTrigger.bEnaCmd = 0x0,
+  .endTrigger.triggerNo = 0x0,
+  .endTrigger.pastTrig = 0x0,
+  .endTime = 0x00000000,
+};
+/*---------------------------------------------------------------------------*/

arch/cpu/simplelink-cc13xx-cc26xx/rf-settings/cc13x0/ieee-settings.h

@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*---------------------------------------------------------------------------*/
+#ifndef IEEE_SETTINGS_H_
+#define IEEE_SETTINGS_H_
+/*---------------------------------------------------------------------------*/
+#include "contiki-conf.h"
+/*---------------------------------------------------------------------------*/
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(driverlib/rf_mailbox.h)
+#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h)
+/*
+ * These two headers must be included "locally" from the arch/cpu directory,
+ * as they aren't defined in CC13x0 driverlib.
+ */
+#include "driverlib/rf_ieee_cmd.h"
+#include "driverlib/rf_ieee_mailbox.h"
+
+#include <ti/drivers/rf/RF.h>
+/*---------------------------------------------------------------------------*/
+/* TI-RTOS RF Mode Object */
+extern RF_Mode               rf_ieee_mode;
+/*---------------------------------------------------------------------------*/
+/* RF Core API commands */
+extern rfc_CMD_RADIO_SETUP_t rf_cmd_ieee_radio_setup;
+extern rfc_CMD_FS_t          rf_cmd_ieee_fs;
+extern rfc_CMD_IEEE_TX_t     rf_cmd_ieee_tx;
+extern rfc_CMD_IEEE_RX_t     rf_cmd_ieee_rx;
+extern rfc_CMD_IEEE_RX_ACK_t rf_cmd_ieee_rx_ack;
+/*---------------------------------------------------------------------------*/
+/* RF Core API Overrides */
+extern uint32_t              rf_ieee_overrides[];
+/*---------------------------------------------------------------------------*/
+#endif /* IEEE_SETTINGS_H_ */
+/*---------------------------------------------------------------------------*/

arch/cpu/simplelink-cc13xx-cc26xx/rf-settings/cc13x0/ieee-tx-power.c

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \addtogroup cc13xx-cc26xx-rf-tx-power
+ * @{
+ *
+ * \file
+ *        Source file for IEEE-mode TX power tables for CC13x0.
+ * \author
+ *        Edvard Pettersen <e.pettersen@ti.com>
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki.h"
+/*---------------------------------------------------------------------------*/
+#include "rf/tx-power.h"
+/*---------------------------------------------------------------------------*/
+/*
+ * TX Power table for CC1350
+ * The RF_TxPowerTable_DEFAULT_PA_ENTRY macro is defined in RF.h and requires the following arguments:
+ * RF_TxPowerTable_DEFAULT_PA_ENTRY(bias, gain, boost coefficient)
+ * See the Technical Reference Manual for further details about the "txPower" Command field.
+ * The PA settings require the CCFG_FORCE_VDDR_HH = 0 unless stated otherwise.
+ */
+tx_power_table_t rf_ieee_tx_power_table_cc1350[] =
+{
+  { -21, RF_TxPowerTable_DEFAULT_PA_ENTRY( 7, 3, 0,  6) },
+  { -18, RF_TxPowerTable_DEFAULT_PA_ENTRY( 9, 3, 0,  6) },
+  { -15, RF_TxPowerTable_DEFAULT_PA_ENTRY(11, 3, 0,  6) },
+  { -12, RF_TxPowerTable_DEFAULT_PA_ENTRY(11, 1, 0, 10) },
+  {  -9, RF_TxPowerTable_DEFAULT_PA_ENTRY(14, 1, 1, 12) },
+  {  -6, RF_TxPowerTable_DEFAULT_PA_ENTRY(18, 1, 1, 14) },
+  {  -3, RF_TxPowerTable_DEFAULT_PA_ENTRY(24, 1, 1, 18) },
+  {   0, RF_TxPowerTable_DEFAULT_PA_ENTRY(33, 1, 1, 24) },
+  {   1, RF_TxPowerTable_DEFAULT_PA_ENTRY(20, 0, 0, 33) },
+  {   2, RF_TxPowerTable_DEFAULT_PA_ENTRY(24, 0, 0, 39) },
+  {   3, RF_TxPowerTable_DEFAULT_PA_ENTRY(28, 0, 0, 45) },
+  {   4, RF_TxPowerTable_DEFAULT_PA_ENTRY(36, 0, 1, 73) },
+  {   5, RF_TxPowerTable_DEFAULT_PA_ENTRY(48, 0, 1, 73) },
+  RF_TxPowerTable_TERMINATION_ENTRY
+};
+/*---------------------------------------------------------------------------*/
+tx_power_table_t rf_ieee_tx_power_table_empty[] =
+{
+  RF_TxPowerTable_TERMINATION_ENTRY
+};
+/*---------------------------------------------------------------------------*/
+/* Only define the symbols if Prop-mode is selected */
+#if (RF_MODE == RF_MODE_2_4_GHZ)
+/*---------------------------------------------------------------------------*/
+/* TX power table, based on which board is used. */
+#if defined(DEVICE_CC1350) || defined(DEVICE_CC1350_4)
+#define TX_POWER_TABLE  rf_ieee_tx_power_table_cc1350
+
+#else
+#define TX_POWER_TABLE  rf_ieee_tx_power_table_empty
+#endif
+
+/*
+ * Define symbols for both the TX power table and its size. The TX power
+ * table size is with one less entry by excluding the termination entry.
+ */
+tx_power_table_t *const rf_tx_power_table = TX_POWER_TABLE;
+const size_t rf_tx_power_table_size = (sizeof(TX_POWER_TABLE) / sizeof(TX_POWER_TABLE[0])) - 1;
+/*---------------------------------------------------------------------------*/
+#endif /* RF_MODE */
+/*---------------------------------------------------------------------------*/

arch/cpu/simplelink-cc13xx-cc26xx/rf-settings/cc13x0/prop-settings.c

@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated - http://www.ti.com/
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*---------------------------------------------------------------------------*/
+/*
+ * Parameter summary
+ * Address: 0
+ * Address0: 0xAA
+ * Address1: 0xBB
+ * Frequency: 868.00000 MHz
+ * Data Format: Serial mode disable
+ * Deviation: 25.000 kHz
+ * pktLen: 30
+ * 802.15.4g Mode: 0
+ * Select bit order to transmit PSDU octets:: 1
+ * Packet Length Config: Variable
+ * Max Packet Length: 255
+ * Packet Length: 0
+ * Packet Data: 255
+ * RX Filter BW: 98 kHz
+ * Symbol Rate: 50.00000 kBaud
+ * Sync Word Length: 24 Bits
+ * TX Power: 14 dBm (requires define CCFG_FORCE_VDDR_HH = 1 in ccfg.c,
+ *                   see CC13xx/CC26xx Technical Reference Manual)
+ * Whitening: Dynamically IEEE 802.15.4g compatible whitener and 16/32-bit CRC
+ */
+/*---------------------------------------------------------------------------*/
+#include "contiki-conf.h"
+#include "sys/cc.h"
+/*---------------------------------------------------------------------------*/
+#include <ti/devices/DeviceFamily.h>
+#include DeviceFamily_constructPath(driverlib/rf_mailbox.h)
+#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h)
+#include DeviceFamily_constructPath(driverlib/rf_prop_cmd.h)
+#include DeviceFamily_constructPath(rf_patches/rf_patch_cpe_genfsk.h)
+#include DeviceFamily_constructPath(rf_patches/rf_patch_rfe_genfsk.h)
+
+#include <ti/drivers/rf/RF.h>
+/*---------------------------------------------------------------------------*/
+#include "prop-settings.h"
+/*---------------------------------------------------------------------------*/
+/* TI-RTOS RF Mode Object */
+RF_Mode rf_prop_mode =
+{
+  .rfMode = RF_MODE_PROPRIETARY_SUB_1,
+  .cpePatchFxn = &rf_patch_cpe_genfsk,
+  .mcePatchFxn = 0,
+  .rfePatchFxn = &rf_patch_rfe_genfsk,
+};
+/*---------------------------------------------------------------------------*/
+#if defined(DEVICE_CC1310)
+/*
+ * CMD_PROP_RADIO_DIV_SETUP must be configured with default TX power value
+ * in the .txPower field. This depends on whether RF_CONF_TXPOWER_BOOST_MODE
+ * is configured or not.
+ */
+#if RF_CONF_TXPOWER_BOOST_MODE
+#define DEFAULT_TX_POWER    0xA73F /* 14 dBm */
+#else
+#define DEFAULT_TX_POWER    0xA63F /* 12.5 dBm (rounded up to 13 dBm) */
+#endif
+
+#endif /* defined(DEVICE_CC1310) */
+/*---------------------------------------------------------------------------*/
+#if defined(DEVICE_CC1350)
+/*
+ * CMD_PROP_RADIO_DIV_SETUP must be configured with default TX power value
+ * in the .txPower field. This depends on whether RF_CONF_TXPOWER_BOOST_MODE
+ * is configured or not.
+ */
+#if RF_CONF_TXPOWER_BOOST_MODE
+#define DEFAULT_TX_POWER    0xAB3F /* 14 dBm */
+#else
+#define DEFAULT_TX_POWER    0xBC2B /* 12 dBm */
+#endif
+
+#endif /* defined(DEVICE_CC1350) */
+    /*---------------------------------------------------------------------------*/
+#if defined(DEVICE_CC1350_4)
+/*
+ * CMD_PROP_RADIO_DIV_SETUP must be configured with default TX power value
+ * in the .txPower field. This depends on whether RF_CONF_TXPOWER_BOOST_MODE
+ * is configured or not.
+ */
+#if RF_CONF_TXPOWER_BOOST_MODE
+#define DEFAULT_TX_POWER    0x913F /* 15 dBm */
+#else
+#define DEFAULT_TX_POWER    0xB83F /* 13.7 dBm (rounded up to 14 dBm) */
+#endif
+
+#endif /* defined(DEVICE_CC1350_4) */
+/*---------------------------------------------------------------------------*/
+/* Overrides for CMD_PROP_RADIO_DIV_SETUP */
+uint32_t rf_prop_overrides[] CC_ALIGN(4) =
+{
+                                      /* override_use_patch_prop_genfsk.xml */
+  MCE_RFE_OVERRIDE(0,4,0,1,0,0),      /* PHY: Use MCE ROM bank 4, RFE RAM patch */
+                                      /* override_synth_prop_863_930_div5.xml */
+  HW_REG_OVERRIDE(0x4038,0x0037),     /* Synth: Set recommended RTRIM to 7 */
+  (uint32_t)0x000684A3,               /* Synth: Set Fref to 4 MHz */
+  HW_REG_OVERRIDE(0x4020,0x7F00),     /* Synth: Configure fine calibration setting */
+  HW_REG_OVERRIDE(0x4064,0x0040),     /* Synth: Configure fine calibration setting */
+  (uint32_t)0xB1070503,               /* Synth: Configure fine calibration setting */
+  (uint32_t)0x05330523,               /* Synth: Configure fine calibration setting */
+  (uint32_t)0x0A480583,               /* Synth: Set loop bandwidth after lock to 20 kHz */
+  (uint32_t)0x7AB80603,               /* Synth: Set loop bandwidth after lock to 20 kHz */
+                                      /* Synth: Configure VCO LDO */
+  ADI_REG_OVERRIDE(1,4,0x9F),         /* (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference) */
+  ADI_HALFREG_OVERRIDE(1,7,0x4,0x4),  /* Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1) */
+  (uint32_t)0x02010403,               /* Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering */
+  (uint32_t)0x00108463,               /* Synth: Configure extra PLL filtering */
+  (uint32_t)0x04B00243,               /* Synth: Increase synth programming timeout (0x04B0 RAT ticks = 300 us) */
+                                      /* override_phy_rx_aaf_bw_0xd.xml */
+                                      /* Rx: Set anti-aliasing filter bandwidth to 0xD */
+  ADI_HALFREG_OVERRIDE(0,61,0xF,0xD), /* (in ADI0, set IFAMPCTL3[7:4]=0xD) */
+                                      /* override_phy_gfsk_rx.xml */
+  (uint32_t)0x00038883,               /* Rx: Set LNA bias current trim offset to 3 */
+  HW_REG_OVERRIDE(0x6084,0x35F1),     /* Rx: Freeze RSSI on sync found event */
+                                      /* override_phy_gfsk_pa_ramp_agc_reflevel_0x1a.xml */
+                                      /* Tx: Configure PA ramping setting (0x41). */
+  HW_REG_OVERRIDE(0x6088,0x411A),     /* Rx: Set AGC reference level to 0x1A. */
+  HW_REG_OVERRIDE(0x608C,0x8213),     /* Tx: Configure PA ramping setting */
+                                      /* override_crc_ieee_802_15_4.xml */
+                                      /* IEEE 802.15.4g: Fix incorrect initialization value for */
+  (uint32_t)0x00000943,               /* CRC-16 calculation (see TRM section 23.7.5.2.1) */
+                                      /* IEEE 802.15.4g: Fix incorrect initialization value for */
+  (uint32_t)0x00000963,               /* CRC-16 calculation (see TRM section 23.7.5.2.1) */
+#if defined(DEVICE_CC1350_4)
+                                      /* override_phy_rx_rssi_offset_neg2db.xml */
+  (uint32_t)0x000288A3,               /* Rx: Set RSSI offset to adjust reported RSSI by -2 dB */
+#else
+                                      /* override_phy_rx_rssi_offset_5db.xml */
+  (uint32_t)0x00FB88A3,               /* Rx: Set RSSI offset to adjust reported RSSI by +5 dB */
+#endif
+                                      /* TX power override */
+#if RF_CONF_TXPOWER_BOOST_MODE
+  ADI_REG_OVERRIDE(0,12,0xF8),        /* Tx: Set PA trim to max (in ADI0, set PACTL0=0xF8) */
+#endif
+  (uint32_t)0xFFFFFFFF,
+};
+/*---------------------------------------------------------------------------*/
+/* CMD_PROP_RADIO_DIV_SETUP */
+/* Proprietary Mode Radio Setup Command for All Frequency Bands */
+rfc_CMD_PROP_RADIO_DIV_SETUP_t rf_cmd_prop_radio_div_setup =
+{
+  .commandNo = CMD_PROP_RADIO_DIV_SETUP,
+  .status = IDLE,
+  .pNextOp = 0,
+  .startTime = 0x00000000,
+  .startTrigger.triggerType = TRIG_NOW,
+  .startTrigger.bEnaCmd = 0x0,
+  .startTrigger.triggerNo = 0x0,
+  .startTrigger.pastTrig = 0x0,
+  .condition.rule = COND_NEVER,
+  .condition.nSkip = 0x0,
+  .modulation.modType = 0x1,
+  .modulation.deviation = 0x64,
+  .symbolRate.preScale = 0xF,
+  .symbolRate.rateWord = 0x8000,
+  .rxBw = 0x24,
+  .preamConf.nPreamBytes = 0x7,
+  .preamConf.preamMode = 0x0,
+  .formatConf.nSwBits = 0x18,
+  .formatConf.bBitReversal = 0x0,
+  .formatConf.bMsbFirst = 0x1,
+  .formatConf.fecMode = 0x0,
+  .formatConf.whitenMode = 0x7,
+  .config.frontEndMode = 0x0, /* set by driver */
+  .config.biasMode = 0x0, /* set by driver */
+  .config.analogCfgMode = 0x0,
+  .config.bNoFsPowerUp = 0x0,
+  .txPower = DEFAULT_TX_POWER,
+  .pRegOverride = rf_prop_overrides,
+  .centerFreq = 0x0364, /* set by driver */
+  .intFreq = 0x8000, /* set by driver */
+  .loDivider = 0x05, /* set by driver */
+};
+/*---------------------------------------------------------------------------*/
+/* CMD_FS */
+/* Frequency Synthesizer Programming Command */
+rfc_CMD_FS_t rf_cmd_prop_fs =
+{
+  .commandNo = CMD_FS,
+  .status = IDLE,
+  .pNextOp = 0,
+  .startTime = 0x00000000,
+  .startTrigger.triggerType = TRIG_NOW,
+  .startTrigger.bEnaCmd = 0x0,
+  .startTrigger.triggerNo = 0x0,
+  .startTrigger.pastTrig = 0x0,
+  .condition.rule = COND_NEVER,
+  .condition.nSkip = 0x0,
+  .frequency = 0x0364, /* set by driver */
+  .fractFreq = 0x0000, /* set by driver */
+  .synthConf.bTxMode = 0x0,
+  .synthConf.refFreq = 0x0,
+  .__dummy0 = 0x00,
+  .__dummy1 = 0x00,
+  .__dummy2 = 0x00,
+  .__dummy3 = 0x0000,
+};
+/*---------------------------------------------------------------------------*/
+/* CMD_PROP_TX_ADV */
+/* Proprietary Mode Advanced Transmit Command */
+rfc_CMD_PROP_TX_ADV_t rf_cmd_prop_tx_adv =
+{
+  .commandNo = CMD_PROP_TX_ADV,
+  .status = IDLE,
+  .pNextOp = 0,
+  .startTime = 0x00000000,
+  .startTrigger.triggerType = TRIG_NOW,
+  .startTrigger.bEnaCmd = 0x0,
+  .startTrigger.triggerNo = 0x0,
+  .startTrigger.pastTrig = 0x0,
+  .condition.rule = COND_NEVER,
+  .condition.nSkip = 0x0,
+  .pktConf.bFsOff = 0x0,
+  .pktConf.bUseCrc = 0x1,
+  .pktConf.bCrcIncSw = 0x0,
+  .pktConf.bCrcIncHdr = 0x0,
+  .numHdrBits = 0x10,
+  .pktLen = 0x0, /* set by driver */
+  .startConf.bExtTxTrig = 0x0,
+  .startConf.inputMode = 0x0,
+  .startConf.source = 0x0,
+  .preTrigger.triggerType = TRIG_REL_START,
+  .preTrigger.bEnaCmd = 0x0,
+  .preTrigger.triggerNo = 0x0,
+  .preTrigger.pastTrig = 0x1,
+  .preTime = 0x00000000,
+  .syncWord = 0x0055904E,
+  .pPkt = 0, /* set by driver */
+};
+/*---------------------------------------------------------------------------*/
+/* CMD_PROP_RX_ADV */
+/* Proprietary Mode Advanced Receive Command */
+rfc_CMD_PROP_RX_ADV_t rf_cmd_prop_rx_adv =
+{
+  .commandNo = CMD_PROP_RX_ADV,
+  .status = IDLE,
+  .pNextOp = 0,
+  .startTime = 0x00000000,
+  .startTrigger.triggerType = TRIG_NOW,
+  .startTrigger.bEnaCmd = 0x0,
+  .startTrigger.triggerNo = 0x0,
+  .startTrigger.pastTrig = 0x0,
+  .condition.rule = COND_NEVER,
+  .condition.nSkip = 0x0,
+  .pktConf.bFsOff = 0x0,
+  .pktConf.bRepeatOk = 0x1,
+  .pktConf.bRepeatNok = 0x1,
+  .pktConf.bUseCrc = 0x1,
+  .pktConf.bCrcIncSw = 0x0,
+  .pktConf.bCrcIncHdr = 0x0,
+  .pktConf.endType = 0x0,
+  .pktConf.filterOp = 0x1,
+  .rxConf.bAutoFlushIgnored = 0x1,
+  .rxConf.bAutoFlushCrcErr = 0x1,
+  .rxConf.bIncludeHdr = 0x0,
+  .rxConf.bIncludeCrc = 0x0,
+  .rxConf.bAppendRssi = 0x1,
+  .rxConf.bAppendTimestamp = 0x0,
+  .rxConf.bAppendStatus = 0x1,
+  .syncWord0 = 0x0055904E,
+  .syncWord1 = 0x00000000,
+  .maxPktLen = 0x0, /* set by driver */
+  .hdrConf.numHdrBits = 0x10,
+  .hdrConf.lenPos = 0x0,
+  .hdrConf.numLenBits = 0x0B,
+  .addrConf.addrType = 0x0,
+  .addrConf.addrSize = 0x0,
+  .addrConf.addrPos = 0x0,
+  .addrConf.numAddr = 0x0,
+  .lenOffset = 0xFC,
+  .endTrigger.triggerType = TRIG_NEVER,
+  .endTrigger.bEnaCmd = 0x0,
+  .endTrigger.triggerNo = 0x0,
+  .endTrigger.pastTrig = 0x0,
+  .endTime = 0x00000000,
+  .pAddr = 0, /* set by driver */
+  .pQueue = 0, /* set by driver */
+  .pOutput = 0, /* set by driver */
+};
+/*---------------------------------------------------------------------------*/