Implement the GPIO HAL for the CC2538
This commit is contained in:
George Oikonomou
parent
f1d1932c5c
commit
ab7d7cd9f4
@ -64,6 +64,8 @@
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/* Path to headers with implementation of mutexes and memory barriers */
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#define MUTEX_CONF_ARCH_HEADER_PATH "mutex-cortex.h"
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#define MEMORY_BARRIER_CONF_ARCH_HEADER_PATH "memory-barrier-cortex.h"
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#define GPIO_HAL_CONF_ARCH_HDR_PATH "dev/gpio-hal-arch.h"
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/*---------------------------------------------------------------------------*/
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#endif /* CC2538_DEF_H_ */
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/*---------------------------------------------------------------------------*/
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196
arch/cpu/cc2538/dev/gpio-hal-arch.c
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196
arch/cpu/cc2538/dev/gpio-hal-arch.c
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@ -0,0 +1,196 @@
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/*
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* Copyright (c) 2017, George Oikonomou - http://www.spd.gr
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*---------------------------------------------------------------------------*/
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/**
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* \addtogroup cc2538-gpio-hal
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* @{
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*
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* \file
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* Implementation file for the CC2538 GPIO HAL functions
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*/
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/*---------------------------------------------------------------------------*/
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#include "contiki.h"
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#include "dev/gpio-hal.h"
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#include "dev/gpio.h"
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#include "dev/ioc.h"
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#include <stdint.h>
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/*---------------------------------------------------------------------------*/
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void
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gpio_hal_arch_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg)
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{
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uint8_t port, pin_num, pin_mask;
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uint32_t port_base;
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port = PIN_TO_PORT(pin);
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port_base = PIN_TO_PORT_BASE(pin);
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pin_num = pin % 8;
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pin_mask = GPIO_PIN_MASK(pin_num);
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gpio_hal_pin_cfg_t tmp;
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tmp = cfg & GPIO_HAL_PIN_CFG_EDGE_BOTH;
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if(tmp == GPIO_HAL_PIN_CFG_EDGE_NONE) {
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GPIO_DISABLE_INTERRUPT(port_base, pin_mask);
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} else if(tmp == GPIO_HAL_PIN_CFG_EDGE_RISING) {
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GPIO_DETECT_EDGE(port_base, pin_mask);
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GPIO_TRIGGER_SINGLE_EDGE(port_base, pin_mask);
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GPIO_DETECT_RISING(port_base, pin_mask);
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} else if(tmp == GPIO_HAL_PIN_CFG_EDGE_FALLING) {
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GPIO_DETECT_EDGE(port_base, pin_mask);
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GPIO_TRIGGER_SINGLE_EDGE(port_base, pin_mask);
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GPIO_DETECT_FALLING(port_base, pin_mask);
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} else if(tmp == GPIO_HAL_PIN_CFG_EDGE_BOTH) {
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GPIO_DETECT_EDGE(port_base, pin_mask);
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GPIO_TRIGGER_BOTH_EDGES(port_base, pin_mask);
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}
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tmp = cfg & GPIO_HAL_PIN_CFG_PULL_MASK;
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if(tmp == GPIO_HAL_PIN_CFG_PULL_NONE) {
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ioc_set_over(port, pin_num, IOC_OVERRIDE_DIS);
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} else if(tmp == GPIO_HAL_PIN_CFG_PULL_DOWN) {
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ioc_set_over(port, pin_num, IOC_OVERRIDE_PDE);
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} else if(tmp == GPIO_HAL_PIN_CFG_PULL_UP) {
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ioc_set_over(port, pin_num, IOC_OVERRIDE_PUE);
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}
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tmp = cfg & GPIO_HAL_PIN_CFG_INT_MASK;
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if(tmp == GPIO_HAL_PIN_CFG_INT_DISABLE) {
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GPIO_DISABLE_INTERRUPT(port_base, pin_mask);
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} else if(tmp == GPIO_HAL_PIN_CFG_INT_ENABLE) {
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GPIO_ENABLE_INTERRUPT(port_base, pin_mask);
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}
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GPIO_SOFTWARE_CONTROL(port_base, pin_mask);
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}
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/*---------------------------------------------------------------------------*/
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gpio_hal_pin_cfg_t
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gpio_hal_arch_pin_cfg_get(gpio_hal_pin_t pin)
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{
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uint8_t port, pin_num, pin_mask;
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uint32_t port_base;
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gpio_hal_pin_cfg_t cfg;
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uint32_t tmp;
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port = PIN_TO_PORT(pin);
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port_base = PIN_TO_PORT_BASE(pin);
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pin_num = pin % 8;
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pin_mask = GPIO_PIN_MASK(pin_num);
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cfg = 0;
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/* Pull */
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tmp = ioc_get_over(port, pin_num);
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if(tmp == IOC_OVERRIDE_PUE) {
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cfg |= GPIO_HAL_PIN_CFG_PULL_UP;
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} else if(tmp == IOC_OVERRIDE_PDE) {
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cfg |= GPIO_HAL_PIN_CFG_PULL_DOWN;
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} else {
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cfg |= GPIO_HAL_PIN_CFG_PULL_NONE;
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}
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/* Interrupt enable/disable */
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tmp = REG((port_base) + GPIO_IE) & pin_mask;
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if(tmp == 0) {
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cfg |= GPIO_HAL_PIN_CFG_INT_DISABLE;
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} else {
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cfg |= GPIO_HAL_PIN_CFG_INT_ENABLE;
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}
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/* Edge detection */
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if(REG((port_base) + GPIO_IS) & pin_mask) {
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cfg |= GPIO_HAL_PIN_CFG_EDGE_NONE;
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} else {
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if(REG((port_base) + GPIO_IBE) & pin_mask) {
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cfg |= GPIO_HAL_PIN_CFG_EDGE_BOTH;
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} else {
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if(REG((port_base) + GPIO_IEV) & pin_mask) {
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cfg |= GPIO_HAL_PIN_CFG_EDGE_RISING;
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} else {
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cfg |= GPIO_HAL_PIN_CFG_EDGE_FALLING;
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}
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}
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}
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return cfg;
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}
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/*---------------------------------------------------------------------------*/
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void
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gpio_hal_arch_write_pin(gpio_hal_pin_t pin, uint8_t value)
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{
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if(value == 1) {
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gpio_hal_arch_set_pin(pin);
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return;
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}
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gpio_hal_arch_clear_pin(pin);
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}
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/*---------------------------------------------------------------------------*/
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void
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gpio_hal_arch_set_pins(gpio_hal_pin_mask_t pins)
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{
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GPIO_SET_PIN(GPIO_A_BASE, pins & 0xFF);
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GPIO_SET_PIN(GPIO_B_BASE, (pins >> 8) & 0xFF);
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GPIO_SET_PIN(GPIO_C_BASE, (pins >> 16) & 0xFF);
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GPIO_SET_PIN(GPIO_D_BASE, (pins >> 24) & 0xFF);
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}
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/*---------------------------------------------------------------------------*/
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void
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gpio_hal_arch_clear_pins(gpio_hal_pin_mask_t pins)
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{
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GPIO_CLR_PIN(GPIO_A_BASE, pins & 0xFF);
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GPIO_CLR_PIN(GPIO_B_BASE, (pins >> 8) & 0xFF);
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GPIO_CLR_PIN(GPIO_C_BASE, (pins >> 16) & 0xFF);
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GPIO_CLR_PIN(GPIO_D_BASE, (pins >> 24) & 0xFF);
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}
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/*---------------------------------------------------------------------------*/
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gpio_hal_pin_mask_t
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gpio_hal_arch_read_pins(gpio_hal_pin_mask_t pins)
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{
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gpio_hal_pin_mask_t rv = 0;
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rv |= GPIO_READ_PIN(GPIO_A_BASE, pins & 0xFF);
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rv |= GPIO_READ_PIN(GPIO_B_BASE, (pins >> 8) & 0xFF) << 8;
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rv |= GPIO_READ_PIN(GPIO_C_BASE, (pins >> 16) & 0xFF) << 16;
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rv |= GPIO_READ_PIN(GPIO_D_BASE, (pins >> 24) & 0xFF) << 24;
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return rv;
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}
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/*---------------------------------------------------------------------------*/
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void
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gpio_hal_arch_write_pins(gpio_hal_pin_mask_t pins, gpio_hal_pin_mask_t value)
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{
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GPIO_WRITE_PIN(GPIO_A_BASE, pins & 0xFF, value & 0xFF);
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GPIO_WRITE_PIN(GPIO_B_BASE, (pins >> 8) & 0xFF, (value >> 8) & 0xFF);
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GPIO_WRITE_PIN(GPIO_C_BASE, (pins >> 16) & 0xFF, (value >> 16) & 0xFF);
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GPIO_WRITE_PIN(GPIO_D_BASE, (pins >> 24) & 0xFF, (value >> 24) & 0xFF);
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}
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/*---------------------------------------------------------------------------*/
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/** @} */
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88
arch/cpu/cc2538/dev/gpio-hal-arch.h
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88
arch/cpu/cc2538/dev/gpio-hal-arch.h
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@ -0,0 +1,88 @@
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/*
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* Copyright (c) 2017, George Oikonomou - http://www.spd.gr
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*---------------------------------------------------------------------------*/
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/**
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* \addtogroup cc2538
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* @{
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*
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* \defgroup cc2538-gpio-hal CC2538 GPIO HAL implementation
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*
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* @{
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*
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* \file
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* Header file for the CC2538 GPIO HAL functions
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*
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* \note
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* Do not include this header directly
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*/
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/*---------------------------------------------------------------------------*/
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#ifndef GPIO_HAL_ARCH_H_
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#define GPIO_HAL_ARCH_H_
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/*---------------------------------------------------------------------------*/
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#include "contiki.h"
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#include "dev/gpio.h"
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#include <stdint.h>
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/*---------------------------------------------------------------------------*/
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#define PIN_TO_PORT(pin) (pin >> 3)
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#define PIN_TO_PORT_BASE(pin) GPIO_PORT_TO_BASE(PIN_TO_PORT(pin))
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/*---------------------------------------------------------------------------*/
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#define gpio_hal_arch_interrupt_enable(p) \
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GPIO_ENABLE_INTERRUPT(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8))
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#define gpio_hal_arch_interrupt_disable(p) \
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GPIO_DISABLE_INTERRUPT(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8))
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#define gpio_hal_arch_pin_set_input(p) do { \
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GPIO_SOFTWARE_CONTROL(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \
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GPIO_SET_INPUT(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \
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} while(0);
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#define gpio_hal_arch_pin_set_output(p) do { \
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GPIO_SOFTWARE_CONTROL(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \
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GPIO_SET_OUTPUT(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)); \
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} while(0);
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#define gpio_hal_arch_set_pin(p) \
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GPIO_SET_PIN(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8))
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#define gpio_hal_arch_clear_pin(p) \
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GPIO_CLR_PIN(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8))
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#define gpio_hal_arch_read_pin(p) \
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(GPIO_READ_PIN(PIN_TO_PORT_BASE(p), GPIO_PIN_MASK((p) % 8)) == 0 ? 0 : 1)
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/*---------------------------------------------------------------------------*/
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#endif /* GPIO_HAL_ARCH_H_ */
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/*---------------------------------------------------------------------------*/
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/**
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* @}
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* @}
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*/
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@ -56,6 +56,12 @@ ioc_set_over(uint8_t port, uint8_t pin, uint8_t over)
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ioc_over[(port << 3) + pin] = over;
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}
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/*---------------------------------------------------------------------------*/
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uint32_t
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ioc_get_over(uint8_t port, uint8_t pin)
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{
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return ioc_over[(port << 3) + pin] & 0x0F;
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}
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/*---------------------------------------------------------------------------*/
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void
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ioc_set_sel(uint8_t port, uint8_t pin, uint8_t sel)
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{
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@ -249,6 +249,22 @@ void ioc_init();
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*/
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void ioc_set_over(uint8_t port, uint8_t pin, uint8_t over);
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/**
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* \brief Get Port:Pin override function
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* \param port The port as a number (PA: 0, PB: 1 etc)
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* \param pin The pin as a number
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* \return The override function
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*
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* The return value can be one of
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*
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* - IOC_OVERRIDE_OE: Output
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* - IOC_OVERRIDE_PUE: Pull-Up
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* - IOC_OVERRIDE_PDE: Pull-Down
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* - IOC_OVERRIDE_ANA: Analog
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* - IOC_OVERRIDE_DIS: Disabled
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*/
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uint32_t ioc_get_over(uint8_t port, uint8_t pin);
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/**
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* \brief Function select for Port:Pin
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* \param port The port as a number (PA: 0, PB: 1 etc)
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