From 0683d4dc3d6972f0aa80cec538ffe516d629b291 Mon Sep 17 00:00:00 2001 From: Niclas Finne Date: Fri, 17 Nov 2017 16:10:45 +0100 Subject: [PATCH 01/27] Imported SPI API from Yanzi Networks internal Contiki fork. --- arch/cpu/cc2538/Makefile.cc2538 | 3 +- arch/cpu/cc2538/spi-dev-arch.c | 185 ++++++++++++++++++++++++++++ arch/cpu/cc2538/spi-dev-arch.h | 44 +++++++ os/dev/spi-dev.c | 207 ++++++++++++++++++++++++++++++++ os/dev/spi-dev.h | 104 ++++++++++++++++ 5 files changed, 542 insertions(+), 1 deletion(-) create mode 100644 arch/cpu/cc2538/spi-dev-arch.c create mode 100644 arch/cpu/cc2538/spi-dev-arch.h create mode 100644 os/dev/spi-dev.c create mode 100644 os/dev/spi-dev.h diff --git a/arch/cpu/cc2538/Makefile.cc2538 b/arch/cpu/cc2538/Makefile.cc2538 index 03758aa9b..eb6d8a6b8 100644 --- a/arch/cpu/cc2538/Makefile.cc2538 +++ b/arch/cpu/cc2538/Makefile.cc2538 @@ -15,7 +15,8 @@ CONTIKI_CPU_DIRS = . dev usb usb/common usb/common/cdc-acm ### CPU-dependent source files CONTIKI_CPU_SOURCEFILES += soc.c clock.c rtimer-arch.c uart.c watchdog.c -CONTIKI_CPU_SOURCEFILES += nvic.c sys-ctrl.c gpio.c ioc.c spi.c adc.c +CONTIKI_CPU_SOURCEFILES += nvic.c sys-ctrl.c gpio.c ioc.c adc.c +CONTIKI_CPU_SOURCEFILES += spi.c spi-dev-arch.c CONTIKI_CPU_SOURCEFILES += crypto.c aes.c ecb.c cbc.c ctr.c cbc-mac.c gcm.c CONTIKI_CPU_SOURCEFILES += ccm.c sha256.c gpio-hal-arch.c CONTIKI_CPU_SOURCEFILES += cc2538-aes-128.c cc2538-ccm-star.c diff --git a/arch/cpu/cc2538/spi-dev-arch.c b/arch/cpu/cc2538/spi-dev-arch.c new file mode 100644 index 000000000..b20e5da5f --- /dev/null +++ b/arch/cpu/cc2538/spi-dev-arch.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2016-2017, Yanzi Networks. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "dev/spi-dev.h" +#include "spi-arch.h" + +#define DEBUG 0 +#if DEBUG +#include +#define PRINTF(...) printf(__VA_ARGS__) +#else +#define PRINTF(...) +#endif + +#ifdef PLATFORM_HAS_SPI_DEV_ARCH +/*---------------------------------------------------------------------------*/ +static void +spix_wait_tx_ready(int spi_instance) +{ + int reg = spi_instance == 0 ? SSI0_BASE : SSI1_BASE; + + /* Infinite loop until SR_TNF - Transmit FIFO Not Full */ + while(!(REG(reg + SSI_SR) & SSI_SR_TNF)); +} +/*---------------------------------------------------------------------------*/ +static int +spix_read_buf(int spi_instance) +{ + int reg = spi_instance == 0 ? SSI0_BASE : SSI1_BASE; + + return REG(reg + SSI_DR); +} +/*---------------------------------------------------------------------------*/ +static void +spix_write_buf(int spi_instance, int data) +{ + int reg = spi_instance == 0 ? SSI0_BASE : SSI1_BASE; + + REG(reg + SSI_DR) = data; +} +/*---------------------------------------------------------------------------*/ +static void +spix_wait_eotx(int spi_instance) +{ + int reg = spi_instance == 0 ? SSI0_BASE : SSI1_BASE; + + /* wait until not busy */ + while(REG(reg + SSI_SR) & SSI_SR_BSY); +} +/*---------------------------------------------------------------------------*/ +static void +spix_wait_eorx(int spi_instance) +{ + int reg = spi_instance == 0 ? SSI0_BASE : SSI1_BASE; + + /* wait as long as receive is empty */ + while(!(REG(reg + SSI_SR) & SSI_SR_RNE)); +} +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_arch_lock(spi_device_t *dev) +{ + spi_bus_t *bus; + bus = dev->bus; + + if(bus->lock) { + return SPI_DEV_STATUS_BUS_LOCKED; + } + /* Add support for timeout also!!! */ + bus->lock = 1; + bus->lock_device = dev; + + PRINTF("SPI: lock\n"); + + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ +int +spi_dev_arch_has_lock(spi_device_t *dev) +{ + return dev->bus->lock_device == dev; +} +/*---------------------------------------------------------------------------*/ +int +spi_dev_arch_is_bus_locked(spi_device_t *dev) +{ + return dev->bus->lock; +} +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_arch_unlock(spi_device_t *dev) +{ + dev->bus->lock = 0; + dev->bus->lock_device = NULL; + + PRINTF("SPI: unlock\n"); + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_arch_restart_timeout(spi_device_t *dev) +{ + /* do nothing at the moment */ + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ +/* Assumes that checking dev and bus is not NULL before calling this */ +spi_dev_status_t +spi_dev_arch_transfer(spi_device_t *dev, + const uint8_t *write_buf, int wlen, + uint8_t *inbuf, int rlen, int ignore_len) +{ + int i; + int totlen; + uint8_t c; + uint8_t spi_instance; + + spi_instance = dev->bus->config.instance; + + PRINTF("SPI: transfer (r:%d,w:%d) ", rlen, wlen); + + if(write_buf == NULL && wlen > 0) { + return SPI_DEV_STATUS_EINVAL; + } + if(inbuf == NULL && rlen > 0) { + return SPI_DEV_STATUS_EINVAL; + } + + totlen = MAX(rlen + ignore_len, wlen); + + if(totlen == 0) { + /* Nothing to do */ + return SPI_DEV_STATUS_OK; + } + + PRINTF("%c%c%c: %u ", rlen > 0 ? 'R' : '-', wlen > 0 ? 'W' : '-', + ignore_len > 0 ? 'S' : '-', totlen); + + for(i = 0; i < totlen; i++) { + spix_wait_tx_ready(spi_instance); + c = i < wlen ? write_buf[i] : 0; + spix_write_buf(spi_instance, c); + PRINTF("%c%02x->", i < rlen ? ' ' : '#', c); + spix_wait_eotx(spi_instance); + spix_wait_eorx(spi_instance); + c = spix_read_buf(spi_instance); + if(i < rlen) { + inbuf[i] = c; + } + PRINTF("%02x", c); + } + + PRINTF("\n"); + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ +#endif /* PLATFORM_HAS_SPI_DEV_ARCH */ diff --git a/arch/cpu/cc2538/spi-dev-arch.h b/arch/cpu/cc2538/spi-dev-arch.h new file mode 100644 index 000000000..88ca67f24 --- /dev/null +++ b/arch/cpu/cc2538/spi-dev-arch.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016-2017, Yanzi Networks. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef SPI_DEV_ARCH_H_ +#define SPI_DEV_ARCH_H_ + +#include + +/* The SPI instance for the CC2538 */ +typedef struct spi_bus_config { + uint8_t instance; +} spi_bus_config_t; + +typedef struct spi_device_config { +} spi_device_config_t; + +#endif /* SPI_DEV_ARCH_H_ */ diff --git a/os/dev/spi-dev.c b/os/dev/spi-dev.c new file mode 100644 index 000000000..be4418fcd --- /dev/null +++ b/os/dev/spi-dev.c @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2016-2017, Yanzi Networks. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "dev/spi-dev.h" + +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_acquire(spi_device_t *dev) +{ + if(dev == NULL || dev->bus == NULL) { + return SPI_DEV_STATUS_EINVAL; + } + /* lock the bus */ + return spi_dev_arch_lock(dev); +} +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_release(spi_device_t *dev) +{ + if(dev == NULL || dev->bus == NULL) { + return SPI_DEV_STATUS_EINVAL; + } + /* unlock the bus */ + return spi_dev_arch_unlock(dev); +} +/*---------------------------------------------------------------------------*/ +int +spi_dev_has_bus(spi_device_t *dev) +{ + if(dev == NULL || dev->bus == NULL) { + return 0; + } + return spi_dev_arch_has_lock(dev); +} +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_restart_timeout(spi_device_t *dev) +{ + if(!spi_dev_has_bus(dev)) { + return SPI_DEV_STATUS_EINVAL; + } + return spi_dev_arch_restart_timeout(dev); +} +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_write_byte(spi_device_t *dev, uint8_t data) +{ + if(dev == NULL || dev->bus == NULL) { + return SPI_DEV_STATUS_EINVAL; + } + + if(!spi_dev_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_LOCKED; + } + return spi_dev_arch_transfer(dev, &data, 1, 0, 0, 0); +} +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_write(spi_device_t *dev, const uint8_t *data, int size) +{ + if(dev == NULL || dev->bus == NULL) { + return SPI_DEV_STATUS_EINVAL; + } + + if(!spi_dev_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_LOCKED; + } + return spi_dev_arch_transfer(dev, data, size, 0, 0, 0); +} +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_read_byte(spi_device_t *dev, uint8_t *buf) +{ + if(dev == NULL || dev->bus == NULL) { + return SPI_DEV_STATUS_EINVAL; + } + + if(!spi_dev_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_LOCKED; + } + return spi_dev_arch_transfer(dev, NULL, 0, buf, 1, 0); +} +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_read(spi_device_t *dev, uint8_t *buf, int size) +{ + if(dev == NULL || dev->bus == NULL) { + return SPI_DEV_STATUS_EINVAL; + } + + if(!spi_dev_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_LOCKED; + } + return spi_dev_arch_transfer(dev, NULL, 0, buf, size, 0); +} +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_read_skip(spi_device_t *dev, int size) +{ + if(dev == NULL || dev->bus == NULL) { + return SPI_DEV_STATUS_EINVAL; + } + + if(!spi_dev_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_LOCKED; + } + return spi_dev_arch_transfer(dev, NULL, 0, NULL, 0, size); +} +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_transfer(spi_device_t *dev, + const uint8_t *wdata, int wsize, + uint8_t *rbuf, int rsize, int ignore) +{ + if(dev == NULL || dev->bus == NULL) { + return SPI_DEV_STATUS_EINVAL; + } + + if(!spi_dev_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_LOCKED; + } + + if(wdata == NULL && wsize > 0) { + return SPI_DEV_STATUS_EINVAL; + } + + if(rbuf == NULL && rsize > 0) { + return SPI_DEV_STATUS_EINVAL; + } + + return spi_dev_arch_transfer(dev, wdata, wsize, rbuf, rsize, ignore); +} +/*---------------------------------------------------------------------------*/ +/* Chip select can only be done when the bus is locked to this device */ +spi_dev_status_t +spi_dev_chip_select(spi_device_t *dev, uint8_t on) +{ + if(dev == NULL || dev->bus == NULL) { + return SPI_DEV_STATUS_EINVAL; + } + if(spi_dev_has_bus(dev)) { + return dev->chip_select(on); + } + return SPI_DEV_STATUS_BUS_NOT_OWNED; +} +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_read_register(spi_device_t *dev, uint8_t reg, uint8_t *data, int size) +{ + spi_dev_status_t status; + if(dev == NULL || dev->bus == NULL) { + return SPI_DEV_STATUS_EINVAL; + } + + /* write the register first (will read a status) */ + status = spi_dev_write_byte(dev, reg); + if(status != SPI_DEV_STATUS_OK) { + return status; + } + /* then read the value (will read the value) */ + status = spi_dev_read(dev, data, size); + if(status != SPI_DEV_STATUS_OK) { + return status; + } + return status; +} +/*---------------------------------------------------------------------------*/ +spi_dev_status_t +spi_dev_strobe(spi_device_t *dev, uint8_t strobe, uint8_t *result) +{ + if(dev == NULL || dev->bus == NULL) { + return SPI_DEV_STATUS_EINVAL; + } + + if(!spi_dev_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_LOCKED; + } + return spi_dev_arch_transfer(dev, &strobe, 1, result, 1, 0); +} +/*---------------------------------------------------------------------------*/ diff --git a/os/dev/spi-dev.h b/os/dev/spi-dev.h new file mode 100644 index 000000000..48068261f --- /dev/null +++ b/os/dev/spi-dev.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016-2017, Yanzi Networks. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef SPI_DEV_H_ +#define SPI_DEV_H_ + +#include "contiki.h" + +#ifdef PLATFORM_HAS_SPI_DEV_ARCH +#include "spi-dev-arch.h" +#endif + +typedef enum { + SPI_DEV_STATUS_OK, + SPI_DEV_STATUS_TIMEOUT, + SPI_DEV_STATUS_EINVAL, + SPI_DEV_STATUS_BUS_LOCKED, + SPI_DEV_STATUS_BUS_NOT_OWNED +} spi_dev_status_t; + +typedef struct spi_device spi_device_t; + +typedef struct spi_bus { + /* for locking the bus */ + spi_device_t *lock_device; + volatile uint8_t lock; +#ifdef PLATFORM_HAS_SPI_DEV_ARCH + spi_bus_config_t config; +#endif /* PLATFORM_HAS_SPI_DEV_ARCH */ +} spi_bus_t; + +struct spi_device { + spi_bus_t *bus; + /* timeout in milliseconds for this device */ + uint16_t timeout; + /* chip-select for this SPI chip - 1 = CS */ + uint8_t (* chip_select)(int on); +#ifdef PLATFORM_HAS_SPI_DEV_ARCH + spi_device_config_t config; +#endif +}; + +/* call for all spi devices */ +spi_dev_status_t spi_dev_acquire(spi_device_t *dev); +spi_dev_status_t spi_dev_release(spi_device_t *dev); +spi_dev_status_t spi_dev_restart_timeout(spi_device_t *dev); +int spi_dev_has_bus(spi_device_t *dev); +spi_dev_status_t spi_dev_write_byte(spi_device_t *dev, uint8_t data); +spi_dev_status_t spi_dev_read_byte(spi_device_t *dev, uint8_t *data); +spi_dev_status_t spi_dev_write(spi_device_t *dev, + const uint8_t *data, int size); +spi_dev_status_t spi_dev_read(spi_device_t *dev, uint8_t *data, int size); +spi_dev_status_t spi_dev_read_skip(spi_device_t *dev, int size); +spi_dev_status_t spi_dev_transfer(spi_device_t *dev, + const uint8_t *data, int wsize, + uint8_t *buf, int rsize, int ignore); +spi_dev_status_t spi_dev_chip_select(spi_device_t *dev, uint8_t on); +spi_dev_status_t spi_dev_strobe(spi_device_t *dev, uint8_t strobe, + uint8_t *status); +spi_dev_status_t spi_dev_read_register(spi_device_t *dev, uint8_t reg, + uint8_t *data, int size); + +/* Arch functions needed per CPU */ +spi_dev_status_t spi_dev_arch_lock(spi_device_t *dev); +spi_dev_status_t spi_dev_arch_unlock(spi_device_t *dev); +int spi_dev_arch_has_lock(spi_device_t *dev); +int spi_dev_arch_is_bus_locked(spi_device_t *dev); + +/* Initialize the spi bus */ +spi_dev_status_t spi_dev_arch_init(spi_device_t *dev); +spi_dev_status_t spi_dev_arch_transfer(spi_device_t *dev, + const uint8_t *data, int wlen, + uint8_t *buf, int rlen, + int ignore_len); +spi_dev_status_t spi_dev_arch_restart_timeout(spi_device_t *dev); + +#endif /* SPI_DEV_H */ From 1bb04f2d20433e3846e0ddb710622c55ee7df411 Mon Sep 17 00:00:00 2001 From: "Xenofon (Fontas) Fafoutis" Date: Mon, 18 Dec 2017 16:33:13 +0000 Subject: [PATCH 02/27] revert cc2538 --- arch/cpu/cc2538/Makefile.cc2538 | 3 +- arch/cpu/cc2538/spi-dev-arch.c | 185 -------------------------------- arch/cpu/cc2538/spi-dev-arch.h | 44 -------- 3 files changed, 1 insertion(+), 231 deletions(-) delete mode 100644 arch/cpu/cc2538/spi-dev-arch.c delete mode 100644 arch/cpu/cc2538/spi-dev-arch.h diff --git a/arch/cpu/cc2538/Makefile.cc2538 b/arch/cpu/cc2538/Makefile.cc2538 index eb6d8a6b8..03758aa9b 100644 --- a/arch/cpu/cc2538/Makefile.cc2538 +++ b/arch/cpu/cc2538/Makefile.cc2538 @@ -15,8 +15,7 @@ CONTIKI_CPU_DIRS = . dev usb usb/common usb/common/cdc-acm ### CPU-dependent source files CONTIKI_CPU_SOURCEFILES += soc.c clock.c rtimer-arch.c uart.c watchdog.c -CONTIKI_CPU_SOURCEFILES += nvic.c sys-ctrl.c gpio.c ioc.c adc.c -CONTIKI_CPU_SOURCEFILES += spi.c spi-dev-arch.c +CONTIKI_CPU_SOURCEFILES += nvic.c sys-ctrl.c gpio.c ioc.c spi.c adc.c CONTIKI_CPU_SOURCEFILES += crypto.c aes.c ecb.c cbc.c ctr.c cbc-mac.c gcm.c CONTIKI_CPU_SOURCEFILES += ccm.c sha256.c gpio-hal-arch.c CONTIKI_CPU_SOURCEFILES += cc2538-aes-128.c cc2538-ccm-star.c diff --git a/arch/cpu/cc2538/spi-dev-arch.c b/arch/cpu/cc2538/spi-dev-arch.c deleted file mode 100644 index b20e5da5f..000000000 --- a/arch/cpu/cc2538/spi-dev-arch.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2016-2017, Yanzi Networks. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include "dev/spi-dev.h" -#include "spi-arch.h" - -#define DEBUG 0 -#if DEBUG -#include -#define PRINTF(...) printf(__VA_ARGS__) -#else -#define PRINTF(...) -#endif - -#ifdef PLATFORM_HAS_SPI_DEV_ARCH -/*---------------------------------------------------------------------------*/ -static void -spix_wait_tx_ready(int spi_instance) -{ - int reg = spi_instance == 0 ? SSI0_BASE : SSI1_BASE; - - /* Infinite loop until SR_TNF - Transmit FIFO Not Full */ - while(!(REG(reg + SSI_SR) & SSI_SR_TNF)); -} -/*---------------------------------------------------------------------------*/ -static int -spix_read_buf(int spi_instance) -{ - int reg = spi_instance == 0 ? SSI0_BASE : SSI1_BASE; - - return REG(reg + SSI_DR); -} -/*---------------------------------------------------------------------------*/ -static void -spix_write_buf(int spi_instance, int data) -{ - int reg = spi_instance == 0 ? SSI0_BASE : SSI1_BASE; - - REG(reg + SSI_DR) = data; -} -/*---------------------------------------------------------------------------*/ -static void -spix_wait_eotx(int spi_instance) -{ - int reg = spi_instance == 0 ? SSI0_BASE : SSI1_BASE; - - /* wait until not busy */ - while(REG(reg + SSI_SR) & SSI_SR_BSY); -} -/*---------------------------------------------------------------------------*/ -static void -spix_wait_eorx(int spi_instance) -{ - int reg = spi_instance == 0 ? SSI0_BASE : SSI1_BASE; - - /* wait as long as receive is empty */ - while(!(REG(reg + SSI_SR) & SSI_SR_RNE)); -} -/*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_arch_lock(spi_device_t *dev) -{ - spi_bus_t *bus; - bus = dev->bus; - - if(bus->lock) { - return SPI_DEV_STATUS_BUS_LOCKED; - } - /* Add support for timeout also!!! */ - bus->lock = 1; - bus->lock_device = dev; - - PRINTF("SPI: lock\n"); - - return SPI_DEV_STATUS_OK; -} -/*---------------------------------------------------------------------------*/ -int -spi_dev_arch_has_lock(spi_device_t *dev) -{ - return dev->bus->lock_device == dev; -} -/*---------------------------------------------------------------------------*/ -int -spi_dev_arch_is_bus_locked(spi_device_t *dev) -{ - return dev->bus->lock; -} -/*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_arch_unlock(spi_device_t *dev) -{ - dev->bus->lock = 0; - dev->bus->lock_device = NULL; - - PRINTF("SPI: unlock\n"); - return SPI_DEV_STATUS_OK; -} -/*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_arch_restart_timeout(spi_device_t *dev) -{ - /* do nothing at the moment */ - return SPI_DEV_STATUS_OK; -} -/*---------------------------------------------------------------------------*/ -/* Assumes that checking dev and bus is not NULL before calling this */ -spi_dev_status_t -spi_dev_arch_transfer(spi_device_t *dev, - const uint8_t *write_buf, int wlen, - uint8_t *inbuf, int rlen, int ignore_len) -{ - int i; - int totlen; - uint8_t c; - uint8_t spi_instance; - - spi_instance = dev->bus->config.instance; - - PRINTF("SPI: transfer (r:%d,w:%d) ", rlen, wlen); - - if(write_buf == NULL && wlen > 0) { - return SPI_DEV_STATUS_EINVAL; - } - if(inbuf == NULL && rlen > 0) { - return SPI_DEV_STATUS_EINVAL; - } - - totlen = MAX(rlen + ignore_len, wlen); - - if(totlen == 0) { - /* Nothing to do */ - return SPI_DEV_STATUS_OK; - } - - PRINTF("%c%c%c: %u ", rlen > 0 ? 'R' : '-', wlen > 0 ? 'W' : '-', - ignore_len > 0 ? 'S' : '-', totlen); - - for(i = 0; i < totlen; i++) { - spix_wait_tx_ready(spi_instance); - c = i < wlen ? write_buf[i] : 0; - spix_write_buf(spi_instance, c); - PRINTF("%c%02x->", i < rlen ? ' ' : '#', c); - spix_wait_eotx(spi_instance); - spix_wait_eorx(spi_instance); - c = spix_read_buf(spi_instance); - if(i < rlen) { - inbuf[i] = c; - } - PRINTF("%02x", c); - } - - PRINTF("\n"); - return SPI_DEV_STATUS_OK; -} -/*---------------------------------------------------------------------------*/ -#endif /* PLATFORM_HAS_SPI_DEV_ARCH */ diff --git a/arch/cpu/cc2538/spi-dev-arch.h b/arch/cpu/cc2538/spi-dev-arch.h deleted file mode 100644 index 88ca67f24..000000000 --- a/arch/cpu/cc2538/spi-dev-arch.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2016-2017, Yanzi Networks. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef SPI_DEV_ARCH_H_ -#define SPI_DEV_ARCH_H_ - -#include - -/* The SPI instance for the CC2538 */ -typedef struct spi_bus_config { - uint8_t instance; -} spi_bus_config_t; - -typedef struct spi_device_config { -} spi_device_config_t; - -#endif /* SPI_DEV_ARCH_H_ */ From 91882209bf5ed50e853e6b5b065a7f8889a55c67 Mon Sep 17 00:00:00 2001 From: "Xenofon (Fontas) Fafoutis" Date: Tue, 28 Nov 2017 19:03:47 +0000 Subject: [PATCH 03/27] HAL SPI API Proposal Documenting the SPI HAL API --- os/dev/spi-dev.h | 104 ---------- os/dev/{spi-dev.c => spi-hal.c} | 174 +++++++++------- os/dev/spi-hal.h | 349 ++++++++++++++++++++++++++++++++ 3 files changed, 445 insertions(+), 182 deletions(-) delete mode 100644 os/dev/spi-dev.h rename os/dev/{spi-dev.c => spi-hal.c} (58%) create mode 100644 os/dev/spi-hal.h diff --git a/os/dev/spi-dev.h b/os/dev/spi-dev.h deleted file mode 100644 index 48068261f..000000000 --- a/os/dev/spi-dev.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2016-2017, Yanzi Networks. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef SPI_DEV_H_ -#define SPI_DEV_H_ - -#include "contiki.h" - -#ifdef PLATFORM_HAS_SPI_DEV_ARCH -#include "spi-dev-arch.h" -#endif - -typedef enum { - SPI_DEV_STATUS_OK, - SPI_DEV_STATUS_TIMEOUT, - SPI_DEV_STATUS_EINVAL, - SPI_DEV_STATUS_BUS_LOCKED, - SPI_DEV_STATUS_BUS_NOT_OWNED -} spi_dev_status_t; - -typedef struct spi_device spi_device_t; - -typedef struct spi_bus { - /* for locking the bus */ - spi_device_t *lock_device; - volatile uint8_t lock; -#ifdef PLATFORM_HAS_SPI_DEV_ARCH - spi_bus_config_t config; -#endif /* PLATFORM_HAS_SPI_DEV_ARCH */ -} spi_bus_t; - -struct spi_device { - spi_bus_t *bus; - /* timeout in milliseconds for this device */ - uint16_t timeout; - /* chip-select for this SPI chip - 1 = CS */ - uint8_t (* chip_select)(int on); -#ifdef PLATFORM_HAS_SPI_DEV_ARCH - spi_device_config_t config; -#endif -}; - -/* call for all spi devices */ -spi_dev_status_t spi_dev_acquire(spi_device_t *dev); -spi_dev_status_t spi_dev_release(spi_device_t *dev); -spi_dev_status_t spi_dev_restart_timeout(spi_device_t *dev); -int spi_dev_has_bus(spi_device_t *dev); -spi_dev_status_t spi_dev_write_byte(spi_device_t *dev, uint8_t data); -spi_dev_status_t spi_dev_read_byte(spi_device_t *dev, uint8_t *data); -spi_dev_status_t spi_dev_write(spi_device_t *dev, - const uint8_t *data, int size); -spi_dev_status_t spi_dev_read(spi_device_t *dev, uint8_t *data, int size); -spi_dev_status_t spi_dev_read_skip(spi_device_t *dev, int size); -spi_dev_status_t spi_dev_transfer(spi_device_t *dev, - const uint8_t *data, int wsize, - uint8_t *buf, int rsize, int ignore); -spi_dev_status_t spi_dev_chip_select(spi_device_t *dev, uint8_t on); -spi_dev_status_t spi_dev_strobe(spi_device_t *dev, uint8_t strobe, - uint8_t *status); -spi_dev_status_t spi_dev_read_register(spi_device_t *dev, uint8_t reg, - uint8_t *data, int size); - -/* Arch functions needed per CPU */ -spi_dev_status_t spi_dev_arch_lock(spi_device_t *dev); -spi_dev_status_t spi_dev_arch_unlock(spi_device_t *dev); -int spi_dev_arch_has_lock(spi_device_t *dev); -int spi_dev_arch_is_bus_locked(spi_device_t *dev); - -/* Initialize the spi bus */ -spi_dev_status_t spi_dev_arch_init(spi_device_t *dev); -spi_dev_status_t spi_dev_arch_transfer(spi_device_t *dev, - const uint8_t *data, int wlen, - uint8_t *buf, int rlen, - int ignore_len); -spi_dev_status_t spi_dev_arch_restart_timeout(spi_device_t *dev); - -#endif /* SPI_DEV_H */ diff --git a/os/dev/spi-dev.c b/os/dev/spi-hal.c similarity index 58% rename from os/dev/spi-dev.c rename to os/dev/spi-hal.c index be4418fcd..c8c84bd7c 100644 --- a/os/dev/spi-dev.c +++ b/os/dev/spi-hal.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2016-2017, Yanzi Networks. + * Copyright (c) 2017, University of Bristol - http://www.bristol.ac.uk/ * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,122 +29,149 @@ * OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "dev/spi-dev.h" +#include "spi-hal.h" /*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_acquire(spi_device_t *dev) +spi_status_t +spi_acquire(spi_device_t *dev) { - if(dev == NULL || dev->bus == NULL) { + spi_status_t r; + + if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { return SPI_DEV_STATUS_EINVAL; } + /* lock the bus */ - return spi_dev_arch_lock(dev); + r = spi_arch_lock(dev); + if(r != SPI_DEV_STATUS_OK) { + return r; + } + + /* open the bus */ + return spi_arch_open(dev); } /*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_release(spi_device_t *dev) +spi_status_t +spi_release(spi_device_t *dev) { - if(dev == NULL || dev->bus == NULL) { + spi_status_t r; + + if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { return SPI_DEV_STATUS_EINVAL; } + /* unlock the bus */ - return spi_dev_arch_unlock(dev); -} -/*---------------------------------------------------------------------------*/ -int -spi_dev_has_bus(spi_device_t *dev) -{ - if(dev == NULL || dev->bus == NULL) { - return 0; + r = spi_arch_close(dev); + if(r != SPI_DEV_STATUS_OK) { + return r; } - return spi_dev_arch_has_lock(dev); + + /* unlock the bus */ + return spi_arch_unlock(dev); } /*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_restart_timeout(spi_device_t *dev) +spi_status_t +spi_select(spi_device_t *dev) { - if(!spi_dev_has_bus(dev)) { - return SPI_DEV_STATUS_EINVAL; + return spi_arch_select(dev); +} +/*---------------------------------------------------------------------------*/ +spi_status_t +spi_deselect(spi_device_t *dev) +{ + return spi_arch_deselect(dev); +} +/*---------------------------------------------------------------------------*/ +bool +spi_has_bus(spi_device_t *dev) +{ + if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { + return false; } - return spi_dev_arch_restart_timeout(dev); + + return spi_arch_has_lock(dev); } /*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_write_byte(spi_device_t *dev, uint8_t data) +spi_status_t +spi_write_byte(spi_device_t *dev, uint8_t data) { - if(dev == NULL || dev->bus == NULL) { + if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { return SPI_DEV_STATUS_EINVAL; } - if(!spi_dev_arch_has_lock(dev)) { + if(!spi_arch_has_lock(dev)) { return SPI_DEV_STATUS_BUS_LOCKED; } - return spi_dev_arch_transfer(dev, &data, 1, 0, 0, 0); + + return spi_arch_transfer(dev, &data, 1, 0, 0, 0); } /*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_write(spi_device_t *dev, const uint8_t *data, int size) +spi_status_t +spi_write(spi_device_t *dev, const uint8_t *data, int size) { - if(dev == NULL || dev->bus == NULL) { + if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { return SPI_DEV_STATUS_EINVAL; } - if(!spi_dev_arch_has_lock(dev)) { + if(!spi_arch_has_lock(dev)) { return SPI_DEV_STATUS_BUS_LOCKED; } - return spi_dev_arch_transfer(dev, data, size, 0, 0, 0); + + return spi_arch_transfer(dev, data, size, 0, 0, 0); } /*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_read_byte(spi_device_t *dev, uint8_t *buf) +spi_status_t +spi_read_byte(spi_device_t *dev, uint8_t *buf) { - if(dev == NULL || dev->bus == NULL) { + if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { return SPI_DEV_STATUS_EINVAL; } - if(!spi_dev_arch_has_lock(dev)) { + if(!spi_arch_has_lock(dev)) { return SPI_DEV_STATUS_BUS_LOCKED; } - return spi_dev_arch_transfer(dev, NULL, 0, buf, 1, 0); + + return spi_arch_transfer(dev, NULL, 0, buf, 1, 0); } /*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_read(spi_device_t *dev, uint8_t *buf, int size) +spi_status_t +spi_read(spi_device_t *dev, uint8_t *buf, int size) { - if(dev == NULL || dev->bus == NULL) { + if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { return SPI_DEV_STATUS_EINVAL; } - if(!spi_dev_arch_has_lock(dev)) { + if(!spi_arch_has_lock(dev)) { return SPI_DEV_STATUS_BUS_LOCKED; } - return spi_dev_arch_transfer(dev, NULL, 0, buf, size, 0); + + return spi_arch_transfer(dev, NULL, 0, buf, size, 0); } /*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_read_skip(spi_device_t *dev, int size) +spi_status_t +spi_read_skip(spi_device_t *dev, int size) { - if(dev == NULL || dev->bus == NULL) { + if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { return SPI_DEV_STATUS_EINVAL; } - if(!spi_dev_arch_has_lock(dev)) { + if(!spi_arch_has_lock(dev)) { return SPI_DEV_STATUS_BUS_LOCKED; } - return spi_dev_arch_transfer(dev, NULL, 0, NULL, 0, size); + + return spi_arch_transfer(dev, NULL, 0, NULL, 0, size); } /*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_transfer(spi_device_t *dev, - const uint8_t *wdata, int wsize, - uint8_t *rbuf, int rsize, int ignore) +spi_status_t +spi_transfer(spi_device_t *dev, + const uint8_t *wdata, int wsize, + uint8_t *rbuf, int rsize, int ignore) { - if(dev == NULL || dev->bus == NULL) { + if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { return SPI_DEV_STATUS_EINVAL; } - if(!spi_dev_arch_has_lock(dev)) { + if(!spi_arch_has_lock(dev)) { return SPI_DEV_STATUS_BUS_LOCKED; } @@ -155,53 +183,43 @@ spi_dev_transfer(spi_device_t *dev, return SPI_DEV_STATUS_EINVAL; } - return spi_dev_arch_transfer(dev, wdata, wsize, rbuf, rsize, ignore); + return spi_arch_transfer(dev, wdata, wsize, rbuf, rsize, ignore); } /*---------------------------------------------------------------------------*/ -/* Chip select can only be done when the bus is locked to this device */ -spi_dev_status_t -spi_dev_chip_select(spi_device_t *dev, uint8_t on) +spi_status_t +spi_read_register(spi_device_t *dev, uint8_t reg, uint8_t *data, int size) { - if(dev == NULL || dev->bus == NULL) { - return SPI_DEV_STATUS_EINVAL; - } - if(spi_dev_has_bus(dev)) { - return dev->chip_select(on); - } - return SPI_DEV_STATUS_BUS_NOT_OWNED; -} -/*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_read_register(spi_device_t *dev, uint8_t reg, uint8_t *data, int size) -{ - spi_dev_status_t status; - if(dev == NULL || dev->bus == NULL) { + spi_status_t status; + if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { return SPI_DEV_STATUS_EINVAL; } /* write the register first (will read a status) */ - status = spi_dev_write_byte(dev, reg); + status = spi_write_byte(dev, reg); if(status != SPI_DEV_STATUS_OK) { return status; } + /* then read the value (will read the value) */ - status = spi_dev_read(dev, data, size); + status = spi_read(dev, data, size); if(status != SPI_DEV_STATUS_OK) { return status; } + return status; } /*---------------------------------------------------------------------------*/ -spi_dev_status_t -spi_dev_strobe(spi_device_t *dev, uint8_t strobe, uint8_t *result) +spi_status_t +spi_strobe(spi_device_t *dev, uint8_t strobe, uint8_t *result) { - if(dev == NULL || dev->bus == NULL) { + if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { return SPI_DEV_STATUS_EINVAL; } - if(!spi_dev_arch_has_lock(dev)) { + if(!spi_arch_has_lock(dev)) { return SPI_DEV_STATUS_BUS_LOCKED; } - return spi_dev_arch_transfer(dev, &strobe, 1, result, 1, 0); + + return spi_arch_transfer(dev, &strobe, 1, result, 1, 0); } /*---------------------------------------------------------------------------*/ diff --git a/os/dev/spi-hal.h b/os/dev/spi-hal.h new file mode 100644 index 000000000..901da2a25 --- /dev/null +++ b/os/dev/spi-hal.h @@ -0,0 +1,349 @@ +/* + * Copyright (c) 2016-2017, Yanzi Networks. + * Copyright (c) 2017, University of Bristol - http://www.bristol.ac.uk/ + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup dev + * @{ + * + * \defgroup spi-hal SPI Hardware Abstraction Layer + * + * The SPI HAL provides a set of common functions that can be used in a + * platform-independent fashion. + * + * + * @{ + * + * \file + * Header file for the SPI HAL + */ +/*---------------------------------------------------------------------------*/ +#ifndef SPI_HAL_H_ +#define SPI_HAL_H_ +/*---------------------------------------------------------------------------*/ +#include "contiki.h" +#include "gpio-hal.h" + +#include +#include +/*---------------------------------------------------------------------------*/ +/* Include Arch-Specific conf */ +#ifdef SPI_HAL_CONF_ARCH_HDR_PATH +#include SPI_HAL_CONF_ARCH_HDR_PATH +#else /* PLATFORM_IMPLEMENTS_SPI_HAL */ +#define BOARD_SPI_CONTROLLERS 0 +#endif /* SPI_HAL_CONF_ARCH_HDR_PATH */ +/*---------------------------------------------------------------------------*/ +/** + * \brief SPI return codes + * + * @{ + */ +typedef enum { + SPI_DEV_STATUS_OK, /* Everything OK */ + SPI_DEV_STATUS_EINVAL, /* Erroneous input value */ + SPI_DEV_STATUS_BUS_LOCKED, /* SPI bus is already locked */ + SPI_DEV_STATUS_BUS_NOT_OWNED, /* SPI bus is locked by someone else */ + SPI_DEV_STATUS_CLOSED /* SPI bus has not opened properly */ +} spi_status_t; +/*---------------------------------------------------------------------------*/ +/** + * \brief SPI Device Configuration + * + * This is a structure to an architecture-independent SPI configuration. + * + * @{ + */ + +typedef struct spi_device { + gpio_hal_pin_t pin_spi_sck; /* SPI SCK pin */ + gpio_hal_pin_t pin_spi_miso; /* SPI MISO pin */ + gpio_hal_pin_t pin_spi_mosi; /* SPI MOSI pin */ + gpio_hal_pin_t pin_spi_cs; /* SPI Chip Select pin */ + uint32_t spi_bit_rate; /* SPI bit rate */ + uint8_t spi_pha; /* SPI mode phase */ + uint8_t spi_pol; /* SPI mode polarity */ + uint8_t spi_controller; /* ID of SPI controller to use */ +} spi_device_t; + +/*---------------------------------------------------------------------------*/ +/* These are architecture-independent functions to be used by SPI devices. */ +/*---------------------------------------------------------------------------*/ +/** + * \brief Locks and then opens an SPI controller + * \param dev An SPI device configuration which defines the controller + * to be locked and the opening configuration. + * \return SPI return code + */ +spi_status_t spi_acquire(spi_device_t *dev); + +/** + * \brief Closes and then unlocks an SPI controller + * \param dev An SPI device configuration which defines the controller + * to be closed and unlocked. + * \return SPI return code + * + * Releasing an SPI controller should put it in low-power mode. + * This should work only if the device has already locked the SPI + * controller. + */ +spi_status_t spi_release(spi_device_t *dev); + +/** + * \brief Selects the SPI peripheral + * \param dev An SPI device configuration which defines the CS pin. + * \return SPI return code + * + * Clears the CS pin. This should work only if the device has + * already locked the SPI controller. + */ +spi_status_t spi_select(spi_device_t *dev); + +/** + * \brief Deselects the SPI peripheral + * \param dev An SPI device configuration which defines the CS pin. + * \return SPI return code + * + * Sets the CS pin. Lock is not required. + */ +spi_status_t spi_deselect(spi_device_t *dev); + +/** + * \brief Checks if a device has locked an SPI controller + * \param dev An SPI device configuration which defines the controller. + * \return true if the device has the lock, false otherwise. + */ +bool spi_has_bus(spi_device_t *dev); + +/** + * \brief Writes a single byte to an SPI device + * \param dev An SPI device configuration. + * \param data A byte of data + * \return SPI return code + * + * It should work only if the device has already locked the SPI controller. + */ +spi_status_t spi_write_byte(spi_device_t *dev, uint8_t data); + +/** + * \brief Reads a single byte from an SPI device + * \param dev An SPI device configuration. + * \param data A pointer to a byte of data + * \return SPI return code + * + * It should work only if the device has already locked the SPI controller. + */ +spi_status_t spi_read_byte(spi_device_t *dev, uint8_t *data); + +/** + * \brief Writes a buffer to an SPI device + * \param dev An SPI device configuration. + * \param data A pointer to the data + * \param size Size of the data to write + * \return SPI return code + * + * It should work only if the device has already locked the SPI controller. + */ +spi_status_t spi_write(spi_device_t *dev, + const uint8_t *data, int size); + +/** + * \brief Reads a buffer from an SPI device + * \param dev An SPI device configuration. + * \param data A pointer to the data + * \param size Size of the data to read + * \return SPI return code + * + * It should work only if the device has already locked the SPI controller. + */ +spi_status_t spi_read(spi_device_t *dev, uint8_t *data, int size); + +/** + * \brief Reads and ignores data from an SPI device + * \param dev An SPI device configuration. + * \param size Size of the data to read and ignore + * \return SPI return code + * + * Reads size bytes from the SPI and throws them away. + * It should work only if the device has already locked the SPI controller. + */ +spi_status_t spi_read_skip(spi_device_t *dev, int size); + +/** + * \brief Performs a generic SPI transfer + * \param dev An SPI device configuration. + * \param data A pointer to the data to be written. Set it to NULL to + * skip writing. + * \param wlen Size of data to write. + * \param buf A pointer to buffer to copy the data read. Set to NULL + * to skip reading. + * \param rlen Size of data to read. + * \param ignore_len Size of data to read and ignore. + * \return SPI return code + * + * It should work only if the device has already locked the SPI controller. + * A total of rlen+ignore_len bytes will be read. The first rlen bytes will + * be copied to buf. The remaining ignore_len bytes won't be copied to the + * buffer. The maximum of wlen and rlen+ignore_len of bytes will be transfered. + */ +spi_status_t spi_transfer(spi_device_t *dev, + const uint8_t *data, int wsize, + uint8_t *buf, int rsize, int ignore); + +/** + * \brief Reads and Writes one byte from/to an SPI device + * \param dev An SPI device configuration. + * \param strobe Byte to write + * \param status Pointer to byte to read + * \return SPI return code + * + * It should work only if the device has already locked the SPI controller. + */ +spi_status_t spi_strobe(spi_device_t *dev, uint8_t strobe, + uint8_t *status); + +/** + * \brief Reads a buffer of bytes from a register of an SPI device + * \param dev An SPI device configuration. + * \param reg Register + * \param data A pointer to the data + * \param size Size of the data to read + * \return SPI return code + * + * It should work only if the device has already locked the SPI controller. + */ +spi_status_t spi_read_register(spi_device_t *dev, uint8_t reg, + uint8_t *data, int size); + +/*---------------------------------------------------------------------------*/ +/* These are architecture-specific functions to be implemented by each CPU. */ +/*---------------------------------------------------------------------------*/ + +/** + * \brief Locks an SPI controller to device dev. + * \param dev An SPI device configuration which defines the controller + * to be locked and the device that locks it. + * \return SPI return code + * + */ +spi_status_t spi_arch_lock(spi_device_t *dev); + +/** + * \brief Unlocks an SPI controller. + * \param dev An SPI device configuration which defines the controller + * to be unlocked and the device that unlocks it. + * \return SPI return code + * + */ +spi_status_t spi_arch_unlock(spi_device_t *dev); + +/** + * \brief Checks if a device has locked an SPI controller + * \param dev An SPI device configuration which defines the controller + * to be checked if it is locked and the respective device. + * \return 1 if the device has the lock, 0 otherwise. + * + */ +bool spi_arch_has_lock(spi_device_t *dev); + +/** + * \brief Checks if an SPI controller is locked by any device + * \param dev An SPI device configuration which defines the controller + * to be checked. + * \return 1 if the controller is locked, 0 otherwise. + * + */ +bool spi_arch_is_bus_locked(spi_device_t *dev); + +/** + * \brief Opens an SPI controller to the configuration specified. + * \param dev An SPI device configuration. + * \return SPI return code + * + * This should work only if the device has already locked the SPI + * controller. + * + */ +spi_status_t spi_arch_open(spi_device_t *dev); + +/** + * \brief Closes an SPI controller + * \param dev An SPI device configuration that specifies the controller. + * \return SPI return code + * + * This should turn off the SPI controller to put it in low power mode. + * It should work only if the device has already locked the SPI + * controller. + * + */ +spi_status_t spi_arch_close(spi_device_t *dev); + +/** + * \brief Performs an SPI transfer + * \param dev An SPI device configuration that specifies the controller. + * \param data A pointer to the data to be written. Set it to NULL to + * skip writing. + * \param wlen Length of data to write. + * \param buf A pointer to buffer to copy the data read. Set to NULL + * to skip reading. + * \param rlen Length of data to read. + * \param ignore_len Length of data to read and ignore. + * \return SPI return code + * + * It should work only if the device has already locked the SPI controller. + * A total of rlen+ignore_len bytes will be read. The first rlen bytes will + * be copied to buf. The remaining ignore_len bytes won't be copied to the + * buffer. The maximum of wlen and rlen+ignore_len of bytes will be transfered. + */ +spi_status_t spi_arch_transfer(spi_device_t *dev, + const uint8_t *data, int wlen, + uint8_t *buf, int rlen, + int ignore_len); + +/** + * \brief Selects an SPI device + * \param dev An SPI device configuration that specifies the CS pin. + * \return SPI return code + * + * Clears the CS pin. It should work only if the device has already + * locked the SPI controller. + */ +spi_status_t spi_arch_select(spi_device_t *dev); + +/** + * \brief Deselects an SPI device + * \param dev An SPI device configuration that specifies the CS pin. + * \return SPI return code + * + * Set the CS pin. Locking the SPI controller is not needed. + */ +spi_status_t spi_arch_deselect(spi_device_t *dev); + +#endif /* SPI_HAL_H_ */ From cf291c22f01fca1cea23abefeb2f74b640e21e9c Mon Sep 17 00:00:00 2001 From: "Xenofon (Fontas) Fafoutis" Date: Wed, 28 Feb 2018 10:41:05 +0000 Subject: [PATCH 04/27] Minor changes in the GPIO HAL --- arch/cpu/cc2538/dev/gpio-hal-arch.h | 1 + os/dev/gpio-hal.h | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/arch/cpu/cc2538/dev/gpio-hal-arch.h b/arch/cpu/cc2538/dev/gpio-hal-arch.h index 0b282c738..25abb3eb4 100644 --- a/arch/cpu/cc2538/dev/gpio-hal-arch.h +++ b/arch/cpu/cc2538/dev/gpio-hal-arch.h @@ -53,6 +53,7 @@ #include /*---------------------------------------------------------------------------*/ #define PIN_TO_PORT(pin) (pin >> 3) +#define PIN_TO_NUM(pin) (pin % 8) #define PIN_TO_PORT_BASE(pin) GPIO_PORT_TO_BASE(PIN_TO_PORT(pin)) /*---------------------------------------------------------------------------*/ #define gpio_hal_arch_interrupt_enable(p) do { \ diff --git a/os/dev/gpio-hal.h b/os/dev/gpio-hal.h index aacbfb1f1..b6af7bf74 100644 --- a/os/dev/gpio-hal.h +++ b/os/dev/gpio-hal.h @@ -130,6 +130,13 @@ typedef struct gpio_hal_event_handler_s { gpio_hal_pin_mask_t pin_mask; } gpio_hal_event_handler_t; /*---------------------------------------------------------------------------*/ +/** + * \brief Unknown GPIO + * + * A default GPIO value for unknown GPIO + */ +#define GPIO_HAL_PIN_UNKNOWN 0xFF +/*---------------------------------------------------------------------------*/ /** * \name Core GPIO functions * From e7d7ee396267a6a827d25a3e2aa2112c929a9668 Mon Sep 17 00:00:00 2001 From: "xenofon (Fontas) Fafoutis" Date: Mon, 20 Nov 2017 17:02:37 +0000 Subject: [PATCH 05/27] generic spi driver for cc26xx-cc13xx launchpad and ext-flash implementation --- arch/cpu/cc26xx-cc13xx/Makefile.cc26xx-cc13xx | 1 + arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c | 248 ++++++++++++++++++ arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.h | 51 ++++ arch/platform/srf06-cc26xx/common/board-spi.c | 163 ------------ arch/platform/srf06-cc26xx/common/board-spi.h | 114 -------- arch/platform/srf06-cc26xx/contiki-conf.h | 3 + .../srf06-cc26xx/launchpad/Makefile.launchpad | 1 - arch/platform/srf06-cc26xx/launchpad/board.c | 2 +- .../srf06-cc26xx/launchpad/cc1310/board.h | 30 ++- .../srf06-cc26xx/launchpad/cc1350/board.h | 31 ++- .../srf06-cc26xx/launchpad/cc2650/board.h | 30 ++- .../common => os/dev}/ext-flash.c | 238 ++++++++++------- .../common => os/dev}/ext-flash.h | 12 +- 13 files changed, 510 insertions(+), 414 deletions(-) create mode 100644 arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c create mode 100644 arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.h delete mode 100644 arch/platform/srf06-cc26xx/common/board-spi.c delete mode 100644 arch/platform/srf06-cc26xx/common/board-spi.h rename {arch/platform/srf06-cc26xx/common => os/dev}/ext-flash.c (66%) rename {arch/platform/srf06-cc26xx/common => os/dev}/ext-flash.h (92%) diff --git a/arch/cpu/cc26xx-cc13xx/Makefile.cc26xx-cc13xx b/arch/cpu/cc26xx-cc13xx/Makefile.cc26xx-cc13xx index 75dbad7ad..aacc98b62 100644 --- a/arch/cpu/cc26xx-cc13xx/Makefile.cc26xx-cc13xx +++ b/arch/cpu/cc26xx-cc13xx/Makefile.cc26xx-cc13xx @@ -36,6 +36,7 @@ CONTIKI_CPU_SOURCEFILES += gpio-interrupt.c gpio-hal-arch.c oscillators.c CONTIKI_CPU_SOURCEFILES += rf-core.c rf-ble.c ieee-mode.c CONTIKI_CPU_SOURCEFILES += ble-cc2650.c ble-hal-cc26xx.c ble-addr.c rf-ble-cmd.c CONTIKI_CPU_SOURCEFILES += random.c soc-trng.c int-master.c +CONTIKI_CPU_SOURCEFILES += spi-hal-arch.c MODULES += os/lib/dbg-io diff --git a/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c b/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c new file mode 100644 index 000000000..c67c0d484 --- /dev/null +++ b/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2017, University of Bristol - http://www.bristol.ac.uk/ + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ti-lib.h" +#include "spi-hal.h" +#include "spi-hal-arch.h" +#include "sys/mutex.h" + +#include +#include + +typedef struct spi_locks_s { + mutex_t lock; + spi_device_t *owner; +} spi_locks_t; + +/* One lock per SPI controller */ +spi_locks_t board_spi_locks_spi[BOARD_SPI_CONTROLLERS] = { { MUTEX_STATUS_UNLOCKED, NULL } }; + +/* Arch-specific properties of each SPI controller */ +static const board_spi_controller_t spi_controller[BOARD_SPI_CONTROLLERS] = { + { + .ssi_base = SSI0_BASE, + .power_domain = PRCM_DOMAIN_SERIAL, + .prcm_periph = PRCM_PERIPH_SSI0, + .ssi_clkgr_clk_en = PRCM_SSICLKGR_CLK_EN_SSI0 + }, + { + .ssi_base = SSI1_BASE, + .power_domain = PRCM_DOMAIN_PERIPH, + .prcm_periph = PRCM_PERIPH_SSI1, + .ssi_clkgr_clk_en = PRCM_SSICLKGR_CLK_EN_SSI1 + } +}; +/*---------------------------------------------------------------------------*/ +spi_status_t +spi_arch_lock(spi_device_t *dev) +{ + if(mutex_try_lock(&board_spi_locks_spi[dev->spi_controller].lock) == false) { + return SPI_DEV_STATUS_BUS_LOCKED; + } + + board_spi_locks_spi[dev->spi_controller].owner = dev; + + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ +bool +spi_arch_has_lock(spi_device_t *dev) +{ + if(board_spi_locks_spi[dev->spi_controller].owner == dev) { + return true; + } + + return false; +} +/*---------------------------------------------------------------------------*/ +bool +spi_arch_is_bus_locked(spi_device_t *dev) +{ + if(board_spi_locks_spi[dev->spi_controller].lock == MUTEX_STATUS_LOCKED) { + return true; + } + + return false; +} +/*---------------------------------------------------------------------------*/ +spi_status_t +spi_arch_unlock(spi_device_t *dev) +{ + if(!spi_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_NOT_OWNED; + } + + board_spi_locks_spi[dev->spi_controller].owner = NULL; + mutex_unlock(&board_spi_locks_spi[dev->spi_controller].lock); + + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ +static uint32_t +get_mode(spi_device_t *dev) +{ + /* Select the correct SPI mode */ + if(dev->spi_pha == 0 && dev->spi_pol == 0) { + return SSI_FRF_MOTO_MODE_0; + } else if(dev->spi_pha != 0 && dev->spi_pol == 0) { + return SSI_FRF_MOTO_MODE_1; + } else if(dev->spi_pha == 0 && dev->spi_pol != 0) { + return SSI_FRF_MOTO_MODE_2; + } else { + return SSI_FRF_MOTO_MODE_3; + } +} +/*---------------------------------------------------------------------------*/ +spi_status_t +spi_arch_open(spi_device_t *dev) +{ + uint32_t c; + + if(!spi_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_NOT_OWNED; + } + + /* CS pin configuration */ + ti_lib_ioc_pin_type_gpio_output(dev->pin_spi_cs); + + /* First, make sure the SERIAL PD is on */ + ti_lib_prcm_power_domain_on(spi_controller[dev->spi_controller].power_domain); + while((ti_lib_prcm_power_domain_status(spi_controller[dev->spi_controller].power_domain) + != PRCM_DOMAIN_POWER_ON)) ; + + /* Enable clock in active mode */ + ti_lib_rom_prcm_peripheral_run_enable(spi_controller[dev->spi_controller].prcm_periph); + ti_lib_prcm_load_set(); + while(!ti_lib_prcm_load_get()) ; + + /* SPI configuration */ + ti_lib_ssi_int_disable(spi_controller[dev->spi_controller].ssi_base, SSI_RXOR | SSI_RXFF | SSI_RXTO | SSI_TXFF); + ti_lib_ssi_int_clear(spi_controller[dev->spi_controller].ssi_base, SSI_RXOR | SSI_RXTO); + ti_lib_rom_ssi_config_set_exp_clk(spi_controller[dev->spi_controller].ssi_base, ti_lib_sys_ctrl_clock_get(), + get_mode(dev), SSI_MODE_MASTER, dev->spi_bit_rate, 8); + ti_lib_rom_ioc_pin_type_ssi_master(spi_controller[dev->spi_controller].ssi_base, dev->pin_spi_miso, + dev->pin_spi_mosi, IOID_UNUSED, dev->pin_spi_sck); + + ti_lib_ssi_enable(spi_controller[dev->spi_controller].ssi_base); + + /* Get rid of residual data from SSI port */ + while(ti_lib_ssi_data_get_non_blocking(spi_controller[dev->spi_controller].ssi_base, &c)) ; + + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ +spi_status_t +spi_arch_close(spi_device_t *dev) +{ + if(!spi_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_NOT_OWNED; + } + + /* Power down SSI */ + ti_lib_rom_prcm_peripheral_run_disable(spi_controller[dev->spi_controller].prcm_periph); + ti_lib_prcm_load_set(); + while(!ti_lib_prcm_load_get()) ; + + /* Restore pins to a low-consumption state */ + ti_lib_ioc_pin_type_gpio_input(dev->pin_spi_miso); + ti_lib_ioc_io_port_pull_set(dev->pin_spi_miso, IOC_IOPULL_DOWN); + + ti_lib_ioc_pin_type_gpio_input(dev->pin_spi_mosi); + ti_lib_ioc_io_port_pull_set(dev->pin_spi_mosi, IOC_IOPULL_DOWN); + + ti_lib_ioc_pin_type_gpio_input(dev->pin_spi_sck); + ti_lib_ioc_io_port_pull_set(dev->pin_spi_sck, IOC_IOPULL_DOWN); + + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ +spi_status_t +spi_arch_transfer(spi_device_t *dev, + const uint8_t *write_buf, int wlen, + uint8_t *inbuf, int rlen, int ignore_len) +{ + int i; + int totlen; + uint32_t c; + + if(!spi_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_NOT_OWNED; + } + + if(ti_lib_prcm_power_domain_status(spi_controller[dev->spi_controller].power_domain) + != PRCM_DOMAIN_POWER_ON) { + return SPI_DEV_STATUS_CLOSED; + } + + /* Then check the 'run mode' clock gate */ + if(!(HWREG(PRCM_BASE + PRCM_O_SSICLKGR) & spi_controller[dev->spi_controller].ssi_clkgr_clk_en)) { + return SPI_DEV_STATUS_CLOSED; + } + + totlen = MAX(rlen + ignore_len, wlen); + + if(totlen == 0) { + /* Nothing to do */ + return SPI_DEV_STATUS_OK; + } + + for(i = 0; i < totlen; i++) { + c = i < wlen ? write_buf[i] : 0; + ti_lib_ssi_data_put(spi_controller[dev->spi_controller].ssi_base, (uint8_t)c); + ti_lib_rom_ssi_data_get(spi_controller[dev->spi_controller].ssi_base, &c); + if(i < rlen) { + inbuf[i] = (uint8_t)c; + } + } + + while(ti_lib_rom_ssi_data_get_non_blocking(spi_controller[dev->spi_controller].ssi_base, &c)) ; + + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ +spi_status_t +spi_arch_select(spi_device_t *dev) +{ + + if(!spi_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_NOT_OWNED; + } + + ti_lib_gpio_clear_dio(dev->pin_spi_cs); + + return SPI_DEV_STATUS_OK; +} +spi_status_t +spi_arch_deselect(spi_device_t *dev) +{ + ti_lib_gpio_set_dio(dev->pin_spi_cs); + + return SPI_DEV_STATUS_OK; +} diff --git a/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.h b/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.h new file mode 100644 index 000000000..afbe3e6c2 --- /dev/null +++ b/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2017, University of Bristol - http://www.bristol.ac.uk/ + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef SPI_ARCH_H_ +#define SPI_ARCH_H_ + +#include "ti-lib.h" + +#include + +/*---------------------------------------------------------------------------*/ +#define BOARD_SPI_CONTROLLERS 2 +/*---------------------------------------------------------------------------*/ +#define BOARD_SPI_CONTROLLER_SPI0 0 +#define BOARD_SPI_CONTROLLER_SPI1 1 +/*---------------------------------------------------------------------------*/ +typedef struct board_spi_controller_s { + uint32_t ssi_base; + uint32_t power_domain; + uint32_t prcm_periph; + uint32_t ssi_clkgr_clk_en; +} board_spi_controller_t; + +#endif /* SPI_ARCH_H_ */ diff --git a/arch/platform/srf06-cc26xx/common/board-spi.c b/arch/platform/srf06-cc26xx/common/board-spi.c deleted file mode 100644 index fb9fecd63..000000000 --- a/arch/platform/srf06-cc26xx/common/board-spi.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 2014, Texas Instruments Incorporated - http://www.ti.com/ - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*---------------------------------------------------------------------------*/ -/** - * \addtogroup sensortag-cc26xx-spi - * @{ - * - * \file - * Board-specific SPI driver common to the Sensortag and LaunchPad - */ -/*---------------------------------------------------------------------------*/ -#include "contiki.h" -#include "ti-lib.h" -#include "board-spi.h" -#include "board.h" - -#include -/*---------------------------------------------------------------------------*/ -static bool -accessible(void) -{ - /* First, check the PD */ - if(ti_lib_prcm_power_domain_status(PRCM_DOMAIN_SERIAL) - != PRCM_DOMAIN_POWER_ON) { - return false; - } - - /* Then check the 'run mode' clock gate */ - if(!(HWREG(PRCM_BASE + PRCM_O_SSICLKGR) & PRCM_SSICLKGR_CLK_EN_SSI0)) { - return false; - } - - return true; -} -/*---------------------------------------------------------------------------*/ -bool -board_spi_write(const uint8_t *buf, size_t len) -{ - if(accessible() == false) { - return false; - } - - while(len > 0) { - uint32_t ul; - - ti_lib_ssi_data_put(SSI0_BASE, *buf); - ti_lib_rom_ssi_data_get(SSI0_BASE, &ul); - len--; - buf++; - } - - return true; -} -/*---------------------------------------------------------------------------*/ -bool -board_spi_read(uint8_t *buf, size_t len) -{ - if(accessible() == false) { - return false; - } - - while(len > 0) { - uint32_t ul; - - if(!ti_lib_rom_ssi_data_put_non_blocking(SSI0_BASE, 0)) { - /* Error */ - return false; - } - ti_lib_rom_ssi_data_get(SSI0_BASE, &ul); - *buf = (uint8_t)ul; - len--; - buf++; - } - return true; -} -/*---------------------------------------------------------------------------*/ -void -board_spi_flush() -{ - if(accessible() == false) { - return; - } - - uint32_t ul; - while(ti_lib_rom_ssi_data_get_non_blocking(SSI0_BASE, &ul)); -} -/*---------------------------------------------------------------------------*/ -void -board_spi_open(uint32_t bit_rate, uint32_t clk_pin) -{ - uint32_t buf; - - /* First, make sure the SERIAL PD is on */ - ti_lib_prcm_power_domain_on(PRCM_DOMAIN_SERIAL); - while((ti_lib_prcm_power_domain_status(PRCM_DOMAIN_SERIAL) - != PRCM_DOMAIN_POWER_ON)); - - /* Enable clock in active mode */ - ti_lib_rom_prcm_peripheral_run_enable(PRCM_PERIPH_SSI0); - ti_lib_prcm_load_set(); - while(!ti_lib_prcm_load_get()); - - /* SPI configuration */ - ti_lib_ssi_int_disable(SSI0_BASE, SSI_RXOR | SSI_RXFF | SSI_RXTO | SSI_TXFF); - ti_lib_ssi_int_clear(SSI0_BASE, SSI_RXOR | SSI_RXTO); - ti_lib_rom_ssi_config_set_exp_clk(SSI0_BASE, ti_lib_sys_ctrl_clock_get(), - SSI_FRF_MOTO_MODE_0, - SSI_MODE_MASTER, bit_rate, 8); - ti_lib_rom_ioc_pin_type_ssi_master(SSI0_BASE, BOARD_IOID_SPI_MISO, - BOARD_IOID_SPI_MOSI, IOID_UNUSED, clk_pin); - ti_lib_ssi_enable(SSI0_BASE); - - /* Get rid of residual data from SSI port */ - while(ti_lib_ssi_data_get_non_blocking(SSI0_BASE, &buf)); -} -/*---------------------------------------------------------------------------*/ -void -board_spi_close() -{ - /* Power down SSI0 */ - ti_lib_rom_prcm_peripheral_run_disable(PRCM_PERIPH_SSI0); - ti_lib_prcm_load_set(); - while(!ti_lib_prcm_load_get()); - - /* Restore pins to a low-consumption state */ - ti_lib_ioc_pin_type_gpio_input(BOARD_IOID_SPI_MISO); - ti_lib_ioc_io_port_pull_set(BOARD_IOID_SPI_MISO, IOC_IOPULL_DOWN); - - ti_lib_ioc_pin_type_gpio_input(BOARD_IOID_SPI_MOSI); - ti_lib_ioc_io_port_pull_set(BOARD_IOID_SPI_MOSI, IOC_IOPULL_DOWN); - - ti_lib_ioc_pin_type_gpio_input(BOARD_IOID_SPI_CLK_FLASH); - ti_lib_ioc_io_port_pull_set(BOARD_IOID_SPI_CLK_FLASH, IOC_IOPULL_DOWN); -} -/*---------------------------------------------------------------------------*/ -/** @} */ diff --git a/arch/platform/srf06-cc26xx/common/board-spi.h b/arch/platform/srf06-cc26xx/common/board-spi.h deleted file mode 100644 index 3699db120..000000000 --- a/arch/platform/srf06-cc26xx/common/board-spi.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2014, Texas Instruments Incorporated - http://www.ti.com/ - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*---------------------------------------------------------------------------*/ -/** - * \addtogroup cc26xx-srf-tag - * @{ - * - * \defgroup common-cc26xx-peripherals CC13xx/CC26xx peripheral driver pool - * - * Drivers for peripherals present on more than one CC13xx/CC26xx board. For - * example, the same external flash driver is used for both the part found on - * the Sensortag as well as the part on the LaunchPad. - * - * @{ - * - * \defgroup sensortag-cc26xx-spi SensorTag/LaunchPad SPI functions - * @{ - * - * \file - * Header file for the Sensortag/LaunchPad SPI Driver - */ -/*---------------------------------------------------------------------------*/ -#ifndef BOARD_SPI_H_ -#define BOARD_SPI_H_ -/*---------------------------------------------------------------------------*/ -#include -#include -#include -/*---------------------------------------------------------------------------*/ -/** - * \brief Initialize the SPI interface - * \param bit_rate The bit rate to use - * \param clk_pin The IOID for the clock pin. This can be IOID_0 etc - * \return none - * - * This function will make sure the peripheral is powered, clocked and - * initialised. A chain of calls to board_spi_read(), board_spi_write() and - * board_spi_flush() must be preceded by a call to this function. It is - * recommended to call board_spi_close() after such chain of calls. - */ -void board_spi_open(uint32_t bit_rate, uint32_t clk_pin); - -/** - * \brief Close the SPI interface - * \return True when successful. - * - * This function will stop clocks to the SSI module and will set MISO, MOSI - * and CLK to a low leakage state. It is recommended to call this function - * after a chain of calls to board_spi_read() and board_spi_write() - */ -void board_spi_close(void); - -/** - * \brief Clear data from the SPI interface - * \return none - */ -void board_spi_flush(void); - -/** - * \brief Read from an SPI device - * \param buf The buffer to store data - * \param length The number of bytes to read - * \return True when successful. - * - * Calls to this function must be preceded by a call to board_spi_open(). It is - * recommended to call board_spi_close() at the end of an operation. - */ -bool board_spi_read(uint8_t *buf, size_t length); - -/** - * \brief Write to an SPI device - * \param buf The buffer with the data to write - * \param length The number of bytes to write - * \return True when successful. - * - * Calls to this function must be preceded by a call to board_spi_open(). It is - * recommended to call board_spi_close() at the end of an operation. - */ -bool board_spi_write(const uint8_t *buf, size_t length); -/*---------------------------------------------------------------------------*/ -#endif /* BOARD_SPI_H_ */ -/*---------------------------------------------------------------------------*/ -/** - * @} - * @} - * @} - */ diff --git a/arch/platform/srf06-cc26xx/contiki-conf.h b/arch/platform/srf06-cc26xx/contiki-conf.h index 4a1470b40..82daed0c1 100644 --- a/arch/platform/srf06-cc26xx/contiki-conf.h +++ b/arch/platform/srf06-cc26xx/contiki-conf.h @@ -72,6 +72,9 @@ /* Platform-specific define to signify sensor reading failure */ #define CC26XX_SENSOR_READING_ERROR 0x80000000 /*---------------------------------------------------------------------------*/ +/* SPI HAL: Path to arch-specific implementation */ +#define SPI_HAL_CONF_ARCH_HDR_PATH "dev/spi-hal-arch.h" +/*---------------------------------------------------------------------------*/ /* Include CPU-related configuration */ #include "cc13xx-cc26xx-conf.h" /*---------------------------------------------------------------------------*/ diff --git a/arch/platform/srf06-cc26xx/launchpad/Makefile.launchpad b/arch/platform/srf06-cc26xx/launchpad/Makefile.launchpad index f10f979da..d3f4ab355 100644 --- a/arch/platform/srf06-cc26xx/launchpad/Makefile.launchpad +++ b/arch/platform/srf06-cc26xx/launchpad/Makefile.launchpad @@ -3,7 +3,6 @@ CFLAGS += -DBOARD_LAUNCHPAD=1 CONTIKI_TARGET_DIRS += launchpad common BOARD_SOURCEFILES += board.c board-buttons.c xmem.c -BOARD_SOURCEFILES += ext-flash.c board-spi.c ### Signal that we can be programmed with cc2538-bsl BOARD_SUPPORTS_BSL=1 diff --git a/arch/platform/srf06-cc26xx/launchpad/board.c b/arch/platform/srf06-cc26xx/launchpad/board.c index 7baf71d47..cda0a7c6c 100644 --- a/arch/platform/srf06-cc26xx/launchpad/board.c +++ b/arch/platform/srf06-cc26xx/launchpad/board.c @@ -93,7 +93,7 @@ board_init() while(!ti_lib_prcm_load_get()); /* Make sure the external flash is in the lower power mode */ - ext_flash_init(); + ext_flash_init(NULL); lpm_register_module(&launchpad_module); diff --git a/arch/platform/srf06-cc26xx/launchpad/cc1310/board.h b/arch/platform/srf06-cc26xx/launchpad/cc1310/board.h index 7c58e1db8..81f820a13 100644 --- a/arch/platform/srf06-cc26xx/launchpad/cc1310/board.h +++ b/arch/platform/srf06-cc26xx/launchpad/cc1310/board.h @@ -103,25 +103,29 @@ #define BOARD_KEY_RIGHT (1 << BOARD_IOID_KEY_RIGHT) /** @} */ /*---------------------------------------------------------------------------*/ -/** - * \brief SPI IOID mappings - * - * Those values are not meant to be modified by the user - * @{ - */ -#define BOARD_IOID_SPI_MOSI IOID_9 -#define BOARD_IOID_SPI_MISO IOID_8 -/** @} */ -/*---------------------------------------------------------------------------*/ /** * \name External flash IOID mapping * * Those values are not meant to be modified by the user * @{ */ -#define BOARD_IOID_FLASH_CS IOID_20 -#define BOARD_FLASH_CS (1 << BOARD_IOID_FLASH_CS) -#define BOARD_IOID_SPI_CLK_FLASH IOID_10 +#define EXT_FLASH_SPI_CONTROLLER BOARD_SPI_CONTROLLER_SPI0 + +#define BOARD_IOID_FLASH_SCK IOID_10 +#define BOARD_IOID_FLASH_MOSI IOID_9 +#define BOARD_IOID_FLASH_MISO IOID_8 +#define BOARD_IOID_FLASH_CS IOID_20 + +#define EXT_FLASH_SPI_PIN_SCK 10 +#define EXT_FLASH_SPI_PIN_MOSI 9 +#define EXT_FLASH_SPI_PIN_MISO 8 +#define EXT_FLASH_SPI_PIN_CS 20 + +#define EXT_FLASH_DEVICE_ID 0x14 +#define EXT_FLASH_MID 0xC2 + +#define EXT_FLASH_PROGRAM_PAGE_SIZE 256 +#define EXT_FLASH_ERASE_SECTOR_SIZE 4096 /** @} */ /*---------------------------------------------------------------------------*/ /** diff --git a/arch/platform/srf06-cc26xx/launchpad/cc1350/board.h b/arch/platform/srf06-cc26xx/launchpad/cc1350/board.h index 63ad25374..5831221bc 100644 --- a/arch/platform/srf06-cc26xx/launchpad/cc1350/board.h +++ b/arch/platform/srf06-cc26xx/launchpad/cc1350/board.h @@ -103,26 +103,29 @@ #define BOARD_KEY_RIGHT (1 << BOARD_IOID_KEY_RIGHT) /** @} */ /*---------------------------------------------------------------------------*/ -/** - * \brief SPI IOID mappings - * - * Those values are not meant to be modified by the user - * @{ - */ -#define BOARD_IOID_SPI_MOSI IOID_9 -#define BOARD_IOID_SPI_MISO IOID_8 -/** @} */ -/*---------------------------------------------------------------------------*/ /** * \name External flash IOID mapping * * Those values are not meant to be modified by the user * @{ */ -#define BOARD_IOID_FLASH_CS IOID_20 -#define BOARD_FLASH_CS (1 << BOARD_IOID_FLASH_CS) -#define BOARD_IOID_SPI_CLK_FLASH IOID_10 -/** @} */ +#define EXT_FLASH_SPI_CONTROLLER BOARD_SPI_CONTROLLER_SPI0 + +#define BOARD_IOID_FLASH_SCK IOID_10 +#define BOARD_IOID_FLASH_MOSI IOID_9 +#define BOARD_IOID_FLASH_MISO IOID_8 +#define BOARD_IOID_FLASH_CS IOID_20 + +#define EXT_FLASH_SPI_PIN_SCK 10 +#define EXT_FLASH_SPI_PIN_MOSI 9 +#define EXT_FLASH_SPI_PIN_MISO 8 +#define EXT_FLASH_SPI_PIN_CS 20 + +#define EXT_FLASH_DEVICE_ID 0x14 +#define EXT_FLASH_MID 0xC2 + +#define EXT_FLASH_PROGRAM_PAGE_SIZE 256 +#define EXT_FLASH_ERASE_SECTOR_SIZE 4096 /*---------------------------------------------------------------------------*/ /** * \brief I2C IOID mappings diff --git a/arch/platform/srf06-cc26xx/launchpad/cc2650/board.h b/arch/platform/srf06-cc26xx/launchpad/cc2650/board.h index 39b906e84..7b2c40403 100644 --- a/arch/platform/srf06-cc26xx/launchpad/cc2650/board.h +++ b/arch/platform/srf06-cc26xx/launchpad/cc2650/board.h @@ -103,25 +103,29 @@ #define BOARD_KEY_RIGHT (1 << BOARD_IOID_KEY_RIGHT) /** @} */ /*---------------------------------------------------------------------------*/ -/** - * \brief SPI IOID mappings - * - * Those values are not meant to be modified by the user - * @{ - */ -#define BOARD_IOID_SPI_MOSI IOID_9 -#define BOARD_IOID_SPI_MISO IOID_8 -/** @} */ -/*---------------------------------------------------------------------------*/ /** * \name External flash IOID mapping * * Those values are not meant to be modified by the user * @{ */ -#define BOARD_IOID_FLASH_CS IOID_20 -#define BOARD_FLASH_CS (1 << BOARD_IOID_FLASH_CS) -#define BOARD_IOID_SPI_CLK_FLASH IOID_10 +#define EXT_FLASH_SPI_CONTROLLER BOARD_SPI_CONTROLLER_SPI0 + +#define BOARD_IOID_FLASH_SCK IOID_10 +#define BOARD_IOID_FLASH_MOSI IOID_9 +#define BOARD_IOID_FLASH_MISO IOID_8 +#define BOARD_IOID_FLASH_CS IOID_20 + +#define EXT_FLASH_SPI_PIN_SCK 10 +#define EXT_FLASH_SPI_PIN_MOSI 9 +#define EXT_FLASH_SPI_PIN_MISO 8 +#define EXT_FLASH_SPI_PIN_CS 20 + +#define EXT_FLASH_DEVICE_ID 0x14 +#define EXT_FLASH_MID 0xC2 + +#define EXT_FLASH_PROGRAM_PAGE_SIZE 256 +#define EXT_FLASH_ERASE_SECTOR_SIZE 4096 /** @} */ /*---------------------------------------------------------------------------*/ /** diff --git a/arch/platform/srf06-cc26xx/common/ext-flash.c b/os/dev/ext-flash.c similarity index 66% rename from arch/platform/srf06-cc26xx/common/ext-flash.c rename to os/dev/ext-flash.c index 5631297ac..b1f428e11 100644 --- a/arch/platform/srf06-cc26xx/common/ext-flash.c +++ b/os/dev/ext-flash.c @@ -38,12 +38,34 @@ /*---------------------------------------------------------------------------*/ #include "contiki.h" #include "ext-flash.h" -#include "ti-lib.h" -#include "board-spi.h" +#include "spi-hal.h" +#include "gpio-hal.h" +#include "sys/log.h" #include #include /*---------------------------------------------------------------------------*/ +#ifndef EXT_FLASH_SPI_CONTROLLER + +#define EXT_FLASH_SPI_CONTROLLER 0xFF /* No controller */ + +#define EXT_FLASH_SPI_PIN_SCK GPIO_HAL_PIN_UNKNOWN +#define EXT_FLASH_SPI_PIN_MOSI GPIO_HAL_PIN_UNKNOWN +#define EXT_FLASH_SPI_PIN_MISO GPIO_HAL_PIN_UNKNOWN +#define EXT_FLASH_SPI_PIN_CS GPIO_HAL_PIN_UNKNOWN + +#define EXT_FLASH_DEVICE_ID 0xFF +#define EXT_FLASH_MID 0xFF + +#define EXT_FLASH_PROGRAM_PAGE_SIZE 256 +#define EXT_FLASH_ERASE_SECTOR_SIZE 4096 + +#endif /* EXT_FLASH_SPI_CONTROLLER */ +/*---------------------------------------------------------------------------*/ +/* Log configuration */ +#define LOG_MODULE "ext-flash" +#define LOG_LEVEL LOG_LEVEL_NONE +/*---------------------------------------------------------------------------*/ /* Instruction codes */ #define BLS_CODE_PROGRAM 0x02 /**< Page Program */ @@ -72,29 +94,33 @@ #define BLS_STATUS_BIT_BUSY 0x01 /**< Busy bit of the status register */ /*---------------------------------------------------------------------------*/ -/* Part specific constants */ -#define BLS_DEVICE_ID_W25X20CL 0x11 -#define BLS_DEVICE_ID_W25X40CL 0x12 -#define BLS_DEVICE_ID_MX25R8035F 0x14 -#define BLS_DEVICE_ID_MX25R1635F 0x15 - -#define BLS_WINBOND_MID 0xEF -#define BLS_MACRONIX_MID 0xC2 - -#define BLS_PROGRAM_PAGE_SIZE 256 -#define BLS_ERASE_SECTOR_SIZE 4096 -/*---------------------------------------------------------------------------*/ +#define VERIFY_PART_LOCKED -2 #define VERIFY_PART_ERROR -1 #define VERIFY_PART_POWERED_DOWN 0 #define VERIFY_PART_OK 1 /*---------------------------------------------------------------------------*/ +static spi_device_t flash_spi_configuration_default = { + .spi_controller = EXT_FLASH_SPI_CONTROLLER, + .pin_spi_sck = EXT_FLASH_SPI_PIN_SCK, + .pin_spi_miso = EXT_FLASH_SPI_PIN_MISO, + .pin_spi_mosi = EXT_FLASH_SPI_PIN_MOSI, + .pin_spi_cs = EXT_FLASH_SPI_PIN_CS, + .spi_bit_rate = 4000000, + .spi_pha = 0, + .spi_pol = 0 +}; + +static spi_device_t *flash_spi_configuration; /** * Clear external flash CSN line */ -static void +static bool select_on_bus(void) { - ti_lib_gpio_clear_dio(BOARD_IOID_FLASH_CS); + if(spi_select(flash_spi_configuration) == SPI_DEV_STATUS_OK) { + return true; + } + return false; } /*---------------------------------------------------------------------------*/ /** @@ -103,7 +129,7 @@ select_on_bus(void) static void deselect(void) { - ti_lib_gpio_set_dio(BOARD_IOID_FLASH_CS); + spi_deselect(flash_spi_configuration); } /*---------------------------------------------------------------------------*/ /** @@ -116,14 +142,13 @@ wait_ready(void) bool ret; const uint8_t wbuf[1] = { BLS_CODE_READ_STATUS }; - select_on_bus(); + if(select_on_bus() == false) { + return false; + } - /* Throw away all garbages */ - board_spi_flush(); + ret = spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)); - ret = board_spi_write(wbuf, sizeof(wbuf)); - - if(ret == false) { + if(ret != SPI_DEV_STATUS_OK) { deselect(); return false; } @@ -135,13 +160,14 @@ wait_ready(void) * Thread could have yielded while waiting for flash * erase/program to complete. */ - ret = board_spi_read(&buf, sizeof(buf)); + ret = spi_read(flash_spi_configuration, &buf, sizeof(buf)); - if(ret == false) { + if(ret != SPI_DEV_STATUS_OK) { /* Error */ deselect(); return false; } + if(!(buf & BLS_STATUS_BIT_BUSY)) { /* Now ready */ break; @@ -165,26 +191,24 @@ verify_part(void) uint8_t rbuf[2] = { 0, 0 }; bool ret; - select_on_bus(); + if(select_on_bus() == false) { + return VERIFY_PART_LOCKED; + } - ret = board_spi_write(wbuf, sizeof(wbuf)); - - if(ret == false) { + if(spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) != SPI_DEV_STATUS_OK) { deselect(); return VERIFY_PART_ERROR; } - ret = board_spi_read(rbuf, sizeof(rbuf)); + ret = spi_read(flash_spi_configuration, rbuf, sizeof(rbuf)); deselect(); - - if(ret == false) { + if(ret != SPI_DEV_STATUS_OK) { return VERIFY_PART_ERROR; } - if((rbuf[0] != BLS_WINBOND_MID && rbuf[0] != BLS_MACRONIX_MID) || - (rbuf[1] != BLS_DEVICE_ID_W25X20CL && rbuf[1] != BLS_DEVICE_ID_W25X40CL - && rbuf[1] != BLS_DEVICE_ID_MX25R8035F - && rbuf[1] != BLS_DEVICE_ID_MX25R1635F)) { + LOG_DBG("Verify: %02x %02x\n", rbuf[0], rbuf[1]); + + if(rbuf[0] != EXT_FLASH_MID || rbuf[1] != EXT_FLASH_DEVICE_ID) { return VERIFY_PART_POWERED_DOWN; } return VERIFY_PART_OK; @@ -194,7 +218,7 @@ verify_part(void) * \brief Put the device in power save mode. No access to data; only * the status register is accessible. */ -static void +static bool power_down(void) { uint8_t cmd; @@ -203,25 +227,32 @@ power_down(void) /* First, wait for the device to be ready */ if(wait_ready() == false) { /* Entering here will leave the device in standby instead of powerdown */ - return; + return false; } cmd = BLS_CODE_PD; - select_on_bus(); - board_spi_write(&cmd, sizeof(cmd)); + if(select_on_bus() == false) { + return false; + } + + if(spi_write_byte(flash_spi_configuration, cmd) != SPI_DEV_STATUS_OK) { + deselect(); + return false; + } deselect(); i = 0; while(i < 10) { if(verify_part() == VERIFY_PART_POWERED_DOWN) { /* Device is powered down */ - return; + return true; } i++; } /* Should not be required */ deselect(); + return false; } /*---------------------------------------------------------------------------*/ /** @@ -235,8 +266,11 @@ power_standby(void) bool success; cmd = BLS_CODE_RPD; - select_on_bus(); - success = board_spi_write(&cmd, sizeof(cmd)); + if(select_on_bus() == false) { + return false; + } + + success = (spi_write(flash_spi_configuration, &cmd, sizeof(cmd)) == SPI_DEV_STATUS_OK); if(success) { success = wait_ready() == true ? true : false; @@ -257,8 +291,11 @@ write_enable(void) bool ret; const uint8_t wbuf[] = { BLS_CODE_WRITE_ENABLE }; - select_on_bus(); - ret = board_spi_write(wbuf, sizeof(wbuf)); + if(select_on_bus() == false) { + return false; + } + + ret = (spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) == SPI_DEV_STATUS_OK); deselect(); if(ret == false) { @@ -270,11 +307,14 @@ write_enable(void) bool ext_flash_open() { - board_spi_open(4000000, BOARD_IOID_SPI_CLK_FLASH); - - /* GPIO pin configuration */ - ti_lib_ioc_pin_type_gpio_output(BOARD_IOID_FLASH_CS); + /* Check if platform has ext-flash */ + if(flash_spi_configuration->pin_spi_sck == 255) { + return false; + } + if(spi_acquire(flash_spi_configuration) != SPI_DEV_STATUS_OK) { + return false; + } /* Default output to clear chip select */ deselect(); @@ -284,23 +324,29 @@ ext_flash_open() return verify_part() == VERIFY_PART_OK ? true : false; } /*---------------------------------------------------------------------------*/ -void +bool ext_flash_close() { /* Put the part in low power mode */ - power_down(); + if(power_down() == false) { + return false; + } - board_spi_close(); + if(spi_release(flash_spi_configuration) != SPI_DEV_STATUS_OK) { + return false; + } + + return true; } /*---------------------------------------------------------------------------*/ bool -ext_flash_read(size_t offset, size_t length, uint8_t *buf) +ext_flash_read(uint32_t offset, uint32_t length, uint8_t *buf) { uint8_t wbuf[4]; + bool ret; /* Wait till previous erase/program operation completes */ - bool ret = wait_ready(); - if(ret == false) { + if(wait_ready() == false) { return false; } @@ -313,15 +359,17 @@ ext_flash_read(size_t offset, size_t length, uint8_t *buf) wbuf[2] = (offset >> 8) & 0xff; wbuf[3] = offset & 0xff; - select_on_bus(); + if(select_on_bus() == false) { + return false; + } - if(board_spi_write(wbuf, sizeof(wbuf)) == false) { + if(spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) != SPI_DEV_STATUS_OK) { /* failure */ deselect(); return false; } - ret = board_spi_read(buf, length); + ret = (spi_read(flash_spi_configuration, buf, length) == SPI_DEV_STATUS_OK); deselect(); @@ -329,25 +377,22 @@ ext_flash_read(size_t offset, size_t length, uint8_t *buf) } /*---------------------------------------------------------------------------*/ bool -ext_flash_write(size_t offset, size_t length, const uint8_t *buf) +ext_flash_write(uint32_t offset, uint32_t length, const uint8_t *buf) { uint8_t wbuf[4]; - bool ret; - size_t ilen; /* interim length per instruction */ + uint32_t ilen; /* interim length per instruction */ while(length > 0) { /* Wait till previous erase/program operation completes */ - ret = wait_ready(); - if(ret == false) { + if(wait_ready() == false) { return false; } - ret = write_enable(); - if(ret == false) { + if(write_enable() == false) { return false; } - ilen = BLS_PROGRAM_PAGE_SIZE - (offset % BLS_PROGRAM_PAGE_SIZE); + ilen = EXT_FLASH_PROGRAM_PAGE_SIZE - (offset % EXT_FLASH_PROGRAM_PAGE_SIZE); if(length < ilen) { ilen = length; } @@ -365,15 +410,17 @@ ext_flash_write(size_t offset, size_t length, const uint8_t *buf) * is not imposed here since above instructions * should be enough to delay * as much. */ - select_on_bus(); + if(select_on_bus() == false) { + return false; + } - if(board_spi_write(wbuf, sizeof(wbuf)) == false) { + if(spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) != SPI_DEV_STATUS_OK) { /* failure */ deselect(); return false; } - if(board_spi_write(buf, ilen) == false) { + if(spi_write(flash_spi_configuration, buf, ilen) != SPI_DEV_STATUS_OK) { /* failure */ deselect(); return false; @@ -386,7 +433,7 @@ ext_flash_write(size_t offset, size_t length, const uint8_t *buf) } /*---------------------------------------------------------------------------*/ bool -ext_flash_erase(size_t offset, size_t length) +ext_flash_erase(uint32_t offset, uint32_t length) { /* * Note that Block erase might be more efficient when the floor map @@ -394,24 +441,21 @@ ext_flash_erase(size_t offset, size_t length) * sector erase is used blindly. */ uint8_t wbuf[4]; - bool ret; - size_t i, numsectors; - size_t endoffset = offset + length - 1; + uint32_t i, numsectors; + uint32_t endoffset = offset + length - 1; - offset = (offset / BLS_ERASE_SECTOR_SIZE) * BLS_ERASE_SECTOR_SIZE; - numsectors = (endoffset - offset + BLS_ERASE_SECTOR_SIZE - 1) / BLS_ERASE_SECTOR_SIZE; + offset = (offset / EXT_FLASH_ERASE_SECTOR_SIZE) * EXT_FLASH_ERASE_SECTOR_SIZE; + numsectors = (endoffset - offset + EXT_FLASH_ERASE_SECTOR_SIZE - 1) / EXT_FLASH_ERASE_SECTOR_SIZE; wbuf[0] = BLS_CODE_SECTOR_ERASE; for(i = 0; i < numsectors; i++) { /* Wait till previous erase/program operation completes */ - ret = wait_ready(); - if(ret == false) { + if(wait_ready() == false) { return false; } - ret = write_enable(); - if(ret == false) { + if(write_enable() == false) { return false; } @@ -419,16 +463,18 @@ ext_flash_erase(size_t offset, size_t length) wbuf[2] = (offset >> 8) & 0xff; wbuf[3] = offset & 0xff; - select_on_bus(); + if(select_on_bus() == false) { + return false; + } - if(board_spi_write(wbuf, sizeof(wbuf)) == false) { + if(spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) != SPI_DEV_STATUS_OK) { /* failure */ deselect(); return false; } deselect(); - offset += BLS_ERASE_SECTOR_SIZE; + offset += EXT_FLASH_ERASE_SECTOR_SIZE; } return true; @@ -437,19 +483,31 @@ ext_flash_erase(size_t offset, size_t length) bool ext_flash_test(void) { - bool ret; + flash_spi_configuration = &flash_spi_configuration_default; - ret = ext_flash_open(); - ext_flash_close(); + if(ext_flash_open() == false) { + return false; + } - return ret; + if(ext_flash_close() == false) { + return false; + } + + LOG_INFO("Flash test successful\n"); + + return true; } /*---------------------------------------------------------------------------*/ -void -ext_flash_init() +bool +ext_flash_init(spi_device_t *conf) { - ext_flash_open(); - ext_flash_close(); + if(conf == NULL) { + flash_spi_configuration = &flash_spi_configuration_default; + } else { + flash_spi_configuration = conf; + } + + return ext_flash_test(); } /*---------------------------------------------------------------------------*/ /** @} */ diff --git a/arch/platform/srf06-cc26xx/common/ext-flash.h b/os/dev/ext-flash.h similarity index 92% rename from arch/platform/srf06-cc26xx/common/ext-flash.h rename to os/dev/ext-flash.h index 5f2717edb..a14ccdbf0 100644 --- a/arch/platform/srf06-cc26xx/common/ext-flash.h +++ b/os/dev/ext-flash.h @@ -42,6 +42,8 @@ #ifndef EXT_FLASH_H_ #define EXT_FLASH_H_ /*---------------------------------------------------------------------------*/ +#include "spi-hal.h" + #include #include #include @@ -57,7 +59,7 @@ bool ext_flash_open(void); * * This call will put the device in its lower power mode (power down). */ -void ext_flash_close(void); +bool ext_flash_close(void); /** * \brief Read storage content @@ -68,7 +70,7 @@ void ext_flash_close(void); * * buf must be allocated by the caller */ -bool ext_flash_read(size_t offset, size_t length, uint8_t *buf); +bool ext_flash_read(uint32_t offset, uint32_t length, uint8_t *buf); /** * \brief Erase storage sectors corresponding to the range. @@ -79,7 +81,7 @@ bool ext_flash_read(size_t offset, size_t length, uint8_t *buf); * The erase operation will be sector-wise, therefore a call to this function * will generally start the erase procedure at an address lower than offset */ -bool ext_flash_erase(size_t offset, size_t length); +bool ext_flash_erase(uint32_t offset, uint32_t length); /** * \brief Write to storage sectors. @@ -89,7 +91,7 @@ bool ext_flash_erase(size_t offset, size_t length); * * \return True when successful. */ -bool ext_flash_write(size_t offset, size_t length, const uint8_t *buf); +bool ext_flash_write(uint32_t offset, uint32_t length, const uint8_t *buf); /** * \brief Test the flash (power on self-test) @@ -106,7 +108,7 @@ bool ext_flash_test(void); * In order to perform any operation, the caller must first wake the device * up by calling ext_flash_open() */ -void ext_flash_init(void); +bool ext_flash_init(spi_device_t *conf); /*---------------------------------------------------------------------------*/ #endif /* EXT_FLASH_H_ */ /*---------------------------------------------------------------------------*/ From 5e79f0a92215fc6802827b7c11404ef5f45620b7 Mon Sep 17 00:00:00 2001 From: "Xenofon (Fontas) Fafoutis" Date: Tue, 19 Dec 2017 15:43:58 +0000 Subject: [PATCH 06/27] spi hal implementation for sensortag --- .../srf06-cc26xx/sensortag/Makefile.sensortag | 4 +-- arch/platform/srf06-cc26xx/sensortag/board.c | 2 +- .../srf06-cc26xx/sensortag/cc1350/board.h | 30 +++++++++------- .../srf06-cc26xx/sensortag/cc2650/board.h | 34 +++++++++---------- 4 files changed, 37 insertions(+), 33 deletions(-) diff --git a/arch/platform/srf06-cc26xx/sensortag/Makefile.sensortag b/arch/platform/srf06-cc26xx/sensortag/Makefile.sensortag index 46cf25a68..5d528b8dc 100644 --- a/arch/platform/srf06-cc26xx/sensortag/Makefile.sensortag +++ b/arch/platform/srf06-cc26xx/sensortag/Makefile.sensortag @@ -6,5 +6,5 @@ CONTIKI_TARGET_DIRS += sensortag common BOARD_SOURCEFILES += sensortag-sensors.c board-buttons.c sensor-common.c BOARD_SOURCEFILES += bmp-280-sensor.c tmp-007-sensor.c opt-3001-sensor.c BOARD_SOURCEFILES += hdc-1000-sensor.c mpu-9250-sensor.c xmem.c -BOARD_SOURCEFILES += ext-flash.c buzzer.c -BOARD_SOURCEFILES += board.c board-spi.c board-i2c.c +BOARD_SOURCEFILES += buzzer.c +BOARD_SOURCEFILES += board.c board-i2c.c diff --git a/arch/platform/srf06-cc26xx/sensortag/board.c b/arch/platform/srf06-cc26xx/sensortag/board.c index e2069f39f..4b6a69bde 100644 --- a/arch/platform/srf06-cc26xx/sensortag/board.c +++ b/arch/platform/srf06-cc26xx/sensortag/board.c @@ -146,7 +146,7 @@ board_init() buzzer_init(); /* Make sure the external flash is in the lower power mode */ - ext_flash_init(); + ext_flash_init(NULL); lpm_register_module(&sensortag_module); diff --git a/arch/platform/srf06-cc26xx/sensortag/cc1350/board.h b/arch/platform/srf06-cc26xx/sensortag/cc1350/board.h index aa8719eea..bd1de7416 100644 --- a/arch/platform/srf06-cc26xx/sensortag/cc1350/board.h +++ b/arch/platform/srf06-cc26xx/sensortag/cc1350/board.h @@ -113,16 +113,6 @@ #define BOARD_KEY_RIGHT (1 << BOARD_IOID_KEY_RIGHT) /** @} */ /*---------------------------------------------------------------------------*/ -/** - * \brief SPI IOID mappings - * - * Those values are not meant to be modified by the user - * @{ - */ -#define BOARD_IOID_SPI_MOSI IOID_19 -#define BOARD_IOID_SPI_MISO IOID_18 -/** @} */ -/*---------------------------------------------------------------------------*/ /** * \name Buzzer configuration * @{ @@ -145,9 +135,23 @@ * Those values are not meant to be modified by the user * @{ */ -#define BOARD_IOID_FLASH_CS IOID_14 -#define BOARD_FLASH_CS (1 << BOARD_IOID_FLASH_CS) -#define BOARD_IOID_SPI_CLK_FLASH IOID_17 +#define EXT_FLASH_SPI_CONTROLLER BOARD_SPI_CONTROLLER_SPI0 + +#define BOARD_IOID_FLASH_SCK IOID_17 +#define BOARD_IOID_FLASH_MOSI IOID_19 +#define BOARD_IOID_FLASH_MISO IOID_18 +#define BOARD_IOID_FLASH_CS IOID_14 + +#define EXT_FLASH_SPI_PIN_SCK 17 +#define EXT_FLASH_SPI_PIN_MOSI 19 +#define EXT_FLASH_SPI_PIN_MISO 18 +#define EXT_FLASH_SPI_PIN_CS 14 + +#define EXT_FLASH_DEVICE_ID 0x14 +#define EXT_FLASH_MID 0xC2 + +#define EXT_FLASH_PROGRAM_PAGE_SIZE 256 +#define EXT_FLASH_ERASE_SECTOR_SIZE 4096 /** @} */ /*---------------------------------------------------------------------------*/ /** diff --git a/arch/platform/srf06-cc26xx/sensortag/cc2650/board.h b/arch/platform/srf06-cc26xx/sensortag/cc2650/board.h index 9543d2713..7db109ece 100644 --- a/arch/platform/srf06-cc26xx/sensortag/cc2650/board.h +++ b/arch/platform/srf06-cc26xx/sensortag/cc2650/board.h @@ -115,20 +115,6 @@ #define BOARD_KEY_RIGHT (1 << BOARD_IOID_KEY_RIGHT) /** @} */ /*---------------------------------------------------------------------------*/ -/** - * \brief SPI IOID mappings - * - * Those values are not meant to be modified by the user - * @{ - */ -#define BOARD_IOID_SPI_SCK IOID_17 -#define BOARD_IOID_SPI_MOSI IOID_19 -#define BOARD_IOID_SPI_MISO IOID_18 -#define BOARD_SPI_SCK (1 << BOARD_IOID_SPI_SCK) -#define BOARD_SPI_MOSI (1 << BOARD_IOID_SPI_MOSI) -#define BOARD_SPI_MISO (1 << BOARD_IOID_SPI_MISO) -/** @} */ -/*---------------------------------------------------------------------------*/ /** * \name Buzzer configuration * @{ @@ -151,9 +137,23 @@ * Those values are not meant to be modified by the user * @{ */ -#define BOARD_IOID_FLASH_CS IOID_14 -#define BOARD_FLASH_CS (1 << BOARD_IOID_FLASH_CS) -#define BOARD_IOID_SPI_CLK_FLASH IOID_17 +#define EXT_FLASH_SPI_CONTROLLER BOARD_SPI_CONTROLLER_SPI0 + +#define BOARD_IOID_FLASH_SCK IOID_17 +#define BOARD_IOID_FLASH_MOSI IOID_19 +#define BOARD_IOID_FLASH_MISO IOID_18 +#define BOARD_IOID_FLASH_CS IOID_14 + +#define EXT_FLASH_SPI_PIN_SCK 17 +#define EXT_FLASH_SPI_PIN_MOSI 19 +#define EXT_FLASH_SPI_PIN_MISO 18 +#define EXT_FLASH_SPI_PIN_CS 14 + +#define EXT_FLASH_DEVICE_ID 0x14 +#define EXT_FLASH_MID 0xC2 + +#define EXT_FLASH_PROGRAM_PAGE_SIZE 256 +#define EXT_FLASH_ERASE_SECTOR_SIZE 4096 /** @} */ /*---------------------------------------------------------------------------*/ /** From 2a7e9f08356bf290ec7060834c734f878d78c32d Mon Sep 17 00:00:00 2001 From: "Xenofon (Fontas) Fafoutis" Date: Wed, 21 Feb 2018 17:33:29 +0000 Subject: [PATCH 07/27] SPI HAL implementation for CC2538 --- arch/cpu/cc2538/Makefile.cc2538 | 1 + arch/cpu/cc2538/cc2538-conf.h | 3 + arch/cpu/cc2538/dev/spi-hal-arch.c | 359 +++++++++++++++++++++++++++++ arch/cpu/cc2538/dev/spi-hal-arch.h | 84 +++++++ 4 files changed, 447 insertions(+) create mode 100644 arch/cpu/cc2538/dev/spi-hal-arch.c create mode 100644 arch/cpu/cc2538/dev/spi-hal-arch.h diff --git a/arch/cpu/cc2538/Makefile.cc2538 b/arch/cpu/cc2538/Makefile.cc2538 index 03758aa9b..ec2f733b5 100644 --- a/arch/cpu/cc2538/Makefile.cc2538 +++ b/arch/cpu/cc2538/Makefile.cc2538 @@ -16,6 +16,7 @@ CONTIKI_CPU_DIRS = . dev usb usb/common usb/common/cdc-acm ### CPU-dependent source files CONTIKI_CPU_SOURCEFILES += soc.c clock.c rtimer-arch.c uart.c watchdog.c CONTIKI_CPU_SOURCEFILES += nvic.c sys-ctrl.c gpio.c ioc.c spi.c adc.c +CONTIKI_CPU_SOURCEFILES += spi-hal-arch.c CONTIKI_CPU_SOURCEFILES += crypto.c aes.c ecb.c cbc.c ctr.c cbc-mac.c gcm.c CONTIKI_CPU_SOURCEFILES += ccm.c sha256.c gpio-hal-arch.c CONTIKI_CPU_SOURCEFILES += cc2538-aes-128.c cc2538-ccm-star.c diff --git a/arch/cpu/cc2538/cc2538-conf.h b/arch/cpu/cc2538/cc2538-conf.h index 725f95439..b0f2ace0c 100644 --- a/arch/cpu/cc2538/cc2538-conf.h +++ b/arch/cpu/cc2538/cc2538-conf.h @@ -325,6 +325,9 @@ #endif /** @} */ /*---------------------------------------------------------------------------*/ +/* SPI HAL: Path to arch-specific implementation */ +#define SPI_HAL_CONF_ARCH_HDR_PATH "dev/spi-hal-arch.h" +/*---------------------------------------------------------------------------*/ #endif /* CC2538_CONF_H_ */ /*---------------------------------------------------------------------------*/ /** @} */ diff --git a/arch/cpu/cc2538/dev/spi-hal-arch.c b/arch/cpu/cc2538/dev/spi-hal-arch.c new file mode 100644 index 000000000..889fd5588 --- /dev/null +++ b/arch/cpu/cc2538/dev/spi-hal-arch.c @@ -0,0 +1,359 @@ +/* + * Copyright (c) 2016-2017, Yanzi Networks. + * Copyright (c) 2018, University of Bristol. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "contiki.h" +#include "reg.h" +#include "spi-hal.h" +#include "spi-hal-arch.h" +#include "gpio-hal-arch.h" +#include "sys/cc.h" +#include "ioc.h" +#include "sys-ctrl.h" +#include "spi.h" +#include "ssi.h" +#include "gpio.h" +#include "sys/log.h" +#include "sys/mutex.h" +/*---------------------------------------------------------------------------*/ +/* Log configuration */ +#define LOG_MODULE "spi-hal-arch" +#define LOG_LEVEL LOG_LEVEL_NONE +/*---------------------------------------------------------------------------*/ +#if (SPI0_CPRS_CPSDVSR & 1) == 1 || SPI0_CPRS_CPSDVSR < 2 || SPI0_CPRS_CPSDVSR > 254 +#error SPI0_CPRS_CPSDVSR must be an even number between 2 and 254 +#endif + +#if (SPI1_CPRS_CPSDVSR & 1) == 1 || SPI1_CPRS_CPSDVSR < 2 || SPI1_CPRS_CPSDVSR > 254 +#error SPI1_CPRS_CPSDVSR must be an even number between 2 and 254 +#endif +/*---------------------------------------------------------------------------*/ +/* + * Clock source from which the baud clock is determined for the SSI, according + * to SSI_CC.CS. + */ +#define SSI_SYS_CLOCK SYS_CTRL_SYS_CLOCK +/*---------------------------------------------------------------------------*/ +typedef struct { + uint32_t base; + uint32_t ioc_ssirxd_ssi; + uint32_t ioc_pxx_sel_ssi_clkout; + uint32_t ioc_pxx_sel_ssi_txd; + uint8_t ssi_cprs_cpsdvsr; +} spi_regs_t; +/*---------------------------------------------------------------------------*/ +static const spi_regs_t spi_regs[SSI_INSTANCE_COUNT] = { + { + .base = SSI0_BASE, + .ioc_ssirxd_ssi = IOC_SSIRXD_SSI0, + .ioc_pxx_sel_ssi_clkout = IOC_PXX_SEL_SSI0_CLKOUT, + .ioc_pxx_sel_ssi_txd = IOC_PXX_SEL_SSI0_TXD, + .ssi_cprs_cpsdvsr = SPI0_CPRS_CPSDVSR, + }, { + .base = SSI1_BASE, + .ioc_ssirxd_ssi = IOC_SSIRXD_SSI1, + .ioc_pxx_sel_ssi_clkout = IOC_PXX_SEL_SSI1_CLKOUT, + .ioc_pxx_sel_ssi_txd = IOC_PXX_SEL_SSI1_TXD, + .ssi_cprs_cpsdvsr = SPI1_CPRS_CPSDVSR, + } +}; + +typedef struct spi_locks_s { + mutex_t lock; + spi_device_t *owner; +} spi_locks_t; + +/* One lock per SPI controller */ +spi_locks_t board_spi_locks_spi[BOARD_SPI_CONTROLLERS] = { { MUTEX_STATUS_UNLOCKED, NULL } }; + +/*---------------------------------------------------------------------------*/ +static void +spix_wait_tx_ready(spi_device_t *dev) +{ + /* Infinite loop until SR_TNF - Transmit FIFO Not Full */ + while(!(REG(spi_regs[dev->spi_controller].base + SSI_SR) & SSI_SR_TNF)); +} +/*---------------------------------------------------------------------------*/ +static int +spix_read_buf(spi_device_t *dev) +{ + return REG(spi_regs[dev->spi_controller].base + SSI_DR); +} +/*---------------------------------------------------------------------------*/ +static void +spix_write_buf(spi_device_t *dev, int data) +{ + REG(spi_regs[dev->spi_controller].base + SSI_DR) = data; +} +/*---------------------------------------------------------------------------*/ +static void +spix_wait_eotx(spi_device_t *dev) +{ + /* wait until not busy */ + while(REG(spi_regs[dev->spi_controller].base + SSI_SR) & SSI_SR_BSY); +} +/*---------------------------------------------------------------------------*/ +static void +spix_wait_eorx(spi_device_t *dev) +{ + /* wait as long as receive is empty */ + while(!(REG(spi_regs[dev->spi_controller].base + SSI_SR) & SSI_SR_RNE)); +} +/*---------------------------------------------------------------------------*/ +spi_status_t +spi_arch_lock(spi_device_t *dev) +{ + if(mutex_try_lock(&board_spi_locks_spi[dev->spi_controller].lock) == false) { + return SPI_DEV_STATUS_BUS_LOCKED; + } + + board_spi_locks_spi[dev->spi_controller].owner = dev; + + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ +bool +spi_arch_has_lock(spi_device_t *dev) +{ + if(board_spi_locks_spi[dev->spi_controller].owner == dev) { + return true; + } + + return false; +} +/*---------------------------------------------------------------------------*/ +bool +spi_arch_is_bus_locked(spi_device_t *dev) +{ + if(board_spi_locks_spi[dev->spi_controller].lock == MUTEX_STATUS_LOCKED) { + return true; + } + + return false; +} +/*---------------------------------------------------------------------------*/ +spi_status_t +spi_arch_unlock(spi_device_t *dev) +{ + if(!spi_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_NOT_OWNED; + } + + board_spi_locks_spi[dev->spi_controller].owner = NULL; + mutex_unlock(&board_spi_locks_spi[dev->spi_controller].lock); + + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ + +spi_status_t +spi_arch_open(spi_device_t *dev) +{ + uint32_t scr; + uint64_t div; + + uint32_t cs_port = PIN_TO_PORT(dev->pin_spi_cs); + uint32_t cs_pin = PIN_TO_NUM(dev->pin_spi_cs); + + uint32_t clk_port = PIN_TO_PORT(dev->pin_spi_sck); + uint32_t clk_pin = PIN_TO_NUM(dev->pin_spi_sck); + + uint32_t miso_port = PIN_TO_PORT(dev->pin_spi_miso); + uint32_t miso_pin = PIN_TO_NUM(dev->pin_spi_miso); + + uint32_t mosi_port = PIN_TO_PORT(dev->pin_spi_mosi); + uint32_t mosi_pin = PIN_TO_NUM(dev->pin_spi_mosi); + + uint32_t mode = 0; + + if(!spi_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_NOT_OWNED; + } + + /* Set SPI phase */ + if(dev->spi_pha != 0){ + mode = mode | SSI_CR0_SPH; + } + + /* Set SPI polarity */ + if(dev->spi_pol !=0){ + mode = mode | SSI_CR0_SPO; + } + + /* CS pin configuration */ + GPIO_SOFTWARE_CONTROL(GPIO_PORT_TO_BASE(cs_port), + GPIO_PIN_MASK(cs_pin)); + ioc_set_over(cs_port, cs_pin, IOC_OVERRIDE_DIS); + GPIO_SET_OUTPUT(GPIO_PORT_TO_BASE(cs_port), GPIO_PIN_MASK(cs_pin)); + GPIO_SET_PIN(GPIO_PORT_TO_BASE(cs_port), GPIO_PIN_MASK(cs_pin)); + + const spi_regs_t *regs; + + regs = &spi_regs[dev->spi_controller]; + + /* SSI Enable */ + REG(SYS_CTRL_RCGCSSI) |= (1 << dev->spi_controller); + + /* Start by disabling the peripheral before configuring it */ + REG(regs->base + SSI_CR1) = 0; + + /* Set the system clock as the SSI clock */ + REG(regs->base + SSI_CC) = 0; + + /* Set the mux correctly to connect the SSI pins to the correct GPIO pins */ + ioc_set_sel(clk_port, clk_pin, regs->ioc_pxx_sel_ssi_clkout); + ioc_set_sel(mosi_port, mosi_pin, regs->ioc_pxx_sel_ssi_txd); + REG(regs->ioc_ssirxd_ssi) = dev->pin_spi_miso; + + /* Put all the SSI gpios into peripheral mode */ + GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(clk_port), + GPIO_PIN_MASK(clk_pin)); + GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(mosi_port), + GPIO_PIN_MASK(mosi_pin)); + GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(miso_port), + GPIO_PIN_MASK(miso_pin)); + + /* Disable any pull ups or the like */ + ioc_set_over(clk_port, clk_pin, IOC_OVERRIDE_DIS); + ioc_set_over(mosi_port, mosi_pin, IOC_OVERRIDE_DIS); + ioc_set_over(miso_port, miso_pin, IOC_OVERRIDE_DIS); + + /* Configure the clock */ + REG(regs->base + SSI_CPSR) = regs->ssi_cprs_cpsdvsr; + + /* Configure the mode */ + REG(regs->base + SSI_CR0) = mode | (0x07); + + /* Configure the SSI serial clock rate */ + if(!dev->spi_bit_rate) { + scr = 255; + } else { + div = (uint64_t)regs->ssi_cprs_cpsdvsr * dev->spi_bit_rate; + scr = (SSI_SYS_CLOCK + div - 1) / div; + scr = MIN(MAX(scr, 1), 256) - 1; + } + REG(regs->base + SSI_CR0) = (REG(regs->base + SSI_CR0) & ~SSI_CR0_SCR_M) | + scr << SSI_CR0_SCR_S; + + /* Enable the SSI */ + REG(regs->base + SSI_CR1) |= SSI_CR1_SSE; + + return SPI_DEV_STATUS_OK; +} + +/*---------------------------------------------------------------------------*/ +spi_status_t +spi_arch_close(spi_device_t *dev) +{ + if(!spi_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_NOT_OWNED; + } + + /* Disable SSI */ + REG(SYS_CTRL_RCGCSSI) &= ~(1 << dev->spi_controller); + + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ +spi_status_t +spi_arch_select(spi_device_t *dev) +{ + + if(!spi_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_NOT_OWNED; + } + + SPIX_CS_CLR(PIN_TO_PORT(dev->pin_spi_cs), PIN_TO_NUM(dev->pin_spi_cs)); + + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ +spi_status_t +spi_arch_deselect(spi_device_t *dev) +{ + SPIX_CS_SET(PIN_TO_PORT(dev->pin_spi_cs), PIN_TO_NUM(dev->pin_spi_cs)); + + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* Assumes that checking dev and bus is not NULL before calling this */ +spi_status_t +spi_arch_transfer(spi_device_t *dev, + const uint8_t *write_buf, int wlen, + uint8_t *inbuf, int rlen, int ignore_len) +{ + int i; + int totlen; + uint8_t c; + + if(!spi_arch_has_lock(dev)) { + return SPI_DEV_STATUS_BUS_NOT_OWNED; + } + + LOG_DBG("SPI: transfer (r:%d,w:%d) ", rlen, wlen); + + if(write_buf == NULL && wlen > 0) { + return SPI_DEV_STATUS_EINVAL; + } + if(inbuf == NULL && rlen > 0) { + return SPI_DEV_STATUS_EINVAL; + } + + totlen = MAX(rlen + ignore_len, wlen); + + if(totlen == 0) { + /* Nothing to do */ + return SPI_DEV_STATUS_OK; + } + + LOG_DBG("%c%c%c: %u ", rlen > 0 ? 'R' : '-', wlen > 0 ? 'W' : '-', + ignore_len > 0 ? 'S' : '-', totlen); + + for(i = 0; i < totlen; i++) { + spix_wait_tx_ready(dev); + c = i < wlen ? write_buf[i] : 0; + spix_write_buf(dev, c); + LOG_DBG("%c%02x->", i < rlen ? ' ' : '#', c); + spix_wait_eotx(dev); + spix_wait_eorx(dev); + c = spix_read_buf(dev); + if(i < rlen) { + inbuf[i] = c; + } + LOG_DBG("%02x", c); + } + LOG_DBG("\n"); + + return SPI_DEV_STATUS_OK; +} +/*---------------------------------------------------------------------------*/ diff --git a/arch/cpu/cc2538/dev/spi-hal-arch.h b/arch/cpu/cc2538/dev/spi-hal-arch.h new file mode 100644 index 000000000..7eb231496 --- /dev/null +++ b/arch/cpu/cc2538/dev/spi-hal-arch.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2013, University of Michigan. + * + * Copyright (c) 2015, Weptech elektronik GmbH + * Author: Ulf Knoblich, ulf.knoblich@weptech.de + * + * Copyright (c) 2018, University of Bristol. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef SPI_ARCH_H_ +#define SPI_ARCH_H_ +/*---------------------------------------------------------------------------*/ +#define BOARD_SPI_CONTROLLERS 2 +/*---------------------------------------------------------------------------*/ +#define BOARD_SPI_CONTROLLER_SPI0 0 +#define BOARD_SPI_CONTROLLER_SPI1 1 +/*---------------------------------------------------------------------------*/ +/* Default values for the clock rate divider */ +#ifdef SPI0_CONF_CPRS_CPSDVSR +#define SPI0_CPRS_CPSDVSR SPI0_CONF_CPRS_CPSDVSR +#else +#define SPI0_CPRS_CPSDVSR 2 +#endif + +#ifdef SPI1_CONF_CPRS_CPSDVSR +#define SPI1_CPRS_CPSDVSR SPI1_CONF_CPRS_CPSDVSR +#else +#define SPI1_CPRS_CPSDVSR 2 +#endif +/*---------------------------------------------------------------------------*/ +/* New API macros */ +#define SPIX_WAITFORTxREADY(spi) do { \ + while(!(REG(SSI_BASE(spi) + SSI_SR) & SSI_SR_TNF)) ; \ +} while(0) +#define SPIX_BUF(spi) REG(SSI_BASE(spi) + SSI_DR) +#define SPIX_WAITFOREOTx(spi) do { \ + while(REG(SSI_BASE(spi) + SSI_SR) & SSI_SR_BSY) ; \ +} while(0) +#define SPIX_WAITFOREORx(spi) do { \ + while(!(REG(SSI_BASE(spi) + SSI_SR) & SSI_SR_RNE)) ; \ +} while(0) +#define SPIX_FLUSH(spi) do { \ + while(REG(SSI_BASE(spi) + SSI_SR) & SSI_SR_RNE) { \ + SPIX_BUF(spi); \ + } \ +} while(0) +#define SPIX_CS_CLR(port, pin) do { \ + GPIO_CLR_PIN(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin)); \ +} while(0) +#define SPIX_CS_SET(port, pin) do { \ + GPIO_SET_PIN(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin)); \ +} while(0) + +#endif /* SPI_ARCH_H_ */ + +/** + * @} + */ From fe05c6f8655021d2cef5008bfcbbd496e9cc3b16 Mon Sep 17 00:00:00 2001 From: George Oikonomou Date: Fri, 2 Mar 2018 18:06:19 +0000 Subject: [PATCH 08/27] Fix doxygen errors --- os/dev/spi-hal.c | 13 ++++++++++++- os/dev/spi-hal.h | 14 ++++++++++---- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/os/dev/spi-hal.c b/os/dev/spi-hal.c index c8c84bd7c..fcb7a8b3e 100644 --- a/os/dev/spi-hal.c +++ b/os/dev/spi-hal.c @@ -28,7 +28,15 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. */ - +/*---------------------------------------------------------------------------*/ +/** + * \addtogroup spi-hal + * @{ + * + * \file + * Implementation of the platform-independent aspects of the SPI HAL + */ +/*---------------------------------------------------------------------------*/ #include "spi-hal.h" /*---------------------------------------------------------------------------*/ @@ -223,3 +231,6 @@ spi_strobe(spi_device_t *dev, uint8_t strobe, uint8_t *result) return spi_arch_transfer(dev, &strobe, 1, result, 1, 0); } /*---------------------------------------------------------------------------*/ +/** + * @} + */ diff --git a/os/dev/spi-hal.h b/os/dev/spi-hal.h index 901da2a25..7bc5f20ee 100644 --- a/os/dev/spi-hal.h +++ b/os/dev/spi-hal.h @@ -73,6 +73,7 @@ typedef enum { SPI_DEV_STATUS_BUS_NOT_OWNED, /* SPI bus is locked by someone else */ SPI_DEV_STATUS_CLOSED /* SPI bus has not opened properly */ } spi_status_t; +/** @} */ /*---------------------------------------------------------------------------*/ /** * \brief SPI Device Configuration @@ -92,7 +93,7 @@ typedef struct spi_device { uint8_t spi_pol; /* SPI mode polarity */ uint8_t spi_controller; /* ID of SPI controller to use */ } spi_device_t; - +/** @} */ /*---------------------------------------------------------------------------*/ /* These are architecture-independent functions to be used by SPI devices. */ /*---------------------------------------------------------------------------*/ @@ -201,11 +202,11 @@ spi_status_t spi_read_skip(spi_device_t *dev, int size); * \param dev An SPI device configuration. * \param data A pointer to the data to be written. Set it to NULL to * skip writing. - * \param wlen Size of data to write. + * \param wsize Size of data to write. * \param buf A pointer to buffer to copy the data read. Set to NULL * to skip reading. - * \param rlen Size of data to read. - * \param ignore_len Size of data to read and ignore. + * \param rsize Size of data to read. + * \param ignore Size of data to read and ignore. * \return SPI return code * * It should work only if the device has already locked the SPI controller. @@ -347,3 +348,8 @@ spi_status_t spi_arch_select(spi_device_t *dev); spi_status_t spi_arch_deselect(spi_device_t *dev); #endif /* SPI_HAL_H_ */ +/*---------------------------------------------------------------------------*/ +/** + * @} + * @} + */ From e7eee05c7d13c08d5c6ec43a8d74c6bd3f79255e Mon Sep 17 00:00:00 2001 From: George Oikonomou Date: Fri, 2 Mar 2018 18:07:42 +0000 Subject: [PATCH 09/27] Add some inludes explicitly --- arch/cpu/cc2538/dev/spi-hal-arch.h | 12 +++++++----- os/dev/spi-hal.c | 3 +++ 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/cpu/cc2538/dev/spi-hal-arch.h b/arch/cpu/cc2538/dev/spi-hal-arch.h index 7eb231496..876e27af4 100644 --- a/arch/cpu/cc2538/dev/spi-hal-arch.h +++ b/arch/cpu/cc2538/dev/spi-hal-arch.h @@ -32,24 +32,26 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ - +/*---------------------------------------------------------------------------*/ #ifndef SPI_ARCH_H_ #define SPI_ARCH_H_ /*---------------------------------------------------------------------------*/ +#include "contiki.h" +/*---------------------------------------------------------------------------*/ #define BOARD_SPI_CONTROLLERS 2 /*---------------------------------------------------------------------------*/ #define BOARD_SPI_CONTROLLER_SPI0 0 #define BOARD_SPI_CONTROLLER_SPI1 1 /*---------------------------------------------------------------------------*/ /* Default values for the clock rate divider */ -#ifdef SPI0_CONF_CPRS_CPSDVSR -#define SPI0_CPRS_CPSDVSR SPI0_CONF_CPRS_CPSDVSR +#ifdef SPI0_CONF_CPRS_CPSDVSR +#define SPI0_CPRS_CPSDVSR SPI0_CONF_CPRS_CPSDVSR #else #define SPI0_CPRS_CPSDVSR 2 #endif -#ifdef SPI1_CONF_CPRS_CPSDVSR -#define SPI1_CPRS_CPSDVSR SPI1_CONF_CPRS_CPSDVSR +#ifdef SPI1_CONF_CPRS_CPSDVSR +#define SPI1_CPRS_CPSDVSR SPI1_CONF_CPRS_CPSDVSR #else #define SPI1_CPRS_CPSDVSR 2 #endif diff --git a/os/dev/spi-hal.c b/os/dev/spi-hal.c index fcb7a8b3e..532e9323f 100644 --- a/os/dev/spi-hal.c +++ b/os/dev/spi-hal.c @@ -37,8 +37,11 @@ * Implementation of the platform-independent aspects of the SPI HAL */ /*---------------------------------------------------------------------------*/ +#include "contiki.h" #include "spi-hal.h" +#include +#include /*---------------------------------------------------------------------------*/ spi_status_t spi_acquire(spi_device_t *dev) From 4a0dcf5f1e8000d4c466a2f51c8400278884c525 Mon Sep 17 00:00:00 2001 From: George Oikonomou Date: Fri, 2 Mar 2018 18:09:09 +0000 Subject: [PATCH 10/27] Minor code style fixes --- arch/cpu/cc2538/dev/spi-hal-arch.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/arch/cpu/cc2538/dev/spi-hal-arch.c b/arch/cpu/cc2538/dev/spi-hal-arch.c index 889fd5588..7b1469f0a 100644 --- a/arch/cpu/cc2538/dev/spi-hal-arch.c +++ b/arch/cpu/cc2538/dev/spi-hal-arch.c @@ -173,24 +173,24 @@ spi_arch_unlock(spi_device_t *dev) return SPI_DEV_STATUS_OK; } /*---------------------------------------------------------------------------*/ - spi_status_t spi_arch_open(spi_device_t *dev) { + const spi_regs_t *regs; uint32_t scr; uint64_t div; uint32_t cs_port = PIN_TO_PORT(dev->pin_spi_cs); - uint32_t cs_pin = PIN_TO_NUM(dev->pin_spi_cs); + uint32_t cs_pin = PIN_TO_NUM(dev->pin_spi_cs); uint32_t clk_port = PIN_TO_PORT(dev->pin_spi_sck); - uint32_t clk_pin = PIN_TO_NUM(dev->pin_spi_sck); + uint32_t clk_pin = PIN_TO_NUM(dev->pin_spi_sck); uint32_t miso_port = PIN_TO_PORT(dev->pin_spi_miso); - uint32_t miso_pin = PIN_TO_NUM(dev->pin_spi_miso); + uint32_t miso_pin = PIN_TO_NUM(dev->pin_spi_miso); uint32_t mosi_port = PIN_TO_PORT(dev->pin_spi_mosi); - uint32_t mosi_pin = PIN_TO_NUM(dev->pin_spi_mosi); + uint32_t mosi_pin = PIN_TO_NUM(dev->pin_spi_mosi); uint32_t mode = 0; @@ -199,12 +199,12 @@ spi_arch_open(spi_device_t *dev) } /* Set SPI phase */ - if(dev->spi_pha != 0){ + if(dev->spi_pha != 0) { mode = mode | SSI_CR0_SPH; } /* Set SPI polarity */ - if(dev->spi_pol !=0){ + if(dev->spi_pol != 0) { mode = mode | SSI_CR0_SPO; } @@ -215,8 +215,6 @@ spi_arch_open(spi_device_t *dev) GPIO_SET_OUTPUT(GPIO_PORT_TO_BASE(cs_port), GPIO_PIN_MASK(cs_pin)); GPIO_SET_PIN(GPIO_PORT_TO_BASE(cs_port), GPIO_PIN_MASK(cs_pin)); - const spi_regs_t *regs; - regs = &spi_regs[dev->spi_controller]; /* SSI Enable */ @@ -261,14 +259,13 @@ spi_arch_open(spi_device_t *dev) scr = MIN(MAX(scr, 1), 256) - 1; } REG(regs->base + SSI_CR0) = (REG(regs->base + SSI_CR0) & ~SSI_CR0_SCR_M) | - scr << SSI_CR0_SCR_S; + scr << SSI_CR0_SCR_S; /* Enable the SSI */ REG(regs->base + SSI_CR1) |= SSI_CR1_SSE; return SPI_DEV_STATUS_OK; } - /*---------------------------------------------------------------------------*/ spi_status_t spi_arch_close(spi_device_t *dev) @@ -303,14 +300,12 @@ spi_arch_deselect(spi_device_t *dev) return SPI_DEV_STATUS_OK; } -/*---------------------------------------------------------------------------*/ - /*---------------------------------------------------------------------------*/ /* Assumes that checking dev and bus is not NULL before calling this */ spi_status_t spi_arch_transfer(spi_device_t *dev, - const uint8_t *write_buf, int wlen, - uint8_t *inbuf, int rlen, int ignore_len) + const uint8_t *write_buf, int wlen, + uint8_t *inbuf, int rlen, int ignore_len) { int i; int totlen; @@ -337,7 +332,7 @@ spi_arch_transfer(spi_device_t *dev, } LOG_DBG("%c%c%c: %u ", rlen > 0 ? 'R' : '-', wlen > 0 ? 'W' : '-', - ignore_len > 0 ? 'S' : '-', totlen); + ignore_len > 0 ? 'S' : '-', totlen); for(i = 0; i < totlen; i++) { spix_wait_tx_ready(dev); From 06958100445f839ed80451bab5fe65d937ee555b Mon Sep 17 00:00:00 2001 From: George Oikonomou Date: Fri, 2 Mar 2018 19:27:17 +0000 Subject: [PATCH 11/27] Rename old CC2538 SPI driver --- arch/cpu/cc2538/Makefile.cc2538 | 2 +- arch/cpu/cc2538/{spi-arch.h => dev/spi-arch-legacy.h} | 8 ++++---- arch/cpu/cc2538/dev/{spi.c => spi-legacy.c} | 2 +- arch/platform/zoul/dev/cc1200-zoul-arch.c | 2 +- arch/platform/zoul/dev/mmc-arch.c | 2 +- arch/platform/zoul/orion/enc28j60-arch-spi.c | 2 +- 6 files changed, 9 insertions(+), 9 deletions(-) rename arch/cpu/cc2538/{spi-arch.h => dev/spi-arch-legacy.h} (98%) rename arch/cpu/cc2538/dev/{spi.c => spi-legacy.c} (99%) diff --git a/arch/cpu/cc2538/Makefile.cc2538 b/arch/cpu/cc2538/Makefile.cc2538 index ec2f733b5..9d61c2f9a 100644 --- a/arch/cpu/cc2538/Makefile.cc2538 +++ b/arch/cpu/cc2538/Makefile.cc2538 @@ -15,7 +15,7 @@ CONTIKI_CPU_DIRS = . dev usb usb/common usb/common/cdc-acm ### CPU-dependent source files CONTIKI_CPU_SOURCEFILES += soc.c clock.c rtimer-arch.c uart.c watchdog.c -CONTIKI_CPU_SOURCEFILES += nvic.c sys-ctrl.c gpio.c ioc.c spi.c adc.c +CONTIKI_CPU_SOURCEFILES += nvic.c sys-ctrl.c gpio.c ioc.c spi-legacy.c adc.c CONTIKI_CPU_SOURCEFILES += spi-hal-arch.c CONTIKI_CPU_SOURCEFILES += crypto.c aes.c ecb.c cbc.c ctr.c cbc-mac.c gcm.c CONTIKI_CPU_SOURCEFILES += ccm.c sha256.c gpio-hal-arch.c diff --git a/arch/cpu/cc2538/spi-arch.h b/arch/cpu/cc2538/dev/spi-arch-legacy.h similarity index 98% rename from arch/cpu/cc2538/spi-arch.h rename to arch/cpu/cc2538/dev/spi-arch-legacy.h index 8cbb87a8f..0204baefa 100644 --- a/arch/cpu/cc2538/spi-arch.h +++ b/arch/cpu/cc2538/dev/spi-arch-legacy.h @@ -78,8 +78,8 @@ * - SPI1_RX_PORT * - SPI1_RX_PIN */ -#ifndef SPI_ARCH_H_ -#define SPI_ARCH_H_ +#ifndef SPI_ARCH_LEGACY_H_ +#define SPI_ARCH_LEGACY_H_ #include "contiki.h" @@ -138,7 +138,7 @@ #define SPI_WAITFOREOTx() SPIX_WAITFOREOTx(SPI_DEFAULT_INSTANCE) #define SPI_WAITFOREORx() SPIX_WAITFOREORx(SPI_DEFAULT_INSTANCE) #ifdef SPI_FLUSH -#error You must include spi-arch.h before spi.h for the CC2538 +#error You must include spi-arch-legacy.h before spi.h for the CC2538 #else #define SPI_FLUSH() SPIX_FLUSH(SPI_DEFAULT_INSTANCE) #endif @@ -215,7 +215,7 @@ void spix_cs_init(uint8_t port, uint8_t pin); /** @} */ -#endif /* SPI_ARCH_H_ */ +#endif /* SPI_ARCH_LEGACY_H_ */ /** * @} diff --git a/arch/cpu/cc2538/dev/spi.c b/arch/cpu/cc2538/dev/spi-legacy.c similarity index 99% rename from arch/cpu/cc2538/dev/spi.c rename to arch/cpu/cc2538/dev/spi-legacy.c index a0ced2dad..417886638 100644 --- a/arch/cpu/cc2538/dev/spi.c +++ b/arch/cpu/cc2538/dev/spi-legacy.c @@ -39,7 +39,7 @@ */ #include "contiki.h" #include "reg.h" -#include "spi-arch.h" +#include "dev/spi-arch-legacy.h" #include "sys/cc.h" #include "dev/ioc.h" #include "dev/sys-ctrl.h" diff --git a/arch/platform/zoul/dev/cc1200-zoul-arch.c b/arch/platform/zoul/dev/cc1200-zoul-arch.c index 1aff2ef40..fb60d1efc 100644 --- a/arch/platform/zoul/dev/cc1200-zoul-arch.c +++ b/arch/platform/zoul/dev/cc1200-zoul-arch.c @@ -46,7 +46,7 @@ #include "contiki-net.h" #include "dev/leds.h" #include "reg.h" -#include "spi-arch.h" +#include "dev/spi-arch-legacy.h" #include "dev/ioc.h" #include "dev/sys-ctrl.h" #include "dev/spi.h" diff --git a/arch/platform/zoul/dev/mmc-arch.c b/arch/platform/zoul/dev/mmc-arch.c index b2aff5a46..2896448b0 100644 --- a/arch/platform/zoul/dev/mmc-arch.c +++ b/arch/platform/zoul/dev/mmc-arch.c @@ -39,7 +39,7 @@ #include #include #include -#include "spi-arch.h" +#include "dev/spi-arch-legacy.h" #include "dev/ioc.h" #include "dev/gpio.h" #include "dev/spi.h" diff --git a/arch/platform/zoul/orion/enc28j60-arch-spi.c b/arch/platform/zoul/orion/enc28j60-arch-spi.c index 59e6e4260..e68452f89 100644 --- a/arch/platform/zoul/orion/enc28j60-arch-spi.c +++ b/arch/platform/zoul/orion/enc28j60-arch-spi.c @@ -43,7 +43,7 @@ * eth-gw SPI arch specifics */ /*---------------------------------------------------------------------------*/ -#include "spi-arch.h" +#include "dev/spi-arch-legacy.h" #include "spi.h" #include "dev/gpio.h" /*---------------------------------------------------------------------------*/ From f6f0c15421ae27eecf4b93d80b6d857ca730e5b8 Mon Sep 17 00:00:00 2001 From: George Oikonomou Date: Fri, 2 Mar 2018 19:29:46 +0000 Subject: [PATCH 12/27] Rename macro and move to HAL --- .../srf06-cc26xx/launchpad/cc1310/board.h | 2 +- .../srf06-cc26xx/launchpad/cc1350/board.h | 2 +- .../srf06-cc26xx/launchpad/cc2650/board.h | 2 +- .../srf06-cc26xx/sensortag/cc1350/board.h | 2 +- .../srf06-cc26xx/sensortag/cc2650/board.h | 2 +- os/dev/spi-hal.h | 15 +++++++++++++-- 6 files changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/platform/srf06-cc26xx/launchpad/cc1310/board.h b/arch/platform/srf06-cc26xx/launchpad/cc1310/board.h index 81f820a13..41e929571 100644 --- a/arch/platform/srf06-cc26xx/launchpad/cc1310/board.h +++ b/arch/platform/srf06-cc26xx/launchpad/cc1310/board.h @@ -109,7 +109,7 @@ * Those values are not meant to be modified by the user * @{ */ -#define EXT_FLASH_SPI_CONTROLLER BOARD_SPI_CONTROLLER_SPI0 +#define EXT_FLASH_SPI_CONTROLLER SPI_CONTROLLER_SPI0 #define BOARD_IOID_FLASH_SCK IOID_10 #define BOARD_IOID_FLASH_MOSI IOID_9 diff --git a/arch/platform/srf06-cc26xx/launchpad/cc1350/board.h b/arch/platform/srf06-cc26xx/launchpad/cc1350/board.h index 5831221bc..643d69e0b 100644 --- a/arch/platform/srf06-cc26xx/launchpad/cc1350/board.h +++ b/arch/platform/srf06-cc26xx/launchpad/cc1350/board.h @@ -109,7 +109,7 @@ * Those values are not meant to be modified by the user * @{ */ -#define EXT_FLASH_SPI_CONTROLLER BOARD_SPI_CONTROLLER_SPI0 +#define EXT_FLASH_SPI_CONTROLLER SPI_CONTROLLER_SPI0 #define BOARD_IOID_FLASH_SCK IOID_10 #define BOARD_IOID_FLASH_MOSI IOID_9 diff --git a/arch/platform/srf06-cc26xx/launchpad/cc2650/board.h b/arch/platform/srf06-cc26xx/launchpad/cc2650/board.h index 7b2c40403..822e776b8 100644 --- a/arch/platform/srf06-cc26xx/launchpad/cc2650/board.h +++ b/arch/platform/srf06-cc26xx/launchpad/cc2650/board.h @@ -109,7 +109,7 @@ * Those values are not meant to be modified by the user * @{ */ -#define EXT_FLASH_SPI_CONTROLLER BOARD_SPI_CONTROLLER_SPI0 +#define EXT_FLASH_SPI_CONTROLLER SPI_CONTROLLER_SPI0 #define BOARD_IOID_FLASH_SCK IOID_10 #define BOARD_IOID_FLASH_MOSI IOID_9 diff --git a/arch/platform/srf06-cc26xx/sensortag/cc1350/board.h b/arch/platform/srf06-cc26xx/sensortag/cc1350/board.h index bd1de7416..6fdab1295 100644 --- a/arch/platform/srf06-cc26xx/sensortag/cc1350/board.h +++ b/arch/platform/srf06-cc26xx/sensortag/cc1350/board.h @@ -135,7 +135,7 @@ * Those values are not meant to be modified by the user * @{ */ -#define EXT_FLASH_SPI_CONTROLLER BOARD_SPI_CONTROLLER_SPI0 +#define EXT_FLASH_SPI_CONTROLLER SPI_CONTROLLER_SPI0 #define BOARD_IOID_FLASH_SCK IOID_17 #define BOARD_IOID_FLASH_MOSI IOID_19 diff --git a/arch/platform/srf06-cc26xx/sensortag/cc2650/board.h b/arch/platform/srf06-cc26xx/sensortag/cc2650/board.h index 7db109ece..7da0e9458 100644 --- a/arch/platform/srf06-cc26xx/sensortag/cc2650/board.h +++ b/arch/platform/srf06-cc26xx/sensortag/cc2650/board.h @@ -137,7 +137,7 @@ * Those values are not meant to be modified by the user * @{ */ -#define EXT_FLASH_SPI_CONTROLLER BOARD_SPI_CONTROLLER_SPI0 +#define EXT_FLASH_SPI_CONTROLLER SPI_CONTROLLER_SPI0 #define BOARD_IOID_FLASH_SCK IOID_17 #define BOARD_IOID_FLASH_MOSI IOID_19 diff --git a/os/dev/spi-hal.h b/os/dev/spi-hal.h index 7bc5f20ee..b8172bd57 100644 --- a/os/dev/spi-hal.h +++ b/os/dev/spi-hal.h @@ -57,10 +57,21 @@ /* Include Arch-Specific conf */ #ifdef SPI_HAL_CONF_ARCH_HDR_PATH #include SPI_HAL_CONF_ARCH_HDR_PATH -#else /* PLATFORM_IMPLEMENTS_SPI_HAL */ -#define BOARD_SPI_CONTROLLERS 0 #endif /* SPI_HAL_CONF_ARCH_HDR_PATH */ /*---------------------------------------------------------------------------*/ +#ifdef SPI_CONF_CONTROLLER_COUNT +/** + * \brief Number of SPI module instances on a chip + */ +#define SPI_CONTROLLER_COUNT SPI_CONF_CONTROLLER_COUNT +#else +#define SPI_CONTROLLER_COUNT 0 +#endif +/*---------------------------------------------------------------------------*/ +/* Convenience macros to enumerate SPI module instances on a chip */ +#define SPI_CONTROLLER_SPI0 0 +#define SPI_CONTROLLER_SPI1 1 +/*---------------------------------------------------------------------------*/ /** * \brief SPI return codes * From 7160e1dbd2e61ef89ca93d1d6ab9a748b9e18f01 Mon Sep 17 00:00:00 2001 From: George Oikonomou Date: Fri, 2 Mar 2018 19:36:22 +0000 Subject: [PATCH 13/27] Change the way of configuring SPI controller count --- arch/cpu/cc2538/cc2538-def.h | 2 ++ arch/cpu/cc2538/dev/spi-hal-arch.c | 2 +- arch/cpu/cc26xx-cc13xx/cc13xx-cc26xx-def.h | 2 ++ arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c | 4 ++-- os/dev/spi-hal.c | 22 +++++++++++----------- 5 files changed, 18 insertions(+), 14 deletions(-) diff --git a/arch/cpu/cc2538/cc2538-def.h b/arch/cpu/cc2538/cc2538-def.h index 32aed6111..e4c7451a6 100644 --- a/arch/cpu/cc2538/cc2538-def.h +++ b/arch/cpu/cc2538/cc2538-def.h @@ -58,6 +58,8 @@ #define TSCH_CONF_HW_FRAME_FILTERING 0 #endif /* MAC_CONF_WITH_TSCH */ /*---------------------------------------------------------------------------*/ +#define SPI_CONF_CONTROLLER_COUNT 2 +/*---------------------------------------------------------------------------*/ /* Path to CMSIS header */ #define CMSIS_CONF_HEADER_PATH "cc2538_cm3.h" diff --git a/arch/cpu/cc2538/dev/spi-hal-arch.c b/arch/cpu/cc2538/dev/spi-hal-arch.c index 7b1469f0a..0c98ff35a 100644 --- a/arch/cpu/cc2538/dev/spi-hal-arch.c +++ b/arch/cpu/cc2538/dev/spi-hal-arch.c @@ -92,7 +92,7 @@ typedef struct spi_locks_s { } spi_locks_t; /* One lock per SPI controller */ -spi_locks_t board_spi_locks_spi[BOARD_SPI_CONTROLLERS] = { { MUTEX_STATUS_UNLOCKED, NULL } }; +spi_locks_t board_spi_locks_spi[SPI_CONTROLLER_COUNT] = { { MUTEX_STATUS_UNLOCKED, NULL } }; /*---------------------------------------------------------------------------*/ static void diff --git a/arch/cpu/cc26xx-cc13xx/cc13xx-cc26xx-def.h b/arch/cpu/cc26xx-cc13xx/cc13xx-cc26xx-def.h index 7b914ac1e..15db03448 100644 --- a/arch/cpu/cc26xx-cc13xx/cc13xx-cc26xx-def.h +++ b/arch/cpu/cc26xx-cc13xx/cc13xx-cc26xx-def.h @@ -104,5 +104,7 @@ /*---------------------------------------------------------------------------*/ #define GPIO_HAL_CONF_ARCH_SW_TOGGLE 0 /*---------------------------------------------------------------------------*/ +#define SPI_CONF_CONTROLLER_COUNT 2 +/*---------------------------------------------------------------------------*/ #endif /* CC13XX_CC26XX_DEF_H_ */ /*---------------------------------------------------------------------------*/ diff --git a/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c b/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c index c67c0d484..89c3e1c7a 100644 --- a/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c +++ b/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c @@ -42,10 +42,10 @@ typedef struct spi_locks_s { } spi_locks_t; /* One lock per SPI controller */ -spi_locks_t board_spi_locks_spi[BOARD_SPI_CONTROLLERS] = { { MUTEX_STATUS_UNLOCKED, NULL } }; +spi_locks_t board_spi_locks_spi[SPI_CONTROLLER_COUNT] = { { MUTEX_STATUS_UNLOCKED, NULL } }; /* Arch-specific properties of each SPI controller */ -static const board_spi_controller_t spi_controller[BOARD_SPI_CONTROLLERS] = { +static const board_spi_controller_t spi_controller[SPI_CONTROLLER_COUNT] = { { .ssi_base = SSI0_BASE, .power_domain = PRCM_DOMAIN_SERIAL, diff --git a/os/dev/spi-hal.c b/os/dev/spi-hal.c index 532e9323f..f4810a97a 100644 --- a/os/dev/spi-hal.c +++ b/os/dev/spi-hal.c @@ -48,7 +48,7 @@ spi_acquire(spi_device_t *dev) { spi_status_t r; - if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { + if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) { return SPI_DEV_STATUS_EINVAL; } @@ -67,7 +67,7 @@ spi_release(spi_device_t *dev) { spi_status_t r; - if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { + if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) { return SPI_DEV_STATUS_EINVAL; } @@ -96,7 +96,7 @@ spi_deselect(spi_device_t *dev) bool spi_has_bus(spi_device_t *dev) { - if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { + if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) { return false; } @@ -106,7 +106,7 @@ spi_has_bus(spi_device_t *dev) spi_status_t spi_write_byte(spi_device_t *dev, uint8_t data) { - if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { + if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) { return SPI_DEV_STATUS_EINVAL; } @@ -120,7 +120,7 @@ spi_write_byte(spi_device_t *dev, uint8_t data) spi_status_t spi_write(spi_device_t *dev, const uint8_t *data, int size) { - if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { + if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) { return SPI_DEV_STATUS_EINVAL; } @@ -134,7 +134,7 @@ spi_write(spi_device_t *dev, const uint8_t *data, int size) spi_status_t spi_read_byte(spi_device_t *dev, uint8_t *buf) { - if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { + if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) { return SPI_DEV_STATUS_EINVAL; } @@ -148,7 +148,7 @@ spi_read_byte(spi_device_t *dev, uint8_t *buf) spi_status_t spi_read(spi_device_t *dev, uint8_t *buf, int size) { - if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { + if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) { return SPI_DEV_STATUS_EINVAL; } @@ -162,7 +162,7 @@ spi_read(spi_device_t *dev, uint8_t *buf, int size) spi_status_t spi_read_skip(spi_device_t *dev, int size) { - if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { + if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) { return SPI_DEV_STATUS_EINVAL; } @@ -178,7 +178,7 @@ spi_transfer(spi_device_t *dev, const uint8_t *wdata, int wsize, uint8_t *rbuf, int rsize, int ignore) { - if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { + if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) { return SPI_DEV_STATUS_EINVAL; } @@ -201,7 +201,7 @@ spi_status_t spi_read_register(spi_device_t *dev, uint8_t reg, uint8_t *data, int size) { spi_status_t status; - if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { + if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) { return SPI_DEV_STATUS_EINVAL; } @@ -223,7 +223,7 @@ spi_read_register(spi_device_t *dev, uint8_t reg, uint8_t *data, int size) spi_status_t spi_strobe(spi_device_t *dev, uint8_t strobe, uint8_t *result) { - if(dev == NULL || dev->spi_controller >= BOARD_SPI_CONTROLLERS) { + if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) { return SPI_DEV_STATUS_EINVAL; } From 03c63bdd0fd7649bb5f172538d6ca64160d7edfe Mon Sep 17 00:00:00 2001 From: George Oikonomou Date: Fri, 2 Mar 2018 19:37:00 +0000 Subject: [PATCH 14/27] Remove spi-hal-arch.h (CC13xx/CC26xx) --- arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c | 11 ++++- arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.h | 51 ----------------------- arch/platform/srf06-cc26xx/contiki-conf.h | 3 -- 3 files changed, 9 insertions(+), 56 deletions(-) delete mode 100644 arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.h diff --git a/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c b/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c index 89c3e1c7a..cab47d9fa 100644 --- a/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c +++ b/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c @@ -27,10 +27,9 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. */ - +#include "contiki.h" #include "ti-lib.h" #include "spi-hal.h" -#include "spi-hal-arch.h" #include "sys/mutex.h" #include @@ -44,7 +43,15 @@ typedef struct spi_locks_s { /* One lock per SPI controller */ spi_locks_t board_spi_locks_spi[SPI_CONTROLLER_COUNT] = { { MUTEX_STATUS_UNLOCKED, NULL } }; +/*---------------------------------------------------------------------------*/ /* Arch-specific properties of each SPI controller */ +typedef struct board_spi_controller_s { + uint32_t ssi_base; + uint32_t power_domain; + uint32_t prcm_periph; + uint32_t ssi_clkgr_clk_en; +} board_spi_controller_t; + static const board_spi_controller_t spi_controller[SPI_CONTROLLER_COUNT] = { { .ssi_base = SSI0_BASE, diff --git a/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.h b/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.h deleted file mode 100644 index afbe3e6c2..000000000 --- a/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2017, University of Bristol - http://www.bristol.ac.uk/ - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef SPI_ARCH_H_ -#define SPI_ARCH_H_ - -#include "ti-lib.h" - -#include - -/*---------------------------------------------------------------------------*/ -#define BOARD_SPI_CONTROLLERS 2 -/*---------------------------------------------------------------------------*/ -#define BOARD_SPI_CONTROLLER_SPI0 0 -#define BOARD_SPI_CONTROLLER_SPI1 1 -/*---------------------------------------------------------------------------*/ -typedef struct board_spi_controller_s { - uint32_t ssi_base; - uint32_t power_domain; - uint32_t prcm_periph; - uint32_t ssi_clkgr_clk_en; -} board_spi_controller_t; - -#endif /* SPI_ARCH_H_ */ diff --git a/arch/platform/srf06-cc26xx/contiki-conf.h b/arch/platform/srf06-cc26xx/contiki-conf.h index 82daed0c1..4a1470b40 100644 --- a/arch/platform/srf06-cc26xx/contiki-conf.h +++ b/arch/platform/srf06-cc26xx/contiki-conf.h @@ -72,9 +72,6 @@ /* Platform-specific define to signify sensor reading failure */ #define CC26XX_SENSOR_READING_ERROR 0x80000000 /*---------------------------------------------------------------------------*/ -/* SPI HAL: Path to arch-specific implementation */ -#define SPI_HAL_CONF_ARCH_HDR_PATH "dev/spi-hal-arch.h" -/*---------------------------------------------------------------------------*/ /* Include CPU-related configuration */ #include "cc13xx-cc26xx-conf.h" /*---------------------------------------------------------------------------*/ From 34df610fccf08e3f2e37d7223ac331411921d3d9 Mon Sep 17 00:00:00 2001 From: George Oikonomou Date: Fri, 2 Mar 2018 19:45:52 +0000 Subject: [PATCH 15/27] Remove spi-hal-arch.h (CC2538) --- arch/cpu/cc2538/cc2538-conf.h | 3 -- arch/cpu/cc2538/dev/spi-hal-arch.c | 34 +++++++++--- arch/cpu/cc2538/dev/spi-hal-arch.h | 86 ------------------------------ 3 files changed, 27 insertions(+), 96 deletions(-) delete mode 100644 arch/cpu/cc2538/dev/spi-hal-arch.h diff --git a/arch/cpu/cc2538/cc2538-conf.h b/arch/cpu/cc2538/cc2538-conf.h index b0f2ace0c..725f95439 100644 --- a/arch/cpu/cc2538/cc2538-conf.h +++ b/arch/cpu/cc2538/cc2538-conf.h @@ -325,9 +325,6 @@ #endif /** @} */ /*---------------------------------------------------------------------------*/ -/* SPI HAL: Path to arch-specific implementation */ -#define SPI_HAL_CONF_ARCH_HDR_PATH "dev/spi-hal-arch.h" -/*---------------------------------------------------------------------------*/ #endif /* CC2538_CONF_H_ */ /*---------------------------------------------------------------------------*/ /** @} */ diff --git a/arch/cpu/cc2538/dev/spi-hal-arch.c b/arch/cpu/cc2538/dev/spi-hal-arch.c index 0c98ff35a..3493af509 100644 --- a/arch/cpu/cc2538/dev/spi-hal-arch.c +++ b/arch/cpu/cc2538/dev/spi-hal-arch.c @@ -33,7 +33,6 @@ #include "contiki.h" #include "reg.h" #include "spi-hal.h" -#include "spi-hal-arch.h" #include "gpio-hal-arch.h" #include "sys/cc.h" #include "ioc.h" @@ -48,13 +47,34 @@ #define LOG_MODULE "spi-hal-arch" #define LOG_LEVEL LOG_LEVEL_NONE /*---------------------------------------------------------------------------*/ -#if (SPI0_CPRS_CPSDVSR & 1) == 1 || SPI0_CPRS_CPSDVSR < 2 || SPI0_CPRS_CPSDVSR > 254 -#error SPI0_CPRS_CPSDVSR must be an even number between 2 and 254 +/* Default values for the clock rate divider */ +#ifdef SPI_ARCH_CONF_SPI0_CPRS_CPSDVSR +#define SPI_ARCH_SPI0_CPRS_CPSDVSR SPI_ARCH_CONF_SPI0_CPRS_CPSDVSR +#else +#define SPI_ARCH_SPI0_CPRS_CPSDVSR 2 #endif -#if (SPI1_CPRS_CPSDVSR & 1) == 1 || SPI1_CPRS_CPSDVSR < 2 || SPI1_CPRS_CPSDVSR > 254 -#error SPI1_CPRS_CPSDVSR must be an even number between 2 and 254 +#ifdef SPI_ARCH_CONF_SPI1_CPRS_CPSDVSR +#define SPI_ARCH_SPI1_CPRS_CPSDVSR SPI_ARCH_CONF_SPI1_CPRS_CPSDVSR +#else +#define SPI_ARCH_SPI1_CPRS_CPSDVSR 2 #endif + +#if (SPI_ARCH_SPI0_CPRS_CPSDVSR & 1) == 1 || \ + SPI_ARCH_SPI0_CPRS_CPSDVSR < 2 || \ + SPI_ARCH_SPI0_CPRS_CPSDVSR > 254 +#error SPI_ARCH_SPI0_CPRS_CPSDVSR must be an even number between 2 and 254 +#endif + +#if (SPI_ARCH_SPI1_CPRS_CPSDVSR & 1) == 1 || \ + SPI_ARCH_SPI1_CPRS_CPSDVSR < 2 || \ + SPI_ARCH_SPI1_CPRS_CPSDVSR > 254 +#error SPI_ARCH_SPI1_CPRS_CPSDVSR must be an even number between 2 and 254 +#endif +/*---------------------------------------------------------------------------*/ +/* CS set and clear macros */ +#define SPIX_CS_CLR(port, pin) GPIO_CLR_PIN(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin)) +#define SPIX_CS_SET(port, pin) GPIO_SET_PIN(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin)) /*---------------------------------------------------------------------------*/ /* * Clock source from which the baud clock is determined for the SSI, according @@ -76,13 +96,13 @@ static const spi_regs_t spi_regs[SSI_INSTANCE_COUNT] = { .ioc_ssirxd_ssi = IOC_SSIRXD_SSI0, .ioc_pxx_sel_ssi_clkout = IOC_PXX_SEL_SSI0_CLKOUT, .ioc_pxx_sel_ssi_txd = IOC_PXX_SEL_SSI0_TXD, - .ssi_cprs_cpsdvsr = SPI0_CPRS_CPSDVSR, + .ssi_cprs_cpsdvsr = SPI_ARCH_SPI0_CPRS_CPSDVSR, }, { .base = SSI1_BASE, .ioc_ssirxd_ssi = IOC_SSIRXD_SSI1, .ioc_pxx_sel_ssi_clkout = IOC_PXX_SEL_SSI1_CLKOUT, .ioc_pxx_sel_ssi_txd = IOC_PXX_SEL_SSI1_TXD, - .ssi_cprs_cpsdvsr = SPI1_CPRS_CPSDVSR, + .ssi_cprs_cpsdvsr = SPI_ARCH_SPI1_CPRS_CPSDVSR, } }; diff --git a/arch/cpu/cc2538/dev/spi-hal-arch.h b/arch/cpu/cc2538/dev/spi-hal-arch.h deleted file mode 100644 index 876e27af4..000000000 --- a/arch/cpu/cc2538/dev/spi-hal-arch.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2013, University of Michigan. - * - * Copyright (c) 2015, Weptech elektronik GmbH - * Author: Ulf Knoblich, ulf.knoblich@weptech.de - * - * Copyright (c) 2018, University of Bristol. - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -/*---------------------------------------------------------------------------*/ -#ifndef SPI_ARCH_H_ -#define SPI_ARCH_H_ -/*---------------------------------------------------------------------------*/ -#include "contiki.h" -/*---------------------------------------------------------------------------*/ -#define BOARD_SPI_CONTROLLERS 2 -/*---------------------------------------------------------------------------*/ -#define BOARD_SPI_CONTROLLER_SPI0 0 -#define BOARD_SPI_CONTROLLER_SPI1 1 -/*---------------------------------------------------------------------------*/ -/* Default values for the clock rate divider */ -#ifdef SPI0_CONF_CPRS_CPSDVSR -#define SPI0_CPRS_CPSDVSR SPI0_CONF_CPRS_CPSDVSR -#else -#define SPI0_CPRS_CPSDVSR 2 -#endif - -#ifdef SPI1_CONF_CPRS_CPSDVSR -#define SPI1_CPRS_CPSDVSR SPI1_CONF_CPRS_CPSDVSR -#else -#define SPI1_CPRS_CPSDVSR 2 -#endif -/*---------------------------------------------------------------------------*/ -/* New API macros */ -#define SPIX_WAITFORTxREADY(spi) do { \ - while(!(REG(SSI_BASE(spi) + SSI_SR) & SSI_SR_TNF)) ; \ -} while(0) -#define SPIX_BUF(spi) REG(SSI_BASE(spi) + SSI_DR) -#define SPIX_WAITFOREOTx(spi) do { \ - while(REG(SSI_BASE(spi) + SSI_SR) & SSI_SR_BSY) ; \ -} while(0) -#define SPIX_WAITFOREORx(spi) do { \ - while(!(REG(SSI_BASE(spi) + SSI_SR) & SSI_SR_RNE)) ; \ -} while(0) -#define SPIX_FLUSH(spi) do { \ - while(REG(SSI_BASE(spi) + SSI_SR) & SSI_SR_RNE) { \ - SPIX_BUF(spi); \ - } \ -} while(0) -#define SPIX_CS_CLR(port, pin) do { \ - GPIO_CLR_PIN(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin)); \ -} while(0) -#define SPIX_CS_SET(port, pin) do { \ - GPIO_SET_PIN(GPIO_PORT_TO_BASE(port), GPIO_PIN_MASK(pin)); \ -} while(0) - -#endif /* SPI_ARCH_H_ */ - -/** - * @} - */ From 448ee8ae9636891f6cb02d698fc0a3a006458fe8 Mon Sep 17 00:00:00 2001 From: George Oikonomou Date: Fri, 2 Mar 2018 19:58:20 +0000 Subject: [PATCH 16/27] Rename arch-specific SPI HAL implementations --- arch/cpu/cc2538/Makefile.cc2538 | 2 +- arch/cpu/cc2538/dev/{spi-hal-arch.c => spi-arch.c} | 0 arch/cpu/cc26xx-cc13xx/Makefile.cc26xx-cc13xx | 2 +- arch/cpu/cc26xx-cc13xx/dev/{spi-hal-arch.c => spi-arch.c} | 0 4 files changed, 2 insertions(+), 2 deletions(-) rename arch/cpu/cc2538/dev/{spi-hal-arch.c => spi-arch.c} (100%) rename arch/cpu/cc26xx-cc13xx/dev/{spi-hal-arch.c => spi-arch.c} (100%) diff --git a/arch/cpu/cc2538/Makefile.cc2538 b/arch/cpu/cc2538/Makefile.cc2538 index 9d61c2f9a..891215093 100644 --- a/arch/cpu/cc2538/Makefile.cc2538 +++ b/arch/cpu/cc2538/Makefile.cc2538 @@ -16,7 +16,7 @@ CONTIKI_CPU_DIRS = . dev usb usb/common usb/common/cdc-acm ### CPU-dependent source files CONTIKI_CPU_SOURCEFILES += soc.c clock.c rtimer-arch.c uart.c watchdog.c CONTIKI_CPU_SOURCEFILES += nvic.c sys-ctrl.c gpio.c ioc.c spi-legacy.c adc.c -CONTIKI_CPU_SOURCEFILES += spi-hal-arch.c +CONTIKI_CPU_SOURCEFILES += spi-arch.c CONTIKI_CPU_SOURCEFILES += crypto.c aes.c ecb.c cbc.c ctr.c cbc-mac.c gcm.c CONTIKI_CPU_SOURCEFILES += ccm.c sha256.c gpio-hal-arch.c CONTIKI_CPU_SOURCEFILES += cc2538-aes-128.c cc2538-ccm-star.c diff --git a/arch/cpu/cc2538/dev/spi-hal-arch.c b/arch/cpu/cc2538/dev/spi-arch.c similarity index 100% rename from arch/cpu/cc2538/dev/spi-hal-arch.c rename to arch/cpu/cc2538/dev/spi-arch.c diff --git a/arch/cpu/cc26xx-cc13xx/Makefile.cc26xx-cc13xx b/arch/cpu/cc26xx-cc13xx/Makefile.cc26xx-cc13xx index aacc98b62..e72954c17 100644 --- a/arch/cpu/cc26xx-cc13xx/Makefile.cc26xx-cc13xx +++ b/arch/cpu/cc26xx-cc13xx/Makefile.cc26xx-cc13xx @@ -36,7 +36,7 @@ CONTIKI_CPU_SOURCEFILES += gpio-interrupt.c gpio-hal-arch.c oscillators.c CONTIKI_CPU_SOURCEFILES += rf-core.c rf-ble.c ieee-mode.c CONTIKI_CPU_SOURCEFILES += ble-cc2650.c ble-hal-cc26xx.c ble-addr.c rf-ble-cmd.c CONTIKI_CPU_SOURCEFILES += random.c soc-trng.c int-master.c -CONTIKI_CPU_SOURCEFILES += spi-hal-arch.c +CONTIKI_CPU_SOURCEFILES += spi-arch.c MODULES += os/lib/dbg-io diff --git a/arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c b/arch/cpu/cc26xx-cc13xx/dev/spi-arch.c similarity index 100% rename from arch/cpu/cc26xx-cc13xx/dev/spi-hal-arch.c rename to arch/cpu/cc26xx-cc13xx/dev/spi-arch.c From ee4e287fc5d3e34bb5e1f97c880af111ecd30340 Mon Sep 17 00:00:00 2001 From: George Oikonomou Date: Fri, 2 Mar 2018 20:17:46 +0000 Subject: [PATCH 17/27] Rename old SPI API to -legacy.h --- arch/cpu/cc2538/dev/spi-arch-legacy.h | 2 +- arch/cpu/cc2538/dev/spi-arch.c | 1 - arch/cpu/cc2538/dev/spi-legacy.c | 2 +- arch/cpu/msp430/cc2420-arch-sfd.c | 2 +- arch/cpu/msp430/cc2420-arch.c | 2 +- arch/cpu/msp430/cc2520-arch-sfd.c | 2 +- arch/cpu/msp430/cc2520-arch.c | 2 +- arch/dev/cc2420/cc2420.c | 2 +- arch/dev/cc2420/cc2420.h | 2 +- arch/platform/sky/dev/i2c.c | 2 +- arch/platform/sky/dev/xmem.c | 2 +- arch/platform/zoul/dev/cc1200-zoul-arch.c | 2 +- arch/platform/zoul/dev/mmc-arch.c | 2 +- arch/platform/zoul/orion/enc28j60-arch-spi.c | 2 +- os/dev/{spi.h => spi-legacy.h} | 6 +++--- 15 files changed, 16 insertions(+), 17 deletions(-) rename os/dev/{spi.h => spi-legacy.h} (97%) diff --git a/arch/cpu/cc2538/dev/spi-arch-legacy.h b/arch/cpu/cc2538/dev/spi-arch-legacy.h index 0204baefa..de7a765bb 100644 --- a/arch/cpu/cc2538/dev/spi-arch-legacy.h +++ b/arch/cpu/cc2538/dev/spi-arch-legacy.h @@ -138,7 +138,7 @@ #define SPI_WAITFOREOTx() SPIX_WAITFOREOTx(SPI_DEFAULT_INSTANCE) #define SPI_WAITFOREORx() SPIX_WAITFOREORx(SPI_DEFAULT_INSTANCE) #ifdef SPI_FLUSH -#error You must include spi-arch-legacy.h before spi.h for the CC2538 +#error You must include spi-arch-legacy.h before spi-legacy.h for the CC2538 #else #define SPI_FLUSH() SPIX_FLUSH(SPI_DEFAULT_INSTANCE) #endif diff --git a/arch/cpu/cc2538/dev/spi-arch.c b/arch/cpu/cc2538/dev/spi-arch.c index 3493af509..49563e15e 100644 --- a/arch/cpu/cc2538/dev/spi-arch.c +++ b/arch/cpu/cc2538/dev/spi-arch.c @@ -37,7 +37,6 @@ #include "sys/cc.h" #include "ioc.h" #include "sys-ctrl.h" -#include "spi.h" #include "ssi.h" #include "gpio.h" #include "sys/log.h" diff --git a/arch/cpu/cc2538/dev/spi-legacy.c b/arch/cpu/cc2538/dev/spi-legacy.c index 417886638..0070df6ef 100644 --- a/arch/cpu/cc2538/dev/spi-legacy.c +++ b/arch/cpu/cc2538/dev/spi-legacy.c @@ -43,7 +43,7 @@ #include "sys/cc.h" #include "dev/ioc.h" #include "dev/sys-ctrl.h" -#include "dev/spi.h" +#include "dev/spi-legacy.h" #include "dev/ssi.h" #include "dev/gpio.h" /*---------------------------------------------------------------------------*/ diff --git a/arch/cpu/msp430/cc2420-arch-sfd.c b/arch/cpu/msp430/cc2420-arch-sfd.c index 6ab9a1365..d1db81ce0 100644 --- a/arch/cpu/msp430/cc2420-arch-sfd.c +++ b/arch/cpu/msp430/cc2420-arch-sfd.c @@ -29,7 +29,7 @@ */ #include "contiki.h" -#include "dev/spi.h" +#include "dev/spi-legacy.h" #include "cc2420.h" #include "isr_compat.h" diff --git a/arch/cpu/msp430/cc2420-arch.c b/arch/cpu/msp430/cc2420-arch.c index 8a6f0234d..c35ce949f 100644 --- a/arch/cpu/msp430/cc2420-arch.c +++ b/arch/cpu/msp430/cc2420-arch.c @@ -31,7 +31,7 @@ #include "contiki.h" #include "contiki-net.h" -#include "dev/spi.h" +#include "dev/spi-legacy.h" #include "cc2420.h" #include "isr_compat.h" diff --git a/arch/cpu/msp430/cc2520-arch-sfd.c b/arch/cpu/msp430/cc2520-arch-sfd.c index e2671ca58..dc0561f94 100644 --- a/arch/cpu/msp430/cc2520-arch-sfd.c +++ b/arch/cpu/msp430/cc2520-arch-sfd.c @@ -28,7 +28,7 @@ */ #include "contiki.h" -#include "dev/spi.h" +#include "dev/spi-legacy.h" #include "dev/cc2520/cc2520.h" #include "isr_compat.h" diff --git a/arch/cpu/msp430/cc2520-arch.c b/arch/cpu/msp430/cc2520-arch.c index 855f8bc7e..e63735271 100644 --- a/arch/cpu/msp430/cc2520-arch.c +++ b/arch/cpu/msp430/cc2520-arch.c @@ -30,7 +30,7 @@ #include "contiki.h" #include "contiki-net.h" -#include "dev/spi.h" +#include "dev/spi-legacy.h" #include "dev/cc2520/cc2520.h" #include "isr_compat.h" diff --git a/arch/dev/cc2420/cc2420.c b/arch/dev/cc2420/cc2420.c index 00ec64675..9310ec9e4 100644 --- a/arch/dev/cc2420/cc2420.c +++ b/arch/dev/cc2420/cc2420.c @@ -39,7 +39,7 @@ #include "sys/energest.h" #include "dev/leds.h" -#include "dev/spi.h" +#include "dev/spi-legacy.h" #include "cc2420.h" #include "cc2420_const.h" diff --git a/arch/dev/cc2420/cc2420.h b/arch/dev/cc2420/cc2420.h index 74b641ad6..a030632a6 100644 --- a/arch/dev/cc2420/cc2420.h +++ b/arch/dev/cc2420/cc2420.h @@ -43,7 +43,7 @@ #define CC2420_H_ #include "contiki.h" -#include "dev/spi.h" +#include "dev/spi-legacy.h" #include "dev/radio.h" #include "cc2420_const.h" #include "lib/aes-128.h" diff --git a/arch/platform/sky/dev/i2c.c b/arch/platform/sky/dev/i2c.c index b9d10a9c7..1acbe897a 100644 --- a/arch/platform/sky/dev/i2c.c +++ b/arch/platform/sky/dev/i2c.c @@ -41,7 +41,7 @@ #include #include -#include +#include "dev/spi-legacy.h" #include #include "dev/i2c.h" diff --git a/arch/platform/sky/dev/xmem.c b/arch/platform/sky/dev/xmem.c index 21814ad04..4ff525bb8 100644 --- a/arch/platform/sky/dev/xmem.c +++ b/arch/platform/sky/dev/xmem.c @@ -43,7 +43,7 @@ #include #include -#include "dev/spi.h" +#include "dev/spi-legacy.h" #include "dev/xmem.h" #include "dev/watchdog.h" diff --git a/arch/platform/zoul/dev/cc1200-zoul-arch.c b/arch/platform/zoul/dev/cc1200-zoul-arch.c index fb60d1efc..8c9d8cdd7 100644 --- a/arch/platform/zoul/dev/cc1200-zoul-arch.c +++ b/arch/platform/zoul/dev/cc1200-zoul-arch.c @@ -49,7 +49,7 @@ #include "dev/spi-arch-legacy.h" #include "dev/ioc.h" #include "dev/sys-ctrl.h" -#include "dev/spi.h" +#include "dev/spi-legacy.h" #include "dev/ssi.h" #include "dev/gpio.h" #include "dev/gpio-hal.h" diff --git a/arch/platform/zoul/dev/mmc-arch.c b/arch/platform/zoul/dev/mmc-arch.c index 2896448b0..f1eca8d32 100644 --- a/arch/platform/zoul/dev/mmc-arch.c +++ b/arch/platform/zoul/dev/mmc-arch.c @@ -42,7 +42,7 @@ #include "dev/spi-arch-legacy.h" #include "dev/ioc.h" #include "dev/gpio.h" -#include "dev/spi.h" +#include "dev/spi-legacy.h" #include "mmc-arch.h" #define USD_SEL_PORT_BASE GPIO_PORT_TO_BASE(USD_SEL_PORT) diff --git a/arch/platform/zoul/orion/enc28j60-arch-spi.c b/arch/platform/zoul/orion/enc28j60-arch-spi.c index e68452f89..bc9c9dadd 100644 --- a/arch/platform/zoul/orion/enc28j60-arch-spi.c +++ b/arch/platform/zoul/orion/enc28j60-arch-spi.c @@ -44,7 +44,7 @@ */ /*---------------------------------------------------------------------------*/ #include "dev/spi-arch-legacy.h" -#include "spi.h" +#include "dev/spi-legacy.h" #include "dev/gpio.h" /*---------------------------------------------------------------------------*/ #define RESET_PORT GPIO_PORT_TO_BASE(ETH_RESET_PORT) diff --git a/os/dev/spi.h b/os/dev/spi-legacy.h similarity index 97% rename from os/dev/spi.h rename to os/dev/spi-legacy.h index 5960c411b..d1600c785 100644 --- a/os/dev/spi.h +++ b/os/dev/spi-legacy.h @@ -36,8 +36,8 @@ * Niclas Finne */ -#ifndef SPI_H_ -#define SPI_H_ +#ifndef SPI_LEGACY_H_ +#define SPI_LEGACY_H_ /* Define macros to use for checking SPI transmission status depending on if it is possible to wait for TX buffer ready. This is possible @@ -89,4 +89,4 @@ void spi_init(void); } while(0) #endif -#endif /* SPI_H_ */ +#endif /* SPI_LEGACY_H_ */ From 8ea998847ba4537acaa2c7f851962ea30e3f5958 Mon Sep 17 00:00:00 2001 From: George Oikonomou Date: Fri, 2 Mar 2018 20:22:30 +0000 Subject: [PATCH 18/27] Rename old msp430/sky SPI driver --- arch/cpu/msp430/f1xxx/{spi.c => spi-legacy.c} | 0 arch/cpu/msp430/f2xxx/{spi.c => spi-legacy.c} | 0 arch/cpu/msp430/f5xxx/{spi.c => spi-legacy.c} | 0 arch/platform/sky/Makefile.common | 2 +- 4 files changed, 1 insertion(+), 1 deletion(-) rename arch/cpu/msp430/f1xxx/{spi.c => spi-legacy.c} (100%) rename arch/cpu/msp430/f2xxx/{spi.c => spi-legacy.c} (100%) rename arch/cpu/msp430/f5xxx/{spi.c => spi-legacy.c} (100%) diff --git a/arch/cpu/msp430/f1xxx/spi.c b/arch/cpu/msp430/f1xxx/spi-legacy.c similarity index 100% rename from arch/cpu/msp430/f1xxx/spi.c rename to arch/cpu/msp430/f1xxx/spi-legacy.c diff --git a/arch/cpu/msp430/f2xxx/spi.c b/arch/cpu/msp430/f2xxx/spi-legacy.c similarity index 100% rename from arch/cpu/msp430/f2xxx/spi.c rename to arch/cpu/msp430/f2xxx/spi-legacy.c diff --git a/arch/cpu/msp430/f5xxx/spi.c b/arch/cpu/msp430/f5xxx/spi-legacy.c similarity index 100% rename from arch/cpu/msp430/f5xxx/spi.c rename to arch/cpu/msp430/f5xxx/spi-legacy.c diff --git a/arch/platform/sky/Makefile.common b/arch/platform/sky/Makefile.common index 1dea28846..081ffaa9f 100644 --- a/arch/platform/sky/Makefile.common +++ b/arch/platform/sky/Makefile.common @@ -1,6 +1,6 @@ # $Id: Makefile.common,v 1.3 2010/08/24 16:24:11 joxe Exp $ -ARCH=spi.c ds2411.c xmem.c i2c.c node-id.c sensors.c cfs-coffee.c \ +ARCH=spi-legacy.c ds2411.c xmem.c i2c.c node-id.c sensors.c cfs-coffee.c \ cc2420.c cc2420-arch.c cc2420-arch-sfd.c \ sky-sensors.c uip-ipchksum.c \ uart1.c slip_uart1.c uart1-putchar.c platform.c From 2cad6263608bd904153c1a0879480b34bf6c52e0 Mon Sep 17 00:00:00 2001 From: George Oikonomou Date: Fri, 2 Mar 2018 20:37:28 +0000 Subject: [PATCH 19/27] Rename new SPI API to spi.[ch] --- arch/cpu/cc2538/dev/spi-arch.c | 2 +- arch/cpu/cc26xx-cc13xx/dev/spi-arch.c | 2 +- os/dev/ext-flash.c | 2 +- os/dev/ext-flash.h | 3 +-- os/dev/{spi-hal.c => spi.c} | 3 +-- os/dev/{spi-hal.h => spi.h} | 6 +++--- 6 files changed, 8 insertions(+), 10 deletions(-) rename os/dev/{spi-hal.c => spi.c} (99%) rename os/dev/{spi-hal.h => spi.h} (99%) diff --git a/arch/cpu/cc2538/dev/spi-arch.c b/arch/cpu/cc2538/dev/spi-arch.c index 49563e15e..5dc44524a 100644 --- a/arch/cpu/cc2538/dev/spi-arch.c +++ b/arch/cpu/cc2538/dev/spi-arch.c @@ -32,7 +32,7 @@ #include #include "contiki.h" #include "reg.h" -#include "spi-hal.h" +#include "dev/spi.h" #include "gpio-hal-arch.h" #include "sys/cc.h" #include "ioc.h" diff --git a/arch/cpu/cc26xx-cc13xx/dev/spi-arch.c b/arch/cpu/cc26xx-cc13xx/dev/spi-arch.c index cab47d9fa..bda3abbe2 100644 --- a/arch/cpu/cc26xx-cc13xx/dev/spi-arch.c +++ b/arch/cpu/cc26xx-cc13xx/dev/spi-arch.c @@ -29,7 +29,7 @@ */ #include "contiki.h" #include "ti-lib.h" -#include "spi-hal.h" +#include "dev/spi.h" #include "sys/mutex.h" #include diff --git a/os/dev/ext-flash.c b/os/dev/ext-flash.c index b1f428e11..7a0e6735b 100644 --- a/os/dev/ext-flash.c +++ b/os/dev/ext-flash.c @@ -38,7 +38,7 @@ /*---------------------------------------------------------------------------*/ #include "contiki.h" #include "ext-flash.h" -#include "spi-hal.h" +#include "dev/spi.h" #include "gpio-hal.h" #include "sys/log.h" diff --git a/os/dev/ext-flash.h b/os/dev/ext-flash.h index a14ccdbf0..14017ab46 100644 --- a/os/dev/ext-flash.h +++ b/os/dev/ext-flash.h @@ -42,8 +42,7 @@ #ifndef EXT_FLASH_H_ #define EXT_FLASH_H_ /*---------------------------------------------------------------------------*/ -#include "spi-hal.h" - +#include "dev/spi.h" #include #include #include diff --git a/os/dev/spi-hal.c b/os/dev/spi.c similarity index 99% rename from os/dev/spi-hal.c rename to os/dev/spi.c index f4810a97a..d1d678a18 100644 --- a/os/dev/spi-hal.c +++ b/os/dev/spi.c @@ -37,9 +37,8 @@ * Implementation of the platform-independent aspects of the SPI HAL */ /*---------------------------------------------------------------------------*/ +#include #include "contiki.h" -#include "spi-hal.h" - #include #include /*---------------------------------------------------------------------------*/ diff --git a/os/dev/spi-hal.h b/os/dev/spi.h similarity index 99% rename from os/dev/spi-hal.h rename to os/dev/spi.h index b8172bd57..95d079263 100644 --- a/os/dev/spi-hal.h +++ b/os/dev/spi.h @@ -45,8 +45,8 @@ * Header file for the SPI HAL */ /*---------------------------------------------------------------------------*/ -#ifndef SPI_HAL_H_ -#define SPI_HAL_H_ +#ifndef SPI_H_ +#define SPI_H_ /*---------------------------------------------------------------------------*/ #include "contiki.h" #include "gpio-hal.h" @@ -358,7 +358,7 @@ spi_status_t spi_arch_select(spi_device_t *dev); */ spi_status_t spi_arch_deselect(spi_device_t *dev); -#endif /* SPI_HAL_H_ */ +#endif /* SPI_H_ */ /*---------------------------------------------------------------------------*/ /** * @} From d7baa54bd03f5d8fab99da467d953767650c542c Mon Sep 17 00:00:00 2001 From: "Xenofon (Fontas) Fafoutis" Date: Tue, 3 Apr 2018 12:58:47 +0100 Subject: [PATCH 20/27] SPI HAL API: lock()/open() and close()/unlock() merged --- arch/cpu/cc2538/dev/spi-arch.c | 40 ++++++++------------------- arch/cpu/cc26xx-cc13xx/dev/spi-arch.c | 40 ++++++++------------------- os/dev/spi.c | 24 +++------------- os/dev/spi.h | 29 ++++--------------- 4 files changed, 32 insertions(+), 101 deletions(-) diff --git a/arch/cpu/cc2538/dev/spi-arch.c b/arch/cpu/cc2538/dev/spi-arch.c index 5dc44524a..5c554e7e7 100644 --- a/arch/cpu/cc2538/dev/spi-arch.c +++ b/arch/cpu/cc2538/dev/spi-arch.c @@ -147,18 +147,6 @@ spix_wait_eorx(spi_device_t *dev) while(!(REG(spi_regs[dev->spi_controller].base + SSI_SR) & SSI_SR_RNE)); } /*---------------------------------------------------------------------------*/ -spi_status_t -spi_arch_lock(spi_device_t *dev) -{ - if(mutex_try_lock(&board_spi_locks_spi[dev->spi_controller].lock) == false) { - return SPI_DEV_STATUS_BUS_LOCKED; - } - - board_spi_locks_spi[dev->spi_controller].owner = dev; - - return SPI_DEV_STATUS_OK; -} -/*---------------------------------------------------------------------------*/ bool spi_arch_has_lock(spi_device_t *dev) { @@ -180,20 +168,7 @@ spi_arch_is_bus_locked(spi_device_t *dev) } /*---------------------------------------------------------------------------*/ spi_status_t -spi_arch_unlock(spi_device_t *dev) -{ - if(!spi_arch_has_lock(dev)) { - return SPI_DEV_STATUS_BUS_NOT_OWNED; - } - - board_spi_locks_spi[dev->spi_controller].owner = NULL; - mutex_unlock(&board_spi_locks_spi[dev->spi_controller].lock); - - return SPI_DEV_STATUS_OK; -} -/*---------------------------------------------------------------------------*/ -spi_status_t -spi_arch_open(spi_device_t *dev) +spi_arch_lock_and_open(spi_device_t *dev) { const spi_regs_t *regs; uint32_t scr; @@ -213,10 +188,13 @@ spi_arch_open(spi_device_t *dev) uint32_t mode = 0; - if(!spi_arch_has_lock(dev)) { - return SPI_DEV_STATUS_BUS_NOT_OWNED; + /* lock the SPI bus */ + if(mutex_try_lock(&board_spi_locks_spi[dev->spi_controller].lock) == false) { + return SPI_DEV_STATUS_BUS_LOCKED; } + board_spi_locks_spi[dev->spi_controller].owner = dev; + /* Set SPI phase */ if(dev->spi_pha != 0) { mode = mode | SSI_CR0_SPH; @@ -287,7 +265,7 @@ spi_arch_open(spi_device_t *dev) } /*---------------------------------------------------------------------------*/ spi_status_t -spi_arch_close(spi_device_t *dev) +spi_arch_close_and_unlock(spi_device_t *dev) { if(!spi_arch_has_lock(dev)) { return SPI_DEV_STATUS_BUS_NOT_OWNED; @@ -296,6 +274,10 @@ spi_arch_close(spi_device_t *dev) /* Disable SSI */ REG(SYS_CTRL_RCGCSSI) &= ~(1 << dev->spi_controller); + /* Unlock the SPI bus */ + board_spi_locks_spi[dev->spi_controller].owner = NULL; + mutex_unlock(&board_spi_locks_spi[dev->spi_controller].lock); + return SPI_DEV_STATUS_OK; } /*---------------------------------------------------------------------------*/ diff --git a/arch/cpu/cc26xx-cc13xx/dev/spi-arch.c b/arch/cpu/cc26xx-cc13xx/dev/spi-arch.c index bda3abbe2..d274a1d52 100644 --- a/arch/cpu/cc26xx-cc13xx/dev/spi-arch.c +++ b/arch/cpu/cc26xx-cc13xx/dev/spi-arch.c @@ -67,18 +67,6 @@ static const board_spi_controller_t spi_controller[SPI_CONTROLLER_COUNT] = { } }; /*---------------------------------------------------------------------------*/ -spi_status_t -spi_arch_lock(spi_device_t *dev) -{ - if(mutex_try_lock(&board_spi_locks_spi[dev->spi_controller].lock) == false) { - return SPI_DEV_STATUS_BUS_LOCKED; - } - - board_spi_locks_spi[dev->spi_controller].owner = dev; - - return SPI_DEV_STATUS_OK; -} -/*---------------------------------------------------------------------------*/ bool spi_arch_has_lock(spi_device_t *dev) { @@ -99,19 +87,6 @@ spi_arch_is_bus_locked(spi_device_t *dev) return false; } /*---------------------------------------------------------------------------*/ -spi_status_t -spi_arch_unlock(spi_device_t *dev) -{ - if(!spi_arch_has_lock(dev)) { - return SPI_DEV_STATUS_BUS_NOT_OWNED; - } - - board_spi_locks_spi[dev->spi_controller].owner = NULL; - mutex_unlock(&board_spi_locks_spi[dev->spi_controller].lock); - - return SPI_DEV_STATUS_OK; -} -/*---------------------------------------------------------------------------*/ static uint32_t get_mode(spi_device_t *dev) { @@ -128,14 +103,17 @@ get_mode(spi_device_t *dev) } /*---------------------------------------------------------------------------*/ spi_status_t -spi_arch_open(spi_device_t *dev) +spi_arch_lock_and_open(spi_device_t *dev) { uint32_t c; - if(!spi_arch_has_lock(dev)) { - return SPI_DEV_STATUS_BUS_NOT_OWNED; + /* Lock the SPI bus */ + if(mutex_try_lock(&board_spi_locks_spi[dev->spi_controller].lock) == false) { + return SPI_DEV_STATUS_BUS_LOCKED; } + board_spi_locks_spi[dev->spi_controller].owner = dev; + /* CS pin configuration */ ti_lib_ioc_pin_type_gpio_output(dev->pin_spi_cs); @@ -166,7 +144,7 @@ spi_arch_open(spi_device_t *dev) } /*---------------------------------------------------------------------------*/ spi_status_t -spi_arch_close(spi_device_t *dev) +spi_arch_close_and_unlock(spi_device_t *dev) { if(!spi_arch_has_lock(dev)) { return SPI_DEV_STATUS_BUS_NOT_OWNED; @@ -187,6 +165,10 @@ spi_arch_close(spi_device_t *dev) ti_lib_ioc_pin_type_gpio_input(dev->pin_spi_sck); ti_lib_ioc_io_port_pull_set(dev->pin_spi_sck, IOC_IOPULL_DOWN); + /* Unlock the SPI bus */ + board_spi_locks_spi[dev->spi_controller].owner = NULL; + mutex_unlock(&board_spi_locks_spi[dev->spi_controller].lock); + return SPI_DEV_STATUS_OK; } /*---------------------------------------------------------------------------*/ diff --git a/os/dev/spi.c b/os/dev/spi.c index d1d678a18..c41cf206f 100644 --- a/os/dev/spi.c +++ b/os/dev/spi.c @@ -45,39 +45,23 @@ spi_status_t spi_acquire(spi_device_t *dev) { - spi_status_t r; - if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) { return SPI_DEV_STATUS_EINVAL; } - /* lock the bus */ - r = spi_arch_lock(dev); - if(r != SPI_DEV_STATUS_OK) { - return r; - } - - /* open the bus */ - return spi_arch_open(dev); + /* lock and open the bus */ + return spi_arch_lock_and_open(dev); } /*---------------------------------------------------------------------------*/ spi_status_t spi_release(spi_device_t *dev) { - spi_status_t r; - if(dev == NULL || dev->spi_controller >= SPI_CONTROLLER_COUNT) { return SPI_DEV_STATUS_EINVAL; } - /* unlock the bus */ - r = spi_arch_close(dev); - if(r != SPI_DEV_STATUS_OK) { - return r; - } - - /* unlock the bus */ - return spi_arch_unlock(dev); + /* close and unlock the bus */ + return spi_arch_close_and_unlock(dev); } /*---------------------------------------------------------------------------*/ spi_status_t diff --git a/os/dev/spi.h b/os/dev/spi.h index 95d079263..0c9aadc73 100644 --- a/os/dev/spi.h +++ b/os/dev/spi.h @@ -258,24 +258,6 @@ spi_status_t spi_read_register(spi_device_t *dev, uint8_t reg, /* These are architecture-specific functions to be implemented by each CPU. */ /*---------------------------------------------------------------------------*/ -/** - * \brief Locks an SPI controller to device dev. - * \param dev An SPI device configuration which defines the controller - * to be locked and the device that locks it. - * \return SPI return code - * - */ -spi_status_t spi_arch_lock(spi_device_t *dev); - -/** - * \brief Unlocks an SPI controller. - * \param dev An SPI device configuration which defines the controller - * to be unlocked and the device that unlocks it. - * \return SPI return code - * - */ -spi_status_t spi_arch_unlock(spi_device_t *dev); - /** * \brief Checks if a device has locked an SPI controller * \param dev An SPI device configuration which defines the controller @@ -295,7 +277,7 @@ bool spi_arch_has_lock(spi_device_t *dev); bool spi_arch_is_bus_locked(spi_device_t *dev); /** - * \brief Opens an SPI controller to the configuration specified. + * \brief Locks and opens an SPI controller to the configuration specified. * \param dev An SPI device configuration. * \return SPI return code * @@ -303,19 +285,20 @@ bool spi_arch_is_bus_locked(spi_device_t *dev); * controller. * */ -spi_status_t spi_arch_open(spi_device_t *dev); +spi_status_t spi_arch_lock_and_open(spi_device_t *dev); /** - * \brief Closes an SPI controller + * \brief Closes and unlocks an SPI controller * \param dev An SPI device configuration that specifies the controller. * \return SPI return code * - * This should turn off the SPI controller to put it in low power mode. + * This should turn off the SPI controller to put it in low power mode + * and unlock it. * It should work only if the device has already locked the SPI * controller. * */ -spi_status_t spi_arch_close(spi_device_t *dev); +spi_status_t spi_arch_close_and_unlock(spi_device_t *dev); /** * \brief Performs an SPI transfer From 1c335e9faacef063f2c48739bb51e509a19e350e Mon Sep 17 00:00:00 2001 From: "Xenofon (Fontas) Fafoutis" Date: Tue, 3 Apr 2018 13:00:23 +0100 Subject: [PATCH 21/27] fix logging error --- arch/cpu/cc2538/dev/spi-arch.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/cpu/cc2538/dev/spi-arch.c b/arch/cpu/cc2538/dev/spi-arch.c index 5c554e7e7..c876e4ed7 100644 --- a/arch/cpu/cc2538/dev/spi-arch.c +++ b/arch/cpu/cc2538/dev/spi-arch.c @@ -332,23 +332,23 @@ spi_arch_transfer(spi_device_t *dev, return SPI_DEV_STATUS_OK; } - LOG_DBG("%c%c%c: %u ", rlen > 0 ? 'R' : '-', wlen > 0 ? 'W' : '-', + LOG_DBG_("%c%c%c: %u ", rlen > 0 ? 'R' : '-', wlen > 0 ? 'W' : '-', ignore_len > 0 ? 'S' : '-', totlen); for(i = 0; i < totlen; i++) { spix_wait_tx_ready(dev); c = i < wlen ? write_buf[i] : 0; spix_write_buf(dev, c); - LOG_DBG("%c%02x->", i < rlen ? ' ' : '#', c); + LOG_DBG_("%c%02x->", i < rlen ? ' ' : '#', c); spix_wait_eotx(dev); spix_wait_eorx(dev); c = spix_read_buf(dev); if(i < rlen) { inbuf[i] = c; } - LOG_DBG("%02x", c); + LOG_DBG_("%02x", c); } - LOG_DBG("\n"); + LOG_DBG_("\n"); return SPI_DEV_STATUS_OK; } From b4b6ab1bdfadfce01952a038309a87419886ca68 Mon Sep 17 00:00:00 2001 From: "Xenofon (Fontas) Fafoutis" Date: Wed, 4 Apr 2018 11:08:18 +0100 Subject: [PATCH 22/27] improvements in ext-flash driver --- os/dev/ext-flash.c | 167 +++++++++++++++++++++++++-------------------- os/dev/ext-flash.h | 22 +++--- 2 files changed, 105 insertions(+), 84 deletions(-) diff --git a/os/dev/ext-flash.c b/os/dev/ext-flash.c index 7a0e6735b..2d84cbdd7 100644 --- a/os/dev/ext-flash.c +++ b/os/dev/ext-flash.c @@ -109,13 +109,22 @@ static spi_device_t flash_spi_configuration_default = { .spi_pha = 0, .spi_pol = 0 }; - -static spi_device_t *flash_spi_configuration; +/*---------------------------------------------------------------------------*/ +/** + * Get spi configuration, return default configuration if NULL + */ +static spi_device_t* +get_spi_conf(spi_device_t *conf) { + if(conf == NULL) { + return &flash_spi_configuration_default; + } + return conf; +}/*---------------------------------------------------------------------------*/ /** * Clear external flash CSN line */ static bool -select_on_bus(void) +select_on_bus(spi_device_t *flash_spi_configuration) { if(spi_select(flash_spi_configuration) == SPI_DEV_STATUS_OK) { return true; @@ -127,7 +136,7 @@ select_on_bus(void) * Set external flash CSN line */ static void -deselect(void) +deselect(spi_device_t *flash_spi_configuration) { spi_deselect(flash_spi_configuration); } @@ -137,19 +146,19 @@ deselect(void) * \return True when successful. */ static bool -wait_ready(void) +wait_ready(spi_device_t *flash_spi_configuration) { bool ret; const uint8_t wbuf[1] = { BLS_CODE_READ_STATUS }; - if(select_on_bus() == false) { + if(select_on_bus(flash_spi_configuration) == false) { return false; } ret = spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)); if(ret != SPI_DEV_STATUS_OK) { - deselect(); + deselect(flash_spi_configuration); return false; } @@ -164,7 +173,7 @@ wait_ready(void) if(ret != SPI_DEV_STATUS_OK) { /* Error */ - deselect(); + deselect(flash_spi_configuration); return false; } @@ -173,7 +182,7 @@ wait_ready(void) break; } } - deselect(); + deselect(flash_spi_configuration); return true; } /*---------------------------------------------------------------------------*/ @@ -185,23 +194,23 @@ wait_ready(void) * was powered down */ static uint8_t -verify_part(void) +verify_part(spi_device_t *flash_spi_configuration) { const uint8_t wbuf[] = { BLS_CODE_MDID, 0xFF, 0xFF, 0x00 }; uint8_t rbuf[2] = { 0, 0 }; bool ret; - if(select_on_bus() == false) { + if(select_on_bus(flash_spi_configuration) == false) { return VERIFY_PART_LOCKED; } if(spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) != SPI_DEV_STATUS_OK) { - deselect(); + deselect(flash_spi_configuration); return VERIFY_PART_ERROR; } ret = spi_read(flash_spi_configuration, rbuf, sizeof(rbuf)); - deselect(); + deselect(flash_spi_configuration); if(ret != SPI_DEV_STATUS_OK) { return VERIFY_PART_ERROR; } @@ -219,31 +228,31 @@ verify_part(void) * the status register is accessible. */ static bool -power_down(void) +power_down(spi_device_t *flash_spi_configuration) { uint8_t cmd; uint8_t i; /* First, wait for the device to be ready */ - if(wait_ready() == false) { + if(wait_ready(flash_spi_configuration) == false) { /* Entering here will leave the device in standby instead of powerdown */ return false; } cmd = BLS_CODE_PD; - if(select_on_bus() == false) { + if(select_on_bus(flash_spi_configuration) == false) { return false; } if(spi_write_byte(flash_spi_configuration, cmd) != SPI_DEV_STATUS_OK) { - deselect(); + deselect(flash_spi_configuration); return false; } - deselect(); + deselect(flash_spi_configuration); i = 0; while(i < 10) { - if(verify_part() == VERIFY_PART_POWERED_DOWN) { + if(verify_part(flash_spi_configuration) == VERIFY_PART_POWERED_DOWN) { /* Device is powered down */ return true; } @@ -251,7 +260,7 @@ power_down(void) } /* Should not be required */ - deselect(); + deselect(flash_spi_configuration); return false; } /*---------------------------------------------------------------------------*/ @@ -260,23 +269,23 @@ power_down(void) * \return True if the command was written successfully */ static bool -power_standby(void) +power_standby(spi_device_t *flash_spi_configuration) { uint8_t cmd; bool success; cmd = BLS_CODE_RPD; - if(select_on_bus() == false) { + if(select_on_bus(flash_spi_configuration) == false) { return false; } success = (spi_write(flash_spi_configuration, &cmd, sizeof(cmd)) == SPI_DEV_STATUS_OK); if(success) { - success = wait_ready() == true ? true : false; + success = wait_ready(flash_spi_configuration) == true ? true : false; } - deselect(); + deselect(flash_spi_configuration); return success; } @@ -286,17 +295,17 @@ power_standby(void) * \return True when successful. */ static bool -write_enable(void) +write_enable(spi_device_t *flash_spi_configuration) { bool ret; const uint8_t wbuf[] = { BLS_CODE_WRITE_ENABLE }; - if(select_on_bus() == false) { + if(select_on_bus(flash_spi_configuration) == false) { return false; } ret = (spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) == SPI_DEV_STATUS_OK); - deselect(); + deselect(flash_spi_configuration); if(ret == false) { return false; @@ -305,8 +314,12 @@ write_enable(void) } /*---------------------------------------------------------------------------*/ bool -ext_flash_open() +ext_flash_open(spi_device_t *conf) { + spi_device_t *flash_spi_configuration; + + flash_spi_configuration = get_spi_conf(conf); + /* Check if platform has ext-flash */ if(flash_spi_configuration->pin_spi_sck == 255) { return false; @@ -316,37 +329,51 @@ ext_flash_open() return false; } /* Default output to clear chip select */ - deselect(); + deselect(flash_spi_configuration); /* Put the part is standby mode */ - power_standby(); + power_standby(flash_spi_configuration); - return verify_part() == VERIFY_PART_OK ? true : false; + if (verify_part(flash_spi_configuration) == VERIFY_PART_OK) { + return true; + } + + /* Failed to verify */ + spi_release(flash_spi_configuration); + return false; } /*---------------------------------------------------------------------------*/ bool -ext_flash_close() +ext_flash_close(spi_device_t *conf) { - /* Put the part in low power mode */ - if(power_down() == false) { - return false; - } + bool ret; + spi_device_t *flash_spi_configuration; + flash_spi_configuration = get_spi_conf(conf); + + /* Put the part in low power mode */ + ret = power_down(flash_spi_configuration); + + /* SPI is released no matter if power_down() succeeds or fails */ if(spi_release(flash_spi_configuration) != SPI_DEV_STATUS_OK) { return false; } - return true; + return ret; } /*---------------------------------------------------------------------------*/ bool -ext_flash_read(uint32_t offset, uint32_t length, uint8_t *buf) +ext_flash_read(spi_device_t *conf, uint32_t offset, uint32_t length, uint8_t *buf) { uint8_t wbuf[4]; bool ret; + spi_device_t *flash_spi_configuration; + + flash_spi_configuration = get_spi_conf(conf); + /* Wait till previous erase/program operation completes */ - if(wait_ready() == false) { + if(wait_ready(flash_spi_configuration) == false) { return false; } @@ -359,36 +386,40 @@ ext_flash_read(uint32_t offset, uint32_t length, uint8_t *buf) wbuf[2] = (offset >> 8) & 0xff; wbuf[3] = offset & 0xff; - if(select_on_bus() == false) { + if(select_on_bus(flash_spi_configuration) == false) { return false; } if(spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) != SPI_DEV_STATUS_OK) { /* failure */ - deselect(); + deselect(flash_spi_configuration); return false; } ret = (spi_read(flash_spi_configuration, buf, length) == SPI_DEV_STATUS_OK); - deselect(); + deselect(flash_spi_configuration); return ret; } /*---------------------------------------------------------------------------*/ bool -ext_flash_write(uint32_t offset, uint32_t length, const uint8_t *buf) +ext_flash_write(spi_device_t *conf, uint32_t offset, uint32_t length, const uint8_t *buf) { uint8_t wbuf[4]; uint32_t ilen; /* interim length per instruction */ + spi_device_t *flash_spi_configuration; + + flash_spi_configuration = get_spi_conf(conf); + while(length > 0) { /* Wait till previous erase/program operation completes */ - if(wait_ready() == false) { + if(wait_ready(flash_spi_configuration) == false) { return false; } - if(write_enable() == false) { + if(write_enable(flash_spi_configuration) == false) { return false; } @@ -410,30 +441,30 @@ ext_flash_write(uint32_t offset, uint32_t length, const uint8_t *buf) * is not imposed here since above instructions * should be enough to delay * as much. */ - if(select_on_bus() == false) { + if(select_on_bus(flash_spi_configuration) == false) { return false; } if(spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) != SPI_DEV_STATUS_OK) { /* failure */ - deselect(); + deselect(flash_spi_configuration); return false; } if(spi_write(flash_spi_configuration, buf, ilen) != SPI_DEV_STATUS_OK) { /* failure */ - deselect(); + deselect(flash_spi_configuration); return false; } buf += ilen; - deselect(); + deselect(flash_spi_configuration); } return true; } /*---------------------------------------------------------------------------*/ bool -ext_flash_erase(uint32_t offset, uint32_t length) +ext_flash_erase(spi_device_t *conf, uint32_t offset, uint32_t length) { /* * Note that Block erase might be more efficient when the floor map @@ -443,6 +474,10 @@ ext_flash_erase(uint32_t offset, uint32_t length) uint8_t wbuf[4]; uint32_t i, numsectors; uint32_t endoffset = offset + length - 1; + + spi_device_t *flash_spi_configuration; + + flash_spi_configuration = get_spi_conf(conf); offset = (offset / EXT_FLASH_ERASE_SECTOR_SIZE) * EXT_FLASH_ERASE_SECTOR_SIZE; numsectors = (endoffset - offset + EXT_FLASH_ERASE_SECTOR_SIZE - 1) / EXT_FLASH_ERASE_SECTOR_SIZE; @@ -451,11 +486,11 @@ ext_flash_erase(uint32_t offset, uint32_t length) for(i = 0; i < numsectors; i++) { /* Wait till previous erase/program operation completes */ - if(wait_ready() == false) { + if(wait_ready(flash_spi_configuration) == false) { return false; } - if(write_enable() == false) { + if(write_enable(flash_spi_configuration) == false) { return false; } @@ -463,16 +498,16 @@ ext_flash_erase(uint32_t offset, uint32_t length) wbuf[2] = (offset >> 8) & 0xff; wbuf[3] = offset & 0xff; - if(select_on_bus() == false) { + if(select_on_bus(flash_spi_configuration) == false) { return false; } if(spi_write(flash_spi_configuration, wbuf, sizeof(wbuf)) != SPI_DEV_STATUS_OK) { /* failure */ - deselect(); + deselect(flash_spi_configuration); return false; } - deselect(); + deselect(flash_spi_configuration); offset += EXT_FLASH_ERASE_SECTOR_SIZE; } @@ -481,33 +516,19 @@ ext_flash_erase(uint32_t offset, uint32_t length) } /*---------------------------------------------------------------------------*/ bool -ext_flash_test(void) +ext_flash_init(spi_device_t *conf) { - flash_spi_configuration = &flash_spi_configuration_default; - - if(ext_flash_open() == false) { + if(ext_flash_open(conf) == false) { return false; } - if(ext_flash_close() == false) { + if(ext_flash_close(conf) == false) { return false; } - LOG_INFO("Flash test successful\n"); + LOG_INFO("Flash init successful\n"); return true; } /*---------------------------------------------------------------------------*/ -bool -ext_flash_init(spi_device_t *conf) -{ - if(conf == NULL) { - flash_spi_configuration = &flash_spi_configuration_default; - } else { - flash_spi_configuration = conf; - } - - return ext_flash_test(); -} -/*---------------------------------------------------------------------------*/ /** @} */ diff --git a/os/dev/ext-flash.h b/os/dev/ext-flash.h index 14017ab46..8012ee6dd 100644 --- a/os/dev/ext-flash.h +++ b/os/dev/ext-flash.h @@ -49,19 +49,22 @@ /*---------------------------------------------------------------------------*/ /** * \brief Initialize storage driver. + * \param SPI bus configuration struct. NULL for default. * \return True when successful. */ -bool ext_flash_open(void); +bool ext_flash_open(spi_device_t *conf); /** * \brief Close the storage driver + * \param SPI bus configuration struct. NULL for default. * * This call will put the device in its lower power mode (power down). */ -bool ext_flash_close(void); +bool ext_flash_close(spi_device_t *conf); /** * \brief Read storage content + * \param SPI bus configuration struct. NULL for default. * \param offset Address to read from * \param length Number of bytes to read * \param buf Buffer where to store the read bytes @@ -69,10 +72,11 @@ bool ext_flash_close(void); * * buf must be allocated by the caller */ -bool ext_flash_read(uint32_t offset, uint32_t length, uint8_t *buf); +bool ext_flash_read(spi_device_t *conf, uint32_t offset, uint32_t length, uint8_t *buf); /** * \brief Erase storage sectors corresponding to the range. + * \param SPI bus configuration struct. NULL for default. * \param offset Address to start erasing * \param length Number of bytes to erase * \return True when successful. @@ -80,26 +84,22 @@ bool ext_flash_read(uint32_t offset, uint32_t length, uint8_t *buf); * The erase operation will be sector-wise, therefore a call to this function * will generally start the erase procedure at an address lower than offset */ -bool ext_flash_erase(uint32_t offset, uint32_t length); +bool ext_flash_erase(spi_device_t *conf, uint32_t offset, uint32_t length); /** * \brief Write to storage sectors. + * \param SPI bus configuration struct. NULL for default. * \param offset Address to write to * \param length Number of bytes to write * \param buf Buffer holding the bytes to be written * * \return True when successful. */ -bool ext_flash_write(uint32_t offset, uint32_t length, const uint8_t *buf); - -/** - * \brief Test the flash (power on self-test) - * \return True when successful. - */ -bool ext_flash_test(void); +bool ext_flash_write(spi_device_t *conf, uint32_t offset, uint32_t length, const uint8_t *buf); /** * \brief Initialise the external flash + * \param SPI bus configuration struct. NULL for default. * * This function will explicitly put the part in its lowest power mode * (power-down). From 46d1dd129359b04a3fdcedf6365b19221807c7d5 Mon Sep 17 00:00:00 2001 From: "Xenofon (Fontas) Fafoutis" Date: Wed, 4 Apr 2018 11:08:35 +0100 Subject: [PATCH 23/27] update xmem --- arch/platform/srf06-cc26xx/common/xmem.c | 26 ++++++++++++------------ 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/platform/srf06-cc26xx/common/xmem.c b/arch/platform/srf06-cc26xx/common/xmem.c index 5a79be6c1..116991c66 100644 --- a/arch/platform/srf06-cc26xx/common/xmem.c +++ b/arch/platform/srf06-cc26xx/common/xmem.c @@ -60,7 +60,7 @@ void xmem_init(void) { - ext_flash_open(); + ext_flash_open(NULL); } @@ -71,21 +71,21 @@ xmem_pread(void *_p, int size, unsigned long addr) uint8_t x; int i; - rv = ext_flash_open(); + rv = ext_flash_open(NULL); if(!rv) { PRINTF("Could not open flash to save config\n"); - ext_flash_close(); + ext_flash_close(NULL); return -1; } - rv = ext_flash_read(addr, size, _p); + rv = ext_flash_read(NULL, addr, size, _p); for (i = 0; i < size; i++){ x = ~*((uint8_t *)_p + i); *((uint8_t *)_p+i) = x; } - ext_flash_close(); + ext_flash_close(NULL); if(rv) return size; @@ -104,11 +104,11 @@ xmem_pwrite(const void *_buf, int size, unsigned long addr) uint8_t tmp_buf[XMEM_BUFF_LENGHT]; - rv = ext_flash_open(); + rv = ext_flash_open(NULL); if(!rv) { PRINTF("Could not open flash to save config!\n"); - ext_flash_close(); + ext_flash_close(NULL); return -1; } @@ -117,14 +117,14 @@ xmem_pwrite(const void *_buf, int size, unsigned long addr) for (i = 0; i < to_write; i++) { tmp_buf[i] = ~*((uint8_t *)_buf + j + i); } - rv = ext_flash_write(addr + j, to_write, tmp_buf); + rv = ext_flash_write(NULL, addr + j, to_write, tmp_buf); if (!rv) { PRINTF("Could not write flash memory!\n"); return size - remain; } } - ext_flash_close(); + ext_flash_close(NULL); return size; } @@ -135,12 +135,12 @@ xmem_erase(long size, unsigned long addr) { int rv; - rv = ext_flash_open(); + rv = ext_flash_open(NULL); if(!rv) { PRINTF("Could not open flash to save config\n"); - ext_flash_close(); + ext_flash_close(NULL); return -1; } @@ -154,9 +154,9 @@ xmem_erase(long size, unsigned long addr) return -1; } - rv = ext_flash_erase(addr, size); + rv = ext_flash_erase(NULL, addr, size); - ext_flash_close(); + ext_flash_close(NULL); watchdog_periodic(); From ab40997fd0c4553af934b198b4727c1b7034041d Mon Sep 17 00:00:00 2001 From: "Xenofon (Fontas) Fafoutis" Date: Wed, 4 Apr 2018 11:10:25 +0100 Subject: [PATCH 24/27] ext-flash driver: minor with pin unknown --- os/dev/ext-flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/os/dev/ext-flash.c b/os/dev/ext-flash.c index 2d84cbdd7..547ec062c 100644 --- a/os/dev/ext-flash.c +++ b/os/dev/ext-flash.c @@ -321,7 +321,7 @@ ext_flash_open(spi_device_t *conf) flash_spi_configuration = get_spi_conf(conf); /* Check if platform has ext-flash */ - if(flash_spi_configuration->pin_spi_sck == 255) { + if(flash_spi_configuration->pin_spi_sck == GPIO_HAL_PIN_UNKNOWN) { return false; } From 629803c5e527ec2cbf63df19500be117319c4959 Mon Sep 17 00:00:00 2001 From: "Xenofon (Fontas) Fafoutis" Date: Wed, 4 Apr 2018 11:30:10 +0100 Subject: [PATCH 25/27] ext-flash driver moved to arch/dev/ --- arch/dev/ext-flash/README.md | 11 +++++++++++ {os/dev => arch/dev/ext-flash}/ext-flash.c | 0 {os/dev => arch/dev/ext-flash}/ext-flash.h | 0 .../srf06-cc26xx/launchpad/Makefile.launchpad | 2 ++ .../srf06-cc26xx/sensortag/Makefile.sensortag | 2 ++ 5 files changed, 15 insertions(+) create mode 100644 arch/dev/ext-flash/README.md rename {os/dev => arch/dev/ext-flash}/ext-flash.c (100%) rename {os/dev => arch/dev/ext-flash}/ext-flash.h (100%) diff --git a/arch/dev/ext-flash/README.md b/arch/dev/ext-flash/README.md new file mode 100644 index 000000000..a16fb9c49 --- /dev/null +++ b/arch/dev/ext-flash/README.md @@ -0,0 +1,11 @@ +# Ext-flash Driver + +This is a generic driver for external SPI flash memories. It has been tested with the following parts: +- Winbond W25X20CL +- Winbond W25X40CL +- Macronix MX25R8035F +- Macronix MX25R1635F +- Macronix MX25R6435F +- Macronix MX25U6435F + +These parts have identical instruction sets; only the manufacturer and device ID differ, which must be specified in `board.h`. \ No newline at end of file diff --git a/os/dev/ext-flash.c b/arch/dev/ext-flash/ext-flash.c similarity index 100% rename from os/dev/ext-flash.c rename to arch/dev/ext-flash/ext-flash.c diff --git a/os/dev/ext-flash.h b/arch/dev/ext-flash/ext-flash.h similarity index 100% rename from os/dev/ext-flash.h rename to arch/dev/ext-flash/ext-flash.h diff --git a/arch/platform/srf06-cc26xx/launchpad/Makefile.launchpad b/arch/platform/srf06-cc26xx/launchpad/Makefile.launchpad index d3f4ab355..09af79c0b 100644 --- a/arch/platform/srf06-cc26xx/launchpad/Makefile.launchpad +++ b/arch/platform/srf06-cc26xx/launchpad/Makefile.launchpad @@ -4,5 +4,7 @@ CONTIKI_TARGET_DIRS += launchpad common BOARD_SOURCEFILES += board.c board-buttons.c xmem.c +MODULES += arch/dev/ext-flash + ### Signal that we can be programmed with cc2538-bsl BOARD_SUPPORTS_BSL=1 diff --git a/arch/platform/srf06-cc26xx/sensortag/Makefile.sensortag b/arch/platform/srf06-cc26xx/sensortag/Makefile.sensortag index 5d528b8dc..5f7712fef 100644 --- a/arch/platform/srf06-cc26xx/sensortag/Makefile.sensortag +++ b/arch/platform/srf06-cc26xx/sensortag/Makefile.sensortag @@ -8,3 +8,5 @@ BOARD_SOURCEFILES += bmp-280-sensor.c tmp-007-sensor.c opt-3001-sensor.c BOARD_SOURCEFILES += hdc-1000-sensor.c mpu-9250-sensor.c xmem.c BOARD_SOURCEFILES += buzzer.c BOARD_SOURCEFILES += board.c board-i2c.c + +MODULES += arch/dev/ext-flash From f91b223c575d6fdc9f5bbd2bd18e6a87cd5bb56f Mon Sep 17 00:00:00 2001 From: "Xenofon (Fontas) Fafoutis" Date: Wed, 4 Apr 2018 12:23:53 +0100 Subject: [PATCH 26/27] ext-flash: doxygen errors fixed --- arch/dev/ext-flash/ext-flash.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/dev/ext-flash/ext-flash.h b/arch/dev/ext-flash/ext-flash.h index 8012ee6dd..20748a2f0 100644 --- a/arch/dev/ext-flash/ext-flash.h +++ b/arch/dev/ext-flash/ext-flash.h @@ -49,14 +49,15 @@ /*---------------------------------------------------------------------------*/ /** * \brief Initialize storage driver. - * \param SPI bus configuration struct. NULL for default. + * \param conf SPI bus configuration struct. NULL for default. * \return True when successful. */ bool ext_flash_open(spi_device_t *conf); /** * \brief Close the storage driver - * \param SPI bus configuration struct. NULL for default. + * \param conf SPI bus configuration struct. NULL for default. + * \return True when successful. * * This call will put the device in its lower power mode (power down). */ @@ -64,7 +65,7 @@ bool ext_flash_close(spi_device_t *conf); /** * \brief Read storage content - * \param SPI bus configuration struct. NULL for default. + * \param conf SPI bus configuration struct. NULL for default. * \param offset Address to read from * \param length Number of bytes to read * \param buf Buffer where to store the read bytes @@ -76,7 +77,7 @@ bool ext_flash_read(spi_device_t *conf, uint32_t offset, uint32_t length, uint8_ /** * \brief Erase storage sectors corresponding to the range. - * \param SPI bus configuration struct. NULL for default. + * \param conf SPI bus configuration struct. NULL for default. * \param offset Address to start erasing * \param length Number of bytes to erase * \return True when successful. @@ -88,7 +89,7 @@ bool ext_flash_erase(spi_device_t *conf, uint32_t offset, uint32_t length); /** * \brief Write to storage sectors. - * \param SPI bus configuration struct. NULL for default. + * \param conf SPI bus configuration struct. NULL for default. * \param offset Address to write to * \param length Number of bytes to write * \param buf Buffer holding the bytes to be written @@ -99,7 +100,7 @@ bool ext_flash_write(spi_device_t *conf, uint32_t offset, uint32_t length, const /** * \brief Initialise the external flash - * \param SPI bus configuration struct. NULL for default. + * \param conf SPI bus configuration struct. NULL for default. * * This function will explicitly put the part in its lowest power mode * (power-down). From 9d471821a91f3b0bb80b8660e565c4a241434857 Mon Sep 17 00:00:00 2001 From: "Xenofon (Fontas) Fafoutis" Date: Wed, 4 Apr 2018 12:26:58 +0100 Subject: [PATCH 27/27] updated cc26xx-web-demo to new ext-flash api --- .../cc26xx/cc26xx-web-demo/cc26xx-web-demo.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/examples/platform-specific/cc26xx/cc26xx-web-demo/cc26xx-web-demo.c b/examples/platform-specific/cc26xx/cc26xx-web-demo/cc26xx-web-demo.c index 306b54640..f69a19478 100644 --- a/examples/platform-specific/cc26xx/cc26xx-web-demo/cc26xx-web-demo.c +++ b/examples/platform-specific/cc26xx/cc26xx-web-demo/cc26xx-web-demo.c @@ -195,15 +195,15 @@ save_config() int rv; cc26xx_web_demo_sensor_reading_t *reading = NULL; - rv = ext_flash_open(); + rv = ext_flash_open(NULL); if(!rv) { printf("Could not open flash to save config\n"); - ext_flash_close(); + ext_flash_close(NULL); return; } - rv = ext_flash_erase(CONFIG_FLASH_OFFSET, sizeof(cc26xx_web_demo_config_t)); + rv = ext_flash_erase(NULL, CONFIG_FLASH_OFFSET, sizeof(cc26xx_web_demo_config_t)); if(!rv) { printf("Error erasing flash\n"); @@ -220,14 +220,14 @@ save_config() } } - rv = ext_flash_write(CONFIG_FLASH_OFFSET, sizeof(cc26xx_web_demo_config_t), + rv = ext_flash_write(NULL, CONFIG_FLASH_OFFSET, sizeof(cc26xx_web_demo_config_t), (uint8_t *)&cc26xx_web_demo_config); if(!rv) { printf("Error saving config\n"); } } - ext_flash_close(); + ext_flash_close(NULL); #endif } /*---------------------------------------------------------------------------*/ @@ -239,18 +239,18 @@ load_config() cc26xx_web_demo_config_t tmp_cfg; cc26xx_web_demo_sensor_reading_t *reading = NULL; - int rv = ext_flash_open(); + int rv = ext_flash_open(NULL); if(!rv) { printf("Could not open flash to load config\n"); - ext_flash_close(); + ext_flash_close(NULL); return; } - rv = ext_flash_read(CONFIG_FLASH_OFFSET, sizeof(tmp_cfg), + rv = ext_flash_read(NULL, CONFIG_FLASH_OFFSET, sizeof(tmp_cfg), (uint8_t *)&tmp_cfg); - ext_flash_close(); + ext_flash_close(NULL); if(!rv) { printf("Error loading config\n");