enc28j60: Add workaround for erratum #2 "CLKRDY set early"

A delay of 1 ms must be added after the System Reset Command. Still wait
for ESTAT.CLKRDY afterwards as a precaution.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>

dev/enc28j60/enc28j60.c

@@ -298,11 +298,14 @@ reset(void)
     see Section 2.2 “Oscillator Start-up Timer.
   */
 
+  softreset();
+
+  /* Workaround for erratum #2. */
+  clock_delay_usec(1000);
+
   /* Wait for OST */
   while((readreg(ESTAT) & ESTAT_CLKRDY) == 0);
 
-  softreset();
-
   setregbank(ERXTX_BANK);
   /* Set up receive buffer */
   writereg(ERXSTL, RX_BUF_START & 0xff);