From ba6a0bc3811b2244e23a260c941b4fe46a941e4f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?=
 <benoit.thebaudeau.dev@gmail.com>
Date: Tue, 14 Jul 2015 18:46:56 +0200
Subject: [PATCH] enc28j60: Add workaround for erratum #2 "CLKRDY set early"
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A delay of 1 ms must be added after the System Reset Command. Still wait
for ESTAT.CLKRDY afterwards as a precaution.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
---
 dev/enc28j60/enc28j60.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/dev/enc28j60/enc28j60.c b/dev/enc28j60/enc28j60.c
index a112e8ac3..0e6d86a44 100644
--- a/dev/enc28j60/enc28j60.c
+++ b/dev/enc28j60/enc28j60.c
@@ -298,11 +298,14 @@ reset(void)
     see Section 2.2 “Oscillator Start-up Timer.
   */
 
+  softreset();
+
+  /* Workaround for erratum #2. */
+  clock_delay_usec(1000);
+
   /* Wait for OST */
   while((readreg(ESTAT) & ESTAT_CLKRDY) == 0);
 
-  softreset();
-
   setregbank(ERXTX_BANK);
   /* Set up receive buffer */
   writereg(ERXSTL, RX_BUF_START & 0xff);