diff --git a/include/maca.h b/include/maca.h index db2ccf097..be0d4221b 100644 --- a/include/maca.h +++ b/include/maca.h @@ -14,8 +14,6 @@ #define MACA_PREAMBLE 0x8000411c #define gMACA_Clock_DIV_c 95 - -void init_phy(void); //rom_base_adr equ 0x00000000 ; rom base address //ram_base_adr equ 0x00400000 ; ram base address @@ -404,6 +402,130 @@ typedef union maca_maskirq_reg_tag #define MACA_WRITE(reg, src) (reg = src) #define MACA_READ(reg) reg +void reset_maca(void); +void init_phy(void); +void ResumeMACASync(void); + +/* Magic data + +better format + +00402e10 : + 402e10: 80004118 .word 0x80004118 + 402e14: 00180012 .word 0x00180012 + 402e18: 80009204 .word 0x80009204 + 402e1c: 00000605 .word 0x00000605 + 402e20: 80009208 .word 0x80009208 + 402e24: 00000504 .word 0x00000504 + 402e28: 8000920c .word 0x8000920c + 402e2c: 00001111 .word 0x00001111 + 402e30: 80009210 .word 0x80009210 + 402e34: 0fc40000 .word 0x0fc40000 + 402e38: 80009300 .word 0x80009300 + 402e3c: 20046000 .word 0x20046000 + 402e40: 80009304 .word 0x80009304 + 402e44: 4005580c .word 0x4005580c + 402e48: 80009308 .word 0x80009308 + 402e4c: 40075801 .word 0x40075801 + 402e50: 8000930c .word 0x8000930c + 402e54: 4005d801 .word 0x4005d801 + 402e58: 80009310 .word 0x80009310 + 402e5c: 5a45d800 .word 0x5a45d800 + 402e60: 80009314 .word 0x80009314 + 402e64: 4a45d800 .word 0x4a45d800 + 402e68: 80009318 .word 0x80009318 + 402e6c: 40044000 .word 0x40044000 + 402e70: 80009380 .word 0x80009380 + 402e74: 00106000 .word 0x00106000 + 402e78: 80009384 .word 0x80009384 + 402e7c: 00083806 .word 0x00083806 + 402e80: 80009388 .word 0x80009388 + 402e84: 00093807 .word 0x00093807 + 402e88: 8000938c .word 0x8000938c + 402e8c: 0009b804 .word 0x0009b804 + 402e90: 80009390 .word 0x80009390 + 402e94: 000db800 .word 0x000db800 + 402e98: 80009394 .word 0x80009394 + 402e9c: 00093802 .word 0x00093802 + 402ea0: 8000a008 .word 0x8000a008 + 402ea4: 00000015 .word 0x00000015 + 402ea8: 8000a018 .word 0x8000a018 + 402eac: 00000002 .word 0x00000002 + 402eb0: 8000a01c .word 0x8000a01c + 402eb4: 0000000f .word 0x0000000f + 402eb8: 80009424 .word 0x80009424 + 402ebc: 0000aaa0 .word 0x0000aaa0 + 402ec0: 80009434 .word 0x80009434 + 402ec4: 01002020 .word 0x01002020 + 402ec8: 80009438 .word 0x80009438 + 402ecc: 016800fe .word 0x016800fe + 402ed0: 8000943c .word 0x8000943c + 402ed4: 8e578248 .word 0x8e578248 + 402ed8: 80009440 .word 0x80009440 + 402edc: 000000dd .word 0x000000dd + 402ee0: 80009444 .word 0x80009444 + 402ee4: 00000946 .word 0x00000946 + 402ee8: 80009448 .word 0x80009448 + 402eec: 0000035a .word 0x0000035a + 402ef0: 8000944c .word 0x8000944c + 402ef4: 00100010 .word 0x00100010 + 402ef8: 80009450 .word 0x80009450 + 402efc: 00000515 .word 0x00000515 + 402f00: 80009460 .word 0x80009460 + 402f04: 00397feb .word 0x00397feb + 402f08: 80009464 .word 0x80009464 + 402f0c: 00180358 .word 0x00180358 + 402f10: 8000947c .word 0x8000947c + 402f14: 00000455 .word 0x00000455 + 402f18: 800094e0 .word 0x800094e0 + 402f1c: 00000001 .word 0x00000001 + 402f20: 800094e4 .word 0x800094e4 + 402f24: 00020003 .word 0x00020003 + 402f28: 800094e8 .word 0x800094e8 + 402f2c: 00040014 .word 0x00040014 + 402f30: 800094ec .word 0x800094ec + 402f34: 00240034 .word 0x00240034 + 402f38: 800094f0 .word 0x800094f0 + 402f3c: 00440144 .word 0x00440144 + 402f40: 800094f4 .word 0x800094f4 + 402f44: 02440344 .word 0x02440344 + 402f48: 800094f8 .word 0x800094f8 + 402f4c: 04440544 .word 0x04440544 + 402f50: 80009470 .word 0x80009470 + 402f54: 0ee7fc00 .word 0x0ee7fc00 + 402f58: 8000981c .word 0x8000981c + 402f5c: 00000082 .word 0x00000082 + 402f60: 80009828 .word 0x80009828 + 402f64: 0000002a .word 0x0000002a + +appears to be addr addr data data addr addr data data + +e.g. 0x80004118 gets 00180012 (MACA_WARMUP) + +00402e10 : + 402e10: 4118 8000 0012 0018 9204 8000 0605 0000 .A.............. + 402e20: 9208 8000 0504 0000 920c 8000 1111 0000 ................ + 402e30: 9210 8000 0000 0fc4 9300 8000 6000 2004 .............`. + 402e40: 9304 8000 580c 4005 9308 8000 5801 4007 .....X.@.....X.@ + 402e50: 930c 8000 d801 4005 9310 8000 d800 5a45 .......@......EZ + 402e60: 9314 8000 d800 4a45 9318 8000 4000 4004 ......EJ.....@.@ + 402e70: 9380 8000 6000 0010 9384 8000 3806 0008 .....`.......8.. + 402e80: 9388 8000 3807 0009 938c 8000 b804 0009 .....8.......... + 402e90: 9390 8000 b800 000d 9394 8000 3802 0009 .............8.. + 402ea0: a008 8000 0015 0000 a018 8000 0002 0000 ................ + 402eb0: a01c 8000 000f 0000 9424 8000 aaa0 0000 ........$....... + 402ec0: 9434 8000 2020 0100 9438 8000 00fe 0168 4... ..8.....h. + 402ed0: 943c 8000 8248 8e57 9440 8000 00dd 0000 <...H.W.@....... + 402ee0: 9444 8000 0946 0000 9448 8000 035a 0000 D...F...H...Z... + 402ef0: 944c 8000 0010 0010 9450 8000 0515 0000 L.......P....... + 402f00: 9460 8000 7feb 0039 9464 8000 0358 0018 `.....9.d...X... + 402f10: 947c 8000 0455 0000 94e0 8000 0001 0000 |...U........... + 402f20: 94e4 8000 0003 0002 94e8 8000 0014 0004 ................ + 402f30: 94ec 8000 0034 0024 94f0 8000 0144 0044 ....4.$.....D.D. + 402f40: 94f4 8000 0344 0244 94f8 8000 0544 0444 ....D.D.....D.D. + 402f50: 9470 8000 fc00 0ee7 981c 8000 0082 0000 p............... + 402f60: 9828 8000 002a 0000 (...*... +*/ #endif // _MACA_H_ diff --git a/src/maca.c b/src/maca.c index 5a3b421a4..9b3221075 100644 --- a/src/maca.c +++ b/src/maca.c @@ -22,6 +22,81 @@ void init_phy(void) maca_txccadelay = 0x00000025; maca_framesync = 0x000000A7; maca_clk = 0x00000008; - maca_maskirq = 0; //(maca_irq_cm | maca_irq_acpl | maca_irq_rst | maca_irq_di | maca_irq_crc | maca_irq_flt ); +// maca_maskirq = 0; //(maca_irq_cm | maca_irq_acpl | maca_irq_rst | maca_irq_di | maca_irq_crc | maca_irq_flt ); + maca_maskirq = maca_irq_rst; maca_slotoffset = 0x00350000; } + +void reset_maca(void) +{ + uint32_t tmp; + MACA_WRITE(maca_control, control_seq_nop); + do + { + tmp = MACA_READ(maca_status); + } + while ((tmp & maca_status_cc_mask) == cc_not_completed); + + /* Clear all interrupts. */ + MACA_WRITE(maca_clrirq, 0xFFFF); +} + + +/* + * Do the ABORT-Wait-NOP-Wait sequence in order to prevent MACA malfunctioning. + * This seqeunce is synchronous and no interrupts should be triggered when it is done. + */ +void ResumeMACASync(void) +{ + uint32_t clk, TsmRxSteps, LastWarmupStep, LastWarmupData, LastWarmdownStep, LastWarmdownData; +// bool_t tmpIsrStatus; + volatile uint32_t i; + +// ITC_DisableInterrupt(gMacaInt_c); +// AppInterrupts_ProtectFromMACAIrq(tmpIsrStatus); <- Original from MAC code, but not sure how is it implemented + + /* Manual TSM modem shutdown */ + + /* read TSM_RX_STEPS */ + TsmRxSteps = (*((volatile uint32_t *)(0x80009204))); + + /* isolate the RX_WU_STEPS */ + /* shift left to align with 32-bit addressing */ + LastWarmupStep = (TsmRxSteps & 0x1f) << 2; + /* Read "current" TSM step and save this value for later */ + LastWarmupData = (*((volatile uint32_t *)(0x80009300 + LastWarmupStep))); + + /* isolate the RX_WD_STEPS */ + /* right-shift bits down to bit 0 position */ + /* left-shift to align with 32-bit addressing */ + LastWarmdownStep = ((TsmRxSteps & 0x1f00) >> 8) << 2; + /* write "last warmdown data" to current TSM step to shutdown rx */ + LastWarmdownData = (*((volatile uint32_t *)(0x80009300 + LastWarmdownStep))); + (*((volatile uint32_t *)(0x80009300 + LastWarmupStep))) = LastWarmdownData; + + /* Abort */ + MACA_WRITE(maca_control, 1); + + /* Wait ~8us */ + for (clk = maca_clk, i = 0; maca_clk - clk < 3 && i < 300; i++) + ; + + /* NOP */ + MACA_WRITE(maca_control, 0); + + /* Wait ~8us */ + for (clk = maca_clk, i = 0; maca_clk - clk < 3 && i < 300; i++) + ; + + + /* restore original "last warmup step" data to TSM (VERY IMPORTANT!!!) */ + (*((volatile uint32_t *)(0x80009300 + LastWarmupStep))) = LastWarmupData; + + + + /* Clear all MACA interrupts - we should have gotten the ABORT IRQ */ + MACA_WRITE(maca_clrirq, 0xFFFF); + +// AppInterrupts_UnprotectFromMACAIrq(tmpIsrStatus); <- Original from MAC code, but not sure how is it implemented +// ITC_EnableInterrupt(gMacaInt_c); +} diff --git a/tests/rftest-rx.c b/tests/rftest-rx.c index 26d11408c..82a229371 100644 --- a/tests/rftest-rx.c +++ b/tests/rftest-rx.c @@ -17,6 +17,8 @@ #define DELAY 400000 #define DATA 0x00401000; +#define NL "\033[K\r\n" + void putc(uint8_t c); void puts(uint8_t *s); void put_hex(uint8_t x); @@ -26,12 +28,57 @@ void put_hex32(uint32_t x); const uint8_t hex[16]={'0','1','2','3','4','5','6','7', '8','9','a','b','c','d','e','f'}; +void magic(void) { +#define X 0x80009a000 +#define Y 0x80009a008 +#define VAL 0x0000f7df + volatile uint32_t x,y; + x = reg(X); /* get X */ + x &= 0xfffeffff; /* clear bit 16 */ + reg(X) = x; /* put it back */ + y = reg(Y); /* get Y */ + y |= VAL; /* or with the VAL */ + x = reg(X); /* get X again */ + x |= 16; /* or with 16 */ + reg(X) = x; /* put X back */ + reg(Y) = y; /* put Y back */ +} + +uint32_t ackBox[10]; + +#define command_xcvr_rx() \ + do { \ + maca_txlen = (uint32_t)1<<16; \ + maca_dmatx = (uint32_t)&ackBox; \ + maca_dmarx = DATA; \ + maca_tmren = (maca_cpl_clk | maca_soft_clk); \ + maca_control = (control_prm | control_asap | control_seq_rx); \ + }while(FALSE) + + +void dump_regs(uint32_t base, uint32_t len) { + volatile uint32_t i; + + puts("base +0 +4 +8 +c +10 +14 +18 +1c \n\r"); + for (i = 0; i < len; i ++) { + if ((i & 7) == 0) { + put_hex16(4 * i); + } + puts(" "); + put_hex32(reg(base+(4*i))); + if ((i & 7) == 7) + puts(NL); + } + puts(NL); +} + __attribute__ ((section ("startup"))) void main(void) { uint8_t c; volatile uint32_t i; uint32_t tmp; volatile uint32_t *data; + uint16_t status; /* Restore UART regs. to default */ /* in case there is still bootloader state leftover */ @@ -50,27 +97,53 @@ void main(void) { reg(UART1_CON) = 0x00000003; /* enable receive and transmit */ reg(GPIO_FUNC_SEL0) = ( (0x01 << (14*2)) | (0x01 << (15*2)) ); /* set GPIO15-14 to UART (UART1 TX and RX)*/ - reg(80009000) = 0x00050100; + /* turn on the voltage regulators for the radio */ + /* you clod! */ + for(i=0; i> 8) << 2; + /* write "last warmdown data" to current TSM step to shutdown rx */ + LastWarmdownData = (*((volatile uint32_t *)(0x80009300 + LastWarmdownStep))); + + puts("LastWarmdownData: "); + put_hex32(LastWarmdownData); + puts(NL); + + + status = reg(MACA_STATUS) & 0x0000ffff; + switch(status) + { + case(cc_aborted): + { + puts("aborted\n\r"); + ResumeMACASync(); + break; + + } + case(cc_not_completed): + { + puts("not completed\n\r"); + ResumeMACASync(); + break; + + } + case(cc_success): + { + puts("success\n\r"); + break; + + } + default: + { + puts("status: "); + put_hex16(status); + } + } + +/* reg(MACA_CONTROL) = 0x00031a04; /\* receive *\/ */ +/* while (((tmp = reg(MACA_STATUS)) & 15) == 14) */ +/* puts("."); */ +/* puts("complete status is "); put_hex32(tmp); puts(NL); */ +/* puts("1 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */ +/* puts("2 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */ +/* puts("3 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */ + +/* puts(NL); */ +/* for(i=0; i