TSCH: move 10ms and 15ms timeslot timings to separate files
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@ -0,0 +1,61 @@
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/*
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* Copyright (c) 2018, RISE SICS.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki operating system.
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*
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*/
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/**
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* \file
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* IEEE 802.15.4 TSCH timeslot timings for 15ms slots
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* \author
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* Simon Duquennoy <simon.duquennoy@ri.se>
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*
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*/
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#include "contiki.h"
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#include "net/mac/tsch/tsch.h"
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/**
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* \brief 15ms TSCH timeslot timings, required for cc2420 platforms as
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* they are unable to keep up with the defulat 10ms timeslots.
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*/
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uint16_t tsch_timeslot_timing_us_15000[tsch_ts_elements_count] = {
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1800, /* CCAOffset */
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128, /* CCA */
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4000, /* TxOffset */
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(4000 - (TSCH_CONF_RX_WAIT / 2)), /* RxOffset */
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3600, /* RxAckDelay */
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4000, /* TxAckDelay */
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TSCH_CONF_RX_WAIT, /* RxWait */
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800, /* AckWait */
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2072, /* RxTx */
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2400, /* MaxAck */
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4256, /* MaxTx */
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15000, /* TimeslotLength */
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};
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@ -17,7 +17,9 @@
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#define NETSTACK_CONF_RADIO cc2420_driver
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#define NETSTACK_CONF_RADIO cc2420_driver
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#endif /* NETSTACK_CONF_RADIO */
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#endif /* NETSTACK_CONF_RADIO */
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/* TSCH 15ms timeslot timing template, required for cc2420 */
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extern uint16_t tsch_timeslot_timing_us_15000[];
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extern uint16_t tsch_timeslot_timing_us_15000[];
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/* The TSCH default slot length of 10ms is a bit too short for this platform,
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/* The TSCH default slot length of 10ms is a bit too short for this platform,
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* use 15ms instead. */
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* use 15ms instead. */
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#ifndef TSCH_CONF_DEFAULT_TIMESLOT_TIMING
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#ifndef TSCH_CONF_DEFAULT_TIMESLOT_TIMING
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@ -64,22 +64,6 @@ extern int msp430_dco_required;
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#include "experiment-setup.h"
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#include "experiment-setup.h"
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#endif
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#endif
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/* TSCH timeslot timing for platforms requiring 15ms slots */
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uint16_t tsch_timeslot_timing_us_15000[tsch_ts_elements_count] = {
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1800, /* CCAOffset */
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128, /* CCA */
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4000, /* TxOffset */
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(4000 - (TSCH_CONF_RX_WAIT / 2)), /* RxOffset */
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3600, /* RxAckDelay */
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4000, /* TxAckDelay */
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TSCH_CONF_RX_WAIT, /* RxWait */
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800, /* AckWait */
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2072, /* RxTx */
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2400, /* MaxAck */
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4256, /* MaxTx */
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15000, /* TimeslotLength */
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};
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void init_platform(void);
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void init_platform(void);
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Log configuration */
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/* Log configuration */
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@ -0,0 +1,79 @@
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/*
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* Copyright (c) 2018, RISE SICS.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki operating system.
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*
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*/
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/**
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* \file
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* IEEE 802.15.4 TSCH timeslot timings
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* \author
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* Simon Duquennoy <simon.duquennoy@ri.se>
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*
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*/
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/**
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* \addtogroup tsch
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* @{
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*/
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#include "contiki.h"
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#include "net/mac/tsch/tsch.h"
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/**
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* \brief The default timeslot timing in the standard is a guard time of
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* 2200 us, a Tx offset of 2120 us and a Rx offset of 1120 us.
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* As a result, the listening device has a guard time not centered
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* on the expected Tx time. This is to be fixed in the next iteration
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* of the standard. This can be enabled with:
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* TxOffset: 2120
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* RxOffset: 1120
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* RxWait: 2200
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*
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* Instead, we align the Rx guard time on expected Tx time. The Rx
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* guard time is user-configurable with TSCH_CONF_RX_WAIT.
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* (TxOffset - (RxWait / 2)) instead
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*/
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uint16_t tsch_timeslot_timing_us_10000[tsch_ts_elements_count] = {
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1800, /* CCAOffset */
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128, /* CCA */
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2120, /* TxOffset */
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(2120 - (TSCH_CONF_RX_WAIT / 2)), /* RxOffset */
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800, /* RxAckDelay */
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1000, /* TxAckDelay */
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TSCH_CONF_RX_WAIT, /* RxWait */
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400, /* AckWait */
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192, /* RxTx */
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2400, /* MaxAck */
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4256, /* MaxTx */
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10000, /* TimeslotLength */
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};
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/** @} */
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@ -101,34 +101,6 @@ NBR_TABLE(struct eb_stat, eb_stats);
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uint8_t tsch_hopping_sequence[TSCH_HOPPING_SEQUENCE_MAX_LEN];
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uint8_t tsch_hopping_sequence[TSCH_HOPPING_SEQUENCE_MAX_LEN];
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struct tsch_asn_divisor_t tsch_hopping_sequence_length;
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struct tsch_asn_divisor_t tsch_hopping_sequence_length;
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/* The default timeslot timing in the standard is a guard time of
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* 2200 us, a Tx offset of 2120 us and a Rx offset of 1120 us.
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* As a result, the listening device has a guard time not centered
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* on the expected Tx time. This is to be fixed in the next iteration
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* of the standard. This can be enabled with:
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* TxOffset: 2120
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* RxOffset: 1120
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* RxWait: 2200
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*
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* Instead, we align the Rx guard time on expected Tx time. The Rx
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* guard time is user-configurable with TSCH_CONF_RX_WAIT.
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* (TxOffset - (RxWait / 2)) instead */
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uint16_t tsch_timeslot_timing_us_10000[tsch_ts_elements_count] = {
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1800, /* CCAOffset */
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128, /* CCA */
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2120, /* TxOffset */
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(2120 - (TSCH_CONF_RX_WAIT / 2)), /* RxOffset */
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800, /* RxAckDelay */
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1000, /* TxAckDelay */
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TSCH_CONF_RX_WAIT, /* RxWait */
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400, /* AckWait */
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192, /* RxTx */
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2400, /* MaxAck */
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4256, /* MaxTx */
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10000, /* TimeslotLength */
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};
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/* Default TSCH timeslot timing (in micro-second) */
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/* Default TSCH timeslot timing (in micro-second) */
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static const uint16_t *tsch_default_timing_us;
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static const uint16_t *tsch_default_timing_us;
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/* TSCH timeslot timing (in micro-second) */
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/* TSCH timeslot timing (in micro-second) */
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@ -180,7 +180,7 @@ extern unsigned long rx_count;
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extern unsigned long sync_count;
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extern unsigned long sync_count;
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extern int32_t min_drift_seen;
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extern int32_t min_drift_seen;
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extern int32_t max_drift_seen;
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extern int32_t max_drift_seen;
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/* The TSCH standard 10ms timeslot timing */
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extern uint16_t tsch_timeslot_timing_us_10000[tsch_ts_elements_count];
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extern uint16_t tsch_timeslot_timing_us_10000[tsch_ts_elements_count];
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/* TSCH processes */
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/* TSCH processes */
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