diff --git a/Makefile.include b/Makefile.include index b4dd036a2..e3e169a37 100644 --- a/Makefile.include +++ b/Makefile.include @@ -4,6 +4,10 @@ ifndef CONTIKI ${error CONTIKI not defined! You must specify where Contiki resides} endif +# Enable Werror by default. To disable from command line, use make WERROR=0. +# Setting this option is also important for tests on Cooja motes to check for warnings. +WERROR ?= 1 + ifeq ($(TARGET),) -include Makefile.target ifeq ($(TARGET),) diff --git a/apps/http-socket/http-socket.c b/apps/http-socket/http-socket.c index b08605213..a085d0954 100644 --- a/apps/http-socket/http-socket.c +++ b/apps/http-socket/http-socket.c @@ -442,12 +442,13 @@ event(struct tcp_socket *tcps, void *ptr, tcp_socket_send_str(tcps, "Range: bytes="); if(s->length) { if(s->pos >= 0) { - sprintf(str, "%llu-%llu", s->pos, s->pos + s->length - 1); + sprintf(str, "%llu-%llu", + (long long unsigned int)s->pos, (long long unsigned int)s->pos + s->length - 1); } else { - sprintf(str, "-%llu", s->length); + sprintf(str, "-%llu", (long long unsigned int)s->length); } } else { - sprintf(str, "%llu-", s->pos); + sprintf(str, "%llu-", (long long unsigned int)s->pos); } tcp_socket_send_str(tcps, str); tcp_socket_send_str(tcps, "\r\n"); diff --git a/apps/unit-test/unit-test.h b/apps/unit-test/unit-test.h index e39025cd0..576f2469d 100644 --- a/apps/unit-test/unit-test.h +++ b/apps/unit-test/unit-test.h @@ -184,7 +184,7 @@ typedef struct unit_test { */ #define UNIT_TEST_RESULT(name) (unit_test_##name.result) -/* The default print function. */ -void unit_test_print_report(const unit_test_t *utp); +/* The print function. */ +void UNIT_TEST_PRINT_FUNCTION(const unit_test_t *utp); #endif /* !UNIT_TEST_H */ diff --git a/core/net/mac/tsch/tsch-adaptive-timesync.c b/core/net/mac/tsch/tsch-adaptive-timesync.c index 2fb2caef9..9c23e8f19 100644 --- a/core/net/mac/tsch/tsch-adaptive-timesync.c +++ b/core/net/mac/tsch/tsch-adaptive-timesync.c @@ -101,7 +101,7 @@ timesync_learn_drift_ticks(uint32_t time_delta_asn, int32_t drift_ticks) TSCH_LOG_ADD(tsch_log_message, snprintf(log->message, sizeof(log->message), - "drift %ld", drift_ppm / 256)); + "drift %ld", (long int)drift_ppm / 256)); } /*---------------------------------------------------------------------------*/ /* Either reset or update the neighbor's drift */ @@ -147,7 +147,7 @@ compensate_internal(uint32_t time_delta_usec, int32_t drift_ppm, int32_t *remain if(ABS(amount_ticks) > RTIMER_ARCH_SECOND / 128) { TSCH_LOG_ADD(tsch_log_message, snprintf(log->message, sizeof(log->message), - "!too big compensation %ld delta %ld", amount_ticks, time_delta_usec)); + "!too big compensation %ld delta %ld", (long int)amount_ticks, (long int)time_delta_usec)); amount_ticks = (amount_ticks > 0 ? RTIMER_ARCH_SECOND : -RTIMER_ARCH_SECOND) / 128; } diff --git a/drivers/cpu/arm/aducrf101/Common/ADuCRF101.h b/drivers/cpu/arm/aducrf101/Common/ADuCRF101.h deleted file mode 100644 index 1e28f5cfb..000000000 --- a/drivers/cpu/arm/aducrf101/Common/ADuCRF101.h +++ /dev/null @@ -1,9875 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/****************************************************************************************************//** - * @file ADuCRF101.h - * - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for - * default ADUCRF101 Device Series - * - * @version V1.0 - * @date Thursday January 10 2013 15:30 - * - *******************************************************************************************************/ - - - -/** @addtogroup ADUCRF101 - * @{ - */ - -#ifndef __ADUCRF101_H__ -#define __ADUCRF101_H__ - -#ifndef __NO_MMR_STRUCTS__ -// The new style CMSIS structure definitions for MMRs clash with -// the old style defs. If the old style are required for compilation -// then set __NO_MMR_STRUCTS__ to 0x1 -#define __NO_MMR_STRUCTS__ 0x0 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum { -/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -// -------------------------- ADUCRF101 Specific Interrupt Numbers ------------------------------ - WUT_IRQn = 0, /*!< 0 WUT */ - EINT0_IRQn = 1, /*!< 1 EINT0 */ - EINT1_IRQn = 2, /*!< 2 EINT1 */ - EINT2_IRQn = 3, /*!< 3 EINT2 */ - EINT3_IRQn = 4, /*!< 4 EINT3 */ - EINT4_IRQn = 5, /*!< 5 EINT4 */ - EINT5_IRQn = 6, /*!< 6 EINT5 */ - EINT6_IRQn = 7, /*!< 7 EINT6 */ - EINT7_IRQn = 8, /*!< 8 EINT7 */ - EINT8_IRQn = 9, /*!< 9 EINT8 */ - UHFTRX_IRQn = 9, /*!< 9 UHFTRX */ - WDT_IRQn = 10, /*!< 10 WDT */ - TIMER0_IRQn = 12, /*!< 12 TIMER0 */ - TIMER1_IRQn = 13, /*!< 13 TIMER1 */ - ADC0_IRQn = 14, /*!< 14 ADC0 */ - FLASH_IRQn = 15, /*!< 15 FLASH */ - UART_IRQn = 16, /*!< 16 UART */ - SPI0_IRQn = 17, /*!< 17 SPI0 */ - SPI1_IRQn = 18, /*!< 18 SPI1 */ - I2CS_IRQn = 19, /*!< 19 I2CS */ - I2CM_IRQn = 20, /*!< 20 I2CM */ - DMA_ERR_IRQn = 23, /*!< 23 DMA_ERR */ - DMA_SPI1_TX_IRQn = 24, /*!< 24 DMA_SPI1_TX */ - DMA_SPI1_RX_IRQn = 25, /*!< 25 DMA_SPI1_RX */ - DMA_UART_TX_IRQn = 26, /*!< 26 DMA_UART_TX */ - DMA_UART_RX_IRQn = 27, /*!< 27 DMA_UART_RX */ - DMA_I2CS_TX_IRQn = 28, /*!< 28 DMA_I2CS_TX */ - DMA_I2CS_RX_IRQn = 29, /*!< 29 DMA_I2CS_RX */ - DMA_I2CM_TX_IRQn = 30, /*!< 30 DMA_I2CM_TX */ - DMA_I2CM_RX_IRQn = 31, /*!< 31 DMA_I2CM_RX */ - DMA_ADC0_IRQn = 35, /*!< 35 DMA_ADC0 */ - DMA_SPI0_TX_IRQn = 36, /*!< 36 DMA_SPI0_TX */ - DMA_SPI0_RX_IRQn = 37, /*!< 37 DMA_SPI0_RX */ - PWM_TRIP_IRQn = 38, /*!< 38 PWM_TRIP */ - PWM_PAIR0_IRQn = 39, /*!< 39 PWM_PAIR0 */ - PWM_PAIR1_IRQn = 40, /*!< 40 PWM_PAIR1 */ - PWM_PAIR2_IRQn = 41, /*!< 41 PWM_PAIR2 */ - PWM_PAIR3_IRQn = 42 /*!< 42 PWM_PAIR3 */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ----------------Configuration of the cm3 Processor and Core Peripherals---------------- */ - -#define __CM3_REV 0x0200 /*!< Cortex-M3 Core Revision */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include /*!< Cortex-M3 processor and core peripherals */ -#include "system_ADuCRF101.h" /*!< ADUCRF101 System */ - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ICCARM__) - #pragma language=extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - - - - -/* TCON[EVENTEN] - Enable event bit. */ -#define TCON_EVENTEN_MSK (0x1 << 12 ) -#define TCON_EVENTEN (0x1 << 12 ) -#define TCON_EVENTEN_DIS (0x0 << 12 ) /* DIS. Cleared by user. */ -#define TCON_EVENTEN_EN (0x1 << 12 ) /* EN. Enable time capture of an event. */ - -/* TCON[EVENT] - Event select bits. Settings not described are reserved and should not be used. */ -#define TCON_EVENT_MSK (0xF << 8 ) - -/* TCON[RLD] - Reload control bit for periodic mode. */ -#define TCON_RLD_MSK (0x1 << 7 ) -#define TCON_RLD (0x1 << 7 ) -#define TCON_RLD_DIS (0x0 << 7 ) /* DIS. Reload on a time out. */ -#define TCON_RLD_EN (0x1 << 7 ) /* EN. Reload the counter on a write to T0CLRI. */ - -/* TCON[CLK] - Clock select. */ -#define TCON_CLK_MSK (0x3 << 5 ) -#define TCON_CLK_UCLK (0x0 << 5 ) /* UCLK. Undivided system clock. */ -#define TCON_CLK_PCLK (0x1 << 5 ) /* PCLK. Peripheral clock. */ -#define TCON_CLK_LFOSC (0x2 << 5 ) /* LFOSC. 32 kHz internal oscillator. */ -#define TCON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL. 32 kHz external crystal. */ - -/* TCON[ENABLE] - Timer enable bit. */ -#define TCON_ENABLE_MSK (0x1 << 4 ) -#define TCON_ENABLE (0x1 << 4 ) -#define TCON_ENABLE_DIS (0x0 << 4 ) /* DIS. Disable the timer. Clearing this bit resets the timer, including the T0VAL register. */ -#define TCON_ENABLE_EN (0x1 << 4 ) /* EN. Enable the timer. The timer starts counting from its initial value, 0 if count-up mode or 0xFFFF if count-down mode. */ - -/* TCON[MOD] - Timer mode. */ -#define TCON_MOD_MSK (0x1 << 3 ) -#define TCON_MOD (0x1 << 3 ) -#define TCON_MOD_FREERUN (0x0 << 3 ) /* FREERUN. Operate in free running mode. */ -#define TCON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC. Operate in periodic mode. */ - -/* TCON[UP] - Count down/up. */ -#define TCON_UP_MSK (0x1 << 2 ) -#define TCON_UP (0x1 << 2 ) -#define TCON_UP_DIS (0x0 << 2 ) /* DIS. Timer to count down. */ -#define TCON_UP_EN (0x1 << 2 ) /* EN. Timer to count up. */ - -/* TCON[PRE] - Prescaler. */ -#define TCON_PRE_MSK (0x3 << 0 ) -#define TCON_PRE_DIV1 (0x0 << 0 ) /* DIV1. Source clock/1.If the selected clock source is UCLK or PCLK this setting results in a prescaler of 4. */ -#define TCON_PRE_DIV16 (0x1 << 0 ) /* DIV16. Source clock/16. */ -#define TCON_PRE_DIV256 (0x2 << 0 ) /* DIV256. Source clock/256. */ -#define TCON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768. Source clock/32768. */ - -/* TCLRI[CAP] - Clear captured event interrupt. */ -#define TCLRI_CAP_MSK (0x1 << 1 ) -#define TCLRI_CAP (0x1 << 1 ) -#define TCLRI_CAP_CLR (0x1 << 1 ) /* CLR. Clear a captured event interrupt. This bit always reads 0. */ - -/* TCLRI[TMOUT] - Clear timeout interrupt. */ -#define TCLRI_TMOUT_MSK (0x1 << 0 ) -#define TCLRI_TMOUT (0x1 << 0 ) -#define TCLRI_TMOUT_CLR (0x1 << 0 ) /* CLR. Clear a timeout interrupt. This bit always reads 0. */ - -/* TSTA[CLRI] - T0CLRI write sync in progress.. */ -#define TSTA_CLRI_MSK (0x1 << 7 ) -#define TSTA_CLRI (0x1 << 7 ) -#define TSTA_CLRI_CLR (0x0 << 7 ) /* CLR. Cleared when the interrupt is cleared in the timer clock domain. */ -#define TSTA_CLRI_SET (0x1 << 7 ) /* SET. Set automatically when the T0CLRI value is being updated in the timer clock domain, indicating that the timer’s configuration is not yet valid. */ - -/* TSTA[CON] - T0CON write sync in progress. */ -#define TSTA_CON_MSK (0x1 << 6 ) -#define TSTA_CON (0x1 << 6 ) -#define TSTA_CON_CLR (0x0 << 6 ) /* CLR. Timer ready to receive commands to T0CON. The previous change of T0CON has been synchronized in the timer clock domain. */ -#define TSTA_CON_SET (0x1 << 6 ) /* SET. Timer not ready to receive commands to T0CON. Previous change of the T0CON value has not been synchronized in the timer clock domain. */ - -/* TSTA[CAP] - Capture event pending. */ -#define TSTA_CAP_MSK (0x1 << 1 ) -#define TSTA_CAP (0x1 << 1 ) -#define TSTA_CAP_CLR (0x0 << 1 ) /* CLR. No capture event is pending. */ -#define TSTA_CAP_SET (0x1 << 1 ) /* SET. Capture event is pending. */ - -/* TSTA[TMOUT] - Time out event occurred. */ -#define TSTA_TMOUT_MSK (0x1 << 0 ) -#define TSTA_TMOUT (0x1 << 0 ) -#define TSTA_TMOUT_CLR (0x0 << 0 ) /* CLR. No timeout event has occurred. */ -#define TSTA_TMOUT_SET (0x1 << 0 ) /* SET. Timeout event has occurred. For count-up mode, this is when the counter reaches full scale. For count-down mode, this is when the counter reaches 0. */ - -/* GPCON[CON7] - Configuration bits for Px.7 (not available for port 1). */ -#define GPCON_CON7_MSK (0x3 << 14 ) - -/* GPCON[CON6] - Configuration bits for Px.6 (not available for port 1). */ -#define GPCON_CON6_MSK (0x3 << 12 ) - -/* GPCON[CON5] - Configuration bits for Px.5. */ -#define GPCON_CON5_MSK (0x3 << 10 ) - -/* GPCON[CON4] - Configuration bits for Px.4. */ -#define GPCON_CON4_MSK (0x3 << 8 ) - -/* GPCON[CON3] - Configuration bits for Px.3. */ -#define GPCON_CON3_MSK (0x3 << 6 ) - -/* GPCON[CON2] - Configuration bits for Px.2. */ -#define GPCON_CON2_MSK (0x3 << 4 ) - -/* GPCON[CON1] - Configuration bits for Px.1. */ -#define GPCON_CON1_MSK (0x3 << 2 ) - -/* GPCON[CON0] - Configuration bits for Px.0. */ -#define GPCON_CON0_MSK (0x3 << 0 ) - -/* GPOEN[OEN7] - Port pin direction. */ -#define GPOEN_OEN7_MSK (0x1 << 7 ) -#define GPOEN_OEN7 (0x1 << 7 ) -#define GPOEN_OEN7_IN (0x0 << 7 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GPOEN_OEN7_OUT (0x1 << 7 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GPOEN[OEN6] - Port pin direction. */ -#define GPOEN_OEN6_MSK (0x1 << 6 ) -#define GPOEN_OEN6 (0x1 << 6 ) -#define GPOEN_OEN6_IN (0x0 << 6 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GPOEN_OEN6_OUT (0x1 << 6 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GPOEN[OEN5] - Port pin direction. */ -#define GPOEN_OEN5_MSK (0x1 << 5 ) -#define GPOEN_OEN5 (0x1 << 5 ) -#define GPOEN_OEN5_IN (0x0 << 5 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GPOEN_OEN5_OUT (0x1 << 5 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GPOEN[OEN4] - Port pin direction. */ -#define GPOEN_OEN4_MSK (0x1 << 4 ) -#define GPOEN_OEN4 (0x1 << 4 ) -#define GPOEN_OEN4_IN (0x0 << 4 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GPOEN_OEN4_OUT (0x1 << 4 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GPOEN[OEN3] - Port pin direction. */ -#define GPOEN_OEN3_MSK (0x1 << 3 ) -#define GPOEN_OEN3 (0x1 << 3 ) -#define GPOEN_OEN3_IN (0x0 << 3 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GPOEN_OEN3_OUT (0x1 << 3 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GPOEN[OEN2] - Port pin direction. */ -#define GPOEN_OEN2_MSK (0x1 << 2 ) -#define GPOEN_OEN2 (0x1 << 2 ) -#define GPOEN_OEN2_IN (0x0 << 2 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GPOEN_OEN2_OUT (0x1 << 2 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GPOEN[OEN1] - Port pin direction. */ -#define GPOEN_OEN1_MSK (0x1 << 1 ) -#define GPOEN_OEN1 (0x1 << 1 ) -#define GPOEN_OEN1_IN (0x0 << 1 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GPOEN_OEN1_OUT (0x1 << 1 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GPOEN[OEN0] - Port pin direction. */ -#define GPOEN_OEN0_MSK (0x1 << 0 ) -#define GPOEN_OEN0 (0x1 << 0 ) -#define GPOEN_OEN0_IN (0x0 << 0 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GPOEN_OEN0_OUT (0x1 << 0 ) /* OUT. Enables the output on corresponding port pin.. */ - -/* GPIN[IN7] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GPIN_IN7_MSK (0x1 << 7 ) -#define GPIN_IN7 (0x1 << 7 ) -#define GPIN_IN7_LOW (0x0 << 7 ) /* LOW */ -#define GPIN_IN7_HIGH (0x1 << 7 ) /* HIGH */ - -/* GPIN[IN6] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GPIN_IN6_MSK (0x1 << 6 ) -#define GPIN_IN6 (0x1 << 6 ) -#define GPIN_IN6_LOW (0x0 << 6 ) /* LOW */ -#define GPIN_IN6_HIGH (0x1 << 6 ) /* HIGH */ - -/* GPIN[IN5] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GPIN_IN5_MSK (0x1 << 5 ) -#define GPIN_IN5 (0x1 << 5 ) -#define GPIN_IN5_LOW (0x0 << 5 ) /* LOW */ -#define GPIN_IN5_HIGH (0x1 << 5 ) /* HIGH */ - -/* GPIN[IN4] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GPIN_IN4_MSK (0x1 << 4 ) -#define GPIN_IN4 (0x1 << 4 ) -#define GPIN_IN4_LOW (0x0 << 4 ) /* LOW */ -#define GPIN_IN4_HIGH (0x1 << 4 ) /* HIGH */ - -/* GPIN[IN3] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GPIN_IN3_MSK (0x1 << 3 ) -#define GPIN_IN3 (0x1 << 3 ) -#define GPIN_IN3_LOW (0x0 << 3 ) /* LOW */ -#define GPIN_IN3_HIGH (0x1 << 3 ) /* HIGH */ - -/* GPIN[IN2] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GPIN_IN2_MSK (0x1 << 2 ) -#define GPIN_IN2 (0x1 << 2 ) -#define GPIN_IN2_LOW (0x0 << 2 ) /* LOW */ -#define GPIN_IN2_HIGH (0x1 << 2 ) /* HIGH */ - -/* GPIN[IN1] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GPIN_IN1_MSK (0x1 << 1 ) -#define GPIN_IN1 (0x1 << 1 ) -#define GPIN_IN1_LOW (0x0 << 1 ) /* LOW */ -#define GPIN_IN1_HIGH (0x1 << 1 ) /* HIGH */ - -/* GPIN[IN0] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GPIN_IN0_MSK (0x1 << 0 ) -#define GPIN_IN0 (0x1 << 0 ) -#define GPIN_IN0_LOW (0x0 << 0 ) /* LOW */ -#define GPIN_IN0_HIGH (0x1 << 0 ) /* HIGH */ - -/* GPOUT[OUT7] - Data out register. */ -#define GPOUT_OUT7_MSK (0x1 << 7 ) -#define GPOUT_OUT7 (0x1 << 7 ) -#define GPOUT_OUT7_LOW (0x0 << 7 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GPOUT_OUT7_HIGH (0x1 << 7 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GPOUT[OUT6] - Data out register. */ -#define GPOUT_OUT6_MSK (0x1 << 6 ) -#define GPOUT_OUT6 (0x1 << 6 ) -#define GPOUT_OUT6_LOW (0x0 << 6 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GPOUT_OUT6_HIGH (0x1 << 6 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GPOUT[OUT5] - Data out register. */ -#define GPOUT_OUT5_MSK (0x1 << 5 ) -#define GPOUT_OUT5 (0x1 << 5 ) -#define GPOUT_OUT5_LOW (0x0 << 5 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GPOUT_OUT5_HIGH (0x1 << 5 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GPOUT[OUT4] - Data out register. */ -#define GPOUT_OUT4_MSK (0x1 << 4 ) -#define GPOUT_OUT4 (0x1 << 4 ) -#define GPOUT_OUT4_LOW (0x0 << 4 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GPOUT_OUT4_HIGH (0x1 << 4 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GPOUT[OUT3] - Data out register. */ -#define GPOUT_OUT3_MSK (0x1 << 3 ) -#define GPOUT_OUT3 (0x1 << 3 ) -#define GPOUT_OUT3_LOW (0x0 << 3 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GPOUT_OUT3_HIGH (0x1 << 3 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GPOUT[OUT2] - Data out register. */ -#define GPOUT_OUT2_MSK (0x1 << 2 ) -#define GPOUT_OUT2 (0x1 << 2 ) -#define GPOUT_OUT2_LOW (0x0 << 2 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GPOUT_OUT2_HIGH (0x1 << 2 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GPOUT[OUT1] - Data out register. */ -#define GPOUT_OUT1_MSK (0x1 << 1 ) -#define GPOUT_OUT1 (0x1 << 1 ) -#define GPOUT_OUT1_LOW (0x0 << 1 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GPOUT_OUT1_HIGH (0x1 << 1 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GPOUT[OUT0] - Data out register. */ -#define GPOUT_OUT0_MSK (0x1 << 0 ) -#define GPOUT_OUT0 (0x1 << 0 ) -#define GPOUT_OUT0_LOW (0x0 << 0 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GPOUT_OUT0_HIGH (0x1 << 0 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GPSET[SET7] - Set output high for corresponding port pin. */ -#define GPSET_SET7_MSK (0x1 << 7 ) -#define GPSET_SET7 (0x1 << 7 ) -#define GPSET_SET7_SET (0x1 << 7 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GPSET[SET6] - Set output high for corresponding port pin. */ -#define GPSET_SET6_MSK (0x1 << 6 ) -#define GPSET_SET6 (0x1 << 6 ) -#define GPSET_SET6_SET (0x1 << 6 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GPSET[SET5] - Set output high for corresponding port pin. */ -#define GPSET_SET5_MSK (0x1 << 5 ) -#define GPSET_SET5 (0x1 << 5 ) -#define GPSET_SET5_SET (0x1 << 5 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GPSET[SET4] - Set output high for corresponding port pin. */ -#define GPSET_SET4_MSK (0x1 << 4 ) -#define GPSET_SET4 (0x1 << 4 ) -#define GPSET_SET4_SET (0x1 << 4 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GPSET[SET3] - Set output high for corresponding port pin. */ -#define GPSET_SET3_MSK (0x1 << 3 ) -#define GPSET_SET3 (0x1 << 3 ) -#define GPSET_SET3_SET (0x1 << 3 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GPSET[SET2] - Set output high for corresponding port pin. */ -#define GPSET_SET2_MSK (0x1 << 2 ) -#define GPSET_SET2 (0x1 << 2 ) -#define GPSET_SET2_SET (0x1 << 2 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GPSET[SET1] - Set output high for corresponding port pin. */ -#define GPSET_SET1_MSK (0x1 << 1 ) -#define GPSET_SET1 (0x1 << 1 ) -#define GPSET_SET1_SET (0x1 << 1 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GPSET[SET0] - Set output high for corresponding port pin. */ -#define GPSET_SET0_MSK (0x1 << 0 ) -#define GPSET_SET0 (0x1 << 0 ) -#define GPSET_SET0_SET (0x1 << 0 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GPCLR[CLR7] - Set by user code to drive the corresponding GPIO low. */ -#define GPCLR_CLR7_MSK (0x1 << 7 ) -#define GPCLR_CLR7 (0x1 << 7 ) -#define GPCLR_CLR7_CLR (0x1 << 7 ) /* CLR */ - -/* GPCLR[CLR6] - Set by user code to drive the corresponding GPIO low. */ -#define GPCLR_CLR6_MSK (0x1 << 6 ) -#define GPCLR_CLR6 (0x1 << 6 ) -#define GPCLR_CLR6_CLR (0x1 << 6 ) /* CLR */ - -/* GPCLR[CLR5] - Set by user code to drive the corresponding GPIO low. */ -#define GPCLR_CLR5_MSK (0x1 << 5 ) -#define GPCLR_CLR5 (0x1 << 5 ) -#define GPCLR_CLR5_CLR (0x1 << 5 ) /* CLR */ - -/* GPCLR[CLR4] - Set by user code to drive the corresponding GPIO low. */ -#define GPCLR_CLR4_MSK (0x1 << 4 ) -#define GPCLR_CLR4 (0x1 << 4 ) -#define GPCLR_CLR4_CLR (0x1 << 4 ) /* CLR */ - -/* GPCLR[CLR3] - Set by user code to drive the corresponding GPIO low. */ -#define GPCLR_CLR3_MSK (0x1 << 3 ) -#define GPCLR_CLR3 (0x1 << 3 ) -#define GPCLR_CLR3_CLR (0x1 << 3 ) /* CLR */ - -/* GPCLR[CLR2] - Set by user code to drive the corresponding GPIO low. */ -#define GPCLR_CLR2_MSK (0x1 << 2 ) -#define GPCLR_CLR2 (0x1 << 2 ) -#define GPCLR_CLR2_CLR (0x1 << 2 ) /* CLR */ - -/* GPCLR[CLR1] - Set by user code to drive the corresponding GPIO low. */ -#define GPCLR_CLR1_MSK (0x1 << 1 ) -#define GPCLR_CLR1 (0x1 << 1 ) -#define GPCLR_CLR1_CLR (0x1 << 1 ) /* CLR */ - -/* GPCLR[CLR0] - Set by user code to drive the corresponding GPIO low. */ -#define GPCLR_CLR0_MSK (0x1 << 0 ) -#define GPCLR_CLR0 (0x1 << 0 ) -#define GPCLR_CLR0_CLR (0x1 << 0 ) /* CLR */ - -/* GPTGL[TGL7] - Toggle for corresponding port pin. */ -#define GPTGL_TGL7_MSK (0x1 << 7 ) -#define GPTGL_TGL7 (0x1 << 7 ) -#define GPTGL_TGL7_TGL (0x1 << 7 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GPTGL[TGL6] - Toggle for corresponding port pin. */ -#define GPTGL_TGL6_MSK (0x1 << 6 ) -#define GPTGL_TGL6 (0x1 << 6 ) -#define GPTGL_TGL6_TGL (0x1 << 6 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GPTGL[TGL5] - Toggle for corresponding port pin. */ -#define GPTGL_TGL5_MSK (0x1 << 5 ) -#define GPTGL_TGL5 (0x1 << 5 ) -#define GPTGL_TGL5_TGL (0x1 << 5 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GPTGL[TGL4] - Toggle for corresponding port pin. */ -#define GPTGL_TGL4_MSK (0x1 << 4 ) -#define GPTGL_TGL4 (0x1 << 4 ) -#define GPTGL_TGL4_TGL (0x1 << 4 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GPTGL[TGL3] - Toggle for corresponding port pin. */ -#define GPTGL_TGL3_MSK (0x1 << 3 ) -#define GPTGL_TGL3 (0x1 << 3 ) -#define GPTGL_TGL3_TGL (0x1 << 3 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GPTGL[TGL2] - Toggle for corresponding port pin. */ -#define GPTGL_TGL2_MSK (0x1 << 2 ) -#define GPTGL_TGL2 (0x1 << 2 ) -#define GPTGL_TGL2_TGL (0x1 << 2 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GPTGL[TGL1] - Toggle for corresponding port pin. */ -#define GPTGL_TGL1_MSK (0x1 << 1 ) -#define GPTGL_TGL1 (0x1 << 1 ) -#define GPTGL_TGL1_TGL (0x1 << 1 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GPTGL[TGL0] - Toggle for corresponding port pin. */ -#define GPTGL_TGL0_MSK (0x1 << 0 ) -#define GPTGL_TGL0 (0x1 << 0 ) -#define GPTGL_TGL0_TGL (0x1 << 0 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* CLK[T1] - T1 clocks enable bit. */ -#define CLK_T1_MSK (0x1 << 11 ) -#define CLK_T1 (0x1 << 11 ) -#define CLK_T1_DIS (0x0 << 11 ) /* DIS. Disable T1 clocks. */ -#define CLK_T1_EN (0x1 << 11 ) /* EN. Enable T1 clocks. */ - -/* CLK[T0] - T0 clocks enable bit. */ -#define CLK_T0_MSK (0x1 << 10 ) -#define CLK_T0 (0x1 << 10 ) -#define CLK_T0_DIS (0x0 << 10 ) /* DIS. Disable T0 clocks. */ -#define CLK_T0_EN (0x1 << 10 ) /* EN. Enable T0 clocks. */ - -/* CLK[PWM] - PWM clocks enable bit. */ -#define CLK_PWM_MSK (0x1 << 9 ) -#define CLK_PWM (0x1 << 9 ) -#define CLK_PWM_DIS (0x0 << 9 ) /* DIS. Disable PWM clocks. */ -#define CLK_PWM_EN (0x1 << 9 ) /* EN. Enable PWM clocks. */ - -/* CLK[I2C] - I2C clocks enable bit. */ -#define CLK_I2C_MSK (0x1 << 8 ) -#define CLK_I2C (0x1 << 8 ) -#define CLK_I2C_DIS (0x0 << 8 ) /* DIS. Disable I2C clocks. */ -#define CLK_I2C_EN (0x1 << 8 ) /* EN. Enable I2C clocks. */ - -/* CLK[COM] - UART clocks enable bit. */ -#define CLK_COM_MSK (0x1 << 7 ) -#define CLK_COM (0x1 << 7 ) -#define CLK_COM_DIS (0x0 << 7 ) /* DIS. Disable UART clocks. */ -#define CLK_COM_EN (0x1 << 7 ) /* EN. Enable UART clocks. */ - -/* CLK[SPI1] - SPI1 clocks enable bit. */ -#define CLK_SPI1_MSK (0x1 << 6 ) -#define CLK_SPI1 (0x1 << 6 ) -#define CLK_SPI1_DIS (0x0 << 6 ) /* DIS. Disable SPI1 clocks. */ -#define CLK_SPI1_EN (0x1 << 6 ) /* EN. Enable SPI1 clocks. */ - -/* CLK[SPI0] - SPI0 clocks enable bit. */ -#define CLK_SPI0_MSK (0x1 << 5 ) -#define CLK_SPI0 (0x1 << 5 ) -#define CLK_SPI0_DIS (0x0 << 5 ) /* DIS. Disable SPI0 clocks. */ -#define CLK_SPI0_EN (0x1 << 5 ) /* EN. Enable SPI0 clocks. */ - -/* CLK[T2] - T2 clocks enable bit. */ -#define CLK_T2_MSK (0x1 << 4 ) -#define CLK_T2 (0x1 << 4 ) -#define CLK_T2_DIS (0x0 << 4 ) /* DIS. Disable T2 clocks. */ -#define CLK_T2_EN (0x1 << 4 ) /* EN. Enable T2 clocks. */ - -/* CLK[ADC] - ADC clocks enable bit. */ -#define CLK_ADC_MSK (0x1 << 3 ) -#define CLK_ADC (0x1 << 3 ) -#define CLK_ADC_DIS (0x0 << 3 ) /* DIS. Disable ADC clocks. */ -#define CLK_ADC_EN (0x1 << 3 ) /* EN. Enable ADC clocks. */ - -/* CLK[SRAM] - SRAM clocks enable bit. */ -#define CLK_SRAM_MSK (0x1 << 2 ) -#define CLK_SRAM (0x1 << 2 ) -#define CLK_SRAM_DIS (0x0 << 2 ) /* DIS. Disable SRAM memory clocks. */ -#define CLK_SRAM_EN (0x1 << 2 ) /* EN. Enable SRAM memory clocks. */ - -/* CLK[FEE] - Flash clocks enable bit. */ -#define CLK_FEE_MSK (0x1 << 1 ) -#define CLK_FEE (0x1 << 1 ) -#define CLK_FEE_DIS (0x0 << 1 ) /* DIS. Disable Flash memory clocks. */ -#define CLK_FEE_EN (0x1 << 1 ) /* EN. Enable Flash memory clocks. */ - -/* CLK[DMA] - DMA clock enable bit. */ -#define CLK_DMA_MSK (0x1 << 0 ) -#define CLK_DMA (0x1 << 0 ) -#define CLK_DMA_DIS (0x0 << 0 ) /* DIS. Disable DMA clock. */ -#define CLK_DMA_EN (0x1 << 0 ) /* EN. Enable DMA clock. */ - -/* SPIDIV[BCRST] - Configures the behavior of SPI communication after an abrupt deassertion of CS. This bit should be set in slave and master mode. */ -#define SPIDIV_BCRST_MSK (0x1 << 7 ) -#define SPIDIV_BCRST (0x1 << 7 ) -#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS. Resumes communication from where it stopped when the CS is deasserted. The rest of the bits are then received/ transmitted when CS returns low. User code should ignore the CSERR interrupt. */ -#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN. Enabled for a clean restart of SPI transfer after a CSERR condition. User code must also clear the SPI enable bit in SPI0CON during the CSERR interrupt. */ - -/* SPIDIV[DIV] - Factor used to divide UCLK in the generation of the master mode serial clock. */ -#define SPIDIV_DIV_MSK (0x3F << 0 ) - -/* SPICON[MOD] - IRQ mode bits. When TIM is set these bits configure when the Tx/Rx interrupts occur in a transfer. For a DMA Rx transfer, these bits should be 00. */ -#define SPICON_MOD_MSK (0x3 << 14 ) -#define SPICON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1. Tx/Rx interrupt occurs when 1 byte has been transmitted/received from/into the FIFO. */ -#define SPICON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2. Tx/Rx interrupt occurs when 2 bytes have been transmitted/received from/into the FIFO. */ -#define SPICON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3. Tx/Rx interrupt occurs when 3 bytes have been transmitted/received from/into the FIFO. */ -#define SPICON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4. Tx/Rx interrupt occurs when 4 bytes have been transmitted/received from/into the FIFO. */ - -/* SPICON[TFLUSH] - Tx FIFO flush enable bit. */ -#define SPICON_TFLUSH_MSK (0x1 << 13 ) -#define SPICON_TFLUSH (0x1 << 13 ) -#define SPICON_TFLUSH_DIS (0x0 << 13 ) /* DIS. Disable Tx FIFO flushing. */ -#define SPICON_TFLUSH_EN (0x1 << 13 ) /* EN. Flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the ZEN bit (SPI0CON[7]). Any writes to the Tx FIFO are ignored while this bit is set. */ - -/* SPICON[RFLUSH] - Rx FIFO flush enable bit. */ -#define SPICON_RFLUSH_MSK (0x1 << 12 ) -#define SPICON_RFLUSH (0x1 << 12 ) -#define SPICON_RFLUSH_DIS (0x0 << 12 ) /* DIS. Disable Rx FIFO flushing. */ -#define SPICON_RFLUSH_EN (0x1 << 12 ) /* EN. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and TIM = 0 (SPI0CON[6]), a read of the Rx FIFO initiates a transfer. */ - -/* SPICON[CON] - Continuous transfer enable bit. */ -#define SPICON_CON_MSK (0x1 << 11 ) -#define SPICON_CON (0x1 << 11 ) -#define SPICON_CON_DIS (0x0 << 11 ) /* DIS. Disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPIxTX register, then a new transfer is initiated after a stall period of one serial clock cycle. The CS line is deactivated for this one serial clock cycle. */ -#define SPICON_CON_EN (0x1 << 11 ) /* EN. Enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. */ - -/* SPICON[LOOPBACK] - Loopback enable bit. */ -#define SPICON_LOOPBACK_MSK (0x1 << 10 ) -#define SPICON_LOOPBACK (0x1 << 10 ) -#define SPICON_LOOPBACK_DIS (0x0 << 10 ) /* DIS. Normal mode. */ -#define SPICON_LOOPBACK_EN (0x1 << 10 ) /* EN. Connect MISO to MOSI, thus, data transmitted from Tx register is looped back to the Rx register. SPI must be configured in master mode. */ - -/* SPICON[SOEN] - Slave output enable bit. */ -#define SPICON_SOEN_MSK (0x1 << 9 ) -#define SPICON_SOEN (0x1 << 9 ) -#define SPICON_SOEN_DIS (0x0 << 9 ) /* DIS. Disable the output driver on the MISO pin. The MISO pin is open-circuit when this bit is clear. */ -#define SPICON_SOEN_EN (0x1 << 9 ) /* EN. MISO operates as normal. */ - -/* SPICON[RXOF] - RX overflow overwrite enable bit. */ -#define SPICON_RXOF_MSK (0x1 << 8 ) -#define SPICON_RXOF (0x1 << 8 ) -#define SPICON_RXOF_DIS (0x0 << 8 ) /* DIS. The new serial byte received is discarded when there is no space left in the FIFO */ -#define SPICON_RXOF_EN (0x1 << 8 ) /* EN. The valid data in the Rx register is overwritten by the new serial byte received when there is no space left in the FIFO. */ - -/* SPICON[ZEN] - Transmit underrun: Transmit 0s when the Tx FIFO is empty */ -#define SPICON_ZEN_MSK (0x1 << 7 ) -#define SPICON_ZEN (0x1 << 7 ) -#define SPICON_ZEN_DIS (0x0 << 7 ) /* DIS. The last byte from the previous transmission is shifted out when a transfer is initiated with no valid data in the FIFO. */ -#define SPICON_ZEN_EN (0x1 << 7 ) /* EN. Transmit 0x00 when a transfer is initiated with no valid data in the FIFO. */ - -/* SPICON[TIM] - Transfer and interrupt mode bit. */ -#define SPICON_TIM_MSK (0x1 << 6 ) -#define SPICON_TIM (0x1 << 6 ) -#define SPICON_TIM_TXWR (0x1 << 6 ) /* TXWR. Initiate transfer with a write to the SPIxTX register. Interrupt only occurs when Tx is empty. */ -#define SPICON_TIM_RXRD (0x0 << 6 ) /* RXRD. Initiate transfer with a read of the SPIxRX register. The read must be done while the SPI interface is idle. Interrupt only occurs when Rx is full. */ - -/* SPICON[LSB] - LSB first transfer enable bit. */ -#define SPICON_LSB_MSK (0x1 << 5 ) -#define SPICON_LSB (0x1 << 5 ) -#define SPICON_LSB_DIS (0x0 << 5 ) /* DIS. MSB is transmitted first. */ -#define SPICON_LSB_EN (0x1 << 5 ) /* EN. LSB is transmitted first. */ - -/* SPICON[WOM] - Wired OR enable bit. */ -#define SPICON_WOM_MSK (0x1 << 4 ) -#define SPICON_WOM (0x1 << 4 ) -#define SPICON_WOM_DIS (0x0 << 4 ) /* DIS. Normal driver output operation. */ -#define SPICON_WOM_EN (0x1 << 4 ) /* EN. Enable open circuit data output for multimaster/multislave configuration. */ - -/* SPICON[CPOL] - Serial clock polarity mode bit. */ -#define SPICON_CPOL_MSK (0x1 << 3 ) -#define SPICON_CPOL (0x1 << 3 ) -#define SPICON_CPOL_LOW (0x0 << 3 ) /* LOW. Serial clock idles low. */ -#define SPICON_CPOL_HIGH (0x1 << 3 ) /* HIGH. Serial clock idles high. */ - -/* SPICON[CPHA] - Serial clock phase mode bit. */ -#define SPICON_CPHA_MSK (0x1 << 2 ) -#define SPICON_CPHA (0x1 << 2 ) -#define SPICON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING. Serial clock pulses at the middle of the first data bit transfer. */ -#define SPICON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING. Serial clock pulses at the start of the first data bit. */ - -/* SPICON[MASEN] - Master mode enable bit. */ -#define SPICON_MASEN_MSK (0x1 << 1 ) -#define SPICON_MASEN (0x1 << 1 ) -#define SPICON_MASEN_DIS (0x0 << 1 ) /* DIS. Configure in slave mode. */ -#define SPICON_MASEN_EN (0x1 << 1 ) /* EN. Configure in master mode. */ - -/* SPICON[ENABLE] - SPI enable bit. */ -#define SPICON_ENABLE_MSK (0x1 << 0 ) -#define SPICON_ENABLE (0x1 << 0 ) -#define SPICON_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable the SPI. Clearing this bit will also reset all the FIFO related logic to enable a clean start. */ -#define SPICON_ENABLE_EN (0x1 << 0 ) /* EN. Enable the SPI. */ - -/* SPIDMA[IENRXDMA] - Receive DMA request enable bit. */ -#define SPIDMA_IENRXDMA_MSK (0x1 << 2 ) -#define SPIDMA_IENRXDMA (0x1 << 2 ) -#define SPIDMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS. Disable Rx DMA requests. */ -#define SPIDMA_IENRXDMA_EN (0x1 << 2 ) /* EN. Enable Rx DMA requests. */ - -/* SPIDMA[IENTXDMA] - Transmit DMA request enable bit. */ -#define SPIDMA_IENTXDMA_MSK (0x1 << 1 ) -#define SPIDMA_IENTXDMA (0x1 << 1 ) -#define SPIDMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS. Disable Tx DMA requests. */ -#define SPIDMA_IENTXDMA_EN (0x1 << 1 ) /* EN. Enable Tx DMA requests. */ - -/* SPIDMA[ENABLE] - DMA data transfer enable bit. */ -#define SPIDMA_ENABLE_MSK (0x1 << 0 ) -#define SPIDMA_ENABLE (0x1 << 0 ) -#define SPIDMA_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable DMA transfer. This bit needs to be cleared to prevent extra DMA request to the µDMA controller. */ -#define SPIDMA_ENABLE_EN (0x1 << 0 ) /* EN. Enable a DMA transfer. Starts the transfer of a master configured to initiate transfer on transmit. */ - -/* SPISTA[CSERR] - CS error status bit. This bit generates an interrupt when detecting an abrupt CS desassertion before the full byte of data is transmitted completely. */ -#define SPISTA_CSERR_MSK (0x1 << 12 ) -#define SPISTA_CSERR (0x1 << 12 ) -#define SPISTA_CSERR_CLR (0x0 << 12 ) /* CLR: Cleared when no CS error is detected. Cleared to 0 on a read of SPI0STA register. */ -#define SPISTA_CSERR_SET (0x1 << 12 ) /* SET: Set when the CS line is deasserted abruptly. */ - -/* SPISTA[RXS] - Rx FIFO excess bytes present. */ -#define SPISTA_RXS_MSK (0x1 << 11 ) -#define SPISTA_RXS (0x1 << 11 ) -#define SPISTA_RXS_CLR (0x0 << 11 ) /* CLR. When the number of bytes in the FIFO is equal or less than the number in SPI0CON[15:14]. This bit is not cleared on a read of SPI0STA register. */ -#define SPISTA_RXS_SET (0x1 << 11 ) /* SET. When there are more bytes in the Rx FIFO than configured in MOD (SPI0CON[15:14]). For example if MOD = TX1RX1, RXS is set when there are 2 or more bytes in the Rx FIFO. This bit does not dependent on SPI0CON[6] and does not cause an interrupt. */ - -/* SPISTA[RXFSTA] - Rx FIFO status bits, indicates how many valid bytes are in the Rx FIFO. */ -#define SPISTA_RXFSTA_MSK (0x7 << 8 ) -#define SPISTA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY. When Rx FIFO is empty. */ -#define SPISTA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE. When 1 valid byte is in the FIFO. */ -#define SPISTA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES. When 2 valid bytes are in the FIFO. */ -#define SPISTA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES. When 3 valid bytes are in the FIFO. */ -#define SPISTA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES. When 4 valid bytes are in the FIFO. */ - -/* SPISTA[RXOF] - Rx FIFO overflow status bit. This bit generates an interrupt. */ -#define SPISTA_RXOF_MSK (0x1 << 7 ) -#define SPISTA_RXOF (0x1 << 7 ) -#define SPISTA_RXOF_CLR (0x0 << 7 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ -#define SPISTA_RXOF_SET (0x1 << 7 ) /* SET. Set when the Rx FIFO is already full when new data is loaded to the FIFO. This bit generates an interrupt except when RFLUSH is set. (SPI0CON[12]). */ - -/* SPISTA[RX] - Rx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */ -#define SPISTA_RX_MSK (0x1 << 6 ) -#define SPISTA_RX (0x1 << 6 ) -#define SPISTA_RX_CLR (0x0 << 6 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ -#define SPISTA_RX_SET (0x1 << 6 ) /* SET. Set when a receive interrupt occurs. This bit is set when TIM (SPI0CON[6]) is cleared and the required number of bytes have been received. */ - -/* SPISTA[TX] - Tx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */ -#define SPISTA_TX_MSK (0x1 << 5 ) -#define SPISTA_TX (0x1 << 5 ) -#define SPISTA_TX_CLR (0x0 << 5 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ -#define SPISTA_TX_SET (0x1 << 5 ) /* SET. Set when a transmit interrupt occurs. This bit is set when TIM (SPI0CON[6]) set and the required number of bytes have been transmitted. */ - -/* SPISTA[TXUR] - Tx FIFO Underrun. This bit generates an interrupt. */ -#define SPISTA_TXUR_MSK (0x1 << 4 ) -#define SPISTA_TXUR (0x1 << 4 ) -#define SPISTA_TXUR_CLR (0x0 << 4 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ -#define SPISTA_TXUR_SET (0x1 << 4 ) /* SET. Set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when TFLUSH is set in SPI0CON. */ - -/* SPISTA[TXFSTA] - Tx FIFO status bits, indicates how many valid bytes are in the Tx FIFO. */ -#define SPISTA_TXFSTA_MSK (0x7 << 1 ) -#define SPISTA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY. Tx FIFO is empty. */ -#define SPISTA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE. 1 valid byte is in the FIFO. */ -#define SPISTA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES. 2 valid bytes are in the FIFO. */ -#define SPISTA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES. 3 valid bytes are in the FIFO. */ -#define SPISTA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES . 4 valid bytes are in the FIFO. */ - -/* SPISTA[IRQ] - Interrupt status bit. */ -#define SPISTA_IRQ_MSK (0x1 << 0 ) -#define SPISTA_IRQ (0x1 << 0 ) -#define SPISTA_IRQ_CLR (0x0 << 0 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ -#define SPISTA_IRQ_SET (0x1 << 0 ) /* SET. Set to 1 when an SPI0 based interrupt occurs. */ - -/* SPIDIV[BCRST] - Configures the behavior of SPI communication after an abrupt deassertion of CS. This bit should be set in slave and master mode. */ -#define SPIDIV_BCRST_MSK (0x1 << 7 ) -#define SPIDIV_BCRST (0x1 << 7 ) -#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS. Resumes communication from where it stopped when the CS is deasserted. The rest of the bits are then received/ transmitted when CS returns low. User code should ignore the CSERR interrupt. */ -#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN. Enabled for a clean restart of SPI transfer after a CSERR condition. User code must also clear the SPI enable bit in SPI0CON during the CSERR interrupt. */ - -/* SPIDIV[DIV] - Factor used to divide UCLK in the generation of the master mode serial clock. */ -#define SPIDIV_DIV_MSK (0x3F << 0 ) -// ------------------------------------------------------------------------------------------------ -// ----- ADC0 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Analog to Digital Converter (pADI_ADC0) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_ADC0 Structure */ - __IO uint16_t ADCCFG; /*!< ADC Configuration Register */ - __I uint16_t RESERVED0; - __IO uint8_t ADCCON; /*!< ADC Control Register */ - __I uint8_t RESERVED1[3]; - __IO uint8_t ADCSTA; /*!< ADC Status Register */ - __I uint8_t RESERVED2[3]; - __IO uint16_t ADCDAT; /*!< ADC Data Register */ - __I uint16_t RESERVED3; - __IO uint16_t ADCGN; /*!< ADC Gain Register */ - __I uint16_t RESERVED4; - __IO uint16_t ADCOF; /*!< ADC Offset Register */ -} ADI_ADC_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define ADCCFG (*(volatile unsigned short int *) 0x40050000) -#define ADCCON (*(volatile unsigned char *) 0x40050004) -#define ADCSTA (*(volatile unsigned char *) 0x40050008) -#define ADCDAT (*(volatile unsigned short int *) 0x4005000C) -#define ADCGN (*(volatile unsigned short int *) 0x40050010) -#define ADCOF (*(volatile unsigned short int *) 0x40050014) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for ADCCFG*/ -#define ADCCFG_RVAL 0xA00 - -/* ADCCFG[REF] - Reference select */ -#define ADCCFG_REF_BBA (*(volatile unsigned long *) 0x42A00034) -#define ADCCFG_REF_MSK (0x1 << 13 ) -#define ADCCFG_REF (0x1 << 13 ) -#define ADCCFG_REF_INTERNAL125V (0x0 << 13 ) /* INTERNAL125V. Select the internal 1.25 V reference as the ADC reference. */ -#define ADCCFG_REF_LVDD (0x1 << 13 ) /* LVDD. Select the 1.8V regulator output (LVDD1) as the ADC reference. */ - -/* ADCCFG[CLK] - ADC clock frequency */ -#define ADCCFG_CLK_MSK (0x7 << 10 ) -#define ADCCFG_CLK_FCORE (0x0 << 10 ) /* FCORE. */ -#define ADCCFG_CLK_FCOREDIV2 (0x1 << 10 ) /* FCOREDIV2. */ -#define ADCCFG_CLK_FCOREDIV4 (0x2 << 10 ) /* FCOREDIV4. */ -#define ADCCFG_CLK_FCOREDIV8 (0x3 << 10 ) /* FCOREDIV8. */ -#define ADCCFG_CLK_FCOREDIV16 (0x4 << 10 ) /* FCOREDIV16. */ -#define ADCCFG_CLK_FCOREDIV32 (0x5 << 10 ) /* FCOREDIV32. */ - -/* ADCCFG[ACQ] - Acquisition clocks */ -#define ADCCFG_ACQ_MSK (0x3 << 8 ) -#define ADCCFG_ACQ_2 (0x0 << 8 ) /* 2. */ -#define ADCCFG_ACQ_4 (0x1 << 8 ) /* 4. */ -#define ADCCFG_ACQ_8 (0x2 << 8 ) /* 8. */ -#define ADCCFG_ACQ_16 (0x3 << 8 ) /* 16. */ - -/* ADCCFG[CHSEL] - Channel select */ -#define ADCCFG_CHSEL_MSK (0xF << 0 ) -#define ADCCFG_CHSEL_ADC0 (0x0 << 0 ) /* ADC0. Single ended ADC0 input. */ -#define ADCCFG_CHSEL_ADC1 (0x1 << 0 ) /* ADC1. Single ended ADC1 input. */ -#define ADCCFG_CHSEL_ADC2 (0x2 << 0 ) /* ADC2. Single ended ADC2 input. */ -#define ADCCFG_CHSEL_ADC3 (0x3 << 0 ) /* ADC3. Single ended ADC3 input. */ -#define ADCCFG_CHSEL_ADC4 (0x4 << 0 ) /* ADC4. Single ended ADC4 input. */ -#define ADCCFG_CHSEL_ADC5 (0x5 << 0 ) /* ADC5. Single ended ADC5 input. */ -#define ADCCFG_CHSEL_DIFF0 (0x6 << 0 ) /* DIFF0. Differential ADC0 - ADC1 inputs. */ -#define ADCCFG_CHSEL_DIFF1 (0x7 << 0 ) /* DIFF1. Differential ADC2 - ADC3 inputs. */ -#define ADCCFG_CHSEL_DIFF2 (0x8 << 0 ) /* DIFF2. Differential ADC4 - ADC5 inputs. */ -#define ADCCFG_CHSEL_TEMP (0x9 << 0 ) /* TEMP. Internal temperature sensor. */ -#define ADCCFG_CHSEL_VBATDIV4 (0xA << 0 ) /* VBATDIV4. Internal supply divided by 4. */ -#define ADCCFG_CHSEL_LVDDDIV2 (0xB << 0 ) /* LVDDDIV2. Internal 1.8V regulator output (LVDD1) divided by 2. */ -#define ADCCFG_CHSEL_VREF (0xC << 0 ) /* VREF. Internal ADC reference input for gain calibration. */ -#define ADCCFG_CHSEL_AGND (0xD << 0 ) /* AGND. Internal ADC ground input for offset calibration. */ - -/* Reset Value for ADCCON*/ -#define ADCCON_RVAL 0x90 - -/* ADCCON[REFBUF] - Reference buffer enable bit. */ -#define ADCCON_REFBUF_BBA (*(volatile unsigned long *) 0x42A0009C) -#define ADCCON_REFBUF_MSK (0x1 << 7 ) -#define ADCCON_REFBUF (0x1 << 7 ) -#define ADCCON_REFBUF_EN (0x0 << 7 ) /* EN. Turn on the reference buffer. The reference buffer takes 5 ms to settle and consumes approximately 210 μA. */ -#define ADCCON_REFBUF_DIS (0x1 << 7 ) /* DIS. Turn off the reference buffer. The internal reference buffer must be turned off if using an external reference. */ - -/* ADCCON[DMA] - DMA transfer enable bit. */ -#define ADCCON_DMA_BBA (*(volatile unsigned long *) 0x42A00098) -#define ADCCON_DMA_MSK (0x1 << 6 ) -#define ADCCON_DMA (0x1 << 6 ) -#define ADCCON_DMA_DIS (0x0 << 6 ) /* DIS. Disable DMA transfer. */ -#define ADCCON_DMA_EN (0x1 << 6 ) /* EN. Enable DMA transfer. */ - -/* ADCCON[IEN] - Interrupt enable. */ -#define ADCCON_IEN_BBA (*(volatile unsigned long *) 0x42A00094) -#define ADCCON_IEN_MSK (0x1 << 5 ) -#define ADCCON_IEN (0x1 << 5 ) -#define ADCCON_IEN_DIS (0x0 << 5 ) /* DIS. Disable the ADC interrupt. */ -#define ADCCON_IEN_EN (0x1 << 5 ) /* EN. Enable the ADC interrupt. An interrupt is generated when new data is available. */ - -/* ADCCON[ENABLE] - ADC enable. */ -#define ADCCON_ENABLE_BBA (*(volatile unsigned long *) 0x42A00090) -#define ADCCON_ENABLE_MSK (0x1 << 4 ) -#define ADCCON_ENABLE (0x1 << 4 ) -#define ADCCON_ENABLE_EN (0x0 << 4 ) /* EN. Enable the ADC. */ -#define ADCCON_ENABLE_DIS (0x1 << 4 ) /* DIS. Disable the ADC. */ - -/* ADCCON[MOD] - Conversion mode. */ -#define ADCCON_MOD_MSK (0x7 << 1 ) -#define ADCCON_MOD_SOFT (0x0 << 1 ) /* SOFT. Software trigger, used in conjunction with the START bit. */ -#define ADCCON_MOD_CONT (0x1 << 1 ) /* CONT. Continuous convert mode. */ -#define ADCCON_MOD_T0OVF (0x3 << 1 ) /* T0OVF. Timer0 overflow. */ -#define ADCCON_MOD_T1OVF (0x4 << 1 ) /* T1OVF. Timer1 overflow. */ -#define ADCCON_MOD_GPIO (0x5 << 1 ) /* GPIO. ADC conversion triggered by P0.3 input. */ - -/* ADCCON[START] - ADC conversion start. */ -#define ADCCON_START_BBA (*(volatile unsigned long *) 0x42A00080) -#define ADCCON_START_MSK (0x1 << 0 ) -#define ADCCON_START (0x1 << 0 ) -#define ADCCON_START_DIS (0x0 << 0 ) /* DIS. Has no effect. */ -#define ADCCON_START_EN (0x1 << 0 ) /* EN. Start conversion when SOFT conversion mode is selected. This bit does not clear after a single software conversion. */ - -/* Reset Value for ADCSTA*/ -#define ADCSTA_RVAL 0x0 - -/* ADCSTA[READY] - ADC Ready bit */ -#define ADCSTA_READY_BBA (*(volatile unsigned long *) 0x42A00100) -#define ADCSTA_READY_MSK (0x1 << 0 ) -#define ADCSTA_READY (0x1 << 0 ) -#define ADCSTA_READY_CLR (0x0 << 0 ) /* CLR. Cleared automatically when ADCDAT is read. */ -#define ADCSTA_READY_EN (0x1 << 0 ) /* EN. Set by the ADC when a conversion is complete. This bit generates an interrupt if enabled (IEN set in ADCCON). */ - -/* Reset Value for ADCDAT*/ -#define ADCDAT_RVAL 0x0 - -/* ADCDAT[VALUE] - ADC result */ -#define ADCDAT_VALUE_MSK (0xFFF << 2 ) - -/* ADCDAT[Value_Reserved] - ADC result / Reserved */ -#define ADCDAT_Value_Reserved_MSK (0x3 << 0 ) - -/* Reset Value for ADCGN*/ -#define ADCGN_RVAL 0x0 - -/* ADCGN[VALUE] - Gain */ -#define ADCGN_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for ADCOF*/ -#define ADCOF_RVAL 0x0 - -/* ADCOF[VALUE] - Offset */ -#define ADCOF_VALUE_MSK (0xFFFF << 0 ) -// ------------------------------------------------------------------------------------------------ -// ----- CLKCTL ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Clock Control (pADI_CLKCTL) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_CLKCTL Structure */ - __IO uint16_t CLKCON; /*!< System Clocking Architecture Control Register */ - __I uint16_t RESERVED0[519]; - __IO uint8_t XOSCCON; /*!< Crystal Oscillator Control Register */ - __I uint8_t RESERVED1[111]; - __IO uint16_t CLKACT; /*!< Clock in Active Mode Enable Register */ - __I uint16_t RESERVED2; - __IO uint16_t CLKPD; /*!< Clock in Power-Down Mode Enable Register */ -} ADI_CLKCTL_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define CLKCON (*(volatile unsigned short int *) 0x40002000) -#define XOSCCON (*(volatile unsigned char *) 0x40002410) -#define CLKACT (*(volatile unsigned short int *) 0x40002480) -#define CLKPD (*(volatile unsigned short int *) 0x40002484) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for CLKCON*/ -#define CLKCON_RVAL 0x0 - -/* CLKCON[CLKOUT] - GPIO output clock multiplexer select bits. */ -#define CLKCON_CLKOUT_MSK (0x7 << 5 ) -#define CLKCON_CLKOUT_UCLKCG (0x0 << 5 ) /* UCLKCG. */ -#define CLKCON_CLKOUT_UCLK (0x1 << 5 ) /* UCLK. */ -#define CLKCON_CLKOUT_PCLK (0x2 << 5 ) /* PCLK. */ -#define CLKCON_CLKOUT_HFOSC (0x5 << 5 ) /* HFOSC. */ -#define CLKCON_CLKOUT_LFOSC (0x6 << 5 ) /* LFOSC. */ -#define CLKCON_CLKOUT_LFXTAL (0x7 << 5 ) /* LFXTAL. */ - -/* CLKCON[CLKMUX] - Digital subsystem clock source select bits. */ -#define CLKCON_CLKMUX_MSK (0x3 << 3 ) -#define CLKCON_CLKMUX_HFOSC (0x0 << 3 ) /* HFOSC. 16MHz internal oscillator. */ -#define CLKCON_CLKMUX_LFXTAL (0x1 << 3 ) /* LFXTAL. 32.768kHz external crystal. */ -#define CLKCON_CLKMUX_LFOSC (0x2 << 3 ) /* LFOSC. 32.768kHz internal oscillator. */ -#define CLKCON_CLKMUX_ECLKIN (0x3 << 3 ) /* ECLKIN. External clock on P0.5. */ - -/* CLKCON[CD] - Clock divide bits. */ -#define CLKCON_CD_MSK (0x7 << 0 ) -#define CLKCON_CD_DIV1 (0x0 << 0 ) /* DIV1. */ -#define CLKCON_CD_DIV2 (0x1 << 0 ) /* DIV2. */ -#define CLKCON_CD_DIV4 (0x2 << 0 ) /* DIV4. */ -#define CLKCON_CD_DIV8 (0x3 << 0 ) /* DIV8. */ -#define CLKCON_CD_DIV16 (0x4 << 0 ) /* DIV16. */ -#define CLKCON_CD_DIV32 (0x5 << 0 ) /* DIV32. */ -#define CLKCON_CD_DIV64 (0x6 << 0 ) /* DIV64. */ -#define CLKCON_CD_DIV128 (0x7 << 0 ) /* DIV128. */ - -/* Reset Value for XOSCCON*/ -#define XOSCCON_RVAL 0x0 - -/* XOSCCON[ENABLE] - Crystal oscillator circuit enable bit. */ -#define XOSCCON_ENABLE_BBA (*(volatile unsigned long *) 0x42048200) -#define XOSCCON_ENABLE_MSK (0x1 << 0 ) -#define XOSCCON_ENABLE (0x1 << 0 ) -#define XOSCCON_ENABLE_DIS (0x0 << 0 ) /* DIS. Disables the watch crystal circuitry.(LFXTAL) */ -#define XOSCCON_ENABLE_EN (0x1 << 0 ) /* EN. Enables the watch crystal circuitry.(LFXTAL) */ - -/* Reset Value for CLKACT*/ -#define CLKACT_RVAL 0x3FFF - -/* CLKACT[T1] - T1 clocks enable bit. */ -#define CLKACT_T1_BBA (*(volatile unsigned long *) 0x4204902C) -#define CLKACT_T1_MSK (0x1 << 11 ) -#define CLKACT_T1 (0x1 << 11 ) -#define CLKACT_T1_DIS (0x0 << 11 ) /* DIS. Disable T1 clocks. */ -#define CLKACT_T1_EN (0x1 << 11 ) /* EN. Enable T1 clocks. */ - -/* CLKACT[T0] - T0 clocks enable bit. */ -#define CLKACT_T0_BBA (*(volatile unsigned long *) 0x42049028) -#define CLKACT_T0_MSK (0x1 << 10 ) -#define CLKACT_T0 (0x1 << 10 ) -#define CLKACT_T0_DIS (0x0 << 10 ) /* DIS. Disable T0 clocks. */ -#define CLKACT_T0_EN (0x1 << 10 ) /* EN. Enable T0 clocks. */ - -/* CLKACT[PWM] - PWM clocks enable bit. */ -#define CLKACT_PWM_BBA (*(volatile unsigned long *) 0x42049024) -#define CLKACT_PWM_MSK (0x1 << 9 ) -#define CLKACT_PWM (0x1 << 9 ) -#define CLKACT_PWM_DIS (0x0 << 9 ) /* DIS. Disable PWM clocks. */ -#define CLKACT_PWM_EN (0x1 << 9 ) /* EN. Enable PWM clocks. */ - -/* CLKACT[I2C] - I2C clocks enable bit. */ -#define CLKACT_I2C_BBA (*(volatile unsigned long *) 0x42049020) -#define CLKACT_I2C_MSK (0x1 << 8 ) -#define CLKACT_I2C (0x1 << 8 ) -#define CLKACT_I2C_DIS (0x0 << 8 ) /* DIS. Disable I2C clocks. */ -#define CLKACT_I2C_EN (0x1 << 8 ) /* EN. Enable I2C clocks. */ - -/* CLKACT[COM] - UART clocks enable bit. */ -#define CLKACT_COM_BBA (*(volatile unsigned long *) 0x4204901C) -#define CLKACT_COM_MSK (0x1 << 7 ) -#define CLKACT_COM (0x1 << 7 ) -#define CLKACT_COM_DIS (0x0 << 7 ) /* DIS. Disable UART clocks. */ -#define CLKACT_COM_EN (0x1 << 7 ) /* EN. Enable UART clocks. */ - -/* CLKACT[SPI1] - SPI1 clocks enable bit. */ -#define CLKACT_SPI1_BBA (*(volatile unsigned long *) 0x42049018) -#define CLKACT_SPI1_MSK (0x1 << 6 ) -#define CLKACT_SPI1 (0x1 << 6 ) -#define CLKACT_SPI1_DIS (0x0 << 6 ) /* DIS. Disable SPI1 clocks. */ -#define CLKACT_SPI1_EN (0x1 << 6 ) /* EN. Enable SPI1 clocks. */ - -/* CLKACT[SPI0] - SPI0 clocks enable bit. */ -#define CLKACT_SPI0_BBA (*(volatile unsigned long *) 0x42049014) -#define CLKACT_SPI0_MSK (0x1 << 5 ) -#define CLKACT_SPI0 (0x1 << 5 ) -#define CLKACT_SPI0_DIS (0x0 << 5 ) /* DIS. Disable SPI0 clocks. */ -#define CLKACT_SPI0_EN (0x1 << 5 ) /* EN. Enable SPI0 clocks. */ - -/* CLKACT[T2] - T2 clocks enable bit. */ -#define CLKACT_T2_BBA (*(volatile unsigned long *) 0x42049010) -#define CLKACT_T2_MSK (0x1 << 4 ) -#define CLKACT_T2 (0x1 << 4 ) -#define CLKACT_T2_DIS (0x0 << 4 ) /* DIS. Disable T2 clocks. */ -#define CLKACT_T2_EN (0x1 << 4 ) /* EN. Enable T2 clocks. */ - -/* CLKACT[ADC] - ADC clocks enable bit. */ -#define CLKACT_ADC_BBA (*(volatile unsigned long *) 0x4204900C) -#define CLKACT_ADC_MSK (0x1 << 3 ) -#define CLKACT_ADC (0x1 << 3 ) -#define CLKACT_ADC_DIS (0x0 << 3 ) /* DIS. Disable ADC clocks. */ -#define CLKACT_ADC_EN (0x1 << 3 ) /* EN. Enable ADC clocks. */ - -/* CLKACT[SRAM] - SRAM clocks enable bit. */ -#define CLKACT_SRAM_BBA (*(volatile unsigned long *) 0x42049008) -#define CLKACT_SRAM_MSK (0x1 << 2 ) -#define CLKACT_SRAM (0x1 << 2 ) -#define CLKACT_SRAM_DIS (0x0 << 2 ) /* DIS. Disable SRAM memory clocks. */ -#define CLKACT_SRAM_EN (0x1 << 2 ) /* EN. Enable SRAM memory clocks. */ - -/* CLKACT[FEE] - Flash clocks enable bit. */ -#define CLKACT_FEE_BBA (*(volatile unsigned long *) 0x42049004) -#define CLKACT_FEE_MSK (0x1 << 1 ) -#define CLKACT_FEE (0x1 << 1 ) -#define CLKACT_FEE_DIS (0x0 << 1 ) /* DIS. Disable Flash memory clocks. */ -#define CLKACT_FEE_EN (0x1 << 1 ) /* EN. Enable Flash memory clocks. */ - -/* CLKACT[DMA] - DMA clock enable bit. */ -#define CLKACT_DMA_BBA (*(volatile unsigned long *) 0x42049000) -#define CLKACT_DMA_MSK (0x1 << 0 ) -#define CLKACT_DMA (0x1 << 0 ) -#define CLKACT_DMA_DIS (0x0 << 0 ) /* DIS.Disable DMA clock. */ -#define CLKACT_DMA_EN (0x1 << 0 ) /* EN. Enable DMA clock. */ - -/* Reset Value for CLKPD*/ -#define CLKPD_RVAL 0x3FFF - -/* CLKPD[T1] - T1 clocks enable bit. */ -#define CLKPD_T1_BBA (*(volatile unsigned long *) 0x420490AC) -#define CLKPD_T1_MSK (0x1 << 11 ) -#define CLKPD_T1 (0x1 << 11 ) -#define CLKPD_T1_DIS (0x0 << 11 ) /* DIS. Disable T1 clocks. */ -#define CLKPD_T1_EN (0x1 << 11 ) /* EN. Enable T1 clocks. */ - -/* CLKPD[T0] - T0 clocks enable bit. */ -#define CLKPD_T0_BBA (*(volatile unsigned long *) 0x420490A8) -#define CLKPD_T0_MSK (0x1 << 10 ) -#define CLKPD_T0 (0x1 << 10 ) -#define CLKPD_T0_DIS (0x0 << 10 ) /* DIS. Disable T0 clocks. */ -#define CLKPD_T0_EN (0x1 << 10 ) /* EN. Enable T0 clocks. */ - -/* CLKPD[PWM] - PWM clocks enable bit. */ -#define CLKPD_PWM_BBA (*(volatile unsigned long *) 0x420490A4) -#define CLKPD_PWM_MSK (0x1 << 9 ) -#define CLKPD_PWM (0x1 << 9 ) -#define CLKPD_PWM_DIS (0x0 << 9 ) /* DIS. Disable PWM clocks. */ -#define CLKPD_PWM_EN (0x1 << 9 ) /* EN. Enable PWM clocks. */ - -/* CLKPD[I2C] - I2C clocks enable bit. */ -#define CLKPD_I2C_BBA (*(volatile unsigned long *) 0x420490A0) -#define CLKPD_I2C_MSK (0x1 << 8 ) -#define CLKPD_I2C (0x1 << 8 ) -#define CLKPD_I2C_DIS (0x0 << 8 ) /* DIS. Disable I2C clocks. */ -#define CLKPD_I2C_EN (0x1 << 8 ) /* EN. Enable I2C clocks. */ - -/* CLKPD[COM] - UART clocks enable bit. */ -#define CLKPD_COM_BBA (*(volatile unsigned long *) 0x4204909C) -#define CLKPD_COM_MSK (0x1 << 7 ) -#define CLKPD_COM (0x1 << 7 ) -#define CLKPD_COM_DIS (0x0 << 7 ) /* DIS. Disable UART clocks. */ -#define CLKPD_COM_EN (0x1 << 7 ) /* EN. Enable UART clocks. */ - -/* CLKPD[SPI1] - SPI1 clocks enable bit. */ -#define CLKPD_SPI1_BBA (*(volatile unsigned long *) 0x42049098) -#define CLKPD_SPI1_MSK (0x1 << 6 ) -#define CLKPD_SPI1 (0x1 << 6 ) -#define CLKPD_SPI1_DIS (0x0 << 6 ) /* DIS. Disable SPI1 clocks. */ -#define CLKPD_SPI1_EN (0x1 << 6 ) /* EN. Enable SPI1 clocks. */ - -/* CLKPD[SPI0] - SPI0 clocks enable bit. */ -#define CLKPD_SPI0_BBA (*(volatile unsigned long *) 0x42049094) -#define CLKPD_SPI0_MSK (0x1 << 5 ) -#define CLKPD_SPI0 (0x1 << 5 ) -#define CLKPD_SPI0_DIS (0x0 << 5 ) /* DIS. Disable SPI0 clocks. */ -#define CLKPD_SPI0_EN (0x1 << 5 ) /* EN. Enable SPI0 clocks. */ - -/* CLKPD[T2] - T2 clocks enable bit. */ -#define CLKPD_T2_BBA (*(volatile unsigned long *) 0x42049090) -#define CLKPD_T2_MSK (0x1 << 4 ) -#define CLKPD_T2 (0x1 << 4 ) -#define CLKPD_T2_DIS (0x0 << 4 ) /* DIS. Disable T2 clocks. */ -#define CLKPD_T2_EN (0x1 << 4 ) /* EN. Enable T2 clocks. */ - -/* CLKPD[ADC] - ADC clocks enable bit. */ -#define CLKPD_ADC_BBA (*(volatile unsigned long *) 0x4204908C) -#define CLKPD_ADC_MSK (0x1 << 3 ) -#define CLKPD_ADC (0x1 << 3 ) -#define CLKPD_ADC_DIS (0x0 << 3 ) /* DIS. Disable ADC clocks. */ -#define CLKPD_ADC_EN (0x1 << 3 ) /* EN. Enable ADC clocks. */ - -/* CLKPD[SRAM] - SRAM clocks enable bit. */ -#define CLKPD_SRAM_BBA (*(volatile unsigned long *) 0x42049088) -#define CLKPD_SRAM_MSK (0x1 << 2 ) -#define CLKPD_SRAM (0x1 << 2 ) -#define CLKPD_SRAM_DIS (0x0 << 2 ) /* DIS. Disable SRAM memory clocks. */ -#define CLKPD_SRAM_EN (0x1 << 2 ) /* EN. Enable SRAM memory clocks. */ - -/* CLKPD[FEE] - Flash clocks enable bit. */ -#define CLKPD_FEE_BBA (*(volatile unsigned long *) 0x42049084) -#define CLKPD_FEE_MSK (0x1 << 1 ) -#define CLKPD_FEE (0x1 << 1 ) -#define CLKPD_FEE_DIS (0x0 << 1 ) /* DIS. Disable Flash memory clocks. */ -#define CLKPD_FEE_EN (0x1 << 1 ) /* EN. Enable Flash memory clocks. */ - -/* CLKPD[DMA] - DMA clock enable bit. */ -#define CLKPD_DMA_BBA (*(volatile unsigned long *) 0x42049080) -#define CLKPD_DMA_MSK (0x1 << 0 ) -#define CLKPD_DMA (0x1 << 0 ) -#define CLKPD_DMA_DIS (0x0 << 0 ) /* DIS. Disable DMA clock. */ -#define CLKPD_DMA_EN (0x1 << 0 ) /* EN. Enable DMA clock. */ -// ------------------------------------------------------------------------------------------------ -// ----- DMA ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Direct Memory Access (pADI_DMA) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_DMA Structure */ - __IO uint32_t DMASTA; /*!< Status Register */ - __IO uint32_t DMACFG; /*!< Configuration Register */ - __IO uint32_t DMAPDBPTR; /*!< Primary Control Database Pointer Register */ - __IO uint32_t DMAADBPTR; /*!< Alternate Control Database Pointer Register */ - __I uint32_t RESERVED0; - __IO uint32_t DMASWREQ; /*!< Channel Software Request Register */ - __I uint32_t RESERVED1[2]; - __IO uint32_t DMARMSKSET; /*!< Channel Request Mask Set Register */ - __IO uint32_t DMARMSKCLR; /*!< Channel Request Mask Clear Register */ - __IO uint32_t DMAENSET; /*!< Channel Enable Set Register */ - __IO uint32_t DMAENCLR; /*!< Channel Enable Clear Register */ - __IO uint32_t DMAALTSET; /*!< Channel Primary-Alternate Set Register */ - __IO uint32_t DMAALTCLR; /*!< Channel Primary-Alternate Clear Register */ - __IO uint32_t DMAPRISET; /*!< Channel Priority Set Register */ - __IO uint32_t DMAPRICLR; /*!< Channel Priority Clear Register */ - __I uint32_t RESERVED2[3]; - __IO uint32_t DMAERRCLR; /*!< Bus Error Clear Register */ -} ADI_DMA_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define DMASTA (*(volatile unsigned long *) 0x40010000) -#define DMACFG (*(volatile unsigned long *) 0x40010004) -#define DMAPDBPTR (*(volatile unsigned long *) 0x40010008) -#define DMAADBPTR (*(volatile unsigned long *) 0x4001000C) -#define DMASWREQ (*(volatile unsigned long *) 0x40010014) -#define DMARMSKSET (*(volatile unsigned long *) 0x40010020) -#define DMARMSKCLR (*(volatile unsigned long *) 0x40010024) -#define DMAENSET (*(volatile unsigned long *) 0x40010028) -#define DMAENCLR (*(volatile unsigned long *) 0x4001002C) -#define DMAALTSET (*(volatile unsigned long *) 0x40010030) -#define DMAALTCLR (*(volatile unsigned long *) 0x40010034) -#define DMAPRISET (*(volatile unsigned long *) 0x40010038) -#define DMAPRICLR (*(volatile unsigned long *) 0x4001003C) -#define DMAERRCLR (*(volatile unsigned long *) 0x4001004C) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for DMASTA*/ -#define DMASTA_RVAL 0xD0000 - -/* DMASTA[CHNLSMINUS1] - Number of available DMA channels minus 1. For example, if there are 14 channels available, the register reads back 0xD for these bits. */ -#define DMASTA_CHNLSMINUS1_MSK (0x1F << 16 ) -#define DMASTA_CHNLSMINUS1_FOURTEENCHNLS (0xD << 16 ) /* FOURTEENCHNLS - Controller configured to use 14 DMA channels. */ - -/* DMASTA[STATE] - Current state of DMA controller state machine. Provides insight into the operation performed by the DMA at the time this register is read. */ -#define DMASTA_STATE_MSK (0xF << 4 ) -#define DMASTA_STATE_IDLE (0x0 << 4 ) /* IDL. Idle. */ -#define DMASTA_STATE_RDCHNLDATA (0x1 << 4 ) /* RDCHNLDATA. Reading channel controller data. */ -#define DMASTA_STATE_RDSRCENDPTR (0x2 << 4 ) /* RDSRCENDPTR. Reading source data end pointer. */ -#define DMASTA_STATE_RDDSTENDPTR (0x3 << 4 ) /* RDDSTENDPTR. Reading destination end pointer. */ -#define DMASTA_STATE_RDSRCDATA (0x4 << 4 ) /* RDSRCDATA. Reading source data. */ -#define DMASTA_STATE_WRDSTDATA (0x5 << 4 ) /* WRDSTDATA. Writing destination data. */ -#define DMASTA_STATE_WAITDMAREQCLR (0x6 << 4 ) /* WAITDMAREQCLR. Waiting for DMA request to clear. */ -#define DMASTA_STATE_WRCHNLDATA (0x7 << 4 ) /* WRCHNLDATA. Writing channel controller data. */ -#define DMASTA_STATE_STALLED (0x8 << 4 ) /* STALLED. Stalled. */ -#define DMASTA_STATE_DONE (0x9 << 4 ) /* DONE. Done. */ -#define DMASTA_STATE_SCATRGATHR (0xA << 4 ) /* SCATRGATHR. Peripheral scatter-gather transition. */ - -/* DMASTA[ENABLE] - Enable status of the controller. */ -#define DMASTA_ENABLE_BBA (*(volatile unsigned long *) 0x42200000) -#define DMASTA_ENABLE_MSK (0x1 << 0 ) -#define DMASTA_ENABLE (0x1 << 0 ) -#define DMASTA_ENABLE_CLR (0x0 << 0 ) /* CLR. Controller is disabled. */ -#define DMASTA_ENABLE_SET (0x1 << 0 ) /* SET. Controller is enabled. */ - -/* Reset Value for DMACFG*/ -#define DMACFG_RVAL 0x0 - -/* DMACFG[ENABLE] - Controller enable. */ -#define DMACFG_ENABLE_BBA (*(volatile unsigned long *) 0x42200080) -#define DMACFG_ENABLE_MSK (0x1 << 0 ) -#define DMACFG_ENABLE (0x1 << 0 ) -#define DMACFG_ENABLE_DIS (0x0 << 0 ) /* DIS. Controller is disabled. */ -#define DMACFG_ENABLE_EN (0x1 << 0 ) /* EN. Controller is enabled. */ - -/* Reset Value for DMAPDBPTR*/ -#define DMAPDBPTR_RVAL 0x0 - -/* DMAPDBPTR[CTRLBASEPTR] - Pointer to the base address of the primary data structure. 5 + log (2)M LSBs are reserved and must be written 0. M is the number of channels. */ -#define DMAPDBPTR_CTRLBASEPTR_MSK (0xFFFFFFFF << 0 ) - -/* Reset Value for DMAADBPTR*/ -#define DMAADBPTR_RVAL 0x100 - -/* DMAADBPTR[ALTCBPTR] - Base address of the alternate data structure. */ -#define DMAADBPTR_ALTCBPTR_MSK (0xFFFFFFFF << 0 ) - -/* Reset Value for DMASWREQ*/ -#define DMASWREQ_RVAL 0x0 - -/* DMASWREQ[SPI0RX] - DMA SPI0 RX. */ -#define DMASWREQ_SPI0RX_BBA (*(volatile unsigned long *) 0x422002B4) -#define DMASWREQ_SPI0RX_MSK (0x1 << 13 ) -#define DMASWREQ_SPI0RX (0x1 << 13 ) -#define DMASWREQ_SPI0RX_DIS (0x0 << 13 ) /* DIS. Does not create a DMA request for SPI0RX. */ -#define DMASWREQ_SPI0RX_EN (0x1 << 13 ) /* EN. Generates a DMA request for SPI0RX. */ - -/* DMASWREQ[SPI0TX] - DMA SPI0 TX. */ -#define DMASWREQ_SPI0TX_BBA (*(volatile unsigned long *) 0x422002B0) -#define DMASWREQ_SPI0TX_MSK (0x1 << 12 ) -#define DMASWREQ_SPI0TX (0x1 << 12 ) -#define DMASWREQ_SPI0TX_DIS (0x0 << 12 ) /* DIS. Does not create a DMA request for SPI0TX. */ -#define DMASWREQ_SPI0TX_EN (0x1 << 12 ) /* EN. Generates a DMA request for SPI0TX. */ - -/* DMASWREQ[ADC] - DMA ADC. */ -#define DMASWREQ_ADC_BBA (*(volatile unsigned long *) 0x422002AC) -#define DMASWREQ_ADC_MSK (0x1 << 11 ) -#define DMASWREQ_ADC (0x1 << 11 ) -#define DMASWREQ_ADC_DIS (0x0 << 11 ) /* DIS. Does not create a DMA request for ADC. */ -#define DMASWREQ_ADC_EN (0x1 << 11 ) /* EN. Generates a DMA request for ADC. */ - -/* DMASWREQ[I2CMRX] - DMA I2C Master RX. */ -#define DMASWREQ_I2CMRX_BBA (*(volatile unsigned long *) 0x4220029C) -#define DMASWREQ_I2CMRX_MSK (0x1 << 7 ) -#define DMASWREQ_I2CMRX (0x1 << 7 ) -#define DMASWREQ_I2CMRX_DIS (0x0 << 7 ) /* DIS. Does not create a DMA request for I2CMRX. */ -#define DMASWREQ_I2CMRX_EN (0x1 << 7 ) /* EN. Generates a DMA request for I2CMRX. */ - -/* DMASWREQ[I2CMTX] - DMA I2C Master TX. */ -#define DMASWREQ_I2CMTX_BBA (*(volatile unsigned long *) 0x42200298) -#define DMASWREQ_I2CMTX_MSK (0x1 << 6 ) -#define DMASWREQ_I2CMTX (0x1 << 6 ) -#define DMASWREQ_I2CMTX_DIS (0x0 << 6 ) /* DIS. Does not create a DMA request for I2CMTX. */ -#define DMASWREQ_I2CMTX_EN (0x1 << 6 ) /* EN. Generates a DMA request for I2CMTX. */ - -/* DMASWREQ[I2CSRX] - DMA I2C Slave RX. */ -#define DMASWREQ_I2CSRX_BBA (*(volatile unsigned long *) 0x42200294) -#define DMASWREQ_I2CSRX_MSK (0x1 << 5 ) -#define DMASWREQ_I2CSRX (0x1 << 5 ) -#define DMASWREQ_I2CSRX_DIS (0x0 << 5 ) /* DIS. Does not create a DMA request for I2CSRX. */ -#define DMASWREQ_I2CSRX_EN (0x1 << 5 ) /* EN. Generates a DMA request for I2CSRX. */ - -/* DMASWREQ[I2CSTX] - DMA I2C Slave TX. */ -#define DMASWREQ_I2CSTX_BBA (*(volatile unsigned long *) 0x42200290) -#define DMASWREQ_I2CSTX_MSK (0x1 << 4 ) -#define DMASWREQ_I2CSTX (0x1 << 4 ) -#define DMASWREQ_I2CSTX_DIS (0x0 << 4 ) /* DIS. Does not create a DMA request for I2CSTX. */ -#define DMASWREQ_I2CSTX_EN (0x1 << 4 ) /* EN. Generates a DMA request for I2CSTX. */ - -/* DMASWREQ[UARTRX] - DMA UART RX. */ -#define DMASWREQ_UARTRX_BBA (*(volatile unsigned long *) 0x4220028C) -#define DMASWREQ_UARTRX_MSK (0x1 << 3 ) -#define DMASWREQ_UARTRX (0x1 << 3 ) -#define DMASWREQ_UARTRX_DIS (0x0 << 3 ) /* DIS. Does not create a DMA request for UARTRX. */ -#define DMASWREQ_UARTRX_EN (0x1 << 3 ) /* EN. Generates a DMA request for UARTRX. */ - -/* DMASWREQ[UARTTX] - DMA UART TX. */ -#define DMASWREQ_UARTTX_BBA (*(volatile unsigned long *) 0x42200288) -#define DMASWREQ_UARTTX_MSK (0x1 << 2 ) -#define DMASWREQ_UARTTX (0x1 << 2 ) -#define DMASWREQ_UARTTX_DIS (0x0 << 2 ) /* DIS. Does not create a DMA request for UARTTX. */ -#define DMASWREQ_UARTTX_EN (0x1 << 2 ) /* EN. Generates a DMA request for UARTTX. */ - -/* DMASWREQ[SPI1RX] - DMA SPI 1 RX. */ -#define DMASWREQ_SPI1RX_BBA (*(volatile unsigned long *) 0x42200284) -#define DMASWREQ_SPI1RX_MSK (0x1 << 1 ) -#define DMASWREQ_SPI1RX (0x1 << 1 ) -#define DMASWREQ_SPI1RX_DIS (0x0 << 1 ) /* DIS. Does not create a DMA request for SPI1RX. */ -#define DMASWREQ_SPI1RX_EN (0x1 << 1 ) /* EN. Generates a DMA request for SPI1RX. */ - -/* DMASWREQ[SPI1TX] - DMA SPI 1 TX. */ -#define DMASWREQ_SPI1TX_BBA (*(volatile unsigned long *) 0x42200280) -#define DMASWREQ_SPI1TX_MSK (0x1 << 0 ) -#define DMASWREQ_SPI1TX (0x1 << 0 ) -#define DMASWREQ_SPI1TX_DIS (0x0 << 0 ) /* DIS. Does not create a DMA request for SPI1TX. */ -#define DMASWREQ_SPI1TX_EN (0x1 << 0 ) /* EN. Generates a DMA request for SPI1TX. */ - -/* Reset Value for DMARMSKSET*/ -#define DMARMSKSET_RVAL 0x0 - -/* DMARMSKSET[SPI0RX] - DMA SPI0 RX. */ -#define DMARMSKSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200434) -#define DMARMSKSET_SPI0RX_MSK (0x1 << 13 ) -#define DMARMSKSET_SPI0RX (0x1 << 13 ) -#define DMARMSKSET_SPI0RX_DIS (0x0 << 13 ) /* DIS. When read: Requests are enabled for SPI0RX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ -#define DMARMSKSET_SPI0RX_EN (0x1 << 13 ) /* EN. When read: Requests are disabled for SPI0RX. When written: Disables peripheral associated with SPI0RX from generating DMA requests. */ - -/* DMARMSKSET[SPI0TX] - DMA SPI0 TX. */ -#define DMARMSKSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200430) -#define DMARMSKSET_SPI0TX_MSK (0x1 << 12 ) -#define DMARMSKSET_SPI0TX (0x1 << 12 ) -#define DMARMSKSET_SPI0TX_DIS (0x0 << 12 ) /* DIS. When read: Requests are enabled for SPI0TX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ -#define DMARMSKSET_SPI0TX_EN (0x1 << 12 ) /* EN. When read: Requests are disabled for SPI0TX. When written: Disables peripheral associated with SPI0TX from generating DMA requests. */ - -/* DMARMSKSET[ADC] - DMA ADC. */ -#define DMARMSKSET_ADC_BBA (*(volatile unsigned long *) 0x4220042C) -#define DMARMSKSET_ADC_MSK (0x1 << 11 ) -#define DMARMSKSET_ADC (0x1 << 11 ) -#define DMARMSKSET_ADC_DIS (0x0 << 11 ) /* DIS. When read: Requests are enabled for ADC. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ -#define DMARMSKSET_ADC_EN (0x1 << 11 ) /* EN. When read: Requests are disabled for ADC. When written: Disables peripheral associated with ADC from generating DMA requests. */ - -/* DMARMSKSET[I2CMRX] - DMA I2C Master RX. */ -#define DMARMSKSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220041C) -#define DMARMSKSET_I2CMRX_MSK (0x1 << 7 ) -#define DMARMSKSET_I2CMRX (0x1 << 7 ) -#define DMARMSKSET_I2CMRX_DIS (0x0 << 7 ) /* DIS. When read: Requests are enabled for I2CMRX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ -#define DMARMSKSET_I2CMRX_EN (0x1 << 7 ) /* EN. When read: Requests are disabled for I2CMRX. When written: Disables peripheral associated with I2CMRX from generating DMA requests. */ - -/* DMARMSKSET[I2CMTX] - DMA I2C Master TX. */ -#define DMARMSKSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200418) -#define DMARMSKSET_I2CMTX_MSK (0x1 << 6 ) -#define DMARMSKSET_I2CMTX (0x1 << 6 ) -#define DMARMSKSET_I2CMTX_DIS (0x0 << 6 ) /* DIS. When read: Requests are enabled for I2CMTX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ -#define DMARMSKSET_I2CMTX_EN (0x1 << 6 ) /* EN. When read: Requests are disabled for I2CMTX. When written: Disables peripheral associated with I2CMTX from generating DMA requests. */ - -/* DMARMSKSET[I2CSRX] - DMA I2C Slave RX. */ -#define DMARMSKSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200414) -#define DMARMSKSET_I2CSRX_MSK (0x1 << 5 ) -#define DMARMSKSET_I2CSRX (0x1 << 5 ) -#define DMARMSKSET_I2CSRX_DIS (0x0 << 5 ) /* DIS. When read: Requests are enabled for I2CSRX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ -#define DMARMSKSET_I2CSRX_EN (0x1 << 5 ) /* EN. When read: Requests are disabled for I2CSRX. When written: Disables peripheral associated with I2CSRX from generating DMA requests. */ - -/* DMARMSKSET[I2CSTX] - DMA I2C Slave TX. */ -#define DMARMSKSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200410) -#define DMARMSKSET_I2CSTX_MSK (0x1 << 4 ) -#define DMARMSKSET_I2CSTX (0x1 << 4 ) -#define DMARMSKSET_I2CSTX_DIS (0x0 << 4 ) /* DIS. When read: Requests are enabled forI2CSTX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ -#define DMARMSKSET_I2CSTX_EN (0x1 << 4 ) /* EN. When read: Requests are disabled for I2CSTX. When written: Disables peripheral associated with I2CSTX from generating DMA requests. */ - -/* DMARMSKSET[UARTRX] - DMA UART RX. */ -#define DMARMSKSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220040C) -#define DMARMSKSET_UARTRX_MSK (0x1 << 3 ) -#define DMARMSKSET_UARTRX (0x1 << 3 ) -#define DMARMSKSET_UARTRX_DIS (0x0 << 3 ) /* DIS. When read: Requests are enabled for UARTRX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ -#define DMARMSKSET_UARTRX_EN (0x1 << 3 ) /* EN. When read: Requests are disabled for UARTRX. When written: Disables peripheral associated with UARTRX from generating DMA requests. */ - -/* DMARMSKSET[UARTTX] - DMA UART TX. */ -#define DMARMSKSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200408) -#define DMARMSKSET_UARTTX_MSK (0x1 << 2 ) -#define DMARMSKSET_UARTTX (0x1 << 2 ) -#define DMARMSKSET_UARTTX_DIS (0x0 << 2 ) /* DIS. When read: Requests are enabled for UARTTX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ -#define DMARMSKSET_UARTTX_EN (0x1 << 2 ) /* EN. When read: Requests are disabled for UARTTX. When written: Disables peripheral associated with UARTTX from generating DMA requests. */ - -/* DMARMSKSET[SPI1RX] - DMA SPI 1 RX. */ -#define DMARMSKSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200404) -#define DMARMSKSET_SPI1RX_MSK (0x1 << 1 ) -#define DMARMSKSET_SPI1RX (0x1 << 1 ) -#define DMARMSKSET_SPI1RX_DIS (0x0 << 1 ) /* DIS. When read: Requests are enabled for SPI1RX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ -#define DMARMSKSET_SPI1RX_EN (0x1 << 1 ) /* EN. When read: Requests are disabled for SPI1RX. When written: Disables peripheral associated with SPI1RX from generating DMA requests. */ - -/* DMARMSKSET[SPI1TX] - DMA SPI 1 TX. */ -#define DMARMSKSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200400) -#define DMARMSKSET_SPI1TX_MSK (0x1 << 0 ) -#define DMARMSKSET_SPI1TX (0x1 << 0 ) -#define DMARMSKSET_SPI1TX_DIS (0x0 << 0 ) /* DIS. When read: Requests are enabled for SPI1TX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ -#define DMARMSKSET_SPI1TX_EN (0x1 << 0 ) /* EN. When read: Requests are disabled for SPI1TX When written: Disables peripheral associated with SPI1TX from generating DMA requests. */ - -/* Reset Value for DMARMSKCLR*/ -#define DMARMSKCLR_RVAL 0x0 - -/* DMARMSKCLR[SPI0RX] - DMA SPI0 RX. */ -#define DMARMSKCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422004B4) -#define DMARMSKCLR_SPI0RX_MSK (0x1 << 13 ) -#define DMARMSKCLR_SPI0RX (0x1 << 13 ) -#define DMARMSKCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ -#define DMARMSKCLR_SPI0RX_EN (0x1 << 13 ) /* EN. Enables peripheral associated with SPI0RX to generate DMA requests. */ - -/* DMARMSKCLR[SPI0TX] - DMA SPI0 TX. */ -#define DMARMSKCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422004B0) -#define DMARMSKCLR_SPI0TX_MSK (0x1 << 12 ) -#define DMARMSKCLR_SPI0TX (0x1 << 12 ) -#define DMARMSKCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ -#define DMARMSKCLR_SPI0TX_EN (0x1 << 12 ) /* EN. Enables peripheral associated with SPI0TX to generate DMA requests. */ - -/* DMARMSKCLR[ADC] - DMA ADC. */ -#define DMARMSKCLR_ADC_BBA (*(volatile unsigned long *) 0x422004AC) -#define DMARMSKCLR_ADC_MSK (0x1 << 11 ) -#define DMARMSKCLR_ADC (0x1 << 11 ) -#define DMARMSKCLR_ADC_DIS (0x0 << 11 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ -#define DMARMSKCLR_ADC_EN (0x1 << 11 ) /* EN. Enables peripheral associated with ADC to generate DMA requests. */ - -/* DMARMSKCLR[I2CMRX] - DMA I2C Master RX. */ -#define DMARMSKCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220049C) -#define DMARMSKCLR_I2CMRX_MSK (0x1 << 7 ) -#define DMARMSKCLR_I2CMRX (0x1 << 7 ) -#define DMARMSKCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ -#define DMARMSKCLR_I2CMRX_EN (0x1 << 7 ) /* EN. Enables peripheral associated with I2CMRX to generate DMA requests. */ - -/* DMARMSKCLR[I2CMTX] - DMA I2C Master TX. */ -#define DMARMSKCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200498) -#define DMARMSKCLR_I2CMTX_MSK (0x1 << 6 ) -#define DMARMSKCLR_I2CMTX (0x1 << 6 ) -#define DMARMSKCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ -#define DMARMSKCLR_I2CMTX_EN (0x1 << 6 ) /* EN. Enables peripheral associated with I2CMTX to generate DMA requests. */ - -/* DMARMSKCLR[I2CSRX] - DMA I2C Slave RX. */ -#define DMARMSKCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200494) -#define DMARMSKCLR_I2CSRX_MSK (0x1 << 5 ) -#define DMARMSKCLR_I2CSRX (0x1 << 5 ) -#define DMARMSKCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ -#define DMARMSKCLR_I2CSRX_EN (0x1 << 5 ) /* EN. Enables peripheral associated with I2CSRX to generate DMA requests. */ - -/* DMARMSKCLR[I2CSTX] - DMA I2C Slave TX. */ -#define DMARMSKCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200490) -#define DMARMSKCLR_I2CSTX_MSK (0x1 << 4 ) -#define DMARMSKCLR_I2CSTX (0x1 << 4 ) -#define DMARMSKCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ -#define DMARMSKCLR_I2CSTX_EN (0x1 << 4 ) /* EN. Enables peripheral associated with I2CSTX to generate DMA requests. */ - -/* DMARMSKCLR[UARTRX] - DMA UART RX. */ -#define DMARMSKCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220048C) -#define DMARMSKCLR_UARTRX_MSK (0x1 << 3 ) -#define DMARMSKCLR_UARTRX (0x1 << 3 ) -#define DMARMSKCLR_UARTRX_DIS (0x0 << 3 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ -#define DMARMSKCLR_UARTRX_EN (0x1 << 3 ) /* EN. Enables peripheral associated with UARTRX to generate DMA requests. */ - -/* DMARMSKCLR[UARTTX] - DMA UART TX. */ -#define DMARMSKCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200488) -#define DMARMSKCLR_UARTTX_MSK (0x1 << 2 ) -#define DMARMSKCLR_UARTTX (0x1 << 2 ) -#define DMARMSKCLR_UARTTX_DIS (0x0 << 2 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ -#define DMARMSKCLR_UARTTX_EN (0x1 << 2 ) /* EN. Enables peripheral associated with UARTTX to generate DMA requests. */ - -/* DMARMSKCLR[SPI1RX] - DMA SPI 1 RX. */ -#define DMARMSKCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200484) -#define DMARMSKCLR_SPI1RX_MSK (0x1 << 1 ) -#define DMARMSKCLR_SPI1RX (0x1 << 1 ) -#define DMARMSKCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ -#define DMARMSKCLR_SPI1RX_EN (0x1 << 1 ) /* EN. Enables peripheral associated with SPI1RX to generate DMA requests. */ - -/* DMARMSKCLR[SPI1TX] - DMA SPI 1 TX. */ -#define DMARMSKCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200480) -#define DMARMSKCLR_SPI1TX_MSK (0x1 << 0 ) -#define DMARMSKCLR_SPI1TX (0x1 << 0 ) -#define DMARMSKCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ -#define DMARMSKCLR_SPI1TX_EN (0x1 << 0 ) /* EN. Enables peripheral associated with SPI1TX to generate DMA requests. */ - -/* Reset Value for DMAENSET*/ -#define DMAENSET_RVAL 0x0 - -/* DMAENSET[SPI0RX] - DMA SPI0 RX */ -#define DMAENSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200534) -#define DMAENSET_SPI0RX_MSK (0x1 << 13 ) -#define DMAENSET_SPI0RX (0x1 << 13 ) -#define DMAENSET_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ -#define DMAENSET_SPI0RX_EN (0x1 << 13 ) /* EN. Enables SPI0RX. */ - -/* DMAENSET[SPI0TX] - DMA SPI0 TX. */ -#define DMAENSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200530) -#define DMAENSET_SPI0TX_MSK (0x1 << 12 ) -#define DMAENSET_SPI0TX (0x1 << 12 ) -#define DMAENSET_SPI0TX_DIS (0x0 << 12 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ -#define DMAENSET_SPI0TX_EN (0x1 << 12 ) /* EN. Enables SPI0TX. */ - -/* DMAENSET[ADC] - DMA ADC. */ -#define DMAENSET_ADC_BBA (*(volatile unsigned long *) 0x4220052C) -#define DMAENSET_ADC_MSK (0x1 << 11 ) -#define DMAENSET_ADC (0x1 << 11 ) -#define DMAENSET_ADC_DIS (0x0 << 11 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ -#define DMAENSET_ADC_EN (0x1 << 11 ) /* EN. Enables ADC. */ - -/* DMAENSET[I2CMRX] - DMA I2C Master RX. */ -#define DMAENSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220051C) -#define DMAENSET_I2CMRX_MSK (0x1 << 7 ) -#define DMAENSET_I2CMRX (0x1 << 7 ) -#define DMAENSET_I2CMRX_DIS (0x0 << 7 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ -#define DMAENSET_I2CMRX_EN (0x1 << 7 ) /* EN. . Enables I2CMRX. */ - -/* DMAENSET[I2CMTX] - DMA I2C Master TX. */ -#define DMAENSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200518) -#define DMAENSET_I2CMTX_MSK (0x1 << 6 ) -#define DMAENSET_I2CMTX (0x1 << 6 ) -#define DMAENSET_I2CMTX_DIS (0x0 << 6 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ -#define DMAENSET_I2CMTX_EN (0x1 << 6 ) /* EN. . Enables I2CMTX. */ - -/* DMAENSET[I2CSRX] - DMA I2C Slave RX. */ -#define DMAENSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200514) -#define DMAENSET_I2CSRX_MSK (0x1 << 5 ) -#define DMAENSET_I2CSRX (0x1 << 5 ) -#define DMAENSET_I2CSRX_DIS (0x0 << 5 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ -#define DMAENSET_I2CSRX_EN (0x1 << 5 ) /* EN. Enables I2CSRX. */ - -/* DMAENSET[I2CSTX] - DMA I2C Slave TX. */ -#define DMAENSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200510) -#define DMAENSET_I2CSTX_MSK (0x1 << 4 ) -#define DMAENSET_I2CSTX (0x1 << 4 ) -#define DMAENSET_I2CSTX_DIS (0x0 << 4 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ -#define DMAENSET_I2CSTX_EN (0x1 << 4 ) /* EN. Enables I2CSTX. */ - -/* DMAENSET[UARTRX] - DMA UART RX. */ -#define DMAENSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220050C) -#define DMAENSET_UARTRX_MSK (0x1 << 3 ) -#define DMAENSET_UARTRX (0x1 << 3 ) -#define DMAENSET_UARTRX_DIS (0x0 << 3 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ -#define DMAENSET_UARTRX_EN (0x1 << 3 ) /* EN. Enables UARTRX. */ - -/* DMAENSET[UARTTX] - DMA UART TX. */ -#define DMAENSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200508) -#define DMAENSET_UARTTX_MSK (0x1 << 2 ) -#define DMAENSET_UARTTX (0x1 << 2 ) -#define DMAENSET_UARTTX_DIS (0x0 << 2 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ -#define DMAENSET_UARTTX_EN (0x1 << 2 ) /* EN. Enables UARTTX. */ - -/* DMAENSET[SPI1RX] - DMA SPI 1 RX. */ -#define DMAENSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200504) -#define DMAENSET_SPI1RX_MSK (0x1 << 1 ) -#define DMAENSET_SPI1RX (0x1 << 1 ) -#define DMAENSET_SPI1RX_DIS (0x0 << 1 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ -#define DMAENSET_SPI1RX_EN (0x1 << 1 ) /* EN. Enables SPI1RX. */ - -/* DMAENSET[SPI1TX] - DMA SPI 1 TX. */ -#define DMAENSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200500) -#define DMAENSET_SPI1TX_MSK (0x1 << 0 ) -#define DMAENSET_SPI1TX (0x1 << 0 ) -#define DMAENSET_SPI1TX_DIS (0x0 << 0 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ -#define DMAENSET_SPI1TX_EN (0x1 << 0 ) /* EN. Enables SPI1TX. */ - -/* Reset Value for DMAENCLR*/ -#define DMAENCLR_RVAL 0x0 - -/* DMAENCLR[SPI0RX] - DMA SPI0 RX */ -#define DMAENCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422005B4) -#define DMAENCLR_SPI0RX_MSK (0x1 << 13 ) -#define DMAENCLR_SPI0RX (0x1 << 13 ) -#define DMAENCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ -#define DMAENCLR_SPI0RX_EN (0x1 << 13 ) /* EN. Disables SPI0RX. */ - -/* DMAENCLR[SPI0TX] - DMA SPI0 TX */ -#define DMAENCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422005B0) -#define DMAENCLR_SPI0TX_MSK (0x1 << 12 ) -#define DMAENCLR_SPI0TX (0x1 << 12 ) -#define DMAENCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ -#define DMAENCLR_SPI0TX_EN (0x1 << 12 ) /* EN. Disables SPI0TX. */ - -/* DMAENCLR[ADC] - DMA ADC. */ -#define DMAENCLR_ADC_BBA (*(volatile unsigned long *) 0x422005AC) -#define DMAENCLR_ADC_MSK (0x1 << 11 ) -#define DMAENCLR_ADC (0x1 << 11 ) -#define DMAENCLR_ADC_DIS (0x0 << 11 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ -#define DMAENCLR_ADC_EN (0x1 << 11 ) /* EN. Disables ADC. */ - -/* DMAENCLR[I2CMRX] - DMA I2C Master RX. */ -#define DMAENCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220059C) -#define DMAENCLR_I2CMRX_MSK (0x1 << 7 ) -#define DMAENCLR_I2CMRX (0x1 << 7 ) -#define DMAENCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ -#define DMAENCLR_I2CMRX_EN (0x1 << 7 ) /* EN. Disables I2CMRX. */ - -/* DMAENCLR[I2CMTX] - DMA I2C Master TX. */ -#define DMAENCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200598) -#define DMAENCLR_I2CMTX_MSK (0x1 << 6 ) -#define DMAENCLR_I2CMTX (0x1 << 6 ) -#define DMAENCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ -#define DMAENCLR_I2CMTX_EN (0x1 << 6 ) /* EN. Disables I2CMTX. */ - -/* DMAENCLR[I2CSRX] - DMA I2C Slave RX. */ -#define DMAENCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200594) -#define DMAENCLR_I2CSRX_MSK (0x1 << 5 ) -#define DMAENCLR_I2CSRX (0x1 << 5 ) -#define DMAENCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ -#define DMAENCLR_I2CSRX_EN (0x1 << 5 ) /* EN. Disables I2CSRX. */ - -/* DMAENCLR[I2CSTX] - DMA I2C Slave TX. */ -#define DMAENCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200590) -#define DMAENCLR_I2CSTX_MSK (0x1 << 4 ) -#define DMAENCLR_I2CSTX (0x1 << 4 ) -#define DMAENCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ -#define DMAENCLR_I2CSTX_EN (0x1 << 4 ) /* EN. Disables I2CSTX. */ - -/* DMAENCLR[UARTRX] - DMA UART RX. */ -#define DMAENCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220058C) -#define DMAENCLR_UARTRX_MSK (0x1 << 3 ) -#define DMAENCLR_UARTRX (0x1 << 3 ) -#define DMAENCLR_UARTRX_DIS (0x0 << 3 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ -#define DMAENCLR_UARTRX_EN (0x1 << 3 ) /* EN. Disables UARTRX. */ - -/* DMAENCLR[UARTTX] - DMA UART TX. */ -#define DMAENCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200588) -#define DMAENCLR_UARTTX_MSK (0x1 << 2 ) -#define DMAENCLR_UARTTX (0x1 << 2 ) -#define DMAENCLR_UARTTX_DIS (0x0 << 2 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ -#define DMAENCLR_UARTTX_EN (0x1 << 2 ) /* EN. Disables UARTTX. */ - -/* DMAENCLR[SPI1RX] - DMA SPI 1 RX. */ -#define DMAENCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200584) -#define DMAENCLR_SPI1RX_MSK (0x1 << 1 ) -#define DMAENCLR_SPI1RX (0x1 << 1 ) -#define DMAENCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ -#define DMAENCLR_SPI1RX_EN (0x1 << 1 ) /* EN. Disables SPI1RX. */ - -/* DMAENCLR[SPI1TX] - DMA SPI 1 TX. */ -#define DMAENCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200580) -#define DMAENCLR_SPI1TX_MSK (0x1 << 0 ) -#define DMAENCLR_SPI1TX (0x1 << 0 ) -#define DMAENCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ -#define DMAENCLR_SPI1TX_EN (0x1 << 0 ) /* EN. Disables SPI1TX. */ - -/* Reset Value for DMAALTSET*/ -#define DMAALTSET_RVAL 0x0 - -/* DMAALTSET[SPI0RX] - DMA SPI0 RX. */ -#define DMAALTSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200634) -#define DMAALTSET_SPI0RX_MSK (0x1 << 13 ) -#define DMAALTSET_SPI0RX (0x1 << 13 ) -#define DMAALTSET_SPI0RX_DIS (0x0 << 13 ) /* DIS. When read: DMA SPI0RX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set SPI0RX to 0. */ -#define DMAALTSET_SPI0RX_EN (0x1 << 13 ) /* EN. When read: DMA SPI0RX is using the alternate data structure. When written: Selects the alternate data structure for SPI0RX. */ - -/* DMAALTSET[SPI0TX] - DMA SPI0 TX. */ -#define DMAALTSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200630) -#define DMAALTSET_SPI0TX_MSK (0x1 << 12 ) -#define DMAALTSET_SPI0TX (0x1 << 12 ) -#define DMAALTSET_SPI0TX_DIS (0x0 << 12 ) /* DIS. When read: DMA SPI0TX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set SPI0TX to 0. */ -#define DMAALTSET_SPI0TX_EN (0x1 << 12 ) /* EN. When read: DMA SPI0TX is using the alternate data structure. When written: Selects the alternate data structure for SPI0TX. */ - -/* DMAALTSET[ADC] - DMA ADC. */ -#define DMAALTSET_ADC_BBA (*(volatile unsigned long *) 0x4220062C) -#define DMAALTSET_ADC_MSK (0x1 << 11 ) -#define DMAALTSET_ADC (0x1 << 11 ) -#define DMAALTSET_ADC_DIS (0x0 << 11 ) /* DIS. When read: DMA ADC is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set ADC to 0. */ -#define DMAALTSET_ADC_EN (0x1 << 11 ) /* EN. When read: DMA ADC is using the alternate data structure. When written: Selects the alternate data structure for ADC. */ - -/* DMAALTSET[I2CMRX] - DMA I2C Master RX. */ -#define DMAALTSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220061C) -#define DMAALTSET_I2CMRX_MSK (0x1 << 7 ) -#define DMAALTSET_I2CMRX (0x1 << 7 ) -#define DMAALTSET_I2CMRX_DIS (0x0 << 7 ) /* DIS. When read: DMA I2CMRX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set I2CMRX to 0. */ -#define DMAALTSET_I2CMRX_EN (0x1 << 7 ) /* EN. When read: DMA I2CMRX is using the alternate data structure. When written: Selects the alternate data structure for I2CMRX. */ - -/* DMAALTSET[I2CMTX] - DMA I2C Master TX. */ -#define DMAALTSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200618) -#define DMAALTSET_I2CMTX_MSK (0x1 << 6 ) -#define DMAALTSET_I2CMTX (0x1 << 6 ) -#define DMAALTSET_I2CMTX_DIS (0x0 << 6 ) /* DIS. When read: DMA I2CMTX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set I2CMTX to 0. */ -#define DMAALTSET_I2CMTX_EN (0x1 << 6 ) /* EN. When read: DMA I2CMTX is using the alternate data structure. When written: Selects the alternate data structure forI2CMTX. */ - -/* DMAALTSET[I2CSRX] - DMA I2C Slave RX. */ -#define DMAALTSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200614) -#define DMAALTSET_I2CSRX_MSK (0x1 << 5 ) -#define DMAALTSET_I2CSRX (0x1 << 5 ) -#define DMAALTSET_I2CSRX_DIS (0x0 << 5 ) /* DIS. When read: DMA I2CSRX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set I2CSRX to 0. */ -#define DMAALTSET_I2CSRX_EN (0x1 << 5 ) /* EN. When read: DMA I2CSRX is using the alternate data structure. When written: Selects the alternate data structure for I2CSRX. */ - -/* DMAALTSET[I2CSTX] - DMA I2C Slave TX. */ -#define DMAALTSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200610) -#define DMAALTSET_I2CSTX_MSK (0x1 << 4 ) -#define DMAALTSET_I2CSTX (0x1 << 4 ) -#define DMAALTSET_I2CSTX_DIS (0x0 << 4 ) /* DIS. When read: DMA I2CSTX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set I2CSTX to 0. */ -#define DMAALTSET_I2CSTX_EN (0x1 << 4 ) /* EN. When read: DMA I2CSTX is using the alternate data structure. When written: Selects the alternate data structure for I2CSTX. */ - -/* DMAALTSET[UARTRX] - DMA UART RX. */ -#define DMAALTSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220060C) -#define DMAALTSET_UARTRX_MSK (0x1 << 3 ) -#define DMAALTSET_UARTRX (0x1 << 3 ) -#define DMAALTSET_UARTRX_DIS (0x0 << 3 ) /* DIS. When read: DMA UARTRX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set UARTRX to 0. */ -#define DMAALTSET_UARTRX_EN (0x1 << 3 ) /* EN. When read: DMA UARTRX is using the alternate data structure. When written: Selects the alternate data structure for UARTRX. */ - -/* DMAALTSET[UARTTX] - DMA UART TX. */ -#define DMAALTSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200608) -#define DMAALTSET_UARTTX_MSK (0x1 << 2 ) -#define DMAALTSET_UARTTX (0x1 << 2 ) -#define DMAALTSET_UARTTX_DIS (0x0 << 2 ) /* DIS. When read: DMA UARTTX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set UARTTX to 0. */ -#define DMAALTSET_UARTTX_EN (0x1 << 2 ) /* EN. When read: DMA UARTTX is using the alternate data structure. When written: Selects the alternate data structure for UARTTX. */ - -/* DMAALTSET[SPI1RX] - DMA SPI 1 RX. */ -#define DMAALTSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200604) -#define DMAALTSET_SPI1RX_MSK (0x1 << 1 ) -#define DMAALTSET_SPI1RX (0x1 << 1 ) -#define DMAALTSET_SPI1RX_DIS (0x0 << 1 ) /* DIS. When read: DMA SPI1RX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set SPI1RX to 0. */ -#define DMAALTSET_SPI1RX_EN (0x1 << 1 ) /* EN. When read: DMA SPI1RX is using the alternate data structure. When written: Selects the alternate data structure for SPI1RX. */ - -/* DMAALTSET[SPI1TX] - DMA SPI 1 TX. */ -#define DMAALTSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200600) -#define DMAALTSET_SPI1TX_MSK (0x1 << 0 ) -#define DMAALTSET_SPI1TX (0x1 << 0 ) -#define DMAALTSET_SPI1TX_DIS (0x0 << 0 ) /* DIS. When read: DMA SPI1TX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set SPI1TX to 0. */ -#define DMAALTSET_SPI1TX_EN (0x1 << 0 ) /* EN. When read: DMA SPI1TX is using the alternate data structure. When written: Selects the alternate data structure for SPI1TX. */ - -/* Reset Value for DMAALTCLR*/ -#define DMAALTCLR_RVAL 0x0 - -/* DMAALTCLR[SPI0RX] - DMA SPI0 RX. */ -#define DMAALTCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422006B4) -#define DMAALTCLR_SPI0RX_MSK (0x1 << 13 ) -#define DMAALTCLR_SPI0RX (0x1 << 13 ) -#define DMAALTCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ -#define DMAALTCLR_SPI0RX_EN (0x1 << 13 ) /* EN. Selects the primary data structure for SPI0RX. */ - -/* DMAALTCLR[SPI0TX] - DMA SPI0 TX. */ -#define DMAALTCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422006B0) -#define DMAALTCLR_SPI0TX_MSK (0x1 << 12 ) -#define DMAALTCLR_SPI0TX (0x1 << 12 ) -#define DMAALTCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ -#define DMAALTCLR_SPI0TX_EN (0x1 << 12 ) /* EN. Selects the primary data structure for SPI0TX. */ - -/* DMAALTCLR[ADC] - DMA ADC. */ -#define DMAALTCLR_ADC_BBA (*(volatile unsigned long *) 0x422006AC) -#define DMAALTCLR_ADC_MSK (0x1 << 11 ) -#define DMAALTCLR_ADC (0x1 << 11 ) -#define DMAALTCLR_ADC_DIS (0x0 << 11 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ -#define DMAALTCLR_ADC_EN (0x1 << 11 ) /* EN. Selects the primary data structure for ADC. */ - -/* DMAALTCLR[I2CMRX] - DMA I2C Master RX. */ -#define DMAALTCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220069C) -#define DMAALTCLR_I2CMRX_MSK (0x1 << 7 ) -#define DMAALTCLR_I2CMRX (0x1 << 7 ) -#define DMAALTCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ -#define DMAALTCLR_I2CMRX_EN (0x1 << 7 ) /* EN. Selects the primary data structure for I2CMRX. */ - -/* DMAALTCLR[I2CMTX] - DMA I2C Master TX. */ -#define DMAALTCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200698) -#define DMAALTCLR_I2CMTX_MSK (0x1 << 6 ) -#define DMAALTCLR_I2CMTX (0x1 << 6 ) -#define DMAALTCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ -#define DMAALTCLR_I2CMTX_EN (0x1 << 6 ) /* EN. Selects the primary data structure for I2CMTX. */ - -/* DMAALTCLR[I2CSRX] - DMA I2C Slave RX. */ -#define DMAALTCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200694) -#define DMAALTCLR_I2CSRX_MSK (0x1 << 5 ) -#define DMAALTCLR_I2CSRX (0x1 << 5 ) -#define DMAALTCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ -#define DMAALTCLR_I2CSRX_EN (0x1 << 5 ) /* EN. Selects the primary data structure for I2CSRX. */ - -/* DMAALTCLR[I2CSTX] - DMA I2C Slave TX. */ -#define DMAALTCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200690) -#define DMAALTCLR_I2CSTX_MSK (0x1 << 4 ) -#define DMAALTCLR_I2CSTX (0x1 << 4 ) -#define DMAALTCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ -#define DMAALTCLR_I2CSTX_EN (0x1 << 4 ) /* EN. Selects the primary data structure for I2CSTX. */ - -/* DMAALTCLR[UARTRX] - DMA UART RX. */ -#define DMAALTCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220068C) -#define DMAALTCLR_UARTRX_MSK (0x1 << 3 ) -#define DMAALTCLR_UARTRX (0x1 << 3 ) -#define DMAALTCLR_UARTRX_DIS (0x0 << 3 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ -#define DMAALTCLR_UARTRX_EN (0x1 << 3 ) /* EN. Selects the primary data structure for UARTRX. */ - -/* DMAALTCLR[UARTTX] - DMA UART TX. */ -#define DMAALTCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200688) -#define DMAALTCLR_UARTTX_MSK (0x1 << 2 ) -#define DMAALTCLR_UARTTX (0x1 << 2 ) -#define DMAALTCLR_UARTTX_DIS (0x0 << 2 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ -#define DMAALTCLR_UARTTX_EN (0x1 << 2 ) /* EN. Selects the primary data structure for UARTTX. */ - -/* DMAALTCLR[SPI1RX] - DMA SPI 1 RX. */ -#define DMAALTCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200684) -#define DMAALTCLR_SPI1RX_MSK (0x1 << 1 ) -#define DMAALTCLR_SPI1RX (0x1 << 1 ) -#define DMAALTCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ -#define DMAALTCLR_SPI1RX_EN (0x1 << 1 ) /* EN. Selects the primary data structure for SPI1RX. */ - -/* DMAALTCLR[SPI1TX] - DMA SPI 1 TX. */ -#define DMAALTCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200680) -#define DMAALTCLR_SPI1TX_MSK (0x1 << 0 ) -#define DMAALTCLR_SPI1TX (0x1 << 0 ) -#define DMAALTCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ -#define DMAALTCLR_SPI1TX_EN (0x1 << 0 ) /* EN. Selects the primary data structure for SPI1TX. */ - -/* Reset Value for DMAPRISET*/ -#define DMAPRISET_RVAL 0x0 - -/* DMAPRISET[SPI0RX] - DMA SPI0 RX. */ -#define DMAPRISET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200734) -#define DMAPRISET_SPI0RX_MSK (0x1 << 13 ) -#define DMAPRISET_SPI0RX (0x1 << 13 ) -#define DMAPRISET_SPI0RX_DIS (0x0 << 13 ) /* DIS. When read: DMA SPI0RX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set SPI0RX to the default priority level. */ -#define DMAPRISET_SPI0RX_EN (0x1 << 13 ) /* EN. When read: DMA SPI0RX is using a high priority level. When written: SPI0RX uses the high priority level. */ - -/* DMAPRISET[SPI0TX] - DMA SPI0 TX. */ -#define DMAPRISET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200730) -#define DMAPRISET_SPI0TX_MSK (0x1 << 12 ) -#define DMAPRISET_SPI0TX (0x1 << 12 ) -#define DMAPRISET_SPI0TX_DIS (0x0 << 12 ) /* DIS. When read: DMA SPI0TX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set SPI0TX to the default priority level. */ -#define DMAPRISET_SPI0TX_EN (0x1 << 12 ) /* EN. When read: DMA SPI0TX is using a high priority level. When written: SPI0TX uses the high priority level. */ - -/* DMAPRISET[ADC] - DMA ADC. */ -#define DMAPRISET_ADC_BBA (*(volatile unsigned long *) 0x4220072C) -#define DMAPRISET_ADC_MSK (0x1 << 11 ) -#define DMAPRISET_ADC (0x1 << 11 ) -#define DMAPRISET_ADC_DIS (0x0 << 11 ) /* DIS. When read: DMA ADC is using the default priority level. When written: No effect. Use the DMAPRICLR register to set ADC to the default priority level. */ -#define DMAPRISET_ADC_EN (0x1 << 11 ) /* EN. When read: DMA ADCs using a high priority level. When written: ADC uses the high priority level. */ - -/* DMAPRISET[I2CMRX] - DMA I2C Master RX. */ -#define DMAPRISET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220071C) -#define DMAPRISET_I2CMRX_MSK (0x1 << 7 ) -#define DMAPRISET_I2CMRX (0x1 << 7 ) -#define DMAPRISET_I2CMRX_DIS (0x0 << 7 ) /* DIS. When read: DMA I2CMRX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set I2CMRX to the default priority level. */ -#define DMAPRISET_I2CMRX_EN (0x1 << 7 ) /* EN. When read: DMA I2CMRX is using a high priority level. When written: I2CMRX uses the high priority level. */ - -/* DMAPRISET[I2CMTX] - DMA I2C Master TX. */ -#define DMAPRISET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200718) -#define DMAPRISET_I2CMTX_MSK (0x1 << 6 ) -#define DMAPRISET_I2CMTX (0x1 << 6 ) -#define DMAPRISET_I2CMTX_DIS (0x0 << 6 ) /* DIS. When read: DMA I2CMTX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set I2CMTX to the default priority level. */ -#define DMAPRISET_I2CMTX_EN (0x1 << 6 ) /* EN. When read: DMA I2CMTX is using a high priority level. When written: I2CMTX uses the high priority level. */ - -/* DMAPRISET[I2CSRX] - DMA I2C Slave RX. */ -#define DMAPRISET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200714) -#define DMAPRISET_I2CSRX_MSK (0x1 << 5 ) -#define DMAPRISET_I2CSRX (0x1 << 5 ) -#define DMAPRISET_I2CSRX_DIS (0x0 << 5 ) /* DIS. When read: DMA I2CSRX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set I2CSRX to the default priority level. */ -#define DMAPRISET_I2CSRX_EN (0x1 << 5 ) /* EN. When read: DMA I2CSRX is using a high priority level. When written: I2CSRX uses the high priority level. */ - -/* DMAPRISET[I2CSTX] - DMA I2C Slave TX. */ -#define DMAPRISET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200710) -#define DMAPRISET_I2CSTX_MSK (0x1 << 4 ) -#define DMAPRISET_I2CSTX (0x1 << 4 ) -#define DMAPRISET_I2CSTX_DIS (0x0 << 4 ) /* DIS. When read: DMA I2CSTX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set I2CSTX to the default priority level. */ -#define DMAPRISET_I2CSTX_EN (0x1 << 4 ) /* EN. When read: DMA I2CSTX is using a high priority level. When written: I2CSTX uses the high priority level. */ - -/* DMAPRISET[UARTRX] - DMA UART RX. */ -#define DMAPRISET_UARTRX_BBA (*(volatile unsigned long *) 0x4220070C) -#define DMAPRISET_UARTRX_MSK (0x1 << 3 ) -#define DMAPRISET_UARTRX (0x1 << 3 ) -#define DMAPRISET_UARTRX_DIS (0x0 << 3 ) /* DIS. When read: DMA UARTRX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set UARTRX to the default priority level. */ -#define DMAPRISET_UARTRX_EN (0x1 << 3 ) /* EN. When read: DMA UARTRX is using a high priority level. When written: UARTRX uses the high priority level. */ - -/* DMAPRISET[UARTTX] - DMA UART TX. */ -#define DMAPRISET_UARTTX_BBA (*(volatile unsigned long *) 0x42200708) -#define DMAPRISET_UARTTX_MSK (0x1 << 2 ) -#define DMAPRISET_UARTTX (0x1 << 2 ) -#define DMAPRISET_UARTTX_DIS (0x0 << 2 ) /* DIS. When read: DMA UARTTX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set UARTTX to the default priority level. */ -#define DMAPRISET_UARTTX_EN (0x1 << 2 ) /* EN. When read: DMA UARTTX is using a high priority level. When written: UARTTX uses the high priority level. */ - -/* DMAPRISET[SPI1RX] - DMA SPI 1 RX. */ -#define DMAPRISET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200704) -#define DMAPRISET_SPI1RX_MSK (0x1 << 1 ) -#define DMAPRISET_SPI1RX (0x1 << 1 ) -#define DMAPRISET_SPI1RX_DIS (0x0 << 1 ) /* DIS. When read: DMA SPI1RX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set SPI1RX to the default priority level. */ -#define DMAPRISET_SPI1RX_EN (0x1 << 1 ) /* EN. When read: DMA SPI1RX is using a high priority level. When written: SPI1RX uses the high priority level. */ - -/* DMAPRISET[SPI1TX] - DMA SPI 1 TX. */ -#define DMAPRISET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200700) -#define DMAPRISET_SPI1TX_MSK (0x1 << 0 ) -#define DMAPRISET_SPI1TX (0x1 << 0 ) -#define DMAPRISET_SPI1TX_DIS (0x0 << 0 ) /* DIS. When read: DMA SPI1TX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set SPI1TX to the default priority level. */ -#define DMAPRISET_SPI1TX_EN (0x1 << 0 ) /* EN. When read: DMA SPI1TX is using a high priority level. When written: SPI1TX uses the high priority level. */ - -/* Reset Value for DMAPRICLR*/ -#define DMAPRICLR_RVAL 0x0 - -/* DMAPRICLR[SPI0RX] - DMA SPI0 RX. */ -#define DMAPRICLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422007B4) -#define DMAPRICLR_SPI0RX_MSK (0x1 << 13 ) -#define DMAPRICLR_SPI0RX (0x1 << 13 ) -#define DMAPRICLR_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMAPRISET register to set SPI0RX to the high priority level. */ -#define DMAPRICLR_SPI0RX_EN (0x1 << 13 ) /* EN. SPI0RX uses the default priority level. */ - -/* DMAPRICLR[SPI0TX] - DMA SPI0 TX. */ -#define DMAPRICLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422007B0) -#define DMAPRICLR_SPI0TX_MSK (0x1 << 12 ) -#define DMAPRICLR_SPI0TX (0x1 << 12 ) -#define DMAPRICLR_SPI0TX_DIS (0x0 << 12 ) /* DIS. No effect. Use the DMAPRISET register to set SPI0TX to the high priority level. */ -#define DMAPRICLR_SPI0TX_EN (0x1 << 12 ) /* EN. SPI0TX uses the default priority level. */ - -/* DMAPRICLR[ADC] - DMA ADC. */ -#define DMAPRICLR_ADC_BBA (*(volatile unsigned long *) 0x422007AC) -#define DMAPRICLR_ADC_MSK (0x1 << 11 ) -#define DMAPRICLR_ADC (0x1 << 11 ) -#define DMAPRICLR_ADC_DIS (0x0 << 11 ) /* DIS. No effect. Use the DMAPRISET register to set ADC to the high priority level. */ -#define DMAPRICLR_ADC_EN (0x1 << 11 ) /* EN. ADC uses the default priority level. */ - -/* DMAPRICLR[I2CMRX] - DMA I2C Master RX. */ -#define DMAPRICLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220079C) -#define DMAPRICLR_I2CMRX_MSK (0x1 << 7 ) -#define DMAPRICLR_I2CMRX (0x1 << 7 ) -#define DMAPRICLR_I2CMRX_DIS (0x0 << 7 ) /* DIS. No effect. Use the DMAPRISET register to set I2CMRX to the high priority level. */ -#define DMAPRICLR_I2CMRX_EN (0x1 << 7 ) /* EN. I2CMRX uses the default priority level. */ - -/* DMAPRICLR[I2CMTX] - DMA I2C Master TX. */ -#define DMAPRICLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200798) -#define DMAPRICLR_I2CMTX_MSK (0x1 << 6 ) -#define DMAPRICLR_I2CMTX (0x1 << 6 ) -#define DMAPRICLR_I2CMTX_DIS (0x0 << 6 ) /* DIS. No effect. Use the DMAPRISET register to set I2CMTX to the high priority level. */ -#define DMAPRICLR_I2CMTX_EN (0x1 << 6 ) /* EN. I2CMTX uses the default priority level. */ - -/* DMAPRICLR[I2CSRX] - DMA I2C Slave RX. */ -#define DMAPRICLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200794) -#define DMAPRICLR_I2CSRX_MSK (0x1 << 5 ) -#define DMAPRICLR_I2CSRX (0x1 << 5 ) -#define DMAPRICLR_I2CSRX_DIS (0x0 << 5 ) /* DIS. No effect. Use the DMAPRISET register to set I2CSRX to the high priority level. */ -#define DMAPRICLR_I2CSRX_EN (0x1 << 5 ) /* EN. I2CSRX uses the default priority level. */ - -/* DMAPRICLR[I2CSTX] - DMA I2C Slave TX. */ -#define DMAPRICLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200790) -#define DMAPRICLR_I2CSTX_MSK (0x1 << 4 ) -#define DMAPRICLR_I2CSTX (0x1 << 4 ) -#define DMAPRICLR_I2CSTX_DIS (0x0 << 4 ) /* DIS. No effect. Use the DMAPRISET register to set I2CSTX to the high priority level. */ -#define DMAPRICLR_I2CSTX_EN (0x1 << 4 ) /* EN. I2CSTX uses the default priority level. */ - -/* DMAPRICLR[UARTRX] - DMA UART RX. */ -#define DMAPRICLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220078C) -#define DMAPRICLR_UARTRX_MSK (0x1 << 3 ) -#define DMAPRICLR_UARTRX (0x1 << 3 ) -#define DMAPRICLR_UARTRX_DIS (0x0 << 3 ) /* DIS. No effect. Use the DMAPRISET register to set UARTRX to the high priority level. */ -#define DMAPRICLR_UARTRX_EN (0x1 << 3 ) /* EN. UARTRX uses the default priority level. */ - -/* DMAPRICLR[UARTTX] - DMA UART TX. */ -#define DMAPRICLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200788) -#define DMAPRICLR_UARTTX_MSK (0x1 << 2 ) -#define DMAPRICLR_UARTTX (0x1 << 2 ) -#define DMAPRICLR_UARTTX_DIS (0x0 << 2 ) /* DIS. No effect. Use the DMAPRISET register to set UARTTX to the high priority level. */ -#define DMAPRICLR_UARTTX_EN (0x1 << 2 ) /* EN. UARTTX uses the default priority level. */ - -/* DMAPRICLR[SPI1RX] - DMA SPI 1 RX. */ -#define DMAPRICLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200784) -#define DMAPRICLR_SPI1RX_MSK (0x1 << 1 ) -#define DMAPRICLR_SPI1RX (0x1 << 1 ) -#define DMAPRICLR_SPI1RX_DIS (0x0 << 1 ) /* DIS. No effect. Use the DMAPRISET register to set SPI1RX to the high priority level. */ -#define DMAPRICLR_SPI1RX_EN (0x1 << 1 ) /* EN. SPI1RX uses the default priority level. */ - -/* DMAPRICLR[SPI1TX] - DMA SPI 1 TX. */ -#define DMAPRICLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200780) -#define DMAPRICLR_SPI1TX_MSK (0x1 << 0 ) -#define DMAPRICLR_SPI1TX (0x1 << 0 ) -#define DMAPRICLR_SPI1TX_DIS (0x0 << 0 ) /* DIS. No effect. Use the DMAPRISET register to set SPI1TX to the high priority level. */ -#define DMAPRICLR_SPI1TX_EN (0x1 << 0 ) /* EN. SPI1TX uses the default priority level. */ - -/* Reset Value for DMAERRCLR*/ -#define DMAERRCLR_RVAL 0x0 - -/* DMAERRCLR[ERROR] - DMA Bus Error status. */ -#define DMAERRCLR_ERROR_BBA (*(volatile unsigned long *) 0x42200980) -#define DMAERRCLR_ERROR_MSK (0x1 << 0 ) -#define DMAERRCLR_ERROR (0x1 << 0 ) -#define DMAERRCLR_ERROR_DIS (0x0 << 0 ) /* DIS. When Read: No bus error occurred. When Written: No effect. */ -#define DMAERRCLR_ERROR_EN (0x1 << 0 ) /* EN. When Read: A bus error is pending. When Written: Bit is cleared. */ -// ------------------------------------------------------------------------------------------------ -// ----- FEE ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Flash Controller (pADI_FEE) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_FEE Structure */ - __IO uint16_t FEESTA; /*!< Status Register */ - __I uint16_t RESERVED0; - __IO uint16_t FEECON0; /*!< Command Control Register */ - __I uint16_t RESERVED1; - __IO uint16_t FEECMD; /*!< Command Register */ - __I uint16_t RESERVED2[3]; - __IO uint16_t FEEADR0L; /*!< Address 0 LSB */ - __I uint16_t RESERVED3; - __IO uint16_t FEEADR0H; /*!< Address 0 MSB */ - __I uint16_t RESERVED4; - __IO uint16_t FEEADR1L; /*!< Address1 LSB */ - __I uint16_t RESERVED5; - __IO uint16_t FEEADR1H; /*!< Address1 MSB */ - __I uint16_t RESERVED6; - __IO uint16_t FEEKEY; /*!< Key Register */ - __I uint16_t RESERVED7[3]; - __IO uint16_t FEEPROL; /*!< Write Protection Register LSB */ - __I uint16_t RESERVED8; - __IO uint16_t FEEPROH; /*!< Write Protection Register MSB */ - __I uint16_t RESERVED9; - __IO uint16_t FEESIGL; /*!< Signature LSB */ - __I uint16_t RESERVED10; - __IO uint16_t FEESIGH; /*!< Signature MSB */ - __I uint16_t RESERVED11; - __IO uint16_t FEECON1; /*!< User Setup Register */ - __I uint16_t RESERVED12[7]; - __IO uint16_t FEEADRAL; /*!< Abort Address Register LSB */ - __I uint16_t RESERVED13; - __IO uint16_t FEEADRAH; /*!< Abort Address Register MSB */ - __I uint16_t RESERVED14[21]; - __IO uint16_t FEEAEN0; /*!< Interrupt Abort Register (Interrupt 15 to Interrupt 0) */ - __I uint16_t RESERVED15; - __IO uint16_t FEEAEN1; /*!< Interrupt Abort Register (Interrupt 31 to Interrupt 16) */ - __I uint16_t RESERVED16; - __IO uint16_t FEEAEN2; /*!< Interrupt Abort Register (Interrupt 42 to Interrupt 32) */ -} ADI_FEE_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define FEESTA (*(volatile unsigned short int *) 0x40002800) -#define FEECON0 (*(volatile unsigned short int *) 0x40002804) -#define FEECMD (*(volatile unsigned short int *) 0x40002808) -#define FEEADR0L (*(volatile unsigned short int *) 0x40002810) -#define FEEADR0H (*(volatile unsigned short int *) 0x40002814) -#define FEEADR1L (*(volatile unsigned short int *) 0x40002818) -#define FEEADR1H (*(volatile unsigned short int *) 0x4000281C) -#define FEEKEY (*(volatile unsigned short int *) 0x40002820) -#define FEEPROL (*(volatile unsigned short int *) 0x40002828) -#define FEEPROH (*(volatile unsigned short int *) 0x4000282C) -#define FEESIGL (*(volatile unsigned short int *) 0x40002830) -#define FEESIGH (*(volatile unsigned short int *) 0x40002834) -#define FEECON1 (*(volatile unsigned short int *) 0x40002838) -#define FEEADRAL (*(volatile unsigned short int *) 0x40002848) -#define FEEADRAH (*(volatile unsigned short int *) 0x4000284C) -#define FEEAEN0 (*(volatile unsigned short int *) 0x40002878) -#define FEEAEN1 (*(volatile unsigned short int *) 0x4000287C) -#define FEEAEN2 (*(volatile unsigned short int *) 0x40002880) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for FEESTA*/ -#define FEESTA_RVAL 0x0 - -/* FEESTA[SIGNERR] - Kernel space signature check on reset error */ -#define FEESTA_SIGNERR_BBA (*(volatile unsigned long *) 0x42050018) -#define FEESTA_SIGNERR_MSK (0x1 << 6 ) -#define FEESTA_SIGNERR (0x1 << 6 ) -#define FEESTA_SIGNERR_CLR (0x0 << 6 ) /* CLR. Cleared, if the signature check of the kernel passes. */ -#define FEESTA_SIGNERR_SET (0x1 << 6 ) /* SET. Set, if the signature check of the kernel fails. User code does not execute. */ - -/* FEESTA[CMDRES] - These two bits indicate the status of a command on completion or the status of a write. If multiple commands are executed or there are multiple writes via the AHB bus without a read of the status register, then the first error encountered is stored. */ -#define FEESTA_CMDRES_MSK (0x3 << 4 ) -#define FEESTA_CMDRES_SUCCESS (0x0 << 4 ) /* SUCCESS. Indicates a successful completion of a command or a write. Also cleared after a read of FEESTA. */ -#define FEESTA_CMDRES_PROTECTED (0x1 << 4 ) /* PROTECTED. Indicates an attempted erase of a protected location. */ -#define FEESTA_CMDRES_VERIFYERR (0x2 << 4 ) /* VERIFYERR. Indicates a read verify error. After an erase the controller reads the corresponding word(s) to verify that the transaction completed successfully. If data read is not all 'F's this is the resulting status. If the Sign command is executed and the resulting signature does not match the data in the upper 4 bytes of the upper page in a block then this is the resulting status. */ -#define FEESTA_CMDRES_ABORT (0x3 << 4 ) /* ABORT. Indicates that a command or a write was aborted by an abort command or a system interrupt has caused an abort. */ - -/* FEESTA[WRDONE] - Write complete. */ -#define FEESTA_WRDONE_BBA (*(volatile unsigned long *) 0x4205000C) -#define FEESTA_WRDONE_MSK (0x1 << 3 ) -#define FEESTA_WRDONE (0x1 << 3 ) -#define FEESTA_WRDONE_CLR (0x0 << 3 ) /* CLR. Cleared after a read of FEESTA. */ -#define FEESTA_WRDONE_SET (0x1 << 3 ) /* SET. Set when a write completes. If there are multiple writes or a burst write, this status bit asserts after the first long word written and stays asserted until read. If there is a burst write to flash, then this bit asserts after every long word written, assuming that user code read FEESTA after every long word written. */ - -/* FEESTA[CMDDONE] - Command complete. */ -#define FEESTA_CMDDONE_BBA (*(volatile unsigned long *) 0x42050008) -#define FEESTA_CMDDONE_MSK (0x1 << 2 ) -#define FEESTA_CMDDONE (0x1 << 2 ) -#define FEESTA_CMDDONE_CLR (0x0 << 2 ) /* CLR. Cleared after a read of FEESTA. */ -#define FEESTA_CMDDONE_SET (0x1 << 2 ) /* SET. Set when a command completes. If there are multiple commands, this status bit asserts after the first command completes and stays asserted until read. */ - -/* FEESTA[WRBUSY] - Write busy. */ -#define FEESTA_WRBUSY_BBA (*(volatile unsigned long *) 0x42050004) -#define FEESTA_WRBUSY_MSK (0x1 << 1 ) -#define FEESTA_WRBUSY (0x1 << 1 ) -#define FEESTA_WRBUSY_CLR (0x0 << 1 ) /* CLR. Cleared after a read of FEESTA. */ -#define FEESTA_WRBUSY_SET (0x1 << 1 ) /* SET. Set when the flash block is executing a write. */ - -/* FEESTA[CMDBUSY] - Command busy. */ -#define FEESTA_CMDBUSY_BBA (*(volatile unsigned long *) 0x42050000) -#define FEESTA_CMDBUSY_MSK (0x1 << 0 ) -#define FEESTA_CMDBUSY (0x1 << 0 ) -#define FEESTA_CMDBUSY_CLR (0x0 << 0 ) /* CLR. Cleared after a read of FEESTA. */ -#define FEESTA_CMDBUSY_SET (0x1 << 0 ) /* SET. Set when the flash block is executing any command entered via the command register. */ - -/* Reset Value for FEECON0*/ -#define FEECON0_RVAL 0x0 - -/* FEECON0[WREN] - Write enable bit. */ -#define FEECON0_WREN_BBA (*(volatile unsigned long *) 0x42050088) -#define FEECON0_WREN_MSK (0x1 << 2 ) -#define FEECON0_WREN (0x1 << 2 ) -#define FEECON0_WREN_DIS (0x0 << 2 ) /* DIS. Disables Flash writes. A flash write when this bit is 0 results in a hard fault system exception error and the write does not take place. */ -#define FEECON0_WREN_EN (0x1 << 2 ) /* EN. Enables Flash writes. */ - -/* FEECON0[IENERR] - Error interrupt enable bit. */ -#define FEECON0_IENERR_BBA (*(volatile unsigned long *) 0x42050084) -#define FEECON0_IENERR_MSK (0x1 << 1 ) -#define FEECON0_IENERR (0x1 << 1 ) -#define FEECON0_IENERR_DIS (0x0 << 1 ) /* DIS. Disables the Flash error interrupt. */ -#define FEECON0_IENERR_EN (0x1 << 1 ) /* EN. An interrupt is generated when a command or flash write completes with an error status. */ - -/* FEECON0[IENCMD] - Command complete interrupt enable bit. */ -#define FEECON0_IENCMD_BBA (*(volatile unsigned long *) 0x42050080) -#define FEECON0_IENCMD_MSK (0x1 << 0 ) -#define FEECON0_IENCMD (0x1 << 0 ) -#define FEECON0_IENCMD_DIS (0x0 << 0 ) /* DIS. Disables the Flash command complete interrupt. */ -#define FEECON0_IENCMD_EN (0x1 << 0 ) /* EN. An interrupt is generated when a command or flash write completes. */ - -/* Reset Value for FEECMD*/ -#define FEECMD_RVAL 0x0 - -/* FEECMD[CMD] - Commands supported by the flash controller. */ -#define FEECMD_CMD_MSK (0xF << 0 ) -#define FEECMD_CMD_IDLE (0x0 << 0 ) /* IDLE. No command executed. */ -#define FEECMD_CMD_ERASEPAGE (0x1 << 0 ) /* ERASEPAGE. Write the address of the page to be erased to FEEADR0L/H, then write this code to the FEECMD register and the flash will erase the page. When the erase has completed, the flash reads every location in the page to verify that all words in the page are erased. If there is a read verify error, this is indicated in FEESTA. To erase multiple pages, wait until a previous page erase has completed. Check the status, and then issue a command to start the next page erase. Before entering this command, 0xF456 followed by 0xF123 must be written to the key register. */ -#define FEECMD_CMD_SIGN (0x2 << 0 ) /* SIGN. Use this command to generate a signature for a block of data. The signature is generated on a page-by-page basis. To generate a signature, the address of the first page of the block is entered in FEEADR0L/FEEADR0H. The address of the last page is written to FEEADR1L/FEEADR1H. Then write this code to the FEECMD register. When the command has completed, the signature is available for reading in FEESIGL/FEESIGH. The last four bytes of the last page in a block is reserved for storing the signature. Before entering this command, 0xF456 followed 0xF123 must be written to the key register. */ -#define FEECMD_CMD_MASSERASE (0x3 << 0 ) /* MASSERASE. Erase all of user space. To enable this operation, 0xF456 followed by 0xF123 must first be written to FEEKEY (this is to prevent accidental erases). When the mass erase has completed, the controller reads every location to verify that all locations are 0xFFFFFFFF. If there is a read verify error this is indicated in FEESTA. */ -#define FEECMD_CMD_ABORT (0x4 << 0 ) /* ABORT. If this command is issued, then any command currently in progress is stopped. The status indicates command completed with an error status in FEESTA[5:4]. Note that this is the only command that can be issued while another command is already in progress. This command can also be used to stop a write that may be in progress. If a write is aborted, the address of the location being written can be read via the FEEADRAL/FEEADRAH register. While the flash controller is writing one longword, another longword write may be in the pipeline from the Cortex-M3 or DMA engine (depending on how the software implements writes). Therefore, both writes may need to be aborted. If a write or erase is aborted, then the flash timing is violated and it is not possible to determine if the write or erase completed successfully. To enable this operation, 0xF456 followed by 0xF123 must first be written to FEEKEY (this is to prevent accidental aborts). */ - -/* Reset Value for FEEADR0L*/ -#define FEEADR0L_RVAL 0x0 - -/* FEEADR0L[VALUE] - Used in conjunction with FEEADR0H, to indicate the page to be erased, or the start of a section to be signed. The address of a memory location inside the page should be stored in FEEADR0L/H, bits[15:0] in FEEADR0L, and bits[17:16] in FEEADR0H. The 9 LSBs of the address are ignored. */ -#define FEEADR0L_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for FEEADR0H*/ -#define FEEADR0H_RVAL 0x0 - -/* FEEADR0H[VALUE] - Used in conjunction with FEEADR0L, to indicate the page to be erased, or the start of a section to be signed. The address of a memory location inside the page should be stored in FEEADR0L/H, bits[15:0] in FEEADR0L, and bits[17:16] in FEEADR0H. */ -#define FEEADR0H_VALUE_MSK (0x3 << 0 ) - -/* Reset Value for FEEADR1L*/ -#define FEEADR1L_RVAL 0x0 - -/* FEEADR1L[VALUE] - Used in conjunction with FEEADR1H, to identify the last page used by the Sign command. The address of a memory location inside the page should be stored in FEEADR1L/H, bits[15:0] in FEEADR1L, and bits[17:16] in FEEADR1H. The 9 LSBs of the address are ignored. */ -#define FEEADR1L_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for FEEADR1H*/ -#define FEEADR1H_RVAL 0x0 - -/* FEEADR1H[VALUE] - Used in conjunction with FEEADR1L, to identify the last page used by the Sign command. The address of a memory location inside the page should be stored in FEEADR1L/H, bits[15:0] in FEEADR1L, and bits[17:16] in FEEADR1H. */ -#define FEEADR1H_VALUE_MSK (0x3 << 0 ) - -/* Reset Value for FEEKEY*/ -#define FEEKEY_RVAL 0x0 - -/* FEEKEY[VALUE] - Enter 0xF456 followed by 0xF123. Returns 0x0 if read. */ -#define FEEKEY_VALUE_MSK (0xFFFF << 0 ) -#define FEEKEY_VALUE_USERKEY1 (0xF456 << 0 ) /* USERKEY1 */ -#define FEEKEY_VALUE_USERKEY2 (0xF123 << 0 ) /* USERKEY2 */ - -/* Reset Value for FEEPROL*/ -#define FEEPROL_RVAL 0xFFFF - -/* FEEPROL[VALUE] - Lower 16 bits of the write protection. This register is read only if the write protection in flash has been programmed, i.e. FEEPROH/L have previously been configured to protect pages. */ -#define FEEPROL_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for FEEPROH*/ -#define FEEPROH_RVAL 0xFFFF - -/* FEEPROH[VALUE] - Upper 16 bits of the write protection. This register is read only if the write protection in flash has been programmed, i.e. FEEPROH/L have previously been configured to protect pages. */ -#define FEEPROH_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for FEESIGL*/ -#define FEESIGL_RVAL 0xFFFF - -/* FEESIGL[VALUE] - Lower 16 bits of the signature. Signature[15:0]. */ -#define FEESIGL_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for FEESIGH*/ -#define FEESIGH_RVAL 0xFFFF - -/* FEESIGH[VALUE] - Upper eight bits of the signature. Signature[23:16]. */ -#define FEESIGH_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for FEECON1*/ -#define FEECON1_RVAL 0x1 - -/* FEECON1[DBG] - Serial Wire debug enable. */ -#define FEECON1_DBG_BBA (*(volatile unsigned long *) 0x42050700) -#define FEECON1_DBG_MSK (0x1 << 0 ) -#define FEECON1_DBG (0x1 << 0 ) -#define FEECON1_DBG_DIS (0x0 << 0 ) /* DIS. Disable access via the serial wire debug interface. */ -#define FEECON1_DBG_EN (0x1 << 0 ) /* EN. Enable access via the serial wire debug interface. */ - -/* Reset Value for FEEADRAL*/ -#define FEEADRAL_RVAL 0x800 - -/* FEEADRAL[VALUE] - Lower 16 bits of the FEEADRA register. If a write is aborted then this will contain the address of the location been written when the write was aborted. */ -#define FEEADRAL_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for FEEADRAH*/ -#define FEEADRAH_RVAL 0x2 - -/* FEEADRAH[VALUE] - Upper 16 bits of the FEEADRA register. */ -#define FEEADRAH_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for FEEAEN0*/ -#define FEEAEN0_RVAL 0x0 - -/* FEEAEN0[FEE] - Flash controller interrupt abort enable bit */ -#define FEEAEN0_FEE_BBA (*(volatile unsigned long *) 0x42050F3C) -#define FEEAEN0_FEE_MSK (0x1 << 15 ) -#define FEEAEN0_FEE (0x1 << 15 ) -#define FEEAEN0_FEE_DIS (0x0 << 15 ) /* DIS. Flash controller interrupt abort disabled. */ -#define FEEAEN0_FEE_EN (0x1 << 15 ) /* EN. Flash controller interrupt abort enabled. */ - -/* FEEAEN0[ADC] - ADC interrupt abort enable bit */ -#define FEEAEN0_ADC_BBA (*(volatile unsigned long *) 0x42050F38) -#define FEEAEN0_ADC_MSK (0x1 << 14 ) -#define FEEAEN0_ADC (0x1 << 14 ) -#define FEEAEN0_ADC_DIS (0x0 << 14 ) /* DIS. ADC interrupt abort disabled. */ -#define FEEAEN0_ADC_EN (0x1 << 14 ) /* EN. ADC interrupt abort enabled. */ - -/* FEEAEN0[T1] - Timer1 interrupt abort enable bit */ -#define FEEAEN0_T1_BBA (*(volatile unsigned long *) 0x42050F34) -#define FEEAEN0_T1_MSK (0x1 << 13 ) -#define FEEAEN0_T1 (0x1 << 13 ) -#define FEEAEN0_T1_DIS (0x0 << 13 ) /* DIS. Timer1 interrupt abort disabled. */ -#define FEEAEN0_T1_EN (0x1 << 13 ) /* EN. Timer1 interrupt abort enabled. */ - -/* FEEAEN0[T0] - Timer0 interrupt abort enable bit */ -#define FEEAEN0_T0_BBA (*(volatile unsigned long *) 0x42050F30) -#define FEEAEN0_T0_MSK (0x1 << 12 ) -#define FEEAEN0_T0 (0x1 << 12 ) -#define FEEAEN0_T0_DIS (0x0 << 12 ) /* DIS. Timer0 interrupt abort disabled. */ -#define FEEAEN0_T0_EN (0x1 << 12 ) /* EN. Timer0 interrupt abort enabled. */ - -/* FEEAEN0[T3] - Timer3 interrupt abort enable bit */ -#define FEEAEN0_T3_BBA (*(volatile unsigned long *) 0x42050F28) -#define FEEAEN0_T3_MSK (0x1 << 10 ) -#define FEEAEN0_T3 (0x1 << 10 ) -#define FEEAEN0_T3_DIS (0x0 << 10 ) /* DIS. Timer3 interrupt abort disabled. */ -#define FEEAEN0_T3_EN (0x1 << 10 ) /* EN. Timer3 interrupt abort enabled. */ - -/* FEEAEN0[EXTINT8] - External interrupt 8 abort enable bit */ -#define FEEAEN0_EXTINT8_BBA (*(volatile unsigned long *) 0x42050F24) -#define FEEAEN0_EXTINT8_MSK (0x1 << 9 ) -#define FEEAEN0_EXTINT8 (0x1 << 9 ) -#define FEEAEN0_EXTINT8_DIS (0x0 << 9 ) /* DIS. External interrupt 8 abort disabled. */ -#define FEEAEN0_EXTINT8_EN (0x1 << 9 ) /* EN. External interrupt 8 abort enabled. */ - -/* FEEAEN0[EXTINT7] - External interrupt 7 abort enable bit */ -#define FEEAEN0_EXTINT7_BBA (*(volatile unsigned long *) 0x42050F20) -#define FEEAEN0_EXTINT7_MSK (0x1 << 8 ) -#define FEEAEN0_EXTINT7 (0x1 << 8 ) -#define FEEAEN0_EXTINT7_DIS (0x0 << 8 ) /* DIS. External interrupt 7 abort disabled. */ -#define FEEAEN0_EXTINT7_EN (0x1 << 8 ) /* EN. External interrupt 7 abort enabled. */ - -/* FEEAEN0[EXTINT6] - External interrupt 6 abort enable bit */ -#define FEEAEN0_EXTINT6_BBA (*(volatile unsigned long *) 0x42050F1C) -#define FEEAEN0_EXTINT6_MSK (0x1 << 7 ) -#define FEEAEN0_EXTINT6 (0x1 << 7 ) -#define FEEAEN0_EXTINT6_DIS (0x0 << 7 ) /* DIS. External interrupt 6 abort disabled. */ -#define FEEAEN0_EXTINT6_EN (0x1 << 7 ) /* EN. External interrupt 6 abort enabled. */ - -/* FEEAEN0[EXTINT5] - External interrupt 5 abort enable bit */ -#define FEEAEN0_EXTINT5_BBA (*(volatile unsigned long *) 0x42050F18) -#define FEEAEN0_EXTINT5_MSK (0x1 << 6 ) -#define FEEAEN0_EXTINT5 (0x1 << 6 ) -#define FEEAEN0_EXTINT5_DIS (0x0 << 6 ) /* DIS. External interrupt 5 abort disabled. */ -#define FEEAEN0_EXTINT5_EN (0x1 << 6 ) /* EN. External interrupt 5 abort enabled. */ - -/* FEEAEN0[EXTINT4] - External interrupt 4 abort enable bit */ -#define FEEAEN0_EXTINT4_BBA (*(volatile unsigned long *) 0x42050F14) -#define FEEAEN0_EXTINT4_MSK (0x1 << 5 ) -#define FEEAEN0_EXTINT4 (0x1 << 5 ) -#define FEEAEN0_EXTINT4_DIS (0x0 << 5 ) /* DIS. External interrupt 4 abort disabled. */ -#define FEEAEN0_EXTINT4_EN (0x1 << 5 ) /* EN. External interrupt 4 abort enabled. */ - -/* FEEAEN0[EXTINT3] - External interrupt 3 abort enable bit */ -#define FEEAEN0_EXTINT3_BBA (*(volatile unsigned long *) 0x42050F10) -#define FEEAEN0_EXTINT3_MSK (0x1 << 4 ) -#define FEEAEN0_EXTINT3 (0x1 << 4 ) -#define FEEAEN0_EXTINT3_DIS (0x0 << 4 ) /* DIS. External interrupt 3 abort disabled. */ -#define FEEAEN0_EXTINT3_EN (0x1 << 4 ) /* EN. External interrupt 3 abort enabled. */ - -/* FEEAEN0[EXTINT2] - External interrupt 2 abort enable bit */ -#define FEEAEN0_EXTINT2_BBA (*(volatile unsigned long *) 0x42050F0C) -#define FEEAEN0_EXTINT2_MSK (0x1 << 3 ) -#define FEEAEN0_EXTINT2 (0x1 << 3 ) -#define FEEAEN0_EXTINT2_DIS (0x0 << 3 ) /* DIS. External interrupt 2 abort disabled. */ -#define FEEAEN0_EXTINT2_EN (0x1 << 3 ) /* EN. External interrupt 2 abort enabled. */ - -/* FEEAEN0[EXTINT1] - External interrupt 1 abort enable bit */ -#define FEEAEN0_EXTINT1_BBA (*(volatile unsigned long *) 0x42050F08) -#define FEEAEN0_EXTINT1_MSK (0x1 << 2 ) -#define FEEAEN0_EXTINT1 (0x1 << 2 ) -#define FEEAEN0_EXTINT1_DIS (0x0 << 2 ) /* DIS. External interrupt 1 abort disabled. */ -#define FEEAEN0_EXTINT1_EN (0x1 << 2 ) /* EN. External interrupt 1 abort enabled. */ - -/* FEEAEN0[EXTINT0] - External interrupt 0 abort enable bit */ -#define FEEAEN0_EXTINT0_BBA (*(volatile unsigned long *) 0x42050F04) -#define FEEAEN0_EXTINT0_MSK (0x1 << 1 ) -#define FEEAEN0_EXTINT0 (0x1 << 1 ) -#define FEEAEN0_EXTINT0_DIS (0x0 << 1 ) /* DIS. External interrupt 0 abort disabled. */ -#define FEEAEN0_EXTINT0_EN (0x1 << 1 ) /* EN. External interrupt 0 abort enabled. */ - -/* FEEAEN0[T2] - Timer2 interrupt abort enable bit */ -#define FEEAEN0_T2_BBA (*(volatile unsigned long *) 0x42050F00) -#define FEEAEN0_T2_MSK (0x1 << 0 ) -#define FEEAEN0_T2 (0x1 << 0 ) -#define FEEAEN0_T2_DIS (0x0 << 0 ) /* DIS. Timer2 interrupt abort disabled. */ -#define FEEAEN0_T2_EN (0x1 << 0 ) /* EN. Timer2 interrupt abort enabled */ - -/* Reset Value for FEEAEN1*/ -#define FEEAEN1_RVAL 0x0 - -/* FEEAEN1[DMAI2CMRX] - I2C master RX DMA interrupt abort enable bit */ -#define FEEAEN1_DMAI2CMRX_BBA (*(volatile unsigned long *) 0x42050FBC) -#define FEEAEN1_DMAI2CMRX_MSK (0x1 << 15 ) -#define FEEAEN1_DMAI2CMRX (0x1 << 15 ) -#define FEEAEN1_DMAI2CMRX_DIS (0x0 << 15 ) /* DIS. I2C master RX DMA interrupt abort disabled. */ -#define FEEAEN1_DMAI2CMRX_EN (0x1 << 15 ) /* EN. I2C master RX DMA interrupt abort enabled. */ - -/* FEEAEN1[DMAI2CMTX] - I2C master TX DMA interrupt abort enable bit */ -#define FEEAEN1_DMAI2CMTX_BBA (*(volatile unsigned long *) 0x42050FB8) -#define FEEAEN1_DMAI2CMTX_MSK (0x1 << 14 ) -#define FEEAEN1_DMAI2CMTX (0x1 << 14 ) -#define FEEAEN1_DMAI2CMTX_DIS (0x0 << 14 ) /* DIS. I2C master TX DMA interrupt abort disabled. */ -#define FEEAEN1_DMAI2CMTX_EN (0x1 << 14 ) /* EN. I2C master TX DMA interrupt abort enabled. */ - -/* FEEAEN1[DMAI2CSRX] - I2C slave RX DMA interrupt abort enable bit */ -#define FEEAEN1_DMAI2CSRX_BBA (*(volatile unsigned long *) 0x42050FB4) -#define FEEAEN1_DMAI2CSRX_MSK (0x1 << 13 ) -#define FEEAEN1_DMAI2CSRX (0x1 << 13 ) -#define FEEAEN1_DMAI2CSRX_DIS (0x0 << 13 ) /* DIS. I2C slave RX DMA interrupt abort disabled. */ -#define FEEAEN1_DMAI2CSRX_EN (0x1 << 13 ) /* EN. I2C slave RX DMA interrupt abort enabled. */ - -/* FEEAEN1[DMAI2CSTX] - I2C slave TX DMA interrupt abort enable bit */ -#define FEEAEN1_DMAI2CSTX_BBA (*(volatile unsigned long *) 0x42050FB0) -#define FEEAEN1_DMAI2CSTX_MSK (0x1 << 12 ) -#define FEEAEN1_DMAI2CSTX (0x1 << 12 ) -#define FEEAEN1_DMAI2CSTX_DIS (0x0 << 12 ) /* DIS. I2C slave TX DMA interrupt abort disabled. */ -#define FEEAEN1_DMAI2CSTX_EN (0x1 << 12 ) /* EN. I2C slave TX DMA interrupt abort enabled. */ - -/* FEEAEN1[DMAUARTRX] - UARTRX DMA interrupt abort enable bit */ -#define FEEAEN1_DMAUARTRX_BBA (*(volatile unsigned long *) 0x42050FAC) -#define FEEAEN1_DMAUARTRX_MSK (0x1 << 11 ) -#define FEEAEN1_DMAUARTRX (0x1 << 11 ) -#define FEEAEN1_DMAUARTRX_DIS (0x0 << 11 ) /* DIS. UARTRX DMA interrupt abort disabled. */ -#define FEEAEN1_DMAUARTRX_EN (0x1 << 11 ) /* EN. UARTRX DMA interrupt abort enabled. */ - -/* FEEAEN1[DMAUARTTX] - UARTTX DMA interrupt abort enable bit */ -#define FEEAEN1_DMAUARTTX_BBA (*(volatile unsigned long *) 0x42050FA8) -#define FEEAEN1_DMAUARTTX_MSK (0x1 << 10 ) -#define FEEAEN1_DMAUARTTX (0x1 << 10 ) -#define FEEAEN1_DMAUARTTX_DIS (0x0 << 10 ) /* DIS. UARTTX DMA interrupt abort disabled. */ -#define FEEAEN1_DMAUARTTX_EN (0x1 << 10 ) /* EN. UARTTX DMA interrupt abort enabled. */ - -/* FEEAEN1[DMASPI1RX] - SPI1RX DMA interrupt abort enable bit */ -#define FEEAEN1_DMASPI1RX_BBA (*(volatile unsigned long *) 0x42050FA4) -#define FEEAEN1_DMASPI1RX_MSK (0x1 << 9 ) -#define FEEAEN1_DMASPI1RX (0x1 << 9 ) -#define FEEAEN1_DMASPI1RX_DIS (0x0 << 9 ) /* DIS. SPI1RX DMA interrupt abort disabled. */ -#define FEEAEN1_DMASPI1RX_EN (0x1 << 9 ) /* EN. SPI1RX DMA interrupt abort enabled. */ - -/* FEEAEN1[DMASPI1TX] - SPI1TX DMA interrupt abort enable bit */ -#define FEEAEN1_DMASPI1TX_BBA (*(volatile unsigned long *) 0x42050FA0) -#define FEEAEN1_DMASPI1TX_MSK (0x1 << 8 ) -#define FEEAEN1_DMASPI1TX (0x1 << 8 ) -#define FEEAEN1_DMASPI1TX_DIS (0x0 << 8 ) /* DIS. SPI1TX DMA interrupt abort disabled. */ -#define FEEAEN1_DMASPI1TX_EN (0x1 << 8 ) /* EN. SPI1TX DMA interrupt abort enabled. */ - -/* FEEAEN1[DMAERROR] - DMA error interrupt abort enable bit */ -#define FEEAEN1_DMAERROR_BBA (*(volatile unsigned long *) 0x42050F9C) -#define FEEAEN1_DMAERROR_MSK (0x1 << 7 ) -#define FEEAEN1_DMAERROR (0x1 << 7 ) -#define FEEAEN1_DMAERROR_DIS (0x0 << 7 ) /* DIS. DMA error interrupt abort disabled. */ -#define FEEAEN1_DMAERROR_EN (0x1 << 7 ) /* EN. DMA error interrupt abort enabled. */ - -/* FEEAEN1[I2CM] - I2C master interrupt abort enable bit */ -#define FEEAEN1_I2CM_BBA (*(volatile unsigned long *) 0x42050F90) -#define FEEAEN1_I2CM_MSK (0x1 << 4 ) -#define FEEAEN1_I2CM (0x1 << 4 ) -#define FEEAEN1_I2CM_DIS (0x0 << 4 ) /* DIS. I2C slave interrupt abort disabled. */ -#define FEEAEN1_I2CM_EN (0x1 << 4 ) /* EN. I2C master interrupt abort enabled. */ - -/* FEEAEN1[I2CS] - I2C slave interrupt abort enable bit */ -#define FEEAEN1_I2CS_BBA (*(volatile unsigned long *) 0x42050F8C) -#define FEEAEN1_I2CS_MSK (0x1 << 3 ) -#define FEEAEN1_I2CS (0x1 << 3 ) -#define FEEAEN1_I2CS_DIS (0x0 << 3 ) /* DIS. I2C slave interrupt abort disabled. */ -#define FEEAEN1_I2CS_EN (0x1 << 3 ) /* EN. I2C slave interrupt abort enabled. */ - -/* FEEAEN1[SPI1] - SPI1 interrupt abort enable bit */ -#define FEEAEN1_SPI1_BBA (*(volatile unsigned long *) 0x42050F88) -#define FEEAEN1_SPI1_MSK (0x1 << 2 ) -#define FEEAEN1_SPI1 (0x1 << 2 ) -#define FEEAEN1_SPI1_DIS (0x0 << 2 ) /* DIS. SPI1 interrupt abort disabled. */ -#define FEEAEN1_SPI1_EN (0x1 << 2 ) /* EN. SPI1 interrupt abort enabled. */ - -/* FEEAEN1[SPI0] - SPI0 interrupt abort enable bit */ -#define FEEAEN1_SPI0_BBA (*(volatile unsigned long *) 0x42050F84) -#define FEEAEN1_SPI0_MSK (0x1 << 1 ) -#define FEEAEN1_SPI0 (0x1 << 1 ) -#define FEEAEN1_SPI0_DIS (0x0 << 1 ) /* DIS. SPI0 interrupt abort disabled. */ -#define FEEAEN1_SPI0_EN (0x1 << 1 ) /* EN. SPI0 interrupt abort enabled. */ - -/* FEEAEN1[UART] - UART interrupt abort enable bit */ -#define FEEAEN1_UART_BBA (*(volatile unsigned long *) 0x42050F80) -#define FEEAEN1_UART_MSK (0x1 << 0 ) -#define FEEAEN1_UART (0x1 << 0 ) -#define FEEAEN1_UART_DIS (0x0 << 0 ) /* DIS. UART interrupt abort disabled. */ -#define FEEAEN1_UART_EN (0x1 << 0 ) /* EN. UART interrupt abort enabled. */ - -/* Reset Value for FEEAEN2*/ -#define FEEAEN2_RVAL 0x0 - -/* FEEAEN2[PWM3] - PWM3 interrupt abort enable bit */ -#define FEEAEN2_PWM3_BBA (*(volatile unsigned long *) 0x42051028) -#define FEEAEN2_PWM3_MSK (0x1 << 10 ) -#define FEEAEN2_PWM3 (0x1 << 10 ) -#define FEEAEN2_PWM3_DIS (0x0 << 10 ) /* DIS. PWM3 interrupt abort disabled. */ -#define FEEAEN2_PWM3_EN (0x1 << 10 ) /* EN. PWM3 interrupt abort enabled. */ - -/* FEEAEN2[PWM2] - PWM2 interrupt abort enable bit */ -#define FEEAEN2_PWM2_BBA (*(volatile unsigned long *) 0x42051024) -#define FEEAEN2_PWM2_MSK (0x1 << 9 ) -#define FEEAEN2_PWM2 (0x1 << 9 ) -#define FEEAEN2_PWM2_DIS (0x0 << 9 ) /* DIS. PWM2 interrupt abort disabled. */ -#define FEEAEN2_PWM2_EN (0x1 << 9 ) /* EN. PWM2 interrupt abort enabled. */ - -/* FEEAEN2[PWM1] - PWM1 interrupt abort enable bit */ -#define FEEAEN2_PWM1_BBA (*(volatile unsigned long *) 0x42051020) -#define FEEAEN2_PWM1_MSK (0x1 << 8 ) -#define FEEAEN2_PWM1 (0x1 << 8 ) -#define FEEAEN2_PWM1_DIS (0x0 << 8 ) /* DIS. PWM1 interrupt abort disabled. */ -#define FEEAEN2_PWM1_EN (0x1 << 8 ) /* EN. PWM1 interrupt abort enabled. */ - -/* FEEAEN2[PWM0] - PWM0 interrupt abort enable bit */ -#define FEEAEN2_PWM0_BBA (*(volatile unsigned long *) 0x4205101C) -#define FEEAEN2_PWM0_MSK (0x1 << 7 ) -#define FEEAEN2_PWM0 (0x1 << 7 ) -#define FEEAEN2_PWM0_DIS (0x0 << 7 ) /* DIS. PWM0 interrupt abort disabled. */ -#define FEEAEN2_PWM0_EN (0x1 << 7 ) /* EN. PWM0 interrupt abort enabled. */ - -/* FEEAEN2[PWMTRIP] - PWMTRIP interrupt abort enable bit */ -#define FEEAEN2_PWMTRIP_BBA (*(volatile unsigned long *) 0x42051018) -#define FEEAEN2_PWMTRIP_MSK (0x1 << 6 ) -#define FEEAEN2_PWMTRIP (0x1 << 6 ) -#define FEEAEN2_PWMTRIP_DIS (0x0 << 6 ) /* DIS. PWMTRIP interrupt abort disabled. */ -#define FEEAEN2_PWMTRIP_EN (0x1 << 6 ) /* EN. PWMTRIP interrupt abort enabled. */ - -/* FEEAEN2[DMASPI0RX] - SPI0RX DMA interrupt abort enable bit */ -#define FEEAEN2_DMASPI0RX_BBA (*(volatile unsigned long *) 0x42051014) -#define FEEAEN2_DMASPI0RX_MSK (0x1 << 5 ) -#define FEEAEN2_DMASPI0RX (0x1 << 5 ) -#define FEEAEN2_DMASPI0RX_DIS (0x0 << 5 ) /* DIS. SPI0RX DMA interrupt abort disabled. */ -#define FEEAEN2_DMASPI0RX_EN (0x1 << 5 ) /* EN. SPI0RX DMA interrupt abort enabled. */ - -/* FEEAEN2[DMASPI0TX] - SPI0TX DMA interrupt abort enable bit */ -#define FEEAEN2_DMASPI0TX_BBA (*(volatile unsigned long *) 0x42051010) -#define FEEAEN2_DMASPI0TX_MSK (0x1 << 4 ) -#define FEEAEN2_DMASPI0TX (0x1 << 4 ) -#define FEEAEN2_DMASPI0TX_DIS (0x0 << 4 ) /* DIS. SPI0TX DMA interrupt abort disabled. */ -#define FEEAEN2_DMASPI0TX_EN (0x1 << 4 ) /* EN. SPI0TX DMA interrupt abort enabled. */ - -/* FEEAEN2[DMAADC] - ADC DMA interrupt abort enable bit */ -#define FEEAEN2_DMAADC_BBA (*(volatile unsigned long *) 0x4205100C) -#define FEEAEN2_DMAADC_MSK (0x1 << 3 ) -#define FEEAEN2_DMAADC (0x1 << 3 ) -#define FEEAEN2_DMAADC_DIS (0x0 << 3 ) /* DIS. ADC DMA interrupt abort disabled. */ -#define FEEAEN2_DMAADC_EN (0x1 << 3 ) /* EN. ADC DMA interrupt abort enabled. */ -// ------------------------------------------------------------------------------------------------ -// ----- GPIO0 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief General Purpose Input Output (pADI_GP0) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_GP0 Structure */ - __IO uint16_t GPCON; /*!< GPIO Port 0 Configuration */ - __I uint16_t RESERVED0; - __IO uint8_t GPOEN; /*!< GPIO Port 0 Output Enable */ - __I uint8_t RESERVED1[3]; - __IO uint8_t GPPUL; /*!< GPIO Port 0 Pull Up Enable */ - __I uint8_t RESERVED2[3]; - __IO uint8_t GPOCE; /*!< GPIO Port 0 Tri State */ - __I uint8_t RESERVED3[7]; - __IO uint8_t GPIN; /*!< GPIO Port 0 Data Input */ - __I uint8_t RESERVED4[3]; - __IO uint8_t GPOUT; /*!< GPIO Port 0 Data Out */ - __I uint8_t RESERVED5[3]; - __IO uint8_t GPSET; /*!< GPIO Port 0 Data Out Set */ - __I uint8_t RESERVED6[3]; - __IO uint8_t GPCLR; /*!< GPIO Port 0 Data Out Clear */ - __I uint8_t RESERVED7[3]; - __IO uint8_t GPTGL; /*!< GPIO Port 0 Pin Toggle */ -} ADI_GPIO_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define GP0CON (*(volatile unsigned short int *) 0x40006000) -#define GP0OEN (*(volatile unsigned char *) 0x40006004) -#define GP0PUL (*(volatile unsigned char *) 0x40006008) -#define GP0OCE (*(volatile unsigned char *) 0x4000600C) -#define GP0IN (*(volatile unsigned char *) 0x40006014) -#define GP0OUT (*(volatile unsigned char *) 0x40006018) -#define GP0SET (*(volatile unsigned char *) 0x4000601C) -#define GP0CLR (*(volatile unsigned char *) 0x40006020) -#define GP0TGL (*(volatile unsigned char *) 0x40006024) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for GP0CON*/ -#define GP0CON_RVAL 0x0 - -/* GP0CON[CON7] - Configuration bits for Px.7 (not available for port 1). */ -#define GP0CON_CON7_MSK (0x3 << 14 ) -#define GP0CON_CON7_GPIOIRQ3 (0x0 << 14 ) /* GPIOIRQ3. GPIO/IRQ3. */ -#define GP0CON_CON7_SPI1CS4 (0x1 << 14 ) /* SPI1CS4. SPI1 CS4 (SPI1). */ -#define GP0CON_CON7_UARTCTS (0x2 << 14 ) /* UARTCTS. UART CTS. */ - -/* GP0CON[CON6] - Configuration bits for Px.6 (not available for port 1). */ -#define GP0CON_CON6_MSK (0x3 << 12 ) -#define GP0CON_CON6_GPIOIRQ2 (0x0 << 12 ) /* GPIOIRQ2. GPIO/IRQ2. */ -#define GP0CON_CON6_SPI1CS3 (0x1 << 12 ) /* SPI1CS3. SPI1 CS3 (SPI1). */ -#define GP0CON_CON6_UARTRTS (0x2 << 12 ) /* UARTRTS. UART RTS. */ -#define GP0CON_CON6_PWM0 (0x3 << 12 ) /* PWM0. PWM0. */ - -/* GP0CON[CON5] - Configuration bits for Px.5. */ -#define GP0CON_CON5_MSK (0x3 << 10 ) -#define GP0CON_CON5_GPIO (0x0 << 10 ) /* GPIO. GPIO. */ -#define GP0CON_CON5_SPI1CS2 (0x1 << 10 ) /* SPI1CS2. SPI1 CS2 (SPI1). */ -#define GP0CON_CON5_ECLKIN (0x2 << 10 ) /* ECLKIN. ECLKIN. */ - -/* GP0CON[CON4] - Configuration bits for Px.4. */ -#define GP0CON_CON4_MSK (0x3 << 8 ) -#define GP0CON_CON4_GPIO (0x0 << 8 ) /* GPIO. GPIO */ -#define GP0CON_CON4_SPI1CS1 (0x1 << 8 ) /* SPI1CS1. SPI1 CS1 (SPI1). */ -#define GP0CON_CON4_ECLKOUT (0x2 << 8 ) /* ECLKOUT. ECLK OUT. */ - -/* GP0CON[CON3] - Configuration bits for Px.3. */ -#define GP0CON_CON3_MSK (0x3 << 6 ) -#define GP0CON_CON3_GPIOIRQ1 (0x0 << 6 ) /* GPIOIRQ1. GPIO/IRQ1. */ -#define GP0CON_CON3_SPI1CS0 (0x1 << 6 ) /* SPI1CS0. SPI1 CS0 (SPI1). */ -#define GP0CON_CON3_ADCCONVST (0x2 << 6 ) /* ADCCONVST. ADCCONVST. */ -#define GP0CON_CON3_PWM1 (0x3 << 6 ) /* PWM1. PWM1. */ - -/* GP0CON[CON2] - Configuration bits for Px.2. */ -#define GP0CON_CON2_MSK (0x3 << 4 ) -#define GP0CON_CON2_GPIO (0x0 << 4 ) /* GPIO. GPIO */ -#define GP0CON_CON2_SPI1MOSI (0x1 << 4 ) /* SPI1MOSI. SPI MOSI (SPI1). */ -#define GP0CON_CON2_PWM0 (0x3 << 4 ) /* PWM0. PWM0 */ - -/* GP0CON[CON1] - Configuration bits for Px.1. */ -#define GP0CON_CON1_MSK (0x3 << 2 ) -#define GP0CON_CON1_GPIO (0x0 << 2 ) /* GPIO. GPIO. */ -#define GP0CON_CON1_SPI1SCLK (0x1 << 2 ) /* SPI1SCLK. SPI SCLK (SPI1). */ - -/* GP0CON[CON0] - Configuration bits for Px.0. */ -#define GP0CON_CON0_MSK (0x3 << 0 ) -#define GP0CON_CON0_GPIO (0x0 << 0 ) /* GPIO. GPIO */ -#define GP0CON_CON0_SPI1MISO (0x1 << 0 ) /* SPI1MISO. SPI MISO (SPI1) */ - -/* Reset Value for GP0OEN*/ -#define GP0OEN_RVAL 0x0 - -/* GP0OEN[OEN7] - Port pin direction. */ -#define GP0OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C009C) -#define GP0OEN_OEN7_MSK (0x1 << 7 ) -#define GP0OEN_OEN7 (0x1 << 7 ) -#define GP0OEN_OEN7_IN (0x0 << 7 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP0OEN_OEN7_OUT (0x1 << 7 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP0OEN[OEN6] - Port pin direction. */ -#define GP0OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0098) -#define GP0OEN_OEN6_MSK (0x1 << 6 ) -#define GP0OEN_OEN6 (0x1 << 6 ) -#define GP0OEN_OEN6_IN (0x0 << 6 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP0OEN_OEN6_OUT (0x1 << 6 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP0OEN[OEN5] - Port pin direction. */ -#define GP0OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0094) -#define GP0OEN_OEN5_MSK (0x1 << 5 ) -#define GP0OEN_OEN5 (0x1 << 5 ) -#define GP0OEN_OEN5_IN (0x0 << 5 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP0OEN_OEN5_OUT (0x1 << 5 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP0OEN[OEN4] - Port pin direction. */ -#define GP0OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0090) -#define GP0OEN_OEN4_MSK (0x1 << 4 ) -#define GP0OEN_OEN4 (0x1 << 4 ) -#define GP0OEN_OEN4_IN (0x0 << 4 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP0OEN_OEN4_OUT (0x1 << 4 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP0OEN[OEN3] - Port pin direction. */ -#define GP0OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C008C) -#define GP0OEN_OEN3_MSK (0x1 << 3 ) -#define GP0OEN_OEN3 (0x1 << 3 ) -#define GP0OEN_OEN3_IN (0x0 << 3 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP0OEN_OEN3_OUT (0x1 << 3 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP0OEN[OEN2] - Port pin direction. */ -#define GP0OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0088) -#define GP0OEN_OEN2_MSK (0x1 << 2 ) -#define GP0OEN_OEN2 (0x1 << 2 ) -#define GP0OEN_OEN2_IN (0x0 << 2 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP0OEN_OEN2_OUT (0x1 << 2 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP0OEN[OEN1] - Port pin direction. */ -#define GP0OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0084) -#define GP0OEN_OEN1_MSK (0x1 << 1 ) -#define GP0OEN_OEN1 (0x1 << 1 ) -#define GP0OEN_OEN1_IN (0x0 << 1 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP0OEN_OEN1_OUT (0x1 << 1 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP0OEN[OEN0] - Port pin direction. */ -#define GP0OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0080) -#define GP0OEN_OEN0_MSK (0x1 << 0 ) -#define GP0OEN_OEN0 (0x1 << 0 ) -#define GP0OEN_OEN0_IN (0x0 << 0 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP0OEN_OEN0_OUT (0x1 << 0 ) /* OUT. Enables the output on corresponding port pin.. */ - -/* Reset Value for GP0PUL*/ -#define GP0PUL_RVAL 0xFF - -/* GP0PUL[PUL7] - Pull Up Enable for port pin. */ -#define GP0PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C011C) -#define GP0PUL_PUL7_MSK (0x1 << 7 ) -#define GP0PUL_PUL7 (0x1 << 7 ) -#define GP0PUL_PUL7_DIS (0x0 << 7 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP0PUL_PUL7_EN (0x1 << 7 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP0PUL[PUL6] - Pull Up Enable for port pin. */ -#define GP0PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0118) -#define GP0PUL_PUL6_MSK (0x1 << 6 ) -#define GP0PUL_PUL6 (0x1 << 6 ) -#define GP0PUL_PUL6_DIS (0x0 << 6 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP0PUL_PUL6_EN (0x1 << 6 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP0PUL[PUL5] - Pull Up Enable for port pin. */ -#define GP0PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0114) -#define GP0PUL_PUL5_MSK (0x1 << 5 ) -#define GP0PUL_PUL5 (0x1 << 5 ) -#define GP0PUL_PUL5_DIS (0x0 << 5 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP0PUL_PUL5_EN (0x1 << 5 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP0PUL[PUL4] - Pull Up Enable for port pin. */ -#define GP0PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0110) -#define GP0PUL_PUL4_MSK (0x1 << 4 ) -#define GP0PUL_PUL4 (0x1 << 4 ) -#define GP0PUL_PUL4_DIS (0x0 << 4 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP0PUL_PUL4_EN (0x1 << 4 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP0PUL[PUL3] - Pull Up Enable for port pin. */ -#define GP0PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C010C) -#define GP0PUL_PUL3_MSK (0x1 << 3 ) -#define GP0PUL_PUL3 (0x1 << 3 ) -#define GP0PUL_PUL3_DIS (0x0 << 3 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP0PUL_PUL3_EN (0x1 << 3 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP0PUL[PUL2] - Pull Up Enable for port pin. */ -#define GP0PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0108) -#define GP0PUL_PUL2_MSK (0x1 << 2 ) -#define GP0PUL_PUL2 (0x1 << 2 ) -#define GP0PUL_PUL2_DIS (0x0 << 2 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP0PUL_PUL2_EN (0x1 << 2 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP0PUL[PUL1] - Pull Up Enable for port pin. */ -#define GP0PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0104) -#define GP0PUL_PUL1_MSK (0x1 << 1 ) -#define GP0PUL_PUL1 (0x1 << 1 ) -#define GP0PUL_PUL1_DIS (0x0 << 1 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP0PUL_PUL1_EN (0x1 << 1 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP0PUL[PUL0] - Pull Up Enable for port pin. */ -#define GP0PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0100) -#define GP0PUL_PUL0_MSK (0x1 << 0 ) -#define GP0PUL_PUL0 (0x1 << 0 ) -#define GP0PUL_PUL0_DIS (0x0 << 0 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP0PUL_PUL0_EN (0x1 << 0 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* Reset Value for GP0OCE*/ -#define GP0OCE_RVAL 0x0 - -/* GP0OCE[OCE7] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP0OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C019C) -#define GP0OCE_OCE7_MSK (0x1 << 7 ) -#define GP0OCE_OCE7 (0x1 << 7 ) -#define GP0OCE_OCE7_DIS (0x0 << 7 ) /* DIS */ -#define GP0OCE_OCE7_EN (0x1 << 7 ) /* EN */ - -/* GP0OCE[OCE6] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP0OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0198) -#define GP0OCE_OCE6_MSK (0x1 << 6 ) -#define GP0OCE_OCE6 (0x1 << 6 ) -#define GP0OCE_OCE6_DIS (0x0 << 6 ) /* DIS */ -#define GP0OCE_OCE6_EN (0x1 << 6 ) /* EN */ - -/* GP0OCE[OCE5] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP0OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0194) -#define GP0OCE_OCE5_MSK (0x1 << 5 ) -#define GP0OCE_OCE5 (0x1 << 5 ) -#define GP0OCE_OCE5_DIS (0x0 << 5 ) /* DIS */ -#define GP0OCE_OCE5_EN (0x1 << 5 ) /* EN */ - -/* GP0OCE[OCE4] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP0OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0190) -#define GP0OCE_OCE4_MSK (0x1 << 4 ) -#define GP0OCE_OCE4 (0x1 << 4 ) -#define GP0OCE_OCE4_DIS (0x0 << 4 ) /* DIS */ -#define GP0OCE_OCE4_EN (0x1 << 4 ) /* EN */ - -/* GP0OCE[OCE3] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP0OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C018C) -#define GP0OCE_OCE3_MSK (0x1 << 3 ) -#define GP0OCE_OCE3 (0x1 << 3 ) -#define GP0OCE_OCE3_DIS (0x0 << 3 ) /* DIS */ -#define GP0OCE_OCE3_EN (0x1 << 3 ) /* EN */ - -/* GP0OCE[OCE2] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP0OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0188) -#define GP0OCE_OCE2_MSK (0x1 << 2 ) -#define GP0OCE_OCE2 (0x1 << 2 ) -#define GP0OCE_OCE2_DIS (0x0 << 2 ) /* DIS */ -#define GP0OCE_OCE2_EN (0x1 << 2 ) /* EN */ - -/* GP0OCE[OCE1] - Output enable. Sets the GPIO pads oncorresponding port to open circuit mode. */ -#define GP0OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0184) -#define GP0OCE_OCE1_MSK (0x1 << 1 ) -#define GP0OCE_OCE1 (0x1 << 1 ) -#define GP0OCE_OCE1_DIS (0x0 << 1 ) /* DIS */ -#define GP0OCE_OCE1_EN (0x1 << 1 ) /* EN */ - -/* GP0OCE[OCE0] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP0OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0180) -#define GP0OCE_OCE0_MSK (0x1 << 0 ) -#define GP0OCE_OCE0 (0x1 << 0 ) -#define GP0OCE_OCE0_DIS (0x0 << 0 ) /* DIS */ -#define GP0OCE_OCE0_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for GP0IN*/ -#define GP0IN_RVAL 0xFF - -/* GP0IN[IN7] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP0IN_IN7_BBA (*(volatile unsigned long *) 0x420C029C) -#define GP0IN_IN7_MSK (0x1 << 7 ) -#define GP0IN_IN7 (0x1 << 7 ) -#define GP0IN_IN7_LOW (0x0 << 7 ) /* LOW */ -#define GP0IN_IN7_HIGH (0x1 << 7 ) /* HIGH */ - -/* GP0IN[IN6] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP0IN_IN6_BBA (*(volatile unsigned long *) 0x420C0298) -#define GP0IN_IN6_MSK (0x1 << 6 ) -#define GP0IN_IN6 (0x1 << 6 ) -#define GP0IN_IN6_LOW (0x0 << 6 ) /* LOW */ -#define GP0IN_IN6_HIGH (0x1 << 6 ) /* HIGH */ - -/* GP0IN[IN5] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP0IN_IN5_BBA (*(volatile unsigned long *) 0x420C0294) -#define GP0IN_IN5_MSK (0x1 << 5 ) -#define GP0IN_IN5 (0x1 << 5 ) -#define GP0IN_IN5_LOW (0x0 << 5 ) /* LOW */ -#define GP0IN_IN5_HIGH (0x1 << 5 ) /* HIGH */ - -/* GP0IN[IN4] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP0IN_IN4_BBA (*(volatile unsigned long *) 0x420C0290) -#define GP0IN_IN4_MSK (0x1 << 4 ) -#define GP0IN_IN4 (0x1 << 4 ) -#define GP0IN_IN4_LOW (0x0 << 4 ) /* LOW */ -#define GP0IN_IN4_HIGH (0x1 << 4 ) /* HIGH */ - -/* GP0IN[IN3] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP0IN_IN3_BBA (*(volatile unsigned long *) 0x420C028C) -#define GP0IN_IN3_MSK (0x1 << 3 ) -#define GP0IN_IN3 (0x1 << 3 ) -#define GP0IN_IN3_LOW (0x0 << 3 ) /* LOW */ -#define GP0IN_IN3_HIGH (0x1 << 3 ) /* HIGH */ - -/* GP0IN[IN2] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP0IN_IN2_BBA (*(volatile unsigned long *) 0x420C0288) -#define GP0IN_IN2_MSK (0x1 << 2 ) -#define GP0IN_IN2 (0x1 << 2 ) -#define GP0IN_IN2_LOW (0x0 << 2 ) /* LOW */ -#define GP0IN_IN2_HIGH (0x1 << 2 ) /* HIGH */ - -/* GP0IN[IN1] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP0IN_IN1_BBA (*(volatile unsigned long *) 0x420C0284) -#define GP0IN_IN1_MSK (0x1 << 1 ) -#define GP0IN_IN1 (0x1 << 1 ) -#define GP0IN_IN1_LOW (0x0 << 1 ) /* LOW */ -#define GP0IN_IN1_HIGH (0x1 << 1 ) /* HIGH */ - -/* GP0IN[IN0] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP0IN_IN0_BBA (*(volatile unsigned long *) 0x420C0280) -#define GP0IN_IN0_MSK (0x1 << 0 ) -#define GP0IN_IN0 (0x1 << 0 ) -#define GP0IN_IN0_LOW (0x0 << 0 ) /* LOW */ -#define GP0IN_IN0_HIGH (0x1 << 0 ) /* HIGH */ - -/* Reset Value for GP0OUT*/ -#define GP0OUT_RVAL 0x0 - -/* GP0OUT[OUT7] - Data out register. */ -#define GP0OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C031C) -#define GP0OUT_OUT7_MSK (0x1 << 7 ) -#define GP0OUT_OUT7 (0x1 << 7 ) -#define GP0OUT_OUT7_LOW (0x0 << 7 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP0OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP0OUT[OUT6] - Data out register. */ -#define GP0OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0318) -#define GP0OUT_OUT6_MSK (0x1 << 6 ) -#define GP0OUT_OUT6 (0x1 << 6 ) -#define GP0OUT_OUT6_LOW (0x0 << 6 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP0OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP0OUT[OUT5] - Data out register. */ -#define GP0OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0314) -#define GP0OUT_OUT5_MSK (0x1 << 5 ) -#define GP0OUT_OUT5 (0x1 << 5 ) -#define GP0OUT_OUT5_LOW (0x0 << 5 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP0OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP0OUT[OUT4] - Data out register. */ -#define GP0OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0310) -#define GP0OUT_OUT4_MSK (0x1 << 4 ) -#define GP0OUT_OUT4 (0x1 << 4 ) -#define GP0OUT_OUT4_LOW (0x0 << 4 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP0OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP0OUT[OUT3] - Data out register. */ -#define GP0OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C030C) -#define GP0OUT_OUT3_MSK (0x1 << 3 ) -#define GP0OUT_OUT3 (0x1 << 3 ) -#define GP0OUT_OUT3_LOW (0x0 << 3 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP0OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP0OUT[OUT2] - Data out register. */ -#define GP0OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0308) -#define GP0OUT_OUT2_MSK (0x1 << 2 ) -#define GP0OUT_OUT2 (0x1 << 2 ) -#define GP0OUT_OUT2_LOW (0x0 << 2 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP0OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP0OUT[OUT1] - Data out register. */ -#define GP0OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0304) -#define GP0OUT_OUT1_MSK (0x1 << 1 ) -#define GP0OUT_OUT1 (0x1 << 1 ) -#define GP0OUT_OUT1_LOW (0x0 << 1 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP0OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP0OUT[OUT0] - Data out register. */ -#define GP0OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0300) -#define GP0OUT_OUT0_MSK (0x1 << 0 ) -#define GP0OUT_OUT0 (0x1 << 0 ) -#define GP0OUT_OUT0_LOW (0x0 << 0 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP0OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* Reset Value for GP0SET*/ -#define GP0SET_RVAL 0x0 - -/* GP0SET[SET7] - Set output high for corresponding port pin. */ -#define GP0SET_SET7_BBA (*(volatile unsigned long *) 0x420C039C) -#define GP0SET_SET7_MSK (0x1 << 7 ) -#define GP0SET_SET7 (0x1 << 7 ) -#define GP0SET_SET7_SET (0x1 << 7 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP0SET[SET6] - Set output high for corresponding port pin. */ -#define GP0SET_SET6_BBA (*(volatile unsigned long *) 0x420C0398) -#define GP0SET_SET6_MSK (0x1 << 6 ) -#define GP0SET_SET6 (0x1 << 6 ) -#define GP0SET_SET6_SET (0x1 << 6 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP0SET[SET5] - Set output high for corresponding port pin. */ -#define GP0SET_SET5_BBA (*(volatile unsigned long *) 0x420C0394) -#define GP0SET_SET5_MSK (0x1 << 5 ) -#define GP0SET_SET5 (0x1 << 5 ) -#define GP0SET_SET5_SET (0x1 << 5 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP0SET[SET4] - Set output high for corresponding port pin. */ -#define GP0SET_SET4_BBA (*(volatile unsigned long *) 0x420C0390) -#define GP0SET_SET4_MSK (0x1 << 4 ) -#define GP0SET_SET4 (0x1 << 4 ) -#define GP0SET_SET4_SET (0x1 << 4 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP0SET[SET3] - Set output high for corresponding port pin. */ -#define GP0SET_SET3_BBA (*(volatile unsigned long *) 0x420C038C) -#define GP0SET_SET3_MSK (0x1 << 3 ) -#define GP0SET_SET3 (0x1 << 3 ) -#define GP0SET_SET3_SET (0x1 << 3 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP0SET[SET2] - Set output high for corresponding port pin. */ -#define GP0SET_SET2_BBA (*(volatile unsigned long *) 0x420C0388) -#define GP0SET_SET2_MSK (0x1 << 2 ) -#define GP0SET_SET2 (0x1 << 2 ) -#define GP0SET_SET2_SET (0x1 << 2 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP0SET[SET1] - Set output high for corresponding port pin. */ -#define GP0SET_SET1_BBA (*(volatile unsigned long *) 0x420C0384) -#define GP0SET_SET1_MSK (0x1 << 1 ) -#define GP0SET_SET1 (0x1 << 1 ) -#define GP0SET_SET1_SET (0x1 << 1 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP0SET[SET0] - Set output high for corresponding port pin. */ -#define GP0SET_SET0_BBA (*(volatile unsigned long *) 0x420C0380) -#define GP0SET_SET0_MSK (0x1 << 0 ) -#define GP0SET_SET0 (0x1 << 0 ) -#define GP0SET_SET0_SET (0x1 << 0 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* Reset Value for GP0CLR*/ -#define GP0CLR_RVAL 0x0 - -/* GP0CLR[CLR7] - Set by user code to drive the corresponding GPIO low. */ -#define GP0CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C041C) -#define GP0CLR_CLR7_MSK (0x1 << 7 ) -#define GP0CLR_CLR7 (0x1 << 7 ) -#define GP0CLR_CLR7_CLR (0x1 << 7 ) /* CLR */ - -/* GP0CLR[CLR6] - Set by user code to drive the corresponding GPIO low. */ -#define GP0CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C0418) -#define GP0CLR_CLR6_MSK (0x1 << 6 ) -#define GP0CLR_CLR6 (0x1 << 6 ) -#define GP0CLR_CLR6_CLR (0x1 << 6 ) /* CLR */ - -/* GP0CLR[CLR5] - Set by user code to drive the corresponding GPIO low. */ -#define GP0CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C0414) -#define GP0CLR_CLR5_MSK (0x1 << 5 ) -#define GP0CLR_CLR5 (0x1 << 5 ) -#define GP0CLR_CLR5_CLR (0x1 << 5 ) /* CLR */ - -/* GP0CLR[CLR4] - Set by user code to drive the corresponding GPIO low. */ -#define GP0CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C0410) -#define GP0CLR_CLR4_MSK (0x1 << 4 ) -#define GP0CLR_CLR4 (0x1 << 4 ) -#define GP0CLR_CLR4_CLR (0x1 << 4 ) /* CLR */ - -/* GP0CLR[CLR3] - Set by user code to drive the corresponding GPIO low. */ -#define GP0CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C040C) -#define GP0CLR_CLR3_MSK (0x1 << 3 ) -#define GP0CLR_CLR3 (0x1 << 3 ) -#define GP0CLR_CLR3_CLR (0x1 << 3 ) /* CLR */ - -/* GP0CLR[CLR2] - Set by user code to drive the corresponding GPIO low. */ -#define GP0CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C0408) -#define GP0CLR_CLR2_MSK (0x1 << 2 ) -#define GP0CLR_CLR2 (0x1 << 2 ) -#define GP0CLR_CLR2_CLR (0x1 << 2 ) /* CLR */ - -/* GP0CLR[CLR1] - Set by user code to drive the corresponding GPIO low. */ -#define GP0CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C0404) -#define GP0CLR_CLR1_MSK (0x1 << 1 ) -#define GP0CLR_CLR1 (0x1 << 1 ) -#define GP0CLR_CLR1_CLR (0x1 << 1 ) /* CLR */ - -/* GP0CLR[CLR0] - Set by user code to drive the corresponding GPIO low. */ -#define GP0CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C0400) -#define GP0CLR_CLR0_MSK (0x1 << 0 ) -#define GP0CLR_CLR0 (0x1 << 0 ) -#define GP0CLR_CLR0_CLR (0x1 << 0 ) /* CLR */ - -/* Reset Value for GP0TGL*/ -#define GP0TGL_RVAL 0x0 - -/* GP0TGL[TGL7] - Toggle for corresponding port pin. */ -#define GP0TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C049C) -#define GP0TGL_TGL7_MSK (0x1 << 7 ) -#define GP0TGL_TGL7 (0x1 << 7 ) -#define GP0TGL_TGL7_TGL (0x1 << 7 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP0TGL[TGL6] - Toggle for corresponding port pin. */ -#define GP0TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C0498) -#define GP0TGL_TGL6_MSK (0x1 << 6 ) -#define GP0TGL_TGL6 (0x1 << 6 ) -#define GP0TGL_TGL6_TGL (0x1 << 6 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP0TGL[TGL5] - Toggle for corresponding port pin. */ -#define GP0TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C0494) -#define GP0TGL_TGL5_MSK (0x1 << 5 ) -#define GP0TGL_TGL5 (0x1 << 5 ) -#define GP0TGL_TGL5_TGL (0x1 << 5 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP0TGL[TGL4] - Toggle for corresponding port pin. */ -#define GP0TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C0490) -#define GP0TGL_TGL4_MSK (0x1 << 4 ) -#define GP0TGL_TGL4 (0x1 << 4 ) -#define GP0TGL_TGL4_TGL (0x1 << 4 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP0TGL[TGL3] - Toggle for corresponding port pin. */ -#define GP0TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C048C) -#define GP0TGL_TGL3_MSK (0x1 << 3 ) -#define GP0TGL_TGL3 (0x1 << 3 ) -#define GP0TGL_TGL3_TGL (0x1 << 3 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP0TGL[TGL2] - Toggle for corresponding port pin. */ -#define GP0TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C0488) -#define GP0TGL_TGL2_MSK (0x1 << 2 ) -#define GP0TGL_TGL2 (0x1 << 2 ) -#define GP0TGL_TGL2_TGL (0x1 << 2 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP0TGL[TGL1] - Toggle for corresponding port pin. */ -#define GP0TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C0484) -#define GP0TGL_TGL1_MSK (0x1 << 1 ) -#define GP0TGL_TGL1 (0x1 << 1 ) -#define GP0TGL_TGL1_TGL (0x1 << 1 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP0TGL[TGL0] - Toggle for corresponding port pin. */ -#define GP0TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C0480) -#define GP0TGL_TGL0_MSK (0x1 << 0 ) -#define GP0TGL_TGL0 (0x1 << 0 ) -#define GP0TGL_TGL0_TGL (0x1 << 0 ) /* TGL. Set by user code to invert the corresponding GPIO. */ -#if (__NO_MMR_STRUCTS__==1) - -#define GP1CON (*(volatile unsigned short int *) 0x40006030) -#define GP1OEN (*(volatile unsigned char *) 0x40006034) -#define GP1PUL (*(volatile unsigned char *) 0x40006038) -#define GP1OCE (*(volatile unsigned char *) 0x4000603C) -#define GP1IN (*(volatile unsigned char *) 0x40006044) -#define GP1OUT (*(volatile unsigned char *) 0x40006048) -#define GP1SET (*(volatile unsigned char *) 0x4000604C) -#define GP1CLR (*(volatile unsigned char *) 0x40006050) -#define GP1TGL (*(volatile unsigned char *) 0x40006054) -#endif // (__NO_MMR_STRUCTS__==1) - -/* Reset Value for GP1CON*/ -#define GP1CON_RVAL 0x0 - -/* GP1CON[CON6] - Configuration bits for P1.6 */ -#define GP1CON_CON6_MSK (0x3 << 12 ) -#define GP1CON_CON6_GPIO (0x0 << 12 ) /* GPIO */ -#define GP1CON_CON6_ADCCONVST (0x1 << 12 ) /* ADCCONVST */ -#define GP1CON_CON6_PWMSYNC (0x3 << 12 ) /* PWMSYNC */ - -/* GP1CON[CON5] - Configuration bits for P1.5 */ -#define GP1CON_CON5_MSK (0x3 << 10 ) -#define GP1CON_CON5_GPIOIRQ6 (0x0 << 10 ) /* GPIOIRQ6 */ -#define GP1CON_CON5_I2C0SDA (0x1 << 10 ) /* I2C0SDA */ -#define GP1CON_CON5_PWM7 (0x2 << 10 ) /* PWM7 */ - -/* GP1CON[CON4] - Configuration bits for P1.4 */ -#define GP1CON_CON4_MSK (0x3 << 8 ) -#define GP1CON_CON4_GPIOIRQ5 (0x0 << 8 ) /* GPIOIRQ5 */ -#define GP1CON_CON4_I2C0SCL (0x1 << 8 ) /* I2C0SCL */ -#define GP1CON_CON4_PWM6 (0x2 << 8 ) /* PWM6 */ - -/* GP1CON[CON3] - Configuration bits for P1.3 */ -#define GP1CON_CON3_MSK (0x3 << 6 ) -#define GP1CON_CON3_GPIO (0x1 << 6 ) /* GPIO */ -#define GP1CON_CON3_PWM5 (0x3 << 6 ) /* PWM5 */ - -/* GP1CON[CON2] - Configuration bits for P1.2 */ -#define GP1CON_CON2_MSK (0x3 << 4 ) -#define GP1CON_CON2_GPIO (0x1 << 4 ) /* GPIO */ -#define GP1CON_CON2_PWM4 (0x3 << 4 ) /* PWM4 */ - -/* GP1CON[CON1] - Configuration bits for P1.1 */ -#define GP1CON_CON1_MSK (0x3 << 2 ) -#define GP1CON_CON1_PORB (0x0 << 2 ) /* PORB */ -#define GP1CON_CON1_GPIO (0x1 << 2 ) /* GPIO */ -#define GP1CON_CON1_UART0TXD (0x2 << 2 ) /* UART0TXD */ -#define GP1CON_CON1_PWM3 (0x3 << 2 ) /* PWM3 */ - -/* GP1CON[CON0] - Configuration bits for P1.0 */ -#define GP1CON_CON0_MSK (0x3 << 0 ) -#define GP1CON_CON0_GPIOIRQ4 (0x0 << 0 ) /* GPIOIRQ4 */ -#define GP1CON_CON0_UART0RXD (0x1 << 0 ) /* UART0RXD */ -#define GP1CON_CON0_SPI1MOSI (0x2 << 0 ) /* SPI1MOSI */ -#define GP1CON_CON0_PWM2 (0x3 << 0 ) /* PWM2 */ - -/* Reset Value for GP1OEN*/ -#define GP1OEN_RVAL 0x0 - -/* GP1OEN[OEN6] - Port pin direction. */ -#define GP1OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0698) -#define GP1OEN_OEN6_MSK (0x1 << 6 ) -#define GP1OEN_OEN6 (0x1 << 6 ) -#define GP1OEN_OEN6_IN (0x0 << 6 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP1OEN_OEN6_OUT (0x1 << 6 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP1OEN[OEN5] - Port pin direction. */ -#define GP1OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0694) -#define GP1OEN_OEN5_MSK (0x1 << 5 ) -#define GP1OEN_OEN5 (0x1 << 5 ) -#define GP1OEN_OEN5_IN (0x0 << 5 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP1OEN_OEN5_OUT (0x1 << 5 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP1OEN[OEN4] - Port pin direction. */ -#define GP1OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0690) -#define GP1OEN_OEN4_MSK (0x1 << 4 ) -#define GP1OEN_OEN4 (0x1 << 4 ) -#define GP1OEN_OEN4_IN (0x0 << 4 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP1OEN_OEN4_OUT (0x1 << 4 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP1OEN[OEN3] - Port pin direction. */ -#define GP1OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C068C) -#define GP1OEN_OEN3_MSK (0x1 << 3 ) -#define GP1OEN_OEN3 (0x1 << 3 ) -#define GP1OEN_OEN3_IN (0x0 << 3 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP1OEN_OEN3_OUT (0x1 << 3 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP1OEN[OEN2] - Port pin direction. */ -#define GP1OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0688) -#define GP1OEN_OEN2_MSK (0x1 << 2 ) -#define GP1OEN_OEN2 (0x1 << 2 ) -#define GP1OEN_OEN2_IN (0x0 << 2 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP1OEN_OEN2_OUT (0x1 << 2 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP1OEN[OEN1] - Port pin direction. */ -#define GP1OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0684) -#define GP1OEN_OEN1_MSK (0x1 << 1 ) -#define GP1OEN_OEN1 (0x1 << 1 ) -#define GP1OEN_OEN1_IN (0x0 << 1 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP1OEN_OEN1_OUT (0x1 << 1 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP1OEN[OEN0] - Port pin direction. */ -#define GP1OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0680) -#define GP1OEN_OEN0_MSK (0x1 << 0 ) -#define GP1OEN_OEN0 (0x1 << 0 ) -#define GP1OEN_OEN0_IN (0x0 << 0 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP1OEN_OEN0_OUT (0x1 << 0 ) /* OUT. Enables the output on corresponding port pin.. */ - -/* Reset Value for GP1PUL*/ -#define GP1PUL_RVAL 0x7F - -/* GP1PUL[PUL6] - Pull Up Enable for port pin. */ -#define GP1PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0718) -#define GP1PUL_PUL6_MSK (0x1 << 6 ) -#define GP1PUL_PUL6 (0x1 << 6 ) -#define GP1PUL_PUL6_DIS (0x0 << 6 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP1PUL_PUL6_EN (0x1 << 6 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP1PUL[PUL5] - Pull Up Enable for port pin. */ -#define GP1PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0714) -#define GP1PUL_PUL5_MSK (0x1 << 5 ) -#define GP1PUL_PUL5 (0x1 << 5 ) -#define GP1PUL_PUL5_DIS (0x0 << 5 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP1PUL_PUL5_EN (0x1 << 5 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP1PUL[PUL4] - Pull Up Enable for port pin. */ -#define GP1PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0710) -#define GP1PUL_PUL4_MSK (0x1 << 4 ) -#define GP1PUL_PUL4 (0x1 << 4 ) -#define GP1PUL_PUL4_DIS (0x0 << 4 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP1PUL_PUL4_EN (0x1 << 4 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP1PUL[PUL3] - Pull Up Enable for port pin. */ -#define GP1PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C070C) -#define GP1PUL_PUL3_MSK (0x1 << 3 ) -#define GP1PUL_PUL3 (0x1 << 3 ) -#define GP1PUL_PUL3_DIS (0x0 << 3 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP1PUL_PUL3_EN (0x1 << 3 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP1PUL[PUL2] - Pull Up Enable for port pin. */ -#define GP1PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0708) -#define GP1PUL_PUL2_MSK (0x1 << 2 ) -#define GP1PUL_PUL2 (0x1 << 2 ) -#define GP1PUL_PUL2_DIS (0x0 << 2 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP1PUL_PUL2_EN (0x1 << 2 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP1PUL[PUL1] - Pull Up Enable for port pin. */ -#define GP1PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0704) -#define GP1PUL_PUL1_MSK (0x1 << 1 ) -#define GP1PUL_PUL1 (0x1 << 1 ) -#define GP1PUL_PUL1_DIS (0x0 << 1 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP1PUL_PUL1_EN (0x1 << 1 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP1PUL[PUL0] - Pull Up Enable for port pin. */ -#define GP1PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0700) -#define GP1PUL_PUL0_MSK (0x1 << 0 ) -#define GP1PUL_PUL0 (0x1 << 0 ) -#define GP1PUL_PUL0_DIS (0x0 << 0 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP1PUL_PUL0_EN (0x1 << 0 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* Reset Value for GP1OCE*/ -#define GP1OCE_RVAL 0x0 - -/* GP1OCE[OCE6] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP1OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0798) -#define GP1OCE_OCE6_MSK (0x1 << 6 ) -#define GP1OCE_OCE6 (0x1 << 6 ) -#define GP1OCE_OCE6_DIS (0x0 << 6 ) /* DIS */ -#define GP1OCE_OCE6_EN (0x1 << 6 ) /* EN */ - -/* GP1OCE[OCE5] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP1OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0794) -#define GP1OCE_OCE5_MSK (0x1 << 5 ) -#define GP1OCE_OCE5 (0x1 << 5 ) -#define GP1OCE_OCE5_DIS (0x0 << 5 ) /* DIS */ -#define GP1OCE_OCE5_EN (0x1 << 5 ) /* EN */ - -/* GP1OCE[OCE4] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP1OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0790) -#define GP1OCE_OCE4_MSK (0x1 << 4 ) -#define GP1OCE_OCE4 (0x1 << 4 ) -#define GP1OCE_OCE4_DIS (0x0 << 4 ) /* DIS */ -#define GP1OCE_OCE4_EN (0x1 << 4 ) /* EN */ - -/* GP1OCE[OCE3] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP1OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C078C) -#define GP1OCE_OCE3_MSK (0x1 << 3 ) -#define GP1OCE_OCE3 (0x1 << 3 ) -#define GP1OCE_OCE3_DIS (0x0 << 3 ) /* DIS */ -#define GP1OCE_OCE3_EN (0x1 << 3 ) /* EN */ - -/* GP1OCE[OCE2] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP1OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0788) -#define GP1OCE_OCE2_MSK (0x1 << 2 ) -#define GP1OCE_OCE2 (0x1 << 2 ) -#define GP1OCE_OCE2_DIS (0x0 << 2 ) /* DIS */ -#define GP1OCE_OCE2_EN (0x1 << 2 ) /* EN */ - -/* GP1OCE[OCE1] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP1OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0784) -#define GP1OCE_OCE1_MSK (0x1 << 1 ) -#define GP1OCE_OCE1 (0x1 << 1 ) -#define GP1OCE_OCE1_DIS (0x0 << 1 ) /* DIS */ -#define GP1OCE_OCE1_EN (0x1 << 1 ) /* EN */ - -/* GP1OCE[OCE0] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP1OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0780) -#define GP1OCE_OCE0_MSK (0x1 << 0 ) -#define GP1OCE_OCE0 (0x1 << 0 ) -#define GP1OCE_OCE0_DIS (0x0 << 0 ) /* DIS */ -#define GP1OCE_OCE0_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for GP1IN*/ -#define GP1IN_RVAL 0x7F - -/* GP1IN[IN6] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP1IN_IN6_BBA (*(volatile unsigned long *) 0x420C0898) -#define GP1IN_IN6_MSK (0x1 << 6 ) -#define GP1IN_IN6 (0x1 << 6 ) -#define GP1IN_IN6_LOW (0x0 << 6 ) /* LOW */ -#define GP1IN_IN6_HIGH (0x1 << 6 ) /* HIGH */ - -/* GP1IN[IN5] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP1IN_IN5_BBA (*(volatile unsigned long *) 0x420C0894) -#define GP1IN_IN5_MSK (0x1 << 5 ) -#define GP1IN_IN5 (0x1 << 5 ) -#define GP1IN_IN5_LOW (0x0 << 5 ) /* LOW */ -#define GP1IN_IN5_HIGH (0x1 << 5 ) /* HIGH */ - -/* GP1IN[IN4] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP1IN_IN4_BBA (*(volatile unsigned long *) 0x420C0890) -#define GP1IN_IN4_MSK (0x1 << 4 ) -#define GP1IN_IN4 (0x1 << 4 ) -#define GP1IN_IN4_LOW (0x0 << 4 ) /* LOW */ -#define GP1IN_IN4_HIGH (0x1 << 4 ) /* HIGH */ - -/* GP1IN[IN3] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP1IN_IN3_BBA (*(volatile unsigned long *) 0x420C088C) -#define GP1IN_IN3_MSK (0x1 << 3 ) -#define GP1IN_IN3 (0x1 << 3 ) -#define GP1IN_IN3_LOW (0x0 << 3 ) /* LOW */ -#define GP1IN_IN3_HIGH (0x1 << 3 ) /* HIGH */ - -/* GP1IN[IN2] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP1IN_IN2_BBA (*(volatile unsigned long *) 0x420C0888) -#define GP1IN_IN2_MSK (0x1 << 2 ) -#define GP1IN_IN2 (0x1 << 2 ) -#define GP1IN_IN2_LOW (0x0 << 2 ) /* LOW */ -#define GP1IN_IN2_HIGH (0x1 << 2 ) /* HIGH */ - -/* GP1IN[IN1] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP1IN_IN1_BBA (*(volatile unsigned long *) 0x420C0884) -#define GP1IN_IN1_MSK (0x1 << 1 ) -#define GP1IN_IN1 (0x1 << 1 ) -#define GP1IN_IN1_LOW (0x0 << 1 ) /* LOW */ -#define GP1IN_IN1_HIGH (0x1 << 1 ) /* HIGH */ - -/* GP1IN[IN0] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP1IN_IN0_BBA (*(volatile unsigned long *) 0x420C0880) -#define GP1IN_IN0_MSK (0x1 << 0 ) -#define GP1IN_IN0 (0x1 << 0 ) -#define GP1IN_IN0_LOW (0x0 << 0 ) /* LOW */ -#define GP1IN_IN0_HIGH (0x1 << 0 ) /* HIGH */ - -/* Reset Value for GP1OUT*/ -#define GP1OUT_RVAL 0x0 - -/* GP1OUT[OUT6] - Output for port pin. */ -#define GP1OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0918) -#define GP1OUT_OUT6_MSK (0x1 << 6 ) -#define GP1OUT_OUT6 (0x1 << 6 ) -#define GP1OUT_OUT6_LOW (0x0 << 6 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP1OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP1OUT[OUT5] - Output for port pin. */ -#define GP1OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0914) -#define GP1OUT_OUT5_MSK (0x1 << 5 ) -#define GP1OUT_OUT5 (0x1 << 5 ) -#define GP1OUT_OUT5_LOW (0x0 << 5 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP1OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP1OUT[OUT4] - Output for port pin. */ -#define GP1OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0910) -#define GP1OUT_OUT4_MSK (0x1 << 4 ) -#define GP1OUT_OUT4 (0x1 << 4 ) -#define GP1OUT_OUT4_LOW (0x0 << 4 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP1OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP1OUT[OUT3] - Output for port pin. */ -#define GP1OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C090C) -#define GP1OUT_OUT3_MSK (0x1 << 3 ) -#define GP1OUT_OUT3 (0x1 << 3 ) -#define GP1OUT_OUT3_LOW (0x0 << 3 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP1OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP1OUT[OUT2] - Output for port pin. */ -#define GP1OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0908) -#define GP1OUT_OUT2_MSK (0x1 << 2 ) -#define GP1OUT_OUT2 (0x1 << 2 ) -#define GP1OUT_OUT2_LOW (0x0 << 2 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP1OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP1OUT[OUT1] - Output for port pin. */ -#define GP1OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0904) -#define GP1OUT_OUT1_MSK (0x1 << 1 ) -#define GP1OUT_OUT1 (0x1 << 1 ) -#define GP1OUT_OUT1_LOW (0x0 << 1 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP1OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP1OUT[OUT0] - Output for port pin. */ -#define GP1OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0900) -#define GP1OUT_OUT0_MSK (0x1 << 0 ) -#define GP1OUT_OUT0 (0x1 << 0 ) -#define GP1OUT_OUT0_LOW (0x0 << 0 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP1OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* Reset Value for GP1SET*/ -#define GP1SET_RVAL 0x0 - -/* GP1SET[SET6] - Set output high for corresponding port pin. */ -#define GP1SET_SET6_BBA (*(volatile unsigned long *) 0x420C0998) -#define GP1SET_SET6_MSK (0x1 << 6 ) -#define GP1SET_SET6 (0x1 << 6 ) -#define GP1SET_SET6_SET (0x1 << 6 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP1SET[SET5] - Set output high for corresponding port pin. */ -#define GP1SET_SET5_BBA (*(volatile unsigned long *) 0x420C0994) -#define GP1SET_SET5_MSK (0x1 << 5 ) -#define GP1SET_SET5 (0x1 << 5 ) -#define GP1SET_SET5_SET (0x1 << 5 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP1SET[SET4] - Set output high for corresponding port pin. */ -#define GP1SET_SET4_BBA (*(volatile unsigned long *) 0x420C0990) -#define GP1SET_SET4_MSK (0x1 << 4 ) -#define GP1SET_SET4 (0x1 << 4 ) -#define GP1SET_SET4_SET (0x1 << 4 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP1SET[SET3] - Set output high for corresponding port pin. */ -#define GP1SET_SET3_BBA (*(volatile unsigned long *) 0x420C098C) -#define GP1SET_SET3_MSK (0x1 << 3 ) -#define GP1SET_SET3 (0x1 << 3 ) -#define GP1SET_SET3_SET (0x1 << 3 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP1SET[SET2] - Set output high for corresponding port pin. */ -#define GP1SET_SET2_BBA (*(volatile unsigned long *) 0x420C0988) -#define GP1SET_SET2_MSK (0x1 << 2 ) -#define GP1SET_SET2 (0x1 << 2 ) -#define GP1SET_SET2_SET (0x1 << 2 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP1SET[SET1] - Set output high for corresponding port pin. */ -#define GP1SET_SET1_BBA (*(volatile unsigned long *) 0x420C0984) -#define GP1SET_SET1_MSK (0x1 << 1 ) -#define GP1SET_SET1 (0x1 << 1 ) -#define GP1SET_SET1_SET (0x1 << 1 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP1SET[SET0] - Set output high for corresponding port pin. */ -#define GP1SET_SET0_BBA (*(volatile unsigned long *) 0x420C0980) -#define GP1SET_SET0_MSK (0x1 << 0 ) -#define GP1SET_SET0 (0x1 << 0 ) -#define GP1SET_SET0_SET (0x1 << 0 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* Reset Value for GP1CLR*/ -#define GP1CLR_RVAL 0x0 - -/* GP1CLR[CLR6] - Set by user code to drive the corresponding GPIO low. */ -#define GP1CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C0A18) -#define GP1CLR_CLR6_MSK (0x1 << 6 ) -#define GP1CLR_CLR6 (0x1 << 6 ) -#define GP1CLR_CLR6_CLR (0x1 << 6 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP1CLR[CLR5] - Set by user code to drive the corresponding GPIO low. */ -#define GP1CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C0A14) -#define GP1CLR_CLR5_MSK (0x1 << 5 ) -#define GP1CLR_CLR5 (0x1 << 5 ) -#define GP1CLR_CLR5_CLR (0x1 << 5 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP1CLR[CLR4] - Set by user code to drive the corresponding GPIO low. */ -#define GP1CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C0A10) -#define GP1CLR_CLR4_MSK (0x1 << 4 ) -#define GP1CLR_CLR4 (0x1 << 4 ) -#define GP1CLR_CLR4_CLR (0x1 << 4 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP1CLR[CLR3] - Set by user code to drive the corresponding GPIO low. */ -#define GP1CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C0A0C) -#define GP1CLR_CLR3_MSK (0x1 << 3 ) -#define GP1CLR_CLR3 (0x1 << 3 ) -#define GP1CLR_CLR3_CLR (0x1 << 3 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP1CLR[CLR2] - Set by user code to drive the corresponding GPIO low. */ -#define GP1CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C0A08) -#define GP1CLR_CLR2_MSK (0x1 << 2 ) -#define GP1CLR_CLR2 (0x1 << 2 ) -#define GP1CLR_CLR2_CLR (0x1 << 2 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP1CLR[CLR1] - Set by user code to drive the corresponding GPIO low. */ -#define GP1CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C0A04) -#define GP1CLR_CLR1_MSK (0x1 << 1 ) -#define GP1CLR_CLR1 (0x1 << 1 ) -#define GP1CLR_CLR1_CLR (0x1 << 1 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP1CLR[CLR0] - Set by user code to drive the corresponding GPIO low. */ -#define GP1CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C0A00) -#define GP1CLR_CLR0_MSK (0x1 << 0 ) -#define GP1CLR_CLR0 (0x1 << 0 ) -#define GP1CLR_CLR0_CLR (0x1 << 0 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* Reset Value for GP1TGL*/ -#define GP1TGL_RVAL 0x0 - -/* GP1TGL[TGL6] - Toggle for corresponding port pin. */ -#define GP1TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C0A98) -#define GP1TGL_TGL6_MSK (0x1 << 6 ) -#define GP1TGL_TGL6 (0x1 << 6 ) -#define GP1TGL_TGL6_TGL (0x1 << 6 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP1TGL[TGL5] - Toggle for corresponding port pin. */ -#define GP1TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C0A94) -#define GP1TGL_TGL5_MSK (0x1 << 5 ) -#define GP1TGL_TGL5 (0x1 << 5 ) -#define GP1TGL_TGL5_TGL (0x1 << 5 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP1TGL[TGL4] - Toggle for corresponding port pin. */ -#define GP1TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C0A90) -#define GP1TGL_TGL4_MSK (0x1 << 4 ) -#define GP1TGL_TGL4 (0x1 << 4 ) -#define GP1TGL_TGL4_TGL (0x1 << 4 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP1TGL[TGL3] - Toggle for corresponding port pin. */ -#define GP1TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C0A8C) -#define GP1TGL_TGL3_MSK (0x1 << 3 ) -#define GP1TGL_TGL3 (0x1 << 3 ) -#define GP1TGL_TGL3_TGL (0x1 << 3 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP1TGL[TGL2] - Toggle for corresponding port pin. */ -#define GP1TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C0A88) -#define GP1TGL_TGL2_MSK (0x1 << 2 ) -#define GP1TGL_TGL2 (0x1 << 2 ) -#define GP1TGL_TGL2_TGL (0x1 << 2 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP1TGL[TGL1] - Toggle for corresponding port pin. */ -#define GP1TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C0A84) -#define GP1TGL_TGL1_MSK (0x1 << 1 ) -#define GP1TGL_TGL1 (0x1 << 1 ) -#define GP1TGL_TGL1_TGL (0x1 << 1 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP1TGL[TGL0] - Toggle for corresponding port pin. */ -#define GP1TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C0A80) -#define GP1TGL_TGL0_MSK (0x1 << 0 ) -#define GP1TGL_TGL0 (0x1 << 0 ) -#define GP1TGL_TGL0_TGL (0x1 << 0 ) /* TGL. Set by user code to invert the corresponding GPIO. */ -#if (__NO_MMR_STRUCTS__==1) - -#define GP2CON (*(volatile unsigned short int *) 0x40006060) -#define GP2OEN (*(volatile unsigned char *) 0x40006064) -#define GP2PUL (*(volatile unsigned char *) 0x40006068) -#define GP2OCE (*(volatile unsigned char *) 0x4000606C) -#define GP2IN (*(volatile unsigned char *) 0x40006074) -#define GP2OUT (*(volatile unsigned char *) 0x40006078) -#define GP2SET (*(volatile unsigned char *) 0x4000607C) -#define GP2CLR (*(volatile unsigned char *) 0x40006080) -#define GP2TGL (*(volatile unsigned char *) 0x40006084) -#endif // (__NO_MMR_STRUCTS__==1) - -/* Reset Value for GP2CON*/ -#define GP2CON_RVAL 0x0 - -/* GP2CON[CON7] - Configuration bits for P2.7 */ -#define GP2CON_CON7_MSK (0x3 << 14 ) -#define GP2CON_CON7_GPIOIRQ7 (0x0 << 14 ) /* GPIOIRQ7 */ - -/* GP2CON[CON6] - Configuration bits for P2.6 */ -#define GP2CON_CON6_MSK (0x3 << 12 ) -#define GP2CON_CON6_GPIO (0x1 << 12 ) /* GPIO */ - -/* GP2CON[CON5] - Configuration bits for P2.5 */ -#define GP2CON_CON5_MSK (0x3 << 10 ) -#define GP2CON_CON5_GPIO (0x2 << 10 ) /* GPIO */ -#define GP2CON_CON5_RF32KHZCLK (0x3 << 10 ) /* RF32KHZCLK */ - -/* GP2CON[CON4] - Configuration bits for P2.4 */ -#define GP2CON_CON4_MSK (0x3 << 8 ) -#define GP2CON_CON4_IRQ8 (0x0 << 8 ) /* IRQ8 */ -#define GP2CON_CON4_GPIO (0x1 << 8 ) /* GPIO */ - -/* GP2CON[CON3] - Configuration bits for P2.3 */ -#define GP2CON_CON3_MSK (0x3 << 6 ) -#define GP2CON_CON3_SPI0CS (0x0 << 6 ) /* SPI0CS */ -#define GP2CON_CON3_GPIO (0x1 << 6 ) /* GPIO */ - -/* GP2CON[CON2] - Configuration bits for P2.2 */ -#define GP2CON_CON2_MSK (0x3 << 4 ) -#define GP2CON_CON2_SPI0MOSI (0x0 << 4 ) /* SPI0MOSI */ -#define GP2CON_CON2_GPIO (0x1 << 4 ) /* GPIO */ - -/* GP2CON[CON1] - Configuration bits for P2.1 */ -#define GP2CON_CON1_MSK (0x3 << 2 ) -#define GP2CON_CON1_SPI0SCLK (0x0 << 2 ) /* SPI0SCLK */ -#define GP2CON_CON1_GPIO (0x1 << 2 ) /* GPIO */ - -/* GP2CON[CON0] - Configuration bits for P2.0 */ -#define GP2CON_CON0_MSK (0x3 << 0 ) -#define GP2CON_CON0_SPI0MISO (0x0 << 0 ) /* SPI0MISO */ -#define GP2CON_CON0_GPIO (0x1 << 0 ) /* GPIO */ - -/* Reset Value for GP2OEN*/ -#define GP2OEN_RVAL 0x0 - -/* GP2OEN[OEN7] - Port pin direction. */ -#define GP2OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C0C9C) -#define GP2OEN_OEN7_MSK (0x1 << 7 ) -#define GP2OEN_OEN7 (0x1 << 7 ) -#define GP2OEN_OEN7_IN (0x0 << 7 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP2OEN_OEN7_OUT (0x1 << 7 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP2OEN[OEN6] - Port pin direction. */ -#define GP2OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0C98) -#define GP2OEN_OEN6_MSK (0x1 << 6 ) -#define GP2OEN_OEN6 (0x1 << 6 ) -#define GP2OEN_OEN6_IN (0x0 << 6 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP2OEN_OEN6_OUT (0x1 << 6 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP2OEN[OEN5] - Port pin direction. */ -#define GP2OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0C94) -#define GP2OEN_OEN5_MSK (0x1 << 5 ) -#define GP2OEN_OEN5 (0x1 << 5 ) -#define GP2OEN_OEN5_IN (0x0 << 5 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP2OEN_OEN5_OUT (0x1 << 5 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP2OEN[OEN4] - Port pin direction. */ -#define GP2OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0C90) -#define GP2OEN_OEN4_MSK (0x1 << 4 ) -#define GP2OEN_OEN4 (0x1 << 4 ) -#define GP2OEN_OEN4_IN (0x0 << 4 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP2OEN_OEN4_OUT (0x1 << 4 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP2OEN[OEN3] - Port pin direction. */ -#define GP2OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C0C8C) -#define GP2OEN_OEN3_MSK (0x1 << 3 ) -#define GP2OEN_OEN3 (0x1 << 3 ) -#define GP2OEN_OEN3_IN (0x0 << 3 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP2OEN_OEN3_OUT (0x1 << 3 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP2OEN[OEN2] - Port pin direction. */ -#define GP2OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0C88) -#define GP2OEN_OEN2_MSK (0x1 << 2 ) -#define GP2OEN_OEN2 (0x1 << 2 ) -#define GP2OEN_OEN2_IN (0x0 << 2 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP2OEN_OEN2_OUT (0x1 << 2 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP2OEN[OEN1] - Port pin direction. */ -#define GP2OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0C84) -#define GP2OEN_OEN1_MSK (0x1 << 1 ) -#define GP2OEN_OEN1 (0x1 << 1 ) -#define GP2OEN_OEN1_IN (0x0 << 1 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP2OEN_OEN1_OUT (0x1 << 1 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP2OEN[OEN0] - Port pin direction. */ -#define GP2OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0C80) -#define GP2OEN_OEN0_MSK (0x1 << 0 ) -#define GP2OEN_OEN0 (0x1 << 0 ) -#define GP2OEN_OEN0_IN (0x0 << 0 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP2OEN_OEN0_OUT (0x1 << 0 ) /* OUT. Enables the output on corresponding port pin. */ - -/* Reset Value for GP2PUL*/ -#define GP2PUL_RVAL 0xFF - -/* GP2PUL[PUL7] - Pull Up Enable for port pin. */ -#define GP2PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C0D1C) -#define GP2PUL_PUL7_MSK (0x1 << 7 ) -#define GP2PUL_PUL7 (0x1 << 7 ) -#define GP2PUL_PUL7_DIS (0x0 << 7 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP2PUL_PUL7_EN (0x1 << 7 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP2PUL[PUL6] - Pull Up Enable for port pin. */ -#define GP2PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0D18) -#define GP2PUL_PUL6_MSK (0x1 << 6 ) -#define GP2PUL_PUL6 (0x1 << 6 ) -#define GP2PUL_PUL6_DIS (0x0 << 6 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP2PUL_PUL6_EN (0x1 << 6 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP2PUL[PUL5] - Pull Up Enable for port pin. */ -#define GP2PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0D14) -#define GP2PUL_PUL5_MSK (0x1 << 5 ) -#define GP2PUL_PUL5 (0x1 << 5 ) -#define GP2PUL_PUL5_DIS (0x0 << 5 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP2PUL_PUL5_EN (0x1 << 5 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP2PUL[PUL4] - Pull Up Enable for port pin. */ -#define GP2PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0D10) -#define GP2PUL_PUL4_MSK (0x1 << 4 ) -#define GP2PUL_PUL4 (0x1 << 4 ) -#define GP2PUL_PUL4_DIS (0x0 << 4 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP2PUL_PUL4_EN (0x1 << 4 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP2PUL[PUL3] - Pull Up Enable for port pin. */ -#define GP2PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C0D0C) -#define GP2PUL_PUL3_MSK (0x1 << 3 ) -#define GP2PUL_PUL3 (0x1 << 3 ) -#define GP2PUL_PUL3_DIS (0x0 << 3 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP2PUL_PUL3_EN (0x1 << 3 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP2PUL[PUL2] - Pull Up Enable for port pin. */ -#define GP2PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0D08) -#define GP2PUL_PUL2_MSK (0x1 << 2 ) -#define GP2PUL_PUL2 (0x1 << 2 ) -#define GP2PUL_PUL2_DIS (0x0 << 2 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP2PUL_PUL2_EN (0x1 << 2 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP2PUL[PUL1] - Pull Up Enable for port pin. */ -#define GP2PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0D04) -#define GP2PUL_PUL1_MSK (0x1 << 1 ) -#define GP2PUL_PUL1 (0x1 << 1 ) -#define GP2PUL_PUL1_DIS (0x0 << 1 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP2PUL_PUL1_EN (0x1 << 1 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP2PUL[PUL0] - Pull Up Enable for port pin. */ -#define GP2PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0D00) -#define GP2PUL_PUL0_MSK (0x1 << 0 ) -#define GP2PUL_PUL0 (0x1 << 0 ) -#define GP2PUL_PUL0_DIS (0x0 << 0 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP2PUL_PUL0_EN (0x1 << 0 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* Reset Value for GP2OCE*/ -#define GP2OCE_RVAL 0x0 - -/* GP2OCE[OCE7] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP2OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C0D9C) -#define GP2OCE_OCE7_MSK (0x1 << 7 ) -#define GP2OCE_OCE7 (0x1 << 7 ) -#define GP2OCE_OCE7_DIS (0x0 << 7 ) /* DIS */ -#define GP2OCE_OCE7_EN (0x1 << 7 ) /* EN */ - -/* GP2OCE[OCE6] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP2OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0D98) -#define GP2OCE_OCE6_MSK (0x1 << 6 ) -#define GP2OCE_OCE6 (0x1 << 6 ) -#define GP2OCE_OCE6_DIS (0x0 << 6 ) /* DIS */ -#define GP2OCE_OCE6_EN (0x1 << 6 ) /* EN */ - -/* GP2OCE[OCE5] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP2OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0D94) -#define GP2OCE_OCE5_MSK (0x1 << 5 ) -#define GP2OCE_OCE5 (0x1 << 5 ) -#define GP2OCE_OCE5_DIS (0x0 << 5 ) /* DIS */ -#define GP2OCE_OCE5_EN (0x1 << 5 ) /* EN */ - -/* GP2OCE[OCE4] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP2OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0D90) -#define GP2OCE_OCE4_MSK (0x1 << 4 ) -#define GP2OCE_OCE4 (0x1 << 4 ) -#define GP2OCE_OCE4_DIS (0x0 << 4 ) /* DIS */ -#define GP2OCE_OCE4_EN (0x1 << 4 ) /* EN */ - -/* GP2OCE[OCE3] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP2OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C0D8C) -#define GP2OCE_OCE3_MSK (0x1 << 3 ) -#define GP2OCE_OCE3 (0x1 << 3 ) -#define GP2OCE_OCE3_DIS (0x0 << 3 ) /* DIS */ -#define GP2OCE_OCE3_EN (0x1 << 3 ) /* EN */ - -/* GP2OCE[OCE2] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP2OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0D88) -#define GP2OCE_OCE2_MSK (0x1 << 2 ) -#define GP2OCE_OCE2 (0x1 << 2 ) -#define GP2OCE_OCE2_DIS (0x0 << 2 ) /* DIS */ -#define GP2OCE_OCE2_EN (0x1 << 2 ) /* EN */ - -/* GP2OCE[OCE1] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP2OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0D84) -#define GP2OCE_OCE1_MSK (0x1 << 1 ) -#define GP2OCE_OCE1 (0x1 << 1 ) -#define GP2OCE_OCE1_DIS (0x0 << 1 ) /* DIS */ -#define GP2OCE_OCE1_EN (0x1 << 1 ) /* EN */ - -/* GP2OCE[OCE0] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP2OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0D80) -#define GP2OCE_OCE0_MSK (0x1 << 0 ) -#define GP2OCE_OCE0 (0x1 << 0 ) -#define GP2OCE_OCE0_DIS (0x0 << 0 ) /* DIS */ -#define GP2OCE_OCE0_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for GP2IN*/ -#define GP2IN_RVAL 0xFF - -/* GP2IN[IN7] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP2IN_IN7_BBA (*(volatile unsigned long *) 0x420C0E9C) -#define GP2IN_IN7_MSK (0x1 << 7 ) -#define GP2IN_IN7 (0x1 << 7 ) -#define GP2IN_IN7_LOW (0x0 << 7 ) /* LOW */ -#define GP2IN_IN7_HIGH (0x1 << 7 ) /* HIGH */ - -/* GP2IN[IN6] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP2IN_IN6_BBA (*(volatile unsigned long *) 0x420C0E98) -#define GP2IN_IN6_MSK (0x1 << 6 ) -#define GP2IN_IN6 (0x1 << 6 ) -#define GP2IN_IN6_LOW (0x0 << 6 ) /* LOW */ -#define GP2IN_IN6_HIGH (0x1 << 6 ) /* HIGH */ - -/* GP2IN[IN5] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP2IN_IN5_BBA (*(volatile unsigned long *) 0x420C0E94) -#define GP2IN_IN5_MSK (0x1 << 5 ) -#define GP2IN_IN5 (0x1 << 5 ) -#define GP2IN_IN5_LOW (0x0 << 5 ) /* LOW */ -#define GP2IN_IN5_HIGH (0x1 << 5 ) /* HIGH */ - -/* GP2IN[IN4] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP2IN_IN4_BBA (*(volatile unsigned long *) 0x420C0E90) -#define GP2IN_IN4_MSK (0x1 << 4 ) -#define GP2IN_IN4 (0x1 << 4 ) -#define GP2IN_IN4_LOW (0x0 << 4 ) /* LOW */ -#define GP2IN_IN4_HIGH (0x1 << 4 ) /* HIGH */ - -/* GP2IN[IN3] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP2IN_IN3_BBA (*(volatile unsigned long *) 0x420C0E8C) -#define GP2IN_IN3_MSK (0x1 << 3 ) -#define GP2IN_IN3 (0x1 << 3 ) -#define GP2IN_IN3_LOW (0x0 << 3 ) /* LOW */ -#define GP2IN_IN3_HIGH (0x1 << 3 ) /* HIGH */ - -/* GP2IN[IN2] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP2IN_IN2_BBA (*(volatile unsigned long *) 0x420C0E88) -#define GP2IN_IN2_MSK (0x1 << 2 ) -#define GP2IN_IN2 (0x1 << 2 ) -#define GP2IN_IN2_LOW (0x0 << 2 ) /* LOW */ -#define GP2IN_IN2_HIGH (0x1 << 2 ) /* HIGH */ - -/* GP2IN[IN1] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP2IN_IN1_BBA (*(volatile unsigned long *) 0x420C0E84) -#define GP2IN_IN1_MSK (0x1 << 1 ) -#define GP2IN_IN1 (0x1 << 1 ) -#define GP2IN_IN1_LOW (0x0 << 1 ) /* LOW */ -#define GP2IN_IN1_HIGH (0x1 << 1 ) /* HIGH */ - -/* GP2IN[IN0] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP2IN_IN0_BBA (*(volatile unsigned long *) 0x420C0E80) -#define GP2IN_IN0_MSK (0x1 << 0 ) -#define GP2IN_IN0 (0x1 << 0 ) -#define GP2IN_IN0_LOW (0x0 << 0 ) /* LOW */ -#define GP2IN_IN0_HIGH (0x1 << 0 ) /* HIGH */ - -/* Reset Value for GP2OUT*/ -#define GP2OUT_RVAL 0x0 - -/* GP2OUT[OUT7] - Output for port pin. */ -#define GP2OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C0F1C) -#define GP2OUT_OUT7_MSK (0x1 << 7 ) -#define GP2OUT_OUT7 (0x1 << 7 ) -#define GP2OUT_OUT7_LOW (0x0 << 7 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP2OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP2OUT[OUT6] - Output for port pin. */ -#define GP2OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0F18) -#define GP2OUT_OUT6_MSK (0x1 << 6 ) -#define GP2OUT_OUT6 (0x1 << 6 ) -#define GP2OUT_OUT6_LOW (0x0 << 6 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP2OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP2OUT[OUT5] - Output for port pin. */ -#define GP2OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0F14) -#define GP2OUT_OUT5_MSK (0x1 << 5 ) -#define GP2OUT_OUT5 (0x1 << 5 ) -#define GP2OUT_OUT5_LOW (0x0 << 5 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP2OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP2OUT[OUT4] - Output for port pin. */ -#define GP2OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0F10) -#define GP2OUT_OUT4_MSK (0x1 << 4 ) -#define GP2OUT_OUT4 (0x1 << 4 ) -#define GP2OUT_OUT4_LOW (0x0 << 4 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP2OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP2OUT[OUT3] - Output for port pin. */ -#define GP2OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C0F0C) -#define GP2OUT_OUT3_MSK (0x1 << 3 ) -#define GP2OUT_OUT3 (0x1 << 3 ) -#define GP2OUT_OUT3_LOW (0x0 << 3 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP2OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP2OUT[OUT2] - Output for port pin. */ -#define GP2OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0F08) -#define GP2OUT_OUT2_MSK (0x1 << 2 ) -#define GP2OUT_OUT2 (0x1 << 2 ) -#define GP2OUT_OUT2_LOW (0x0 << 2 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP2OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP2OUT[OUT1] - Output for port pin. */ -#define GP2OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0F04) -#define GP2OUT_OUT1_MSK (0x1 << 1 ) -#define GP2OUT_OUT1 (0x1 << 1 ) -#define GP2OUT_OUT1_LOW (0x0 << 1 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP2OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP2OUT[OUT0] - Output for port pin. */ -#define GP2OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0F00) -#define GP2OUT_OUT0_MSK (0x1 << 0 ) -#define GP2OUT_OUT0 (0x1 << 0 ) -#define GP2OUT_OUT0_LOW (0x0 << 0 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP2OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* Reset Value for GP2SET*/ -#define GP2SET_RVAL 0x0 - -/* GP2SET[SET7] - Set output high for corresponding port pin. */ -#define GP2SET_SET7_BBA (*(volatile unsigned long *) 0x420C0F9C) -#define GP2SET_SET7_MSK (0x1 << 7 ) -#define GP2SET_SET7 (0x1 << 7 ) -#define GP2SET_SET7_SET (0x1 << 7 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP2SET[SET6] - Set output high for corresponding port pin. */ -#define GP2SET_SET6_BBA (*(volatile unsigned long *) 0x420C0F98) -#define GP2SET_SET6_MSK (0x1 << 6 ) -#define GP2SET_SET6 (0x1 << 6 ) -#define GP2SET_SET6_SET (0x1 << 6 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP2SET[SET5] - Set output high for corresponding port pin. */ -#define GP2SET_SET5_BBA (*(volatile unsigned long *) 0x420C0F94) -#define GP2SET_SET5_MSK (0x1 << 5 ) -#define GP2SET_SET5 (0x1 << 5 ) -#define GP2SET_SET5_SET (0x1 << 5 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP2SET[SET4] - Set output high for corresponding port pin. */ -#define GP2SET_SET4_BBA (*(volatile unsigned long *) 0x420C0F90) -#define GP2SET_SET4_MSK (0x1 << 4 ) -#define GP2SET_SET4 (0x1 << 4 ) -#define GP2SET_SET4_SET (0x1 << 4 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP2SET[SET3] - Set output high for corresponding port pin. */ -#define GP2SET_SET3_BBA (*(volatile unsigned long *) 0x420C0F8C) -#define GP2SET_SET3_MSK (0x1 << 3 ) -#define GP2SET_SET3 (0x1 << 3 ) -#define GP2SET_SET3_SET (0x1 << 3 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP2SET[SET2] - Set output high for corresponding port pin. */ -#define GP2SET_SET2_BBA (*(volatile unsigned long *) 0x420C0F88) -#define GP2SET_SET2_MSK (0x1 << 2 ) -#define GP2SET_SET2 (0x1 << 2 ) -#define GP2SET_SET2_SET (0x1 << 2 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP2SET[SET1] - Set output high for corresponding port pin. */ -#define GP2SET_SET1_BBA (*(volatile unsigned long *) 0x420C0F84) -#define GP2SET_SET1_MSK (0x1 << 1 ) -#define GP2SET_SET1 (0x1 << 1 ) -#define GP2SET_SET1_SET (0x1 << 1 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP2SET[SET0] - Set output high for corresponding port pin. */ -#define GP2SET_SET0_BBA (*(volatile unsigned long *) 0x420C0F80) -#define GP2SET_SET0_MSK (0x1 << 0 ) -#define GP2SET_SET0 (0x1 << 0 ) -#define GP2SET_SET0_SET (0x1 << 0 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* Reset Value for GP2CLR*/ -#define GP2CLR_RVAL 0x0 - -/* GP2CLR[CLR7] - Set by user code to drive the corresponding GPIO low. */ -#define GP2CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C101C) -#define GP2CLR_CLR7_MSK (0x1 << 7 ) -#define GP2CLR_CLR7 (0x1 << 7 ) -#define GP2CLR_CLR7_CLR (0x1 << 7 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP2CLR[CLR6] - Set by user code to drive the corresponding GPIO low. */ -#define GP2CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C1018) -#define GP2CLR_CLR6_MSK (0x1 << 6 ) -#define GP2CLR_CLR6 (0x1 << 6 ) -#define GP2CLR_CLR6_CLR (0x1 << 6 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP2CLR[CLR5] - Set by user code to drive the corresponding GPIO low. */ -#define GP2CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C1014) -#define GP2CLR_CLR5_MSK (0x1 << 5 ) -#define GP2CLR_CLR5 (0x1 << 5 ) -#define GP2CLR_CLR5_CLR (0x1 << 5 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP2CLR[CLR4] - Set by user code to drive the corresponding GPIO low. */ -#define GP2CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C1010) -#define GP2CLR_CLR4_MSK (0x1 << 4 ) -#define GP2CLR_CLR4 (0x1 << 4 ) -#define GP2CLR_CLR4_CLR (0x1 << 4 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP2CLR[CLR3] - Set by user code to drive the corresponding GPIO low. */ -#define GP2CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C100C) -#define GP2CLR_CLR3_MSK (0x1 << 3 ) -#define GP2CLR_CLR3 (0x1 << 3 ) -#define GP2CLR_CLR3_CLR (0x1 << 3 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP2CLR[CLR2] - Set by user code to drive the corresponding GPIO low. */ -#define GP2CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C1008) -#define GP2CLR_CLR2_MSK (0x1 << 2 ) -#define GP2CLR_CLR2 (0x1 << 2 ) -#define GP2CLR_CLR2_CLR (0x1 << 2 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP2CLR[CLR1] - Set by user code to drive the corresponding GPIO low. */ -#define GP2CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C1004) -#define GP2CLR_CLR1_MSK (0x1 << 1 ) -#define GP2CLR_CLR1 (0x1 << 1 ) -#define GP2CLR_CLR1_CLR (0x1 << 1 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP2CLR[CLR0] - Set by user code to drive the corresponding GPIO low. */ -#define GP2CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C1000) -#define GP2CLR_CLR0_MSK (0x1 << 0 ) -#define GP2CLR_CLR0 (0x1 << 0 ) -#define GP2CLR_CLR0_CLR (0x1 << 0 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* Reset Value for GP2TGL*/ -#define GP2TGL_RVAL 0x0 - -/* GP2TGL[TGL7] - Toggle for corresponding port pin. */ -#define GP2TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C109C) -#define GP2TGL_TGL7_MSK (0x1 << 7 ) -#define GP2TGL_TGL7 (0x1 << 7 ) -#define GP2TGL_TGL7_TGL (0x1 << 7 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP2TGL[TGL6] - Toggle for corresponding port pin. */ -#define GP2TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C1098) -#define GP2TGL_TGL6_MSK (0x1 << 6 ) -#define GP2TGL_TGL6 (0x1 << 6 ) -#define GP2TGL_TGL6_TGL (0x1 << 6 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP2TGL[TGL5] - Toggle for corresponding port pin. */ -#define GP2TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C1094) -#define GP2TGL_TGL5_MSK (0x1 << 5 ) -#define GP2TGL_TGL5 (0x1 << 5 ) -#define GP2TGL_TGL5_TGL (0x1 << 5 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP2TGL[TGL4] - Toggle for corresponding port pin. */ -#define GP2TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C1090) -#define GP2TGL_TGL4_MSK (0x1 << 4 ) -#define GP2TGL_TGL4 (0x1 << 4 ) -#define GP2TGL_TGL4_TGL (0x1 << 4 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP2TGL[TGL3] - Toggle for corresponding port pin. */ -#define GP2TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C108C) -#define GP2TGL_TGL3_MSK (0x1 << 3 ) -#define GP2TGL_TGL3 (0x1 << 3 ) -#define GP2TGL_TGL3_TGL (0x1 << 3 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP2TGL[TGL2] - Toggle for corresponding port pin. */ -#define GP2TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C1088) -#define GP2TGL_TGL2_MSK (0x1 << 2 ) -#define GP2TGL_TGL2 (0x1 << 2 ) -#define GP2TGL_TGL2_TGL (0x1 << 2 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP2TGL[TGL1] - Toggle for corresponding port pin. */ -#define GP2TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C1084) -#define GP2TGL_TGL1_MSK (0x1 << 1 ) -#define GP2TGL_TGL1 (0x1 << 1 ) -#define GP2TGL_TGL1_TGL (0x1 << 1 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP2TGL[TGL0] - Toggle for corresponding port pin. */ -#define GP2TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C1080) -#define GP2TGL_TGL0_MSK (0x1 << 0 ) -#define GP2TGL_TGL0 (0x1 << 0 ) -#define GP2TGL_TGL0_TGL (0x1 << 0 ) /* TGL. Set by user code to invert the corresponding GPIO. */ -#if (__NO_MMR_STRUCTS__==1) - -#define GP3CON (*(volatile unsigned short int *) 0x40006090) -#define GP3OEN (*(volatile unsigned char *) 0x40006094) -#define GP3PUL (*(volatile unsigned char *) 0x40006098) -#define GP3OCE (*(volatile unsigned char *) 0x4000609C) -#define GP3IN (*(volatile unsigned char *) 0x400060A4) -#define GP3OUT (*(volatile unsigned char *) 0x400060A8) -#define GP3SET (*(volatile unsigned char *) 0x400060AC) -#define GP3CLR (*(volatile unsigned char *) 0x400060B0) -#define GP3TGL (*(volatile unsigned char *) 0x400060B4) -#endif // (__NO_MMR_STRUCTS__==1) - -/* Reset Value for GP3CON*/ -#define GP3CON_RVAL 0x0 - -/* GP3CON[CON7] - Configuration bits for P3.7 */ -#define GP3CON_CON7_MSK (0x3 << 14 ) -#define GP3CON_CON7_GPIOIRQ0 (0x1 << 14 ) /* GPIOIRQ0 */ - -/* GP3CON[CON6] - Configuration bits for P3.6 */ -#define GP3CON_CON6_MSK (0x3 << 12 ) -#define GP3CON_CON6_GPIO (0x1 << 12 ) /* GPIO */ - -/* GP3CON[CON5] - Configuration bits for P3.5 */ -#define GP3CON_CON5_MSK (0x3 << 10 ) -#define GP3CON_CON5_GPIO (0x1 << 10 ) /* GPIO */ -#define GP3CON_CON5_SPI0MOSI (0x3 << 10 ) /* SPI0MOSI */ - -/* GP3CON[CON4] - Configuration bits for P3.4 */ -#define GP3CON_CON4_MSK (0x3 << 8 ) -#define GP3CON_CON4_GPIO (0x1 << 8 ) /* GPIO */ - -/* GP3CON[CON3] - Configuration bits for P3.3 */ -#define GP3CON_CON3_MSK (0x3 << 6 ) -#define GP3CON_CON3_GPIO (0x1 << 6 ) /* GPIO */ -#define GP3CON_CON3_PWMTRIP (0x2 << 6 ) /* PWMTRIP */ -#define GP3CON_CON3_SPI0SCLK (0x3 << 6 ) /* SPI0SCLK */ - -/* GP3CON[CON2] - Configuration bits for P3.2 */ -#define GP3CON_CON2_MSK (0x3 << 4 ) -#define GP3CON_CON2_GPIO (0x1 << 4 ) /* GPIO */ -#define GP3CON_CON2_PWMSYNC (0x2 << 4 ) /* PWMSYNC */ -#define GP3CON_CON2_SPI0MISO (0x3 << 4 ) /* SPI0MISO */ - -/* GP3CON[CON1] - Configuration bits for P3.1 */ -#define GP3CON_CON1_MSK (0x3 << 2 ) -#define GP3CON_CON1_GPIO (0x0 << 2 ) /* GPIO */ - -/* GP3CON[CON0] - Configuration bits for P3.0 */ -#define GP3CON_CON0_MSK (0x3 << 0 ) -#define GP3CON_CON0_GPIO (0x0 << 0 ) /* GPIO */ -#define GP3CON_CON0_PWMTRIP (0x3 << 0 ) /* PWMTRIP */ - -/* Reset Value for GP3OEN*/ -#define GP3OEN_RVAL 0x0 - -/* GP3OEN[OEN7] - Port pin direction. */ -#define GP3OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C129C) -#define GP3OEN_OEN7_MSK (0x1 << 7 ) -#define GP3OEN_OEN7 (0x1 << 7 ) -#define GP3OEN_OEN7_IN (0x0 << 7 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP3OEN_OEN7_OUT (0x1 << 7 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP3OEN[OEN6] - Port pin direction. */ -#define GP3OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C1298) -#define GP3OEN_OEN6_MSK (0x1 << 6 ) -#define GP3OEN_OEN6 (0x1 << 6 ) -#define GP3OEN_OEN6_IN (0x0 << 6 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP3OEN_OEN6_OUT (0x1 << 6 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP3OEN[OEN5] - Port pin direction. */ -#define GP3OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C1294) -#define GP3OEN_OEN5_MSK (0x1 << 5 ) -#define GP3OEN_OEN5 (0x1 << 5 ) -#define GP3OEN_OEN5_IN (0x0 << 5 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP3OEN_OEN5_OUT (0x1 << 5 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP3OEN[OEN4] - Port pin direction. */ -#define GP3OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C1290) -#define GP3OEN_OEN4_MSK (0x1 << 4 ) -#define GP3OEN_OEN4 (0x1 << 4 ) -#define GP3OEN_OEN4_IN (0x0 << 4 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP3OEN_OEN4_OUT (0x1 << 4 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP3OEN[OEN3] - Port pin direction. */ -#define GP3OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C128C) -#define GP3OEN_OEN3_MSK (0x1 << 3 ) -#define GP3OEN_OEN3 (0x1 << 3 ) -#define GP3OEN_OEN3_IN (0x0 << 3 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP3OEN_OEN3_OUT (0x1 << 3 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP3OEN[OEN2] - Port pin direction. */ -#define GP3OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C1288) -#define GP3OEN_OEN2_MSK (0x1 << 2 ) -#define GP3OEN_OEN2 (0x1 << 2 ) -#define GP3OEN_OEN2_IN (0x0 << 2 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP3OEN_OEN2_OUT (0x1 << 2 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP3OEN[OEN1] - Port pin direction. */ -#define GP3OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C1284) -#define GP3OEN_OEN1_MSK (0x1 << 1 ) -#define GP3OEN_OEN1 (0x1 << 1 ) -#define GP3OEN_OEN1_IN (0x0 << 1 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP3OEN_OEN1_OUT (0x1 << 1 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP3OEN[OEN0] - Port pin direction. */ -#define GP3OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C1280) -#define GP3OEN_OEN0_MSK (0x1 << 0 ) -#define GP3OEN_OEN0 (0x1 << 0 ) -#define GP3OEN_OEN0_IN (0x0 << 0 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP3OEN_OEN0_OUT (0x1 << 0 ) /* OUT. Enables the output on corresponding port pin. */ - -/* Reset Value for GP3PUL*/ -#define GP3PUL_RVAL 0xFF - -/* GP3PUL[PUL7] - Pull Up Enable for port pin. */ -#define GP3PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C131C) -#define GP3PUL_PUL7_MSK (0x1 << 7 ) -#define GP3PUL_PUL7 (0x1 << 7 ) -#define GP3PUL_PUL7_DIS (0x0 << 7 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP3PUL_PUL7_EN (0x1 << 7 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP3PUL[PUL6] - Pull Up Enable for port pin. */ -#define GP3PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C1318) -#define GP3PUL_PUL6_MSK (0x1 << 6 ) -#define GP3PUL_PUL6 (0x1 << 6 ) -#define GP3PUL_PUL6_DIS (0x0 << 6 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP3PUL_PUL6_EN (0x1 << 6 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP3PUL[PUL5] - Pull Up Enable for port pin. */ -#define GP3PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C1314) -#define GP3PUL_PUL5_MSK (0x1 << 5 ) -#define GP3PUL_PUL5 (0x1 << 5 ) -#define GP3PUL_PUL5_DIS (0x0 << 5 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP3PUL_PUL5_EN (0x1 << 5 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP3PUL[PUL4] - Pull Up Enable for port pin. */ -#define GP3PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C1310) -#define GP3PUL_PUL4_MSK (0x1 << 4 ) -#define GP3PUL_PUL4 (0x1 << 4 ) -#define GP3PUL_PUL4_DIS (0x0 << 4 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP3PUL_PUL4_EN (0x1 << 4 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP3PUL[PUL3] - Pull Up Enable for port pin. */ -#define GP3PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C130C) -#define GP3PUL_PUL3_MSK (0x1 << 3 ) -#define GP3PUL_PUL3 (0x1 << 3 ) -#define GP3PUL_PUL3_DIS (0x0 << 3 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP3PUL_PUL3_EN (0x1 << 3 ) /* EN. Enables the internal pull up oncorresponding port pin. */ - -/* GP3PUL[PUL2] - Pull Up Enable for port pin. */ -#define GP3PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C1308) -#define GP3PUL_PUL2_MSK (0x1 << 2 ) -#define GP3PUL_PUL2 (0x1 << 2 ) -#define GP3PUL_PUL2_DIS (0x0 << 2 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP3PUL_PUL2_EN (0x1 << 2 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP3PUL[PUL1] - Pull Up Enable for port pin. */ -#define GP3PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C1304) -#define GP3PUL_PUL1_MSK (0x1 << 1 ) -#define GP3PUL_PUL1 (0x1 << 1 ) -#define GP3PUL_PUL1_DIS (0x0 << 1 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP3PUL_PUL1_EN (0x1 << 1 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP3PUL[PUL0] - Pull Up Enable for port pin. */ -#define GP3PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C1300) -#define GP3PUL_PUL0_MSK (0x1 << 0 ) -#define GP3PUL_PUL0 (0x1 << 0 ) -#define GP3PUL_PUL0_DIS (0x0 << 0 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP3PUL_PUL0_EN (0x1 << 0 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* Reset Value for GP3OCE*/ -#define GP3OCE_RVAL 0x0 - -/* GP3OCE[OCE7] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP3OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C139C) -#define GP3OCE_OCE7_MSK (0x1 << 7 ) -#define GP3OCE_OCE7 (0x1 << 7 ) -#define GP3OCE_OCE7_DIS (0x0 << 7 ) /* DIS */ -#define GP3OCE_OCE7_EN (0x1 << 7 ) /* EN */ - -/* GP3OCE[OCE6] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP3OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C1398) -#define GP3OCE_OCE6_MSK (0x1 << 6 ) -#define GP3OCE_OCE6 (0x1 << 6 ) -#define GP3OCE_OCE6_DIS (0x0 << 6 ) /* DIS */ -#define GP3OCE_OCE6_EN (0x1 << 6 ) /* EN */ - -/* GP3OCE[OCE5] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP3OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C1394) -#define GP3OCE_OCE5_MSK (0x1 << 5 ) -#define GP3OCE_OCE5 (0x1 << 5 ) -#define GP3OCE_OCE5_DIS (0x0 << 5 ) /* DIS */ -#define GP3OCE_OCE5_EN (0x1 << 5 ) /* EN */ - -/* GP3OCE[OCE4] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP3OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C1390) -#define GP3OCE_OCE4_MSK (0x1 << 4 ) -#define GP3OCE_OCE4 (0x1 << 4 ) -#define GP3OCE_OCE4_DIS (0x0 << 4 ) /* DIS */ -#define GP3OCE_OCE4_EN (0x1 << 4 ) /* EN */ - -/* GP3OCE[OCE3] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP3OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C138C) -#define GP3OCE_OCE3_MSK (0x1 << 3 ) -#define GP3OCE_OCE3 (0x1 << 3 ) -#define GP3OCE_OCE3_DIS (0x0 << 3 ) /* DIS */ -#define GP3OCE_OCE3_EN (0x1 << 3 ) /* EN */ - -/* GP3OCE[OCE2] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP3OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C1388) -#define GP3OCE_OCE2_MSK (0x1 << 2 ) -#define GP3OCE_OCE2 (0x1 << 2 ) -#define GP3OCE_OCE2_DIS (0x0 << 2 ) /* DIS */ -#define GP3OCE_OCE2_EN (0x1 << 2 ) /* EN */ - -/* GP3OCE[OCE1] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP3OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C1384) -#define GP3OCE_OCE1_MSK (0x1 << 1 ) -#define GP3OCE_OCE1 (0x1 << 1 ) -#define GP3OCE_OCE1_DIS (0x0 << 1 ) /* DIS */ -#define GP3OCE_OCE1_EN (0x1 << 1 ) /* EN */ - -/* GP3OCE[OCE0] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP3OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C1380) -#define GP3OCE_OCE0_MSK (0x1 << 0 ) -#define GP3OCE_OCE0 (0x1 << 0 ) -#define GP3OCE_OCE0_DIS (0x0 << 0 ) /* DIS */ -#define GP3OCE_OCE0_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for GP3IN*/ -#define GP3IN_RVAL 0xFF - -/* GP3IN[IN7] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP3IN_IN7_BBA (*(volatile unsigned long *) 0x420C149C) -#define GP3IN_IN7_MSK (0x1 << 7 ) -#define GP3IN_IN7 (0x1 << 7 ) -#define GP3IN_IN7_LOW (0x0 << 7 ) /* LOW */ -#define GP3IN_IN7_HIGH (0x1 << 7 ) /* HIGH */ - -/* GP3IN[IN6] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP3IN_IN6_BBA (*(volatile unsigned long *) 0x420C1498) -#define GP3IN_IN6_MSK (0x1 << 6 ) -#define GP3IN_IN6 (0x1 << 6 ) -#define GP3IN_IN6_LOW (0x0 << 6 ) /* LOW */ -#define GP3IN_IN6_HIGH (0x1 << 6 ) /* HIGH */ - -/* GP3IN[IN5] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP3IN_IN5_BBA (*(volatile unsigned long *) 0x420C1494) -#define GP3IN_IN5_MSK (0x1 << 5 ) -#define GP3IN_IN5 (0x1 << 5 ) -#define GP3IN_IN5_LOW (0x0 << 5 ) /* LOW */ -#define GP3IN_IN5_HIGH (0x1 << 5 ) /* HIGH */ - -/* GP3IN[IN4] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP3IN_IN4_BBA (*(volatile unsigned long *) 0x420C1490) -#define GP3IN_IN4_MSK (0x1 << 4 ) -#define GP3IN_IN4 (0x1 << 4 ) -#define GP3IN_IN4_LOW (0x0 << 4 ) /* LOW */ -#define GP3IN_IN4_HIGH (0x1 << 4 ) /* HIGH */ - -/* GP3IN[IN3] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP3IN_IN3_BBA (*(volatile unsigned long *) 0x420C148C) -#define GP3IN_IN3_MSK (0x1 << 3 ) -#define GP3IN_IN3 (0x1 << 3 ) -#define GP3IN_IN3_LOW (0x0 << 3 ) /* LOW */ -#define GP3IN_IN3_HIGH (0x1 << 3 ) /* HIGH */ - -/* GP3IN[IN2] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP3IN_IN2_BBA (*(volatile unsigned long *) 0x420C1488) -#define GP3IN_IN2_MSK (0x1 << 2 ) -#define GP3IN_IN2 (0x1 << 2 ) -#define GP3IN_IN2_LOW (0x0 << 2 ) /* LOW */ -#define GP3IN_IN2_HIGH (0x1 << 2 ) /* HIGH */ - -/* GP3IN[IN1] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP3IN_IN1_BBA (*(volatile unsigned long *) 0x420C1484) -#define GP3IN_IN1_MSK (0x1 << 1 ) -#define GP3IN_IN1 (0x1 << 1 ) -#define GP3IN_IN1_LOW (0x0 << 1 ) /* LOW */ -#define GP3IN_IN1_HIGH (0x1 << 1 ) /* HIGH */ - -/* GP3IN[IN0] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP3IN_IN0_BBA (*(volatile unsigned long *) 0x420C1480) -#define GP3IN_IN0_MSK (0x1 << 0 ) -#define GP3IN_IN0 (0x1 << 0 ) -#define GP3IN_IN0_LOW (0x0 << 0 ) /* LOW */ -#define GP3IN_IN0_HIGH (0x1 << 0 ) /* HIGH */ - -/* Reset Value for GP3OUT*/ -#define GP3OUT_RVAL 0x0 - -/* GP3OUT[OUT7] - Output for port pin. */ -#define GP3OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C151C) -#define GP3OUT_OUT7_MSK (0x1 << 7 ) -#define GP3OUT_OUT7 (0x1 << 7 ) -#define GP3OUT_OUT7_LOW (0x0 << 7 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP3OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP3OUT[OUT6] - Output for port pin. */ -#define GP3OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C1518) -#define GP3OUT_OUT6_MSK (0x1 << 6 ) -#define GP3OUT_OUT6 (0x1 << 6 ) -#define GP3OUT_OUT6_LOW (0x0 << 6 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP3OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP3OUT[OUT5] - Output for port pin. */ -#define GP3OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C1514) -#define GP3OUT_OUT5_MSK (0x1 << 5 ) -#define GP3OUT_OUT5 (0x1 << 5 ) -#define GP3OUT_OUT5_LOW (0x0 << 5 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP3OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP3OUT[OUT4] - Output for port pin. */ -#define GP3OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C1510) -#define GP3OUT_OUT4_MSK (0x1 << 4 ) -#define GP3OUT_OUT4 (0x1 << 4 ) -#define GP3OUT_OUT4_LOW (0x0 << 4 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP3OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP3OUT[OUT3] - Output for port pin. */ -#define GP3OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C150C) -#define GP3OUT_OUT3_MSK (0x1 << 3 ) -#define GP3OUT_OUT3 (0x1 << 3 ) -#define GP3OUT_OUT3_LOW (0x0 << 3 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP3OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP3OUT[OUT2] - Output for port pin. */ -#define GP3OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C1508) -#define GP3OUT_OUT2_MSK (0x1 << 2 ) -#define GP3OUT_OUT2 (0x1 << 2 ) -#define GP3OUT_OUT2_LOW (0x0 << 2 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP3OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP3OUT[OUT1] - Output for port pin. */ -#define GP3OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C1504) -#define GP3OUT_OUT1_MSK (0x1 << 1 ) -#define GP3OUT_OUT1 (0x1 << 1 ) -#define GP3OUT_OUT1_LOW (0x0 << 1 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP3OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP3OUT[OUT0] - Output for port pin. */ -#define GP3OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C1500) -#define GP3OUT_OUT0_MSK (0x1 << 0 ) -#define GP3OUT_OUT0 (0x1 << 0 ) -#define GP3OUT_OUT0_LOW (0x0 << 0 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP3OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* Reset Value for GP3SET*/ -#define GP3SET_RVAL 0x0 - -/* GP3SET[SET7] - Set output high for corresponding port pin. */ -#define GP3SET_SET7_BBA (*(volatile unsigned long *) 0x420C159C) -#define GP3SET_SET7_MSK (0x1 << 7 ) -#define GP3SET_SET7 (0x1 << 7 ) -#define GP3SET_SET7_SET (0x1 << 7 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP3SET[SET6] - Set output high for corresponding port pin. */ -#define GP3SET_SET6_BBA (*(volatile unsigned long *) 0x420C1598) -#define GP3SET_SET6_MSK (0x1 << 6 ) -#define GP3SET_SET6 (0x1 << 6 ) -#define GP3SET_SET6_SET (0x1 << 6 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP3SET[SET5] - Set output high for corresponding port pin. */ -#define GP3SET_SET5_BBA (*(volatile unsigned long *) 0x420C1594) -#define GP3SET_SET5_MSK (0x1 << 5 ) -#define GP3SET_SET5 (0x1 << 5 ) -#define GP3SET_SET5_SET (0x1 << 5 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP3SET[SET4] - Set output high for corresponding port pin. */ -#define GP3SET_SET4_BBA (*(volatile unsigned long *) 0x420C1590) -#define GP3SET_SET4_MSK (0x1 << 4 ) -#define GP3SET_SET4 (0x1 << 4 ) -#define GP3SET_SET4_SET (0x1 << 4 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP3SET[SET3] - Set output high for corresponding port pin. */ -#define GP3SET_SET3_BBA (*(volatile unsigned long *) 0x420C158C) -#define GP3SET_SET3_MSK (0x1 << 3 ) -#define GP3SET_SET3 (0x1 << 3 ) -#define GP3SET_SET3_SET (0x1 << 3 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP3SET[SET2] - Set output high for corresponding port pin. */ -#define GP3SET_SET2_BBA (*(volatile unsigned long *) 0x420C1588) -#define GP3SET_SET2_MSK (0x1 << 2 ) -#define GP3SET_SET2 (0x1 << 2 ) -#define GP3SET_SET2_SET (0x1 << 2 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP3SET[SET1] - Set output high for corresponding port pin. */ -#define GP3SET_SET1_BBA (*(volatile unsigned long *) 0x420C1584) -#define GP3SET_SET1_MSK (0x1 << 1 ) -#define GP3SET_SET1 (0x1 << 1 ) -#define GP3SET_SET1_SET (0x1 << 1 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP3SET[SET0] - Set output high for corresponding port pin. */ -#define GP3SET_SET0_BBA (*(volatile unsigned long *) 0x420C1580) -#define GP3SET_SET0_MSK (0x1 << 0 ) -#define GP3SET_SET0 (0x1 << 0 ) -#define GP3SET_SET0_SET (0x1 << 0 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* Reset Value for GP3CLR*/ -#define GP3CLR_RVAL 0x0 - -/* GP3CLR[CLR7] - Set by user code to drive the corresponding GPIO low. */ -#define GP3CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C161C) -#define GP3CLR_CLR7_MSK (0x1 << 7 ) -#define GP3CLR_CLR7 (0x1 << 7 ) -#define GP3CLR_CLR7_CLR (0x1 << 7 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP3CLR[CLR6] - Set by user code to drive the corresponding GPIO low. */ -#define GP3CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C1618) -#define GP3CLR_CLR6_MSK (0x1 << 6 ) -#define GP3CLR_CLR6 (0x1 << 6 ) -#define GP3CLR_CLR6_CLR (0x1 << 6 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP3CLR[CLR5] - Set by user code to drive the corresponding GPIO low. */ -#define GP3CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C1614) -#define GP3CLR_CLR5_MSK (0x1 << 5 ) -#define GP3CLR_CLR5 (0x1 << 5 ) -#define GP3CLR_CLR5_CLR (0x1 << 5 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP3CLR[CLR4] - Set by user code to drive the corresponding GPIO low. */ -#define GP3CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C1610) -#define GP3CLR_CLR4_MSK (0x1 << 4 ) -#define GP3CLR_CLR4 (0x1 << 4 ) -#define GP3CLR_CLR4_CLR (0x1 << 4 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP3CLR[CLR3] - Set by user code to drive the corresponding GPIO low. */ -#define GP3CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C160C) -#define GP3CLR_CLR3_MSK (0x1 << 3 ) -#define GP3CLR_CLR3 (0x1 << 3 ) -#define GP3CLR_CLR3_CLR (0x1 << 3 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP3CLR[CLR2] - Set by user code to drive the corresponding GPIO low. */ -#define GP3CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C1608) -#define GP3CLR_CLR2_MSK (0x1 << 2 ) -#define GP3CLR_CLR2 (0x1 << 2 ) -#define GP3CLR_CLR2_CLR (0x1 << 2 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP3CLR[CLR1] - Set by user code to drive the corresponding GPIO low. */ -#define GP3CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C1604) -#define GP3CLR_CLR1_MSK (0x1 << 1 ) -#define GP3CLR_CLR1 (0x1 << 1 ) -#define GP3CLR_CLR1_CLR (0x1 << 1 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP3CLR[CLR0] - Set by user code to drive the corresponding GPIO low. */ -#define GP3CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C1600) -#define GP3CLR_CLR0_MSK (0x1 << 0 ) -#define GP3CLR_CLR0 (0x1 << 0 ) -#define GP3CLR_CLR0_CLR (0x1 << 0 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* Reset Value for GP3TGL*/ -#define GP3TGL_RVAL 0x0 - -/* GP3TGL[TGL7] - Toggle for corresponding port pin. */ -#define GP3TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C169C) -#define GP3TGL_TGL7_MSK (0x1 << 7 ) -#define GP3TGL_TGL7 (0x1 << 7 ) -#define GP3TGL_TGL7_TGL (0x1 << 7 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP3TGL[TGL6] - Toggle for corresponding port pin. */ -#define GP3TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C1698) -#define GP3TGL_TGL6_MSK (0x1 << 6 ) -#define GP3TGL_TGL6 (0x1 << 6 ) -#define GP3TGL_TGL6_TGL (0x1 << 6 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP3TGL[TGL5] - Toggle for corresponding port pin. */ -#define GP3TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C1694) -#define GP3TGL_TGL5_MSK (0x1 << 5 ) -#define GP3TGL_TGL5 (0x1 << 5 ) -#define GP3TGL_TGL5_TGL (0x1 << 5 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP3TGL[TGL4] - Toggle for corresponding port pin. */ -#define GP3TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C1690) -#define GP3TGL_TGL4_MSK (0x1 << 4 ) -#define GP3TGL_TGL4 (0x1 << 4 ) -#define GP3TGL_TGL4_TGL (0x1 << 4 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP3TGL[TGL3] - Toggle for corresponding port pin. */ -#define GP3TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C168C) -#define GP3TGL_TGL3_MSK (0x1 << 3 ) -#define GP3TGL_TGL3 (0x1 << 3 ) -#define GP3TGL_TGL3_TGL (0x1 << 3 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP3TGL[TGL2] - Toggle for corresponding port pin. */ -#define GP3TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C1688) -#define GP3TGL_TGL2_MSK (0x1 << 2 ) -#define GP3TGL_TGL2 (0x1 << 2 ) -#define GP3TGL_TGL2_TGL (0x1 << 2 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP3TGL[TGL1] - Toggle for corresponding port pin. */ -#define GP3TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C1684) -#define GP3TGL_TGL1_MSK (0x1 << 1 ) -#define GP3TGL_TGL1 (0x1 << 1 ) -#define GP3TGL_TGL1_TGL (0x1 << 1 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP3TGL[TGL0] - Toggle for corresponding port pin. */ -#define GP3TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C1680) -#define GP3TGL_TGL0_MSK (0x1 << 0 ) -#define GP3TGL_TGL0 (0x1 << 0 ) -#define GP3TGL_TGL0_TGL (0x1 << 0 ) /* TGL. Set by user code to invert the corresponding GPIO. */ -#if (__NO_MMR_STRUCTS__==1) - -#define GP4CON (*(volatile unsigned short int *) 0x400060C0) -#define GP4OEN (*(volatile unsigned char *) 0x400060C4) -#define GP4PUL (*(volatile unsigned char *) 0x400060C8) -#define GP4OCE (*(volatile unsigned char *) 0x400060CC) -#define GP4IN (*(volatile unsigned char *) 0x400060D4) -#define GP4OUT (*(volatile unsigned char *) 0x400060D8) -#define GP4SET (*(volatile unsigned char *) 0x400060DC) -#define GP4CLR (*(volatile unsigned char *) 0x400060E0) -#define GP4TGL (*(volatile unsigned char *) 0x400060E4) -#endif // (__NO_MMR_STRUCTS__==1) - -/* Reset Value for GP4CON*/ -#define GP4CON_RVAL 0x0 - -/* GP4CON[CON7] - Configuration bits for P4.7 */ -#define GP4CON_CON7_MSK (0x3 << 14 ) -#define GP4CON_CON7_GPIO (0x1 << 14 ) /* GPIO */ -#define GP4CON_CON7_PWM7 (0x2 << 14 ) /* PWM7 */ - -/* GP4CON[CON6] - Configuration bits for P4.6 */ -#define GP4CON_CON6_MSK (0x3 << 12 ) -#define GP4CON_CON6_GPIO (0x1 << 12 ) /* GPIO */ -#define GP4CON_CON6_PWM6 (0x2 << 12 ) /* PWM6 */ - -/* GP4CON[CON5] - Configuration bits for P4.5 */ -#define GP4CON_CON5_MSK (0x3 << 10 ) -#define GP4CON_CON5_GPIO (0x1 << 10 ) /* GPIO */ -#define GP4CON_CON5_PWM5 (0x2 << 10 ) /* PWM5 */ - -/* GP4CON[CON4] - Configuration bits for P4.4 */ -#define GP4CON_CON4_MSK (0x3 << 8 ) -#define GP4CON_CON4_GPIO (0x1 << 8 ) /* GPIO */ -#define GP4CON_CON4_PWM4 (0x2 << 8 ) /* PWM4 */ - -/* GP4CON[CON3] - Configuration bits for P4.3 */ -#define GP4CON_CON3_MSK (0x3 << 6 ) -#define GP4CON_CON3_GPIO (0x1 << 6 ) /* GPIO */ -#define GP4CON_CON3_PWM3 (0x2 << 6 ) /* PWM3 */ - -/* GP4CON[CON2] - Configuration bits for P4.2 */ -#define GP4CON_CON2_MSK (0x3 << 4 ) -#define GP4CON_CON2_GPIO (0x1 << 4 ) /* GPIO */ -#define GP4CON_CON2_PWM2 (0x2 << 4 ) /* PWM2 */ -#define GP4CON_CON2_SPI0CS (0x3 << 4 ) /* SPI0CS */ - -/* GP4CON[CON1] - Configuration bits for P4.1 */ -#define GP4CON_CON1_MSK (0x3 << 2 ) -#define GP4CON_CON1_GPIO (0x1 << 2 ) /* GPIO */ -#define GP4CON_CON1_PWM1 (0x2 << 2 ) /* PWM1 */ - -/* GP4CON[CON0] - Configuration bits for P4.0 */ -#define GP4CON_CON0_MSK (0x3 << 0 ) -#define GP4CON_CON0_GPIO (0x1 << 0 ) /* GPIO */ -#define GP4CON_CON0_PWM0 (0x2 << 0 ) /* PWM0 */ - -/* Reset Value for GP4OEN*/ -#define GP4OEN_RVAL 0x0 - -/* GP4OEN[OEN7] - Port pin direction. */ -#define GP4OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C189C) -#define GP4OEN_OEN7_MSK (0x1 << 7 ) -#define GP4OEN_OEN7 (0x1 << 7 ) -#define GP4OEN_OEN7_IN (0x0 << 7 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP4OEN_OEN7_OUT (0x1 << 7 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP4OEN[OEN6] - Port pin direction. */ -#define GP4OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C1898) -#define GP4OEN_OEN6_MSK (0x1 << 6 ) -#define GP4OEN_OEN6 (0x1 << 6 ) -#define GP4OEN_OEN6_IN (0x0 << 6 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP4OEN_OEN6_OUT (0x1 << 6 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP4OEN[OEN5] - Port pin direction. */ -#define GP4OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C1894) -#define GP4OEN_OEN5_MSK (0x1 << 5 ) -#define GP4OEN_OEN5 (0x1 << 5 ) -#define GP4OEN_OEN5_IN (0x0 << 5 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP4OEN_OEN5_OUT (0x1 << 5 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP4OEN[OEN4] - Port pin direction. */ -#define GP4OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C1890) -#define GP4OEN_OEN4_MSK (0x1 << 4 ) -#define GP4OEN_OEN4 (0x1 << 4 ) -#define GP4OEN_OEN4_IN (0x0 << 4 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP4OEN_OEN4_OUT (0x1 << 4 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP4OEN[OEN3] - Port pin direction. */ -#define GP4OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C188C) -#define GP4OEN_OEN3_MSK (0x1 << 3 ) -#define GP4OEN_OEN3 (0x1 << 3 ) -#define GP4OEN_OEN3_IN (0x0 << 3 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP4OEN_OEN3_OUT (0x1 << 3 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP4OEN[OEN2] - Port pin direction. */ -#define GP4OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C1888) -#define GP4OEN_OEN2_MSK (0x1 << 2 ) -#define GP4OEN_OEN2 (0x1 << 2 ) -#define GP4OEN_OEN2_IN (0x0 << 2 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP4OEN_OEN2_OUT (0x1 << 2 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP4OEN[OEN1] - Port pin direction. */ -#define GP4OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C1884) -#define GP4OEN_OEN1_MSK (0x1 << 1 ) -#define GP4OEN_OEN1 (0x1 << 1 ) -#define GP4OEN_OEN1_IN (0x0 << 1 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP4OEN_OEN1_OUT (0x1 << 1 ) /* OUT. Enables the output on corresponding port pin. */ - -/* GP4OEN[OEN0] - Port pin direction. */ -#define GP4OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C1880) -#define GP4OEN_OEN0_MSK (0x1 << 0 ) -#define GP4OEN_OEN0 (0x1 << 0 ) -#define GP4OEN_OEN0_IN (0x0 << 0 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ -#define GP4OEN_OEN0_OUT (0x1 << 0 ) /* OUT. Enables the output on corresponding port pin. */ - -/* Reset Value for GP4PUL*/ -#define GP4PUL_RVAL 0xFF - -/* GP4PUL[PUL7] - Pull Up Enable for port pin. */ -#define GP4PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C191C) -#define GP4PUL_PUL7_MSK (0x1 << 7 ) -#define GP4PUL_PUL7 (0x1 << 7 ) -#define GP4PUL_PUL7_DIS (0x0 << 7 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP4PUL_PUL7_EN (0x1 << 7 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP4PUL[PUL6] - Pull Up Enable for port pin. */ -#define GP4PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C1918) -#define GP4PUL_PUL6_MSK (0x1 << 6 ) -#define GP4PUL_PUL6 (0x1 << 6 ) -#define GP4PUL_PUL6_DIS (0x0 << 6 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP4PUL_PUL6_EN (0x1 << 6 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP4PUL[PUL5] - Pull Up Enable for port pin. */ -#define GP4PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C1914) -#define GP4PUL_PUL5_MSK (0x1 << 5 ) -#define GP4PUL_PUL5 (0x1 << 5 ) -#define GP4PUL_PUL5_DIS (0x0 << 5 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP4PUL_PUL5_EN (0x1 << 5 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP4PUL[PUL4] - Pull Up Enable for port pin. */ -#define GP4PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C1910) -#define GP4PUL_PUL4_MSK (0x1 << 4 ) -#define GP4PUL_PUL4 (0x1 << 4 ) -#define GP4PUL_PUL4_DIS (0x0 << 4 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP4PUL_PUL4_EN (0x1 << 4 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP4PUL[PUL3] - Pull Up Enable for port pin. */ -#define GP4PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C190C) -#define GP4PUL_PUL3_MSK (0x1 << 3 ) -#define GP4PUL_PUL3 (0x1 << 3 ) -#define GP4PUL_PUL3_DIS (0x0 << 3 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP4PUL_PUL3_EN (0x1 << 3 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP4PUL[PUL2] - Pull Up Enable for port pin. */ -#define GP4PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C1908) -#define GP4PUL_PUL2_MSK (0x1 << 2 ) -#define GP4PUL_PUL2 (0x1 << 2 ) -#define GP4PUL_PUL2_DIS (0x0 << 2 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP4PUL_PUL2_EN (0x1 << 2 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP4PUL[PUL1] - Pull Up Enable for port pin. */ -#define GP4PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C1904) -#define GP4PUL_PUL1_MSK (0x1 << 1 ) -#define GP4PUL_PUL1 (0x1 << 1 ) -#define GP4PUL_PUL1_DIS (0x0 << 1 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP4PUL_PUL1_EN (0x1 << 1 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* GP4PUL[PUL0] - Pull Up Enable for port pin. */ -#define GP4PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C1900) -#define GP4PUL_PUL0_MSK (0x1 << 0 ) -#define GP4PUL_PUL0 (0x1 << 0 ) -#define GP4PUL_PUL0_DIS (0x0 << 0 ) /* DIS. Disables the internal pull up on corresponding port pin. */ -#define GP4PUL_PUL0_EN (0x1 << 0 ) /* EN. Enables the internal pull up on corresponding port pin. */ - -/* Reset Value for GP4OCE*/ -#define GP4OCE_RVAL 0x0 - -/* GP4OCE[OCE7] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP4OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C199C) -#define GP4OCE_OCE7_MSK (0x1 << 7 ) -#define GP4OCE_OCE7 (0x1 << 7 ) -#define GP4OCE_OCE7_DIS (0x0 << 7 ) /* DIS */ -#define GP4OCE_OCE7_EN (0x1 << 7 ) /* EN */ - -/* GP4OCE[OCE6] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP4OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C1998) -#define GP4OCE_OCE6_MSK (0x1 << 6 ) -#define GP4OCE_OCE6 (0x1 << 6 ) -#define GP4OCE_OCE6_DIS (0x0 << 6 ) /* DIS */ -#define GP4OCE_OCE6_EN (0x1 << 6 ) /* EN */ - -/* GP4OCE[OCE5] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP4OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C1994) -#define GP4OCE_OCE5_MSK (0x1 << 5 ) -#define GP4OCE_OCE5 (0x1 << 5 ) -#define GP4OCE_OCE5_DIS (0x0 << 5 ) /* DIS */ -#define GP4OCE_OCE5_EN (0x1 << 5 ) /* EN */ - -/* GP4OCE[OCE4] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP4OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C1990) -#define GP4OCE_OCE4_MSK (0x1 << 4 ) -#define GP4OCE_OCE4 (0x1 << 4 ) -#define GP4OCE_OCE4_DIS (0x0 << 4 ) /* DIS */ -#define GP4OCE_OCE4_EN (0x1 << 4 ) /* EN */ - -/* GP4OCE[OCE3] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP4OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C198C) -#define GP4OCE_OCE3_MSK (0x1 << 3 ) -#define GP4OCE_OCE3 (0x1 << 3 ) -#define GP4OCE_OCE3_DIS (0x0 << 3 ) /* DIS */ -#define GP4OCE_OCE3_EN (0x1 << 3 ) /* EN */ - -/* GP4OCE[OCE2] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP4OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C1988) -#define GP4OCE_OCE2_MSK (0x1 << 2 ) -#define GP4OCE_OCE2 (0x1 << 2 ) -#define GP4OCE_OCE2_DIS (0x0 << 2 ) /* DIS */ -#define GP4OCE_OCE2_EN (0x1 << 2 ) /* EN */ - -/* GP4OCE[OCE1] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP4OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C1984) -#define GP4OCE_OCE1_MSK (0x1 << 1 ) -#define GP4OCE_OCE1 (0x1 << 1 ) -#define GP4OCE_OCE1_DIS (0x0 << 1 ) /* DIS */ -#define GP4OCE_OCE1_EN (0x1 << 1 ) /* EN */ - -/* GP4OCE[OCE0] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ -#define GP4OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C1980) -#define GP4OCE_OCE0_MSK (0x1 << 0 ) -#define GP4OCE_OCE0 (0x1 << 0 ) -#define GP4OCE_OCE0_DIS (0x0 << 0 ) /* DIS */ -#define GP4OCE_OCE0_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for GP4IN*/ -#define GP4IN_RVAL 0xFF - -/* GP4IN[IN7] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP4IN_IN7_BBA (*(volatile unsigned long *) 0x420C1A9C) -#define GP4IN_IN7_MSK (0x1 << 7 ) -#define GP4IN_IN7 (0x1 << 7 ) -#define GP4IN_IN7_LOW (0x0 << 7 ) /* LOW */ -#define GP4IN_IN7_HIGH (0x1 << 7 ) /* HIGH */ - -/* GP4IN[IN6] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP4IN_IN6_BBA (*(volatile unsigned long *) 0x420C1A98) -#define GP4IN_IN6_MSK (0x1 << 6 ) -#define GP4IN_IN6 (0x1 << 6 ) -#define GP4IN_IN6_LOW (0x0 << 6 ) /* LOW */ -#define GP4IN_IN6_HIGH (0x1 << 6 ) /* HIGH */ - -/* GP4IN[IN5] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP4IN_IN5_BBA (*(volatile unsigned long *) 0x420C1A94) -#define GP4IN_IN5_MSK (0x1 << 5 ) -#define GP4IN_IN5 (0x1 << 5 ) -#define GP4IN_IN5_LOW (0x0 << 5 ) /* LOW */ -#define GP4IN_IN5_HIGH (0x1 << 5 ) /* HIGH */ - -/* GP4IN[IN4] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP4IN_IN4_BBA (*(volatile unsigned long *) 0x420C1A90) -#define GP4IN_IN4_MSK (0x1 << 4 ) -#define GP4IN_IN4 (0x1 << 4 ) -#define GP4IN_IN4_LOW (0x0 << 4 ) /* LOW */ -#define GP4IN_IN4_HIGH (0x1 << 4 ) /* HIGH */ - -/* GP4IN[IN3] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP4IN_IN3_BBA (*(volatile unsigned long *) 0x420C1A8C) -#define GP4IN_IN3_MSK (0x1 << 3 ) -#define GP4IN_IN3 (0x1 << 3 ) -#define GP4IN_IN3_LOW (0x0 << 3 ) /* LOW */ -#define GP4IN_IN3_HIGH (0x1 << 3 ) /* HIGH */ - -/* GP4IN[IN2] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP4IN_IN2_BBA (*(volatile unsigned long *) 0x420C1A88) -#define GP4IN_IN2_MSK (0x1 << 2 ) -#define GP4IN_IN2 (0x1 << 2 ) -#define GP4IN_IN2_LOW (0x0 << 2 ) /* LOW */ -#define GP4IN_IN2_HIGH (0x1 << 2 ) /* HIGH */ - -/* GP4IN[IN1] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP4IN_IN1_BBA (*(volatile unsigned long *) 0x420C1A84) -#define GP4IN_IN1_MSK (0x1 << 1 ) -#define GP4IN_IN1 (0x1 << 1 ) -#define GP4IN_IN1_LOW (0x0 << 1 ) /* LOW */ -#define GP4IN_IN1_HIGH (0x1 << 1 ) /* HIGH */ - -/* GP4IN[IN0] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ -#define GP4IN_IN0_BBA (*(volatile unsigned long *) 0x420C1A80) -#define GP4IN_IN0_MSK (0x1 << 0 ) -#define GP4IN_IN0 (0x1 << 0 ) -#define GP4IN_IN0_LOW (0x0 << 0 ) /* LOW */ -#define GP4IN_IN0_HIGH (0x1 << 0 ) /* HIGH */ - -/* Reset Value for GP4OUT*/ -#define GP4OUT_RVAL 0x0 - -/* GP4OUT[OUT7] - Output for port pin. */ -#define GP4OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C1B1C) -#define GP4OUT_OUT7_MSK (0x1 << 7 ) -#define GP4OUT_OUT7 (0x1 << 7 ) -#define GP4OUT_OUT7_LOW (0x0 << 7 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP4OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP4OUT[OUT6] - Output for port pin. */ -#define GP4OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C1B18) -#define GP4OUT_OUT6_MSK (0x1 << 6 ) -#define GP4OUT_OUT6 (0x1 << 6 ) -#define GP4OUT_OUT6_LOW (0x0 << 6 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP4OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP4OUT[OUT5] - Output for port pin. */ -#define GP4OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C1B14) -#define GP4OUT_OUT5_MSK (0x1 << 5 ) -#define GP4OUT_OUT5 (0x1 << 5 ) -#define GP4OUT_OUT5_LOW (0x0 << 5 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP4OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP4OUT[OUT4] - Output for port pin. */ -#define GP4OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C1B10) -#define GP4OUT_OUT4_MSK (0x1 << 4 ) -#define GP4OUT_OUT4 (0x1 << 4 ) -#define GP4OUT_OUT4_LOW (0x0 << 4 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP4OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP4OUT[OUT3] - Output for port pin. */ -#define GP4OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C1B0C) -#define GP4OUT_OUT3_MSK (0x1 << 3 ) -#define GP4OUT_OUT3 (0x1 << 3 ) -#define GP4OUT_OUT3_LOW (0x0 << 3 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP4OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP4OUT[OUT2] - Output for port pin. */ -#define GP4OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C1B08) -#define GP4OUT_OUT2_MSK (0x1 << 2 ) -#define GP4OUT_OUT2 (0x1 << 2 ) -#define GP4OUT_OUT2_LOW (0x0 << 2 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP4OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP4OUT[OUT1] - Output for port pin. */ -#define GP4OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C1B04) -#define GP4OUT_OUT1_MSK (0x1 << 1 ) -#define GP4OUT_OUT1 (0x1 << 1 ) -#define GP4OUT_OUT1_LOW (0x0 << 1 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP4OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* GP4OUT[OUT0] - Output for port pin. */ -#define GP4OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C1B00) -#define GP4OUT_OUT0_MSK (0x1 << 0 ) -#define GP4OUT_OUT0 (0x1 << 0 ) -#define GP4OUT_OUT0_LOW (0x0 << 0 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ -#define GP4OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ - -/* Reset Value for GP4SET*/ -#define GP4SET_RVAL 0x0 - -/* GP4SET[SET7] - Set output high for corresponding port pin. */ -#define GP4SET_SET7_BBA (*(volatile unsigned long *) 0x420C1B9C) -#define GP4SET_SET7_MSK (0x1 << 7 ) -#define GP4SET_SET7 (0x1 << 7 ) -#define GP4SET_SET7_SET (0x1 << 7 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP4SET[SET6] - Set output high for corresponding port pin. */ -#define GP4SET_SET6_BBA (*(volatile unsigned long *) 0x420C1B98) -#define GP4SET_SET6_MSK (0x1 << 6 ) -#define GP4SET_SET6 (0x1 << 6 ) -#define GP4SET_SET6_SET (0x1 << 6 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP4SET[SET5] - Set output high for corresponding port pin. */ -#define GP4SET_SET5_BBA (*(volatile unsigned long *) 0x420C1B94) -#define GP4SET_SET5_MSK (0x1 << 5 ) -#define GP4SET_SET5 (0x1 << 5 ) -#define GP4SET_SET5_SET (0x1 << 5 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP4SET[SET4] - Set output high for corresponding port pin. */ -#define GP4SET_SET4_BBA (*(volatile unsigned long *) 0x420C1B90) -#define GP4SET_SET4_MSK (0x1 << 4 ) -#define GP4SET_SET4 (0x1 << 4 ) -#define GP4SET_SET4_SET (0x1 << 4 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP4SET[SET3] - Set output high for corresponding port pin. */ -#define GP4SET_SET3_BBA (*(volatile unsigned long *) 0x420C1B8C) -#define GP4SET_SET3_MSK (0x1 << 3 ) -#define GP4SET_SET3 (0x1 << 3 ) -#define GP4SET_SET3_SET (0x1 << 3 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP4SET[SET2] - Set output high for corresponding port pin. */ -#define GP4SET_SET2_BBA (*(volatile unsigned long *) 0x420C1B88) -#define GP4SET_SET2_MSK (0x1 << 2 ) -#define GP4SET_SET2 (0x1 << 2 ) -#define GP4SET_SET2_SET (0x1 << 2 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP4SET[SET1] - Set output high for corresponding port pin. */ -#define GP4SET_SET1_BBA (*(volatile unsigned long *) 0x420C1B84) -#define GP4SET_SET1_MSK (0x1 << 1 ) -#define GP4SET_SET1 (0x1 << 1 ) -#define GP4SET_SET1_SET (0x1 << 1 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* GP4SET[SET0] - Set output high for corresponding port pin. */ -#define GP4SET_SET0_BBA (*(volatile unsigned long *) 0x420C1B80) -#define GP4SET_SET0_MSK (0x1 << 0 ) -#define GP4SET_SET0 (0x1 << 0 ) -#define GP4SET_SET0_SET (0x1 << 0 ) /* SET. Set by user code to drive the corresponding GPIO high. */ - -/* Reset Value for GP4CLR*/ -#define GP4CLR_RVAL 0x0 - -/* GP4CLR[CLR7] - Set by user code to drive the corresponding GPIO low. */ -#define GP4CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C1C1C) -#define GP4CLR_CLR7_MSK (0x1 << 7 ) -#define GP4CLR_CLR7 (0x1 << 7 ) -#define GP4CLR_CLR7_CLR (0x1 << 7 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP4CLR[CLR6] - Set by user code to drive the corresponding GPIO low. */ -#define GP4CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C1C18) -#define GP4CLR_CLR6_MSK (0x1 << 6 ) -#define GP4CLR_CLR6 (0x1 << 6 ) -#define GP4CLR_CLR6_CLR (0x1 << 6 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP4CLR[CLR5] - Set by user code to drive the corresponding GPIO low. */ -#define GP4CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C1C14) -#define GP4CLR_CLR5_MSK (0x1 << 5 ) -#define GP4CLR_CLR5 (0x1 << 5 ) -#define GP4CLR_CLR5_CLR (0x1 << 5 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP4CLR[CLR4] - Set by user code to drive the corresponding GPIO low. */ -#define GP4CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C1C10) -#define GP4CLR_CLR4_MSK (0x1 << 4 ) -#define GP4CLR_CLR4 (0x1 << 4 ) -#define GP4CLR_CLR4_CLR (0x1 << 4 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP4CLR[CLR3] - Set by user code to drive the corresponding GPIO low. */ -#define GP4CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C1C0C) -#define GP4CLR_CLR3_MSK (0x1 << 3 ) -#define GP4CLR_CLR3 (0x1 << 3 ) -#define GP4CLR_CLR3_CLR (0x1 << 3 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP4CLR[CLR2] - Set by user code to drive the corresponding GPIO low. */ -#define GP4CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C1C08) -#define GP4CLR_CLR2_MSK (0x1 << 2 ) -#define GP4CLR_CLR2 (0x1 << 2 ) -#define GP4CLR_CLR2_CLR (0x1 << 2 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP4CLR[CLR1] - Set by user code to drive the corresponding GPIO low. */ -#define GP4CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C1C04) -#define GP4CLR_CLR1_MSK (0x1 << 1 ) -#define GP4CLR_CLR1 (0x1 << 1 ) -#define GP4CLR_CLR1_CLR (0x1 << 1 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* GP4CLR[CLR0] - Set by user code to drive the corresponding GPIO low. */ -#define GP4CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C1C00) -#define GP4CLR_CLR0_MSK (0x1 << 0 ) -#define GP4CLR_CLR0 (0x1 << 0 ) -#define GP4CLR_CLR0_CLR (0x1 << 0 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ - -/* Reset Value for GP4TGL*/ -#define GP4TGL_RVAL 0x0 - -/* GP4TGL[TGL7] - Toggle for corresponding port pin. */ -#define GP4TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C1C9C) -#define GP4TGL_TGL7_MSK (0x1 << 7 ) -#define GP4TGL_TGL7 (0x1 << 7 ) -#define GP4TGL_TGL7_TGL (0x1 << 7 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP4TGL[TGL6] - Toggle for corresponding port pin. */ -#define GP4TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C1C98) -#define GP4TGL_TGL6_MSK (0x1 << 6 ) -#define GP4TGL_TGL6 (0x1 << 6 ) -#define GP4TGL_TGL6_TGL (0x1 << 6 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP4TGL[TGL5] - Toggle for corresponding port pin. */ -#define GP4TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C1C94) -#define GP4TGL_TGL5_MSK (0x1 << 5 ) -#define GP4TGL_TGL5 (0x1 << 5 ) -#define GP4TGL_TGL5_TGL (0x1 << 5 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP4TGL[TGL4] - Toggle for corresponding port pin. */ -#define GP4TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C1C90) -#define GP4TGL_TGL4_MSK (0x1 << 4 ) -#define GP4TGL_TGL4 (0x1 << 4 ) -#define GP4TGL_TGL4_TGL (0x1 << 4 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP4TGL[TGL3] - Toggle for corresponding port pin. */ -#define GP4TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C1C8C) -#define GP4TGL_TGL3_MSK (0x1 << 3 ) -#define GP4TGL_TGL3 (0x1 << 3 ) -#define GP4TGL_TGL3_TGL (0x1 << 3 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP4TGL[TGL2] - Toggle for corresponding port pin. */ -#define GP4TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C1C88) -#define GP4TGL_TGL2_MSK (0x1 << 2 ) -#define GP4TGL_TGL2 (0x1 << 2 ) -#define GP4TGL_TGL2_TGL (0x1 << 2 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP4TGL[TGL1] - Toggle for corresponding port pin. */ -#define GP4TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C1C84) -#define GP4TGL_TGL1_MSK (0x1 << 1 ) -#define GP4TGL_TGL1 (0x1 << 1 ) -#define GP4TGL_TGL1_TGL (0x1 << 1 ) /* TGL. Set by user code to invert the corresponding GPIO. */ - -/* GP4TGL[TGL0] - Toggle for corresponding port pin. */ -#define GP4TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C1C80) -#define GP4TGL_TGL0_MSK (0x1 << 0 ) -#define GP4TGL_TGL0 (0x1 << 0 ) -#define GP4TGL_TGL0_TGL (0x1 << 0 ) /* TGL. Set by user code to invert the corresponding GPIO. */ -// ------------------------------------------------------------------------------------------------ -// ----- GPIOCMN ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief General Purpose Input Output (pADI_GPIOCMN) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_GPIOCMN Structure */ - __IO uint8_t GPDWN; /*!< GPIO P3.4 Pull Down Control */ -} ADI_GPIOCMN_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define GPDWN (*(volatile unsigned char *) 0x400060F0) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for GPDWN*/ -#define GPDWN_RVAL 0x1 - -/* GPDWN[DWN1] - Pull down resistor control bit */ -#define GPDWN_DWN1_BBA (*(volatile unsigned long *) 0x420C1E04) -#define GPDWN_DWN1_MSK (0x1 << 1 ) -#define GPDWN_DWN1 (0x1 << 1 ) -#define GPDWN_DWN1_EN (0x0 << 1 ) /* EN to enable the pull down resistor on P3.4 by software. The hardware only enables this pull down automatically at power up. */ -#define GPDWN_DWN1_DIS (0x1 << 1 ) /* DIS to disable the pull down resistor on P3.4. Disabled automatically by hardware if GP3PUL[4] =1 or if GP3OEN[4]=1. */ -// ------------------------------------------------------------------------------------------------ -// ----- MISC ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief General Purpose Input Output (pADI_MISC) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_MISC Structure */ - __I uint32_t RESERVED0; - __IO uint16_t RFTST; /*!< Internal Radio Test Mode Access */ - __I uint16_t RESERVED1[5]; - __IO uint8_t SWACT; /*!< Serial Wire Activity Register */ -} ADI_MISC_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define RFTST (*(volatile unsigned short int *) 0x40008824) -#define SWACT (*(volatile unsigned char *) 0x40008830) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for RFTST*/ -#define RFTST_RVAL 0x0 - -/* RFTST[DIR] - Controls the pin direction in RF test mode. */ -#define RFTST_DIR_MSK (0x7FF << 5 ) - -/* RFTST[AN1] - Enable RF Analog test 2 mode. */ -#define RFTST_AN1_BBA (*(volatile unsigned long *) 0x4211048C) -#define RFTST_AN1_MSK (0x1 << 3 ) -#define RFTST_AN1 (0x1 << 3 ) -#define RFTST_AN1_DIS (0x0 << 3 ) /* DIS */ -#define RFTST_AN1_EN (0x1 << 3 ) /* EN */ - -/* RFTST[AN0] - Enable RF Analog test mode. */ -#define RFTST_AN0_BBA (*(volatile unsigned long *) 0x42110488) -#define RFTST_AN0_MSK (0x1 << 2 ) -#define RFTST_AN0 (0x1 << 2 ) -#define RFTST_AN0_DIS (0x0 << 2 ) /* DIS */ -#define RFTST_AN0_EN (0x1 << 2 ) /* EN */ - -/* RFTST[SPI0] - Enable the internal SPI0 signals to P0.0, P0.1, P0.2 and P0.3. */ -#define RFTST_SPI0_BBA (*(volatile unsigned long *) 0x42110484) -#define RFTST_SPI0_MSK (0x1 << 1 ) -#define RFTST_SPI0 (0x1 << 1 ) -#define RFTST_SPI0_DIS (0x0 << 1 ) /* DIS */ -#define RFTST_SPI0_EN (0x1 << 1 ) /* EN */ - -/* RFTST[GPX] - Connect the internal GPIOs GP0-GP5 of the RF transceiver to external GPIOs P0.6, P0.7, P1.0, P1.1, P1.4, P1.5. */ -#define RFTST_GPX_BBA (*(volatile unsigned long *) 0x42110480) -#define RFTST_GPX_MSK (0x1 << 0 ) -#define RFTST_GPX (0x1 << 0 ) -#define RFTST_GPX_DIS (0x0 << 0 ) /* DIS */ -#define RFTST_GPX_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for SWACT*/ -#define SWACT_RVAL 0x0 - -/* SWACT[ACT] - Serial Wire Activity */ -#define SWACT_ACT_BBA (*(volatile unsigned long *) 0x42110600) -#define SWACT_ACT_MSK (0x1 << 0 ) -#define SWACT_ACT (0x1 << 0 ) -#define SWACT_ACT_DIS (0x0 << 0 ) /* DIS */ -#define SWACT_ACT_EN (0x1 << 0 ) /* EN */ -// ------------------------------------------------------------------------------------------------ -// ----- I2C ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief I2C (pADI_I2C) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_I2C Structure */ - __IO uint16_t I2CMCON; /*!< Master Control Register */ - __I uint16_t RESERVED0; - __IO uint16_t I2CMSTA; /*!< Master Status Register */ - __I uint16_t RESERVED1; - __IO uint16_t I2CMRX; /*!< Master Receive Data Register */ - __I uint16_t RESERVED2; - __IO uint16_t I2CMTX; /*!< Master Transmit Data Register */ - __I uint16_t RESERVED3; - __IO uint16_t I2CMRXCNT; /*!< Master Receive Data Count Register */ - __I uint16_t RESERVED4; - __IO uint16_t I2CMCRXCNT; /*!< Master Current Receive Data Count Register */ - __I uint16_t RESERVED5; - __IO uint8_t I2CADR0; /*!< First Master Address Byte Register */ - __I uint8_t RESERVED6[3]; - __IO uint8_t I2CADR1; /*!< Second Master Address Byte Register */ - __I uint8_t RESERVED7[7]; - __IO uint16_t I2CDIV; /*!< Serial Clock Period Divisor Register */ - __I uint16_t RESERVED8; - __IO uint16_t I2CSCON; /*!< Slave Control Register */ - __I uint16_t RESERVED9; - __IO uint16_t I2CSSTA; /*!< Slave I2C Status, Error and Interrupt Register */ - __I uint16_t RESERVED10; - __IO uint16_t I2CSRX; /*!< Slave Receive Data Register */ - __I uint16_t RESERVED11; - __IO uint16_t I2CSTX; /*!< Slave Transmit Data Register */ - __I uint16_t RESERVED12; - __IO uint16_t I2CALT; /*!< Hardware General Call ID Register */ - __I uint16_t RESERVED13; - __IO uint16_t I2CID0; /*!< First Slave Address Device ID */ - __I uint16_t RESERVED14; - __IO uint16_t I2CID1; /*!< Second Slave Address Device ID */ - __I uint16_t RESERVED15; - __IO uint16_t I2CID2; /*!< Third Slave Address Device ID */ - __I uint16_t RESERVED16; - __IO uint16_t I2CID3; /*!< Fourth Slave Address Device ID */ - __I uint16_t RESERVED17; - __IO uint16_t I2CFSTA; /*!< Master and Slave Rx/Tx FIFO Status Register */ -} ADI_I2C_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define I2CMCON (*(volatile unsigned short int *) 0x40003000) -#define I2CMSTA (*(volatile unsigned short int *) 0x40003004) -#define I2CMRX (*(volatile unsigned short int *) 0x40003008) -#define I2CMTX (*(volatile unsigned short int *) 0x4000300C) -#define I2CMRXCNT (*(volatile unsigned short int *) 0x40003010) -#define I2CMCRXCNT (*(volatile unsigned short int *) 0x40003014) -#define I2CADR0 (*(volatile unsigned char *) 0x40003018) -#define I2CADR1 (*(volatile unsigned char *) 0x4000301C) -#define I2CDIV (*(volatile unsigned short int *) 0x40003024) -#define I2CSCON (*(volatile unsigned short int *) 0x40003028) -#define I2CSSTA (*(volatile unsigned short int *) 0x4000302C) -#define I2CSRX (*(volatile unsigned short int *) 0x40003030) -#define I2CSTX (*(volatile unsigned short int *) 0x40003034) -#define I2CALT (*(volatile unsigned short int *) 0x40003038) -#define I2CID0 (*(volatile unsigned short int *) 0x4000303C) -#define I2CID1 (*(volatile unsigned short int *) 0x40003040) -#define I2CID2 (*(volatile unsigned short int *) 0x40003044) -#define I2CID3 (*(volatile unsigned short int *) 0x40003048) -#define I2CFSTA (*(volatile unsigned short int *) 0x4000304C) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for I2CMCON*/ -#define I2CMCON_RVAL 0x0 - -/* I2CMCON[TXDMA] - Enable master Tx DMA request. */ -#define I2CMCON_TXDMA_BBA (*(volatile unsigned long *) 0x4206002C) -#define I2CMCON_TXDMA_MSK (0x1 << 11 ) -#define I2CMCON_TXDMA (0x1 << 11 ) -#define I2CMCON_TXDMA_DIS (0x0 << 11 ) /* DIS. Disable Tx DMA mode. */ -#define I2CMCON_TXDMA_EN (0x1 << 11 ) /* EN. Enable I2C master DMA requests. */ - -/* I2CMCON[RXDMA] - Enable master Rx DMA request. */ -#define I2CMCON_RXDMA_BBA (*(volatile unsigned long *) 0x42060028) -#define I2CMCON_RXDMA_MSK (0x1 << 10 ) -#define I2CMCON_RXDMA (0x1 << 10 ) -#define I2CMCON_RXDMA_DIS (0x0 << 10 ) /* DIS. Disable Rx DMA mode. */ -#define I2CMCON_RXDMA_EN (0x1 << 10 ) /* EN. Enable I2C master DMA requests. */ - -/* I2CMCON[IENCMP] - Transaction completed (or stop detected) interrupt enable. */ -#define I2CMCON_IENCMP_BBA (*(volatile unsigned long *) 0x42060020) -#define I2CMCON_IENCMP_MSK (0x1 << 8 ) -#define I2CMCON_IENCMP (0x1 << 8 ) -#define I2CMCON_IENCMP_DIS (0x0 << 8 ) /* DIS. Interrupt disabled. */ -#define I2CMCON_IENCMP_EN (0x1 << 8 ) /* EN. Interrupt enabled. A master I2C interrupt is generated when a STOP is detected. Enables TCOMP to geneerate an interrupt. */ - -/* I2CMCON[IENNACK] - NACK received interrupt enable. */ -#define I2CMCON_IENNACK_BBA (*(volatile unsigned long *) 0x4206001C) -#define I2CMCON_IENNACK_MSK (0x1 << 7 ) -#define I2CMCON_IENNACK (0x1 << 7 ) -#define I2CMCON_IENNACK_DIS (0x0 << 7 ) /* DIS. Interrupt disabled. */ -#define I2CMCON_IENNACK_EN (0x1 << 7 ) /* EN, enables NACKADDR(I2CMSTA[4]) and NACKDATA (I2CMSTA[7]) to generate an interrupt. */ - -/* I2CMCON[IENALOST] - Arbitration lost interrupt enable. */ -#define I2CMCON_IENALOST_BBA (*(volatile unsigned long *) 0x42060018) -#define I2CMCON_IENALOST_MSK (0x1 << 6 ) -#define I2CMCON_IENALOST (0x1 << 6 ) -#define I2CMCON_IENALOST_DIS (0x0 << 6 ) /* DIS. Interrupt disabled. */ -#define I2CMCON_IENALOST_EN (0x1 << 6 ) /* EN. Interrupt enabled. A master I2C interrupt is generated if the master looses arbitration.Enables ALOST to generate an interrupt. */ - -/* I2CMCON[IENTX] - Transmit request interrupt enable. */ -#define I2CMCON_IENTX_BBA (*(volatile unsigned long *) 0x42060014) -#define I2CMCON_IENTX_MSK (0x1 << 5 ) -#define I2CMCON_IENTX (0x1 << 5 ) -#define I2CMCON_IENTX_DIS (0x0 << 5 ) /* DIS. Interrupt disabled. */ -#define I2CMCON_IENTX_EN (0x1 << 5 ) /* EN. Interrupt enabled. A master I2C interrupt is generated when the Tx FIFO is not full and the direction bit is 0. */ - -/* I2CMCON[IENRX] - Receive request interrupt enable. */ -#define I2CMCON_IENRX_BBA (*(volatile unsigned long *) 0x42060010) -#define I2CMCON_IENRX_MSK (0x1 << 4 ) -#define I2CMCON_IENRX (0x1 << 4 ) -#define I2CMCON_IENRX_DIS (0x0 << 4 ) /* DIS. Interrupt disabled. */ -#define I2CMCON_IENRX_EN (0x1 << 4 ) /* EN. Interrupt enabled. A master I2C interrupt is generated when data is in the receive FIFO. */ - -/* I2CMCON[STRETCH] - Stretch I2CSCL enable. */ -#define I2CMCON_STRETCH_BBA (*(volatile unsigned long *) 0x4206000C) -#define I2CMCON_STRETCH_MSK (0x1 << 3 ) -#define I2CMCON_STRETCH (0x1 << 3 ) -#define I2CMCON_STRETCH_DIS (0x0 << 3 ) /* DIS. Disable */ -#define I2CMCON_STRETCH_EN (0x1 << 3 ) /* EN. Setting this bit instructs the device that if I2CSCL is 0, hold it at 0. Or if I2CSCL is 1, then when it next goes to 0, hold it at 0. */ - -/* I2CMCON[LOOPBACK] - Internal loop back enable. */ -#define I2CMCON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42060008) -#define I2CMCON_LOOPBACK_MSK (0x1 << 2 ) -#define I2CMCON_LOOPBACK (0x1 << 2 ) -#define I2CMCON_LOOPBACK_DIS (0x0 << 2 ) /* DIS. Disable. */ -#define I2CMCON_LOOPBACK_EN (0x1 << 2 ) /* EN. I2CSCL and I2CSDA out of the device are muxed onto their corresponding inputs. Note that is also possible for the master to loop back a transfer to the slave as long as the device address corresponds, that is, external loopback. */ - -/* I2CMCON[COMPETE] - Start back-off disable. */ -#define I2CMCON_COMPETE_BBA (*(volatile unsigned long *) 0x42060004) -#define I2CMCON_COMPETE_MSK (0x1 << 1 ) -#define I2CMCON_COMPETE (0x1 << 1 ) -#define I2CMCON_COMPETE_DIS (0x0 << 1 ) /* DIS. Disable. */ -#define I2CMCON_COMPETE_EN (0x1 << 1 ) /* EN. Enables the device to compete for ownership even if another device is currently driving a start condition. */ - -/* I2CMCON[MAS] - Master enable bit. */ -#define I2CMCON_MAS_BBA (*(volatile unsigned long *) 0x42060000) -#define I2CMCON_MAS_MSK (0x1 << 0 ) -#define I2CMCON_MAS (0x1 << 0 ) -#define I2CMCON_MAS_DIS (0x0 << 0 ) /* DIS. The master is disabled. The master state machine is reset.The master should be disabled when not in use. This bit should not be cleared until a transaction has completed. TCOMP in I2CMSTA indicates when a transaction is complete. */ -#define I2CMCON_MAS_EN (0x1 << 0 ) /* EN. Enable master. */ - -/* Reset Value for I2CMSTA*/ -#define I2CMSTA_RVAL 0x0 - -/* I2CMSTA[TXUR] - Master transmit FIFO underrun. */ -#define I2CMSTA_TXUR_BBA (*(volatile unsigned long *) 0x420600B0) -#define I2CMSTA_TXUR_MSK (0x1 << 12 ) -#define I2CMSTA_TXUR (0x1 << 12 ) -#define I2CMSTA_TXUR_CLR (0x0 << 12 ) /* CLR. Cleared. */ -#define I2CMSTA_TXUR_SET (0x1 << 12 ) /* SET. Set when the I2C master ends the transaction due to a Tx FIFO empty condition. This bit is only set when IENTX (I2CSCON[5]) is set. */ - -/* I2CMSTA[MSTOP] - STOP driven by the I2C master. */ -#define I2CMSTA_MSTOP_BBA (*(volatile unsigned long *) 0x420600AC) -#define I2CMSTA_MSTOP_MSK (0x1 << 11 ) -#define I2CMSTA_MSTOP (0x1 << 11 ) -#define I2CMSTA_MSTOP_CLR (0x0 << 11 ) /* CLR. Cleared. */ -#define I2CMSTA_MSTOP_SET (0x1 << 11 ) /* SET. Set when the I2C master drives a stop condition on the I2C bus, therefore indicating a transaction completion, Tx underrun, Rx overflow, or a NACK by the slave. It is different from TCOMP because it is not set when the stop condition occurs due to any other master on the I2C bus. This bit does not generate an interrupt. See the TCOMP description for available interrupts related to the stop condition. */ - -/* I2CMSTA[LINEBUSY] - Line is busy. */ -#define I2CMSTA_LINEBUSY_BBA (*(volatile unsigned long *) 0x420600A8) -#define I2CMSTA_LINEBUSY_MSK (0x1 << 10 ) -#define I2CMSTA_LINEBUSY (0x1 << 10 ) -#define I2CMSTA_LINEBUSY_CLR (0x0 << 10 ) /* CLR. Cleared when a stop is detected on the I2C bus. */ -#define I2CMSTA_LINEBUSY_SET (0x1 << 10 ) /* SET. Set when a start is detected on the I2C bus. */ - -/* I2CMSTA[RXOF] - Receive FIFO overflow. */ -#define I2CMSTA_RXOF_BBA (*(volatile unsigned long *) 0x420600A4) -#define I2CMSTA_RXOF_MSK (0x1 << 9 ) -#define I2CMSTA_RXOF (0x1 << 9 ) -#define I2CMSTA_RXOF_CLR (0x0 << 9 ) /* CLR. CLeared. */ -#define I2CMSTA_RXOF_SET (0x1 << 9 ) /* SET. Set when a byte is written to the receive FIFO when the FIFO is already full. */ - -/* I2CMSTA[TCOMP] - Transaction completed (or stop detected). (Can drive an interrupt). */ -#define I2CMSTA_TCOMP_BBA (*(volatile unsigned long *) 0x420600A0) -#define I2CMSTA_TCOMP_MSK (0x1 << 8 ) -#define I2CMSTA_TCOMP (0x1 << 8 ) -#define I2CMSTA_TCOMP_CLR (0x0 << 8 ) /* CLR. Cleared. */ -#define I2CMSTA_TCOMP_SET (0x1 << 8 ) /* SET. Set when a STOP condition is detected on the I2C bus. If IENCMP is 1, an interrupt is generated when this bit asserts. This bit only asserts if the master is enabled (MASEN = 1). This bit should be used to determine when it is safe to disable the master. It can also be used to wait for another master's transaction to complete on the I2C bus when this master loses arbitration. */ - -/* I2CMSTA[NACKDATA] - NACK received in response to data write. (Can drive an interrupt). */ -#define I2CMSTA_NACKDATA_BBA (*(volatile unsigned long *) 0x4206009C) -#define I2CMSTA_NACKDATA_MSK (0x1 << 7 ) -#define I2CMSTA_NACKDATA (0x1 << 7 ) -#define I2CMSTA_NACKDATA_CLR (0x0 << 7 ) /* CLR. Cleared on a read of the I2CMSTA register. */ -#define I2CMSTA_NACKDATA_SET (0x1 << 7 ) /* SET. Set when a NACK is received in response to a data write transfer. If IENNACK is 1, an interrupt is generated when this bit asserts. */ - -/* I2CMSTA[BUSY] - Master busy. */ -#define I2CMSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060098) -#define I2CMSTA_BUSY_MSK (0x1 << 6 ) -#define I2CMSTA_BUSY (0x1 << 6 ) -#define I2CMSTA_BUSY_CLR (0x0 << 6 ) /* CLR. Cleared if the state machine is idle or another device has control of the I2C bus. */ -#define I2CMSTA_BUSY_SET (0x1 << 6 ) /* SET. Set when the master state machine is servicing a transaction. */ - -/* I2CMSTA[ALOST] - Arbitration lost. (Can drive an interrupt). */ -#define I2CMSTA_ALOST_BBA (*(volatile unsigned long *) 0x42060094) -#define I2CMSTA_ALOST_MSK (0x1 << 5 ) -#define I2CMSTA_ALOST (0x1 << 5 ) -#define I2CMSTA_ALOST_CLR (0x0 << 5 ) /* CLR. Cleared on a read of the I2CMSTA register. */ -#define I2CMSTA_ALOST_SET (0x1 << 5 ) /* SET. Set if the master looses arbitration. If IENALOST is 1, an interrupt is generated when this bit asserts. */ - -/* I2CMSTA[NACKADDR] - NACK received in response to an address. (Can drive an interrupt). */ -#define I2CMSTA_NACKADDR_BBA (*(volatile unsigned long *) 0x42060090) -#define I2CMSTA_NACKADDR_MSK (0x1 << 4 ) -#define I2CMSTA_NACKADDR (0x1 << 4 ) -#define I2CMSTA_NACKADDR_CLR (0x0 << 4 ) /* CLR. Cleared on a read of the I2CMSTA register. */ -#define I2CMSTA_NACKADDR_SET (0x1 << 4 ) /* SET. Set if a NACK received in response to an address. If IENNACK is 1, an interrupt is generated when this bit asserts. */ - -/* I2CMSTA[RXREQ] - Receive Request. (Can drive an interrupt). */ -#define I2CMSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206008C) -#define I2CMSTA_RXREQ_MSK (0x1 << 3 ) -#define I2CMSTA_RXREQ (0x1 << 3 ) -#define I2CMSTA_RXREQ_CLR (0x0 << 3 ) /* CLR. Cleared. */ -#define I2CMSTA_RXREQ_SET (0x1 << 3 ) /* SET. Set when there is data in the receive FIFO. If IENRX is 1, an interrupt is generated when this bit asserts. */ - -/* I2CMSTA[TXREQ] - Transmit Request. (Can drive an interrupt). */ -#define I2CMSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060088) -#define I2CMSTA_TXREQ_MSK (0x1 << 2 ) -#define I2CMSTA_TXREQ (0x1 << 2 ) -#define I2CMSTA_TXREQ_CLR (0x0 << 2 ) /* CLR. Cleared when the transmit FIFO underrun condition is not met. */ -#define I2CMSTA_TXREQ_SET (0x1 << 2 ) /* SET. Set when the direction bit is 0 and the transmit FIFO is either empty or not full. If IENTX is 1, an interrupt is generated when this bit asserts. */ - -/* I2CMSTA[TXFSTA] - Transmit FIFO Status. */ -#define I2CMSTA_TXFSTA_MSK (0x3 << 0 ) -#define I2CMSTA_TXFSTA_EMPTY (0x0 << 0 ) /* EMPTY. FIFO empty. */ -#define I2CMSTA_TXFSTA_ONEBYTE (0x2 << 0 ) /* ONEBYTE. 1 byte in FIFO. */ -#define I2CMSTA_TXFSTA_FULL (0x3 << 0 ) /* FULL. FIFO full. */ - -/* Reset Value for I2CMRX*/ -#define I2CMRX_RVAL 0x0 - -/* I2CMRX[VALUE] - Receive register. This register allows access to the receive data FIFO. The FIFO can hold two bytes. */ -#define I2CMRX_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for I2CMTX*/ -#define I2CMTX_RVAL 0x0 - -/* I2CMTX[VALUE] - Transmit register. This register allows access to the transmit data FIFO. The FIFO can hold two bytes. */ -#define I2CMTX_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for I2CMRXCNT*/ -#define I2CMRXCNT_RVAL 0x0 - -/* I2CMRXCNT[EXTEND] - Extended read: Use this bit if greater than 256 bytes are required on a read. For example: To receive 412 bytes, write 0x100 (EXTEND = 1) to this register (I2CMRXCNT). Wait for the first byte to be received, then check the I2CMCRXCNT register for every byte received thereafter. When I2CMCRXCNT returns to 0, 256 bytes have been received. Then, write 0x09C (412 - 256 = 156 decimal (equal to 0x9C) – with the EXTEND bit set to 0) to this register (I2CMRXCNT). */ -#define I2CMRXCNT_EXTEND_BBA (*(volatile unsigned long *) 0x42060220) -#define I2CMRXCNT_EXTEND_MSK (0x1 << 8 ) -#define I2CMRXCNT_EXTEND (0x1 << 8 ) -#define I2CMRXCNT_EXTEND_DIS (0x0 << 8 ) /* DIS */ -#define I2CMRXCNT_EXTEND_EN (0x1 << 8 ) /* EN */ - -/* I2CMRXCNT[COUNT] - Receive count. Program the number of bytes required minus one to this register. If just one byte is required write 0 to this register. If greater than 256 bytes are required, then use EXTEND. */ -#define I2CMRXCNT_COUNT_MSK (0xFF << 0 ) - -/* Reset Value for I2CMCRXCNT*/ -#define I2CMCRXCNT_RVAL 0x0 - -/* I2CMCRXCNT[VALUE] - Current receive count. This register gives the total number of bytes received so far. If 256 bytes are requested, then this register reads 0 when the transaction has completed. */ -#define I2CMCRXCNT_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for I2CADR0*/ -#define I2CADR0_RVAL 0x0 - -/* I2CADR0[VALUE] - Address byte. If a 7-bit address is required, then I2CADR0[7:1] is programmed with the address and I2CADR0[0] is programmed with the direction (read or write). If a 10-bit address is required then I2CADR0[7:3] is programmed with '11110', I2CADR0[2:1] is programmed with the two MSBs of the address, and, again, I2CADR0[0] is programmed with the direction bit (read or write). */ -#define I2CADR0_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for I2CADR1*/ -#define I2CADR1_RVAL 0x0 - -/* I2CADR1[VALUE] - Address byte. This register is only required when addressing a slave with 10-bit addressing. I2CADR1[7:0] is programmed with the lower eight bits of the address. */ -#define I2CADR1_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for I2CDIV*/ -#define I2CDIV_RVAL 0x1F1F - -/* I2CDIV[HIGH] - Serial clock high time. This register controls the clock high time. See the serial clock generation section for more details. */ -#define I2CDIV_HIGH_MSK (0xFF << 8 ) - -/* I2CDIV[LOW] - Serial clock low time. This register controls the clock low time. See the serial clock generation section for more details. */ -#define I2CDIV_LOW_MSK (0xFF << 0 ) - -/* Reset Value for I2CSCON*/ -#define I2CSCON_RVAL 0x0 - -/* I2CSCON[TXDMA] - Enable slave Tx DMA request. */ -#define I2CSCON_TXDMA_BBA (*(volatile unsigned long *) 0x42060538) -#define I2CSCON_TXDMA_MSK (0x1 << 14 ) -#define I2CSCON_TXDMA (0x1 << 14 ) -#define I2CSCON_TXDMA_DIS (0x0 << 14 ) /* DIS. Disable DMA mode. */ -#define I2CSCON_TXDMA_EN (0x1 << 14 ) /* EN. Enable I2C slave DMA requests. */ - -/* I2CSCON[RXDMA] - Enable slave Rx DMA request. */ -#define I2CSCON_RXDMA_BBA (*(volatile unsigned long *) 0x42060534) -#define I2CSCON_RXDMA_MSK (0x1 << 13 ) -#define I2CSCON_RXDMA (0x1 << 13 ) -#define I2CSCON_RXDMA_DIS (0x0 << 13 ) /* DIS. Disable DMA mode. */ -#define I2CSCON_RXDMA_EN (0x1 << 13 ) /* EN. Enable I2C slave DMA requests. */ - -/* I2CSCON[IENREPST] - Repeated start interrupt enable. */ -#define I2CSCON_IENREPST_BBA (*(volatile unsigned long *) 0x42060530) -#define I2CSCON_IENREPST_MSK (0x1 << 12 ) -#define I2CSCON_IENREPST (0x1 << 12 ) -#define I2CSCON_IENREPST_DIS (0x0 << 12 ) /* DIS. Disable an interrupt when the REPSTART status bit asserts. */ -#define I2CSCON_IENREPST_EN (0x1 << 12 ) /* EN. Generate an interrupt when the REPSTART status bit asserts. */ - -/* I2CSCON[IENTX] - Transmit request interrupt enable. */ -#define I2CSCON_IENTX_BBA (*(volatile unsigned long *) 0x42060528) -#define I2CSCON_IENTX_MSK (0x1 << 10 ) -#define I2CSCON_IENTX (0x1 << 10 ) -#define I2CSCON_IENTX_DIS (0x0 << 10 ) /* DIS. Disable transmit request interrupt. */ -#define I2CSCON_IENTX_EN (0x1 << 10 ) /* EN. Enable transmit request interrupt. */ - -/* I2CSCON[IENRX] - Receive request interrupt enable. */ -#define I2CSCON_IENRX_BBA (*(volatile unsigned long *) 0x42060524) -#define I2CSCON_IENRX_MSK (0x1 << 9 ) -#define I2CSCON_IENRX (0x1 << 9 ) -#define I2CSCON_IENRX_DIS (0x0 << 9 ) /* DIS. Disable receive request interrupt. */ -#define I2CSCON_IENRX_EN (0x1 << 9 ) /* EN. Enable receive request interrupt. */ - -/* I2CSCON[IENSTOP] - Stop condition detected interrupt enable. */ -#define I2CSCON_IENSTOP_BBA (*(volatile unsigned long *) 0x42060520) -#define I2CSCON_IENSTOP_MSK (0x1 << 8 ) -#define I2CSCON_IENSTOP (0x1 << 8 ) -#define I2CSCON_IENSTOP_DIS (0x0 << 8 ) /* DIS. Disable stop condition detect interrupt. */ -#define I2CSCON_IENSTOP_EN (0x1 << 8 ) /* EN. Enable stop condition detect interrupt. Enables STOP (I2CSSTA[10]) to generate an interrupt */ - -/* I2CSCON[NACK] - NACK next communication. */ -#define I2CSCON_NACK_BBA (*(volatile unsigned long *) 0x4206051C) -#define I2CSCON_NACK_MSK (0x1 << 7 ) -#define I2CSCON_NACK (0x1 << 7 ) -#define I2CSCON_NACK_DIS (0x0 << 7 ) /* DIS. Disable. */ -#define I2CSCON_NACK_EN (0x1 << 7 ) /* EN. Allow the next communication to be NACK'ed. This can be used for example if during a 24xx I2C serial eeprom style access, an attempt was made to write to a read only or nonexisting location in system memory. That is the indirect address in a 24xx I2C serial eeprom style write pointed to an unwritable memory location. */ - -/* I2CSCON[STRETCH] - Stretch I2CSCL enable. */ -#define I2CSCON_STRETCH_BBA (*(volatile unsigned long *) 0x42060518) -#define I2CSCON_STRETCH_MSK (0x1 << 6 ) -#define I2CSCON_STRETCH (0x1 << 6 ) -#define I2CSCON_STRETCH_DIS (0x0 << 6 ) /* DIS. Disable. */ -#define I2CSCON_STRETCH_EN (0x1 << 6 ) /* EN. Tell the device that, if I2CSCL is 0, hold it at 0. Or if I2CSCL is 1, then when it next goes to 0 hold it at 0. */ - -/* I2CSCON[EARLYTXR] - Early transmit request mode. */ -#define I2CSCON_EARLYTXR_BBA (*(volatile unsigned long *) 0x42060514) -#define I2CSCON_EARLYTXR_MSK (0x1 << 5 ) -#define I2CSCON_EARLYTXR (0x1 << 5 ) -#define I2CSCON_EARLYTXR_DIS (0x0 << 5 ) /* DIS. Disable. */ -#define I2CSCON_EARLYTXR_EN (0x1 << 5 ) /* EN. Enable a transmit request just after the positive edge of the direction bit (READ/WRITE) I2CSCL clock pulse. */ - -/* I2CSCON[GCSB] - General call status bit clear. */ -#define I2CSCON_GCSB_BBA (*(volatile unsigned long *) 0x42060510) -#define I2CSCON_GCSB_MSK (0x1 << 4 ) -#define I2CSCON_GCSB (0x1 << 4 ) -#define I2CSCON_GCSB_CLR (0x1 << 4 ) /* CLR. Clear the General Call status and General Call ID bits. The General Call status and General Call ID bits are not reset by anything other than a write to this bit or a full reset. */ - -/* I2CSCON[HGC] - Hardware general call enable. */ -#define I2CSCON_HGC_BBA (*(volatile unsigned long *) 0x4206050C) -#define I2CSCON_HGC_MSK (0x1 << 3 ) -#define I2CSCON_HGC (0x1 << 3 ) -#define I2CSCON_HGC_DIS (0x0 << 3 ) /* DIS. Disable. */ -#define I2CSCON_HGC_EN (0x1 << 3 ) /* EN. When this bit and the General Call enable bit are set the device after receiving a general call, Address 0x00 and a data byte checks the contents of the I2CALT against the receive shift register. If they match, the device has received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a broadcast message to all master devices in the bus. The device that requires attention embeds its own address into the message. The LSB of the I2CALT register should always be written to a 1. */ - -/* I2CSCON[GC] - General call enable. */ -#define I2CSCON_GC_BBA (*(volatile unsigned long *) 0x42060508) -#define I2CSCON_GC_MSK (0x1 << 2 ) -#define I2CSCON_GC (0x1 << 2 ) -#define I2CSCON_GC_DIS (0x0 << 2 ) /* DIS. Disable. */ -#define I2CSCON_GC_EN (0x1 << 2 ) /* EN. Enable the I2C slave to ACK an I2C general call, Address 0x00 (write). */ - -/* I2CSCON[ADR10] - Enable 10 bit addressing. */ -#define I2CSCON_ADR10_BBA (*(volatile unsigned long *) 0x42060504) -#define I2CSCON_ADR10_MSK (0x1 << 1 ) -#define I2CSCON_ADR10 (0x1 << 1 ) -#define I2CSCON_ADR10_DIS (0x0 << 1 ) /* DIS. If this bit is clear, the slave can support four slave addresses, programmed in Registers I2CID0 to I2CID3. */ -#define I2CSCON_ADR10_EN (0x1 << 1 ) /* EN. Enable 10-bit addressing. One 10-bit address is supported by the slave and is stored in I2CID0 and I2CID1, where I2CID0 contains the first byte of the address and the upper five bits must be programmed to 11110' I2CID2 and I2CID3 can be programmed with 7-bit addresses at the same time. */ - -/* I2CSCON[SLV] - Slave enable. */ -#define I2CSCON_SLV_BBA (*(volatile unsigned long *) 0x42060500) -#define I2CSCON_SLV_MSK (0x1 << 0 ) -#define I2CSCON_SLV (0x1 << 0 ) -#define I2CSCON_SLV_DIS (0x0 << 0 ) /* DIS. Disable the slave and all slave state machine flops are held in reset. */ -#define I2CSCON_SLV_EN (0x1 << 0 ) /* EN. Enable slave. */ - -/* Reset Value for I2CSSTA*/ -#define I2CSSTA_RVAL 0x1 - -/* I2CSSTA[START] - Start and matching address. */ -#define I2CSSTA_START_BBA (*(volatile unsigned long *) 0x420605B8) -#define I2CSSTA_START_MSK (0x1 << 14 ) -#define I2CSSTA_START (0x1 << 14 ) -#define I2CSSTA_START_CLR (0x0 << 14 ) /* CLR. Cleared on receipt of either a stop or start condition. */ -#define I2CSSTA_START_SET (0x1 << 14 ) /* SET. Set if a start is detected on I2CSCL/I2CSDA and one of the following is true: The device address is matched. A general call (GC = 0000_0000) code is received and GC is enabled. A high speed (HS = 0000_1XXX) code is received. A start byte (0000_0001) is received. */ - -/* I2CSSTA[REPSTART] - Repeated start and matching address. (Can drive an interrupt). */ -#define I2CSSTA_REPSTART_BBA (*(volatile unsigned long *) 0x420605B4) -#define I2CSSTA_REPSTART_MSK (0x1 << 13 ) -#define I2CSSTA_REPSTART (0x1 << 13 ) -#define I2CSSTA_REPSTART_CLR (0x0 << 13 ) /* CLR. Cleared when read or on receipt of a stop condition. */ -#define I2CSSTA_REPSTART_SET (0x1 << 13 ) /* SET. Set if START (I2CSSTA[14]) is already asserted and then a repeated start is detected. */ - -/* I2CSSTA[IDMAT] - Device ID matched. */ -#define I2CSSTA_IDMAT_MSK (0x3 << 11 ) - -/* I2CSSTA[STOP] - Stop after start and matching address. (Can drive an interrupt). */ -#define I2CSSTA_STOP_BBA (*(volatile unsigned long *) 0x420605A8) -#define I2CSSTA_STOP_MSK (0x1 << 10 ) -#define I2CSSTA_STOP (0x1 << 10 ) -#define I2CSSTA_STOP_CLR (0x0 << 10 ) /* CLR. Cleared by a read of the status register. */ -#define I2CSSTA_STOP_SET (0x1 << 10 ) /* SET. Set if the slave device received a stop condition after a previous start condition and a matching address. */ - -/* I2CSSTA[GCID] - General call ID. Cleared when the GCSBCLR (I2CSCON[4]) is written to 1. These status bits are not cleared by a general call reset. */ -#define I2CSSTA_GCID_MSK (0x3 << 8 ) - -/* I2CSSTA[GCINT] - General call interrupt. (Always drives an interrupt). */ -#define I2CSSTA_GCINT_BBA (*(volatile unsigned long *) 0x4206059C) -#define I2CSSTA_GCINT_MSK (0x1 << 7 ) -#define I2CSSTA_GCINT (0x1 << 7 ) -#define I2CSSTA_GCINT_CLR (0x0 << 7 ) /* CLR. To clear this bit, write 1 to the I2CSCON[4]. If it was a general call reset, all registers are at their default values. If it was a hardware general call, the Rx FIFO holds the second byte of the general call and this can be compared with the ALT register. */ -#define I2CSSTA_GCINT_SET (0x1 << 7 ) /* SET. Set if the slave device receives a general call of any type. */ - -/* I2CSSTA[BUSY] - Slave busy. */ -#define I2CSSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060598) -#define I2CSSTA_BUSY_MSK (0x1 << 6 ) -#define I2CSSTA_BUSY (0x1 << 6 ) -#define I2CSSTA_BUSY_CLR (0x0 << 6 ) /* CLR. Cleared by hardware on any of the following conditions: The address does not match an ID register, the slave device receives a I2C stop condition or if a repeated start address doesn’t match. */ -#define I2CSSTA_BUSY_SET (0x1 << 6 ) /* SET. Set if the slave device receives an I2C start condition. */ - -/* I2CSSTA[NOACK] - NACK generated by the slave. */ -#define I2CSSTA_NOACK_BBA (*(volatile unsigned long *) 0x42060594) -#define I2CSSTA_NOACK_MSK (0x1 << 5 ) -#define I2CSSTA_NOACK (0x1 << 5 ) -#define I2CSSTA_NOACK_CLR (0x0 << 5 ) /* CLR. Cleared on a read of the I2CSSTA register. */ -#define I2CSSTA_NOACK_SET (0x1 << 5 ) /* SET. Set to indicate that the slave responded to its device address with a NACK. Set under any of the following conditions: If there was no data to transmit and sequence was a slave read, the device address is NACK'ed or if the NACK bit was set in the slave control register and the device was addressed. */ - -/* I2CSSTA[RXOF] - Receive FIFO overflow. */ -#define I2CSSTA_RXOF_BBA (*(volatile unsigned long *) 0x42060590) -#define I2CSSTA_RXOF_MSK (0x1 << 4 ) -#define I2CSSTA_RXOF (0x1 << 4 ) -#define I2CSSTA_RXOF_CLR (0x0 << 4 ) /* CLR. Cleared. */ -#define I2CSSTA_RXOF_SET (0x1 << 4 ) /* SET. Set when a byte is written to the receive FIFO when the FIFO is already full. */ - -/* I2CSSTA[RXREQ] - Receive request. (Can drive an interrupt). */ -#define I2CSSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206058C) -#define I2CSSTA_RXREQ_MSK (0x1 << 3 ) -#define I2CSSTA_RXREQ (0x1 << 3 ) -#define I2CSSTA_RXREQ_CLR (0x0 << 3 ) /* CLR. Cleared when the receive FIFO is read or flushed. */ -#define I2CSSTA_RXREQ_SET (0x1 << 3 ) /* SET. Set when the receive FIFO is not empty. Set on the falling edge of the I2CSCL clock pulse that clocks in the last data bit of a byte. */ - -/* I2CSSTA[TXREQ] - Transmit request. (Can drive an interrupt). */ -#define I2CSSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060588) -#define I2CSSTA_TXREQ_MSK (0x1 << 2 ) -#define I2CSSTA_TXREQ (0x1 << 2 ) -#define I2CSSTA_TXREQ_CLR (0x0 << 2 ) /* CLR. This bit is cleared on a read of the I2CSSTA register. */ -#define I2CSSTA_TXREQ_SET (0x1 << 2 ) /* SET. If EARLYTXR = 0, TXREQ is set when the direction bit for a transfer is received high. Thereafter, as long as the transmit FIFO is not full, this bit remains asserted. Initially, it is asserted on the negative edge of the SCL pulse that clocks in the direction bit (if the device address matched also). If EARLYTXR = 1, TXREQ is set when the direction bit for a transfer is received high. Thereafter, as long as the transmit FIFO is not full, this bit will remain asserted. Initially, it is asserted after the positive edge of the SCL pulse that clocks in the direction bit (if the device address matched also). */ - -/* I2CSSTA[TXUR] - Transmit FIFO underflow. */ -#define I2CSSTA_TXUR_BBA (*(volatile unsigned long *) 0x42060584) -#define I2CSSTA_TXUR_MSK (0x1 << 1 ) -#define I2CSSTA_TXUR (0x1 << 1 ) -#define I2CSSTA_TXUR_CLR (0x0 << 1 ) /* CLR. Cleared. */ -#define I2CSSTA_TXUR_SET (0x1 << 1 ) /* SET. Set to 1 if a master requests data from the device and the Tx FIFO is empty for the rising edge of SCL. */ - -/* I2CSSTA[TXFSEREQ] - Tx FIFO status. */ -#define I2CSSTA_TXFSEREQ_BBA (*(volatile unsigned long *) 0x42060580) -#define I2CSSTA_TXFSEREQ_MSK (0x1 << 0 ) -#define I2CSSTA_TXFSEREQ (0x1 << 0 ) -#define I2CSSTA_TXFSEREQ_CLR (0x0 << 0 ) /* CLR. Cleared. */ -#define I2CSSTA_TXFSEREQ_SET (0x1 << 0 ) /* SET. Set whenever the slave Tx FIFO is empty. */ - -/* Reset Value for I2CSRX*/ -#define I2CSRX_RVAL 0x0 - -/* I2CSRX[VALUE] - Receive register. */ -#define I2CSRX_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for I2CSTX*/ -#define I2CSTX_RVAL 0x0 - -/* I2CSTX[VALUE] - Transmit register. */ -#define I2CSTX_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for I2CALT*/ -#define I2CALT_RVAL 0x0 - -/* I2CALT[VALUE] - ALT register.This register is used in conjunction with HGC (I2CSCON[3]) to match a master generating a hardware general call. It is used in the case where a master device cannot be programmed with a slave’s address and, instead, the slave must recognize the master’s address. */ -#define I2CALT_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for I2CID0*/ -#define I2CID0_RVAL 0x0 - -/* I2CID0[VALUE] - Slave ID. */ -#define I2CID0_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for I2CID1*/ -#define I2CID1_RVAL 0x0 - -/* I2CID1[VALUE] - Slave ID. */ -#define I2CID1_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for I2CID2*/ -#define I2CID2_RVAL 0x0 - -/* I2CID2[VALUE] - Slave ID. */ -#define I2CID2_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for I2CID3*/ -#define I2CID3_RVAL 0x0 - -/* I2CID3[VALUE] - Slave ID. */ -#define I2CID3_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for I2CFSTA*/ -#define I2CFSTA_RVAL 0x0 - -/* I2CFSTA[MFLUSH] - Master Transmit FIFO Flush. */ -#define I2CFSTA_MFLUSH_BBA (*(volatile unsigned long *) 0x420609A4) -#define I2CFSTA_MFLUSH_MSK (0x1 << 9 ) -#define I2CFSTA_MFLUSH (0x1 << 9 ) -#define I2CFSTA_MFLUSH_DIS (0x0 << 9 ) /* DIS. For normal FIFO operation. */ -#define I2CFSTA_MFLUSH_EN (0x1 << 9 ) /* EN. FIFO flush enabled, to keep the FIFO empty. */ - -/* I2CFSTA[SFLUSH] - Slave Transmit FIFO Flush. */ -#define I2CFSTA_SFLUSH_BBA (*(volatile unsigned long *) 0x420609A0) -#define I2CFSTA_SFLUSH_MSK (0x1 << 8 ) -#define I2CFSTA_SFLUSH (0x1 << 8 ) -#define I2CFSTA_SFLUSH_DIS (0x0 << 8 ) /* DIS. For normal FIFO operation. */ -#define I2CFSTA_SFLUSH_EN (0x1 << 8 ) /* EN. FIFO flush enabled, to keep the FIFO empty. */ - -/* I2CFSTA[MRXFSTA] - Master Receive FIFO status. */ -#define I2CFSTA_MRXFSTA_MSK (0x3 << 6 ) -#define I2CFSTA_MRXFSTA_EMPTY (0x0 << 6 ) /* EMPTY */ -#define I2CFSTA_MRXFSTA_ONEBYTE (0x1 << 6 ) /* ONEBYTE */ -#define I2CFSTA_MRXFSTA_TWOBYTES (0x2 << 6 ) /* TWOBYTES */ - -/* I2CFSTA[MTXFSTA] - Master Transmit FIFO status. */ -#define I2CFSTA_MTXFSTA_MSK (0x3 << 4 ) -#define I2CFSTA_MTXFSTA_EMPTY (0x0 << 4 ) /* EMPTY */ -#define I2CFSTA_MTXFSTA_ONEBYTE (0x1 << 4 ) /* ONEBYTE */ -#define I2CFSTA_MTXFSTA_TWOBYTES (0x2 << 4 ) /* TWOBYTES */ - -/* I2CFSTA[SRXFSTA] - Slave Receive FIFO status. */ -#define I2CFSTA_SRXFSTA_MSK (0x3 << 2 ) -#define I2CFSTA_SRXFSTA_EMPTY (0x0 << 2 ) /* EMPTY */ -#define I2CFSTA_SRXFSTA_ONEBYTE (0x1 << 2 ) /* ONEBYTE */ -#define I2CFSTA_SRXFSTA_TWOBYTES (0x2 << 2 ) /* TWOBYTES */ - -/* I2CFSTA[STXFSTA] - Slave Transmit FIFO status. */ -#define I2CFSTA_STXFSTA_MSK (0x3 << 0 ) -#define I2CFSTA_STXFSTA_EMPTY (0x0 << 0 ) /* EMPTY */ -#define I2CFSTA_STXFSTA_ONEBYTE (0x1 << 0 ) /* ONEBYTE */ -#define I2CFSTA_STXFSTA_TWOBYTES (0x2 << 0 ) /* TWOBYTES */ -// ------------------------------------------------------------------------------------------------ -// ----- INTERRUPT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Interrupts (pADI_INTERRUPT) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_INTERRUPT Structure */ - __IO uint16_t EI0CFG; /*!< External Interrupt Configuration Register 0 */ - __I uint16_t RESERVED0; - __IO uint16_t EI1CFG; /*!< External Interrupt Configuration Register 1 */ - __I uint16_t RESERVED1; - __IO uint16_t EI2CFG; /*!< External Interrupt Configuration Register 2 */ - __I uint16_t RESERVED2[3]; - __IO uint16_t EICLR; /*!< External Interrupts Clear Register */ - __I uint16_t RESERVED3; - __IO uint8_t NMICLR; /*!< NMI Clear Register */ -} ADI_INTERRUPT_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define EI0CFG (*(volatile unsigned short int *) 0x40002420) -#define EI1CFG (*(volatile unsigned short int *) 0x40002424) -#define EI2CFG (*(volatile unsigned short int *) 0x40002428) -#define EICLR (*(volatile unsigned short int *) 0x40002430) -#define NMICLR (*(volatile unsigned char *) 0x40002434) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for EI0CFG*/ -#define EI0CFG_RVAL 0x0 - -/* EI0CFG[IRQ3EN] - External interrupt 3 enable bit. */ -#define EI0CFG_IRQ3EN_BBA (*(volatile unsigned long *) 0x4204843C) -#define EI0CFG_IRQ3EN_MSK (0x1 << 15 ) -#define EI0CFG_IRQ3EN (0x1 << 15 ) -#define EI0CFG_IRQ3EN_DIS (0x0 << 15 ) /* DIS. External interrupt 3 disabled. */ -#define EI0CFG_IRQ3EN_EN (0x1 << 15 ) /* EN. External Interrupt 3 enabled. */ - -/* EI0CFG[IRQ3MDE] - External interrupt 3 detection mode. */ -#define EI0CFG_IRQ3MDE_MSK (0x7 << 12 ) -#define EI0CFG_IRQ3MDE_RISE (0x0 << 12 ) /* RISE. Rising edge. */ -#define EI0CFG_IRQ3MDE_FALL (0x1 << 12 ) /* FALL. Falling edge. */ -#define EI0CFG_IRQ3MDE_RISEORFALL (0x2 << 12 ) /* RISEORFALL. Rising or falling edge. */ -#define EI0CFG_IRQ3MDE_HIGHLEVEL (0x3 << 12 ) /* HIGHLEVEL. High level. */ -#define EI0CFG_IRQ3MDE_LOWLEVEL (0x4 << 12 ) /* LOWLEVEL. Low level. */ - -/* EI0CFG[IRQ2EN] - External interrupt 2 enable bit. */ -#define EI0CFG_IRQ2EN_BBA (*(volatile unsigned long *) 0x4204842C) -#define EI0CFG_IRQ2EN_MSK (0x1 << 11 ) -#define EI0CFG_IRQ2EN (0x1 << 11 ) -#define EI0CFG_IRQ2EN_DIS (0x0 << 11 ) /* DIS. External interrupt 2 disabled. */ -#define EI0CFG_IRQ2EN_EN (0x1 << 11 ) /* EN. External Interrupt 2 enabled. */ - -/* EI0CFG[IRQ2MDE] - External interrupt 2 detection mode. */ -#define EI0CFG_IRQ2MDE_MSK (0x7 << 8 ) -#define EI0CFG_IRQ2MDE_RISE (0x0 << 8 ) /* RISE. Rising edge. */ -#define EI0CFG_IRQ2MDE_FALL (0x1 << 8 ) /* FALL. Falling edge. */ -#define EI0CFG_IRQ2MDE_RISEORFALL (0x2 << 8 ) /* RISEORFALL. Rising or falling edge. */ -#define EI0CFG_IRQ2MDE_HIGHLEVEL (0x3 << 8 ) /* HIGHLEVEL. High level. */ -#define EI0CFG_IRQ2MDE_LOWLEVEL (0x4 << 8 ) /* LOWLEVEL. Low level. */ - -/* EI0CFG[IRQ1EN] - External interrupt 1 enable bit. */ -#define EI0CFG_IRQ1EN_BBA (*(volatile unsigned long *) 0x4204841C) -#define EI0CFG_IRQ1EN_MSK (0x1 << 7 ) -#define EI0CFG_IRQ1EN (0x1 << 7 ) -#define EI0CFG_IRQ1EN_DIS (0x0 << 7 ) /* DIS. External interrupt 1 disabled. */ -#define EI0CFG_IRQ1EN_EN (0x1 << 7 ) /* EN. External Interrupt 1 enabled. */ - -/* EI0CFG[IRQ1MDE] - External interrupt 1 detection mode. */ -#define EI0CFG_IRQ1MDE_MSK (0x7 << 4 ) -#define EI0CFG_IRQ1MDE_RISE (0x0 << 4 ) /* RISE. Rising edge. */ -#define EI0CFG_IRQ1MDE_FALL (0x1 << 4 ) /* FALL. Falling edge. */ -#define EI0CFG_IRQ1MDE_RISEORFALL (0x2 << 4 ) /* RISEORFALL. Rising or falling edge. */ -#define EI0CFG_IRQ1MDE_HIGHLEVEL (0x3 << 4 ) /* HIGHLEVEL. High level. */ -#define EI0CFG_IRQ1MDE_LOWLEVEL (0x4 << 4 ) /* LOWLEVEL. Low level. */ - -/* EI0CFG[IRQ0EN] - RF transceiver clock IRQ enable bit. */ -#define EI0CFG_IRQ0EN_BBA (*(volatile unsigned long *) 0x4204840C) -#define EI0CFG_IRQ0EN_MSK (0x1 << 3 ) -#define EI0CFG_IRQ0EN (0x1 << 3 ) -#define EI0CFG_IRQ0EN_DIS (0x0 << 3 ) /* DIS. RF transceiver clock IRQ disabled. */ -#define EI0CFG_IRQ0EN_EN (0x1 << 3 ) /* EN. RF transceiver clock IRQ enabled. */ - -/* EI0CFG[IRQ0MDE] - RF transceiver clock detection mode. */ -#define EI0CFG_IRQ0MDE_MSK (0x7 << 0 ) -#define EI0CFG_IRQ0MDE_RISE (0x0 << 0 ) /* RISE. Rising edge. */ -#define EI0CFG_IRQ0MDE_FALL (0x1 << 0 ) /* FALL. Falling edge. */ -#define EI0CFG_IRQ0MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL. Rising or falling edge. */ -#define EI0CFG_IRQ0MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL. High level. */ -#define EI0CFG_IRQ0MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL. Low level. */ - -/* Reset Value for EI1CFG*/ -#define EI1CFG_RVAL 0x0 - -/* EI1CFG[IRQ7EN] - External interrupt 7 enable bit. */ -#define EI1CFG_IRQ7EN_BBA (*(volatile unsigned long *) 0x420484BC) -#define EI1CFG_IRQ7EN_MSK (0x1 << 15 ) -#define EI1CFG_IRQ7EN (0x1 << 15 ) -#define EI1CFG_IRQ7EN_DIS (0x0 << 15 ) /* DIS. External interrupt 7 disabled. */ -#define EI1CFG_IRQ7EN_EN (0x1 << 15 ) /* EN. External interrupt 7 enabled. */ - -/* EI1CFG[IRQ7MDE] - External interrupt 7 detection mode. */ -#define EI1CFG_IRQ7MDE_MSK (0x7 << 12 ) -#define EI1CFG_IRQ7MDE_RISE (0x0 << 12 ) /* RISE. Rising edge. */ -#define EI1CFG_IRQ7MDE_FALL (0x1 << 12 ) /* FALL. Falling edge. */ -#define EI1CFG_IRQ7MDE_RISEORFALL (0x2 << 12 ) /* RISEORFALL. Rising or falling edge. */ -#define EI1CFG_IRQ7MDE_HIGHLEVEL (0x3 << 12 ) /* HIGHLEVEL. High level. */ -#define EI1CFG_IRQ7MDE_LOWLEVEL (0x4 << 12 ) /* LOWLEVEL. Low level. */ - -/* EI1CFG[IRQ6EN] - External interrupt 6 enable bit. */ -#define EI1CFG_IRQ6EN_BBA (*(volatile unsigned long *) 0x420484AC) -#define EI1CFG_IRQ6EN_MSK (0x1 << 11 ) -#define EI1CFG_IRQ6EN (0x1 << 11 ) -#define EI1CFG_IRQ6EN_DIS (0x0 << 11 ) /* DIS. External interrupt 6 disabled. */ -#define EI1CFG_IRQ6EN_EN (0x1 << 11 ) /* EN. External Interrupt 6 enabled. */ - -/* EI1CFG[IRQ6MDE] - External interrupt 6 detection mode. */ -#define EI1CFG_IRQ6MDE_MSK (0x7 << 8 ) -#define EI1CFG_IRQ6MDE_RISE (0x0 << 8 ) /* RISE. Rising edge. */ -#define EI1CFG_IRQ6MDE_FALL (0x1 << 8 ) /* FALL. Falling edge. */ -#define EI1CFG_IRQ6MDE_RISEORFALL (0x2 << 8 ) /* RISEORFALL. Rising or falling edge. */ -#define EI1CFG_IRQ6MDE_HIGHLEVEL (0x3 << 8 ) /* HIGHLEVEL. High level. */ -#define EI1CFG_IRQ6MDE_LOWLEVEL (0x4 << 8 ) /* LOWLEVEL. Low Level. */ - -/* EI1CFG[IRQ5EN] - External interrupt 5 enable bit. */ -#define EI1CFG_IRQ5EN_BBA (*(volatile unsigned long *) 0x4204849C) -#define EI1CFG_IRQ5EN_MSK (0x1 << 7 ) -#define EI1CFG_IRQ5EN (0x1 << 7 ) -#define EI1CFG_IRQ5EN_DIS (0x0 << 7 ) /* DIS. External interrupt 5 disabled. */ -#define EI1CFG_IRQ5EN_EN (0x1 << 7 ) /* EN. External Interrupt 5 enabled. */ - -/* EI1CFG[IRQ5MDE] - External interrupt 5 detection mode. */ -#define EI1CFG_IRQ5MDE_MSK (0x7 << 4 ) -#define EI1CFG_IRQ5MDE_RISE (0x0 << 4 ) /* RISE. Rising edge. */ -#define EI1CFG_IRQ5MDE_FALL (0x1 << 4 ) /* FALL. Falling edge. */ -#define EI1CFG_IRQ5MDE_RISEORFALL (0x2 << 4 ) /* RISEORFALL. Rising or falling edge. */ -#define EI1CFG_IRQ5MDE_HIGHLEVEL (0x3 << 4 ) /* HIGHLEVEL. High level. */ -#define EI1CFG_IRQ5MDE_LOWLEVEL (0x4 << 4 ) /* LOWLEVEL. Low Level. */ - -/* EI1CFG[IRQ4EN] - External interrupt 4 enable bit. */ -#define EI1CFG_IRQ4EN_BBA (*(volatile unsigned long *) 0x4204848C) -#define EI1CFG_IRQ4EN_MSK (0x1 << 3 ) -#define EI1CFG_IRQ4EN (0x1 << 3 ) -#define EI1CFG_IRQ4EN_DIS (0x0 << 3 ) /* DIS. External interrupt 4 disabled. */ -#define EI1CFG_IRQ4EN_EN (0x1 << 3 ) /* EN. External Interrupt 4 enabled. */ - -/* EI1CFG[IRQ4MDE] - External interrupt 4 detection mode. */ -#define EI1CFG_IRQ4MDE_MSK (0x7 << 0 ) -#define EI1CFG_IRQ4MDE_RISE (0x0 << 0 ) /* RISE. Rising edge. */ -#define EI1CFG_IRQ4MDE_FALL (0x1 << 0 ) /* FALL. Falling edge. */ -#define EI1CFG_IRQ4MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL. Rising or falling edge. */ -#define EI1CFG_IRQ4MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL. High level. */ -#define EI1CFG_IRQ4MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL. Low Level. */ - -/* Reset Value for EI2CFG*/ -#define EI2CFG_RVAL 0x0 - -/* EI2CFG[IRQ8EN] - RF transceiver IRQ enable bit. */ -#define EI2CFG_IRQ8EN_BBA (*(volatile unsigned long *) 0x4204850C) -#define EI2CFG_IRQ8EN_MSK (0x1 << 3 ) -#define EI2CFG_IRQ8EN (0x1 << 3 ) -#define EI2CFG_IRQ8EN_DIS (0x0 << 3 ) /* DIS. RF transceiver IRQ disabled. */ -#define EI2CFG_IRQ8EN_EN (0x1 << 3 ) /* EN. RF transceiver IRQ enabled. */ - -/* EI2CFG[IRQ8MDE] - RF transceiver IRQ detection mode. */ -#define EI2CFG_IRQ8MDE_MSK (0x7 << 0 ) -#define EI2CFG_IRQ8MDE_RISE (0x0 << 0 ) /* RISE. Rising edge. */ -#define EI2CFG_IRQ8MDE_FALL (0x1 << 0 ) /* FALL. Falling edge. */ -#define EI2CFG_IRQ8MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL. Rising or falling edge. */ -#define EI2CFG_IRQ8MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL. High level. */ -#define EI2CFG_IRQ8MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL. Low level. */ - -/* Reset Value for EICLR*/ -#define EICLR_RVAL 0x0 - -/* EICLR[IRQ8] - External interrupt 8 (RF transceiver) clear bit. */ -#define EICLR_IRQ8_BBA (*(volatile unsigned long *) 0x42048620) -#define EICLR_IRQ8_MSK (0x1 << 8 ) -#define EICLR_IRQ8 (0x1 << 8 ) -#define EICLR_IRQ8_CLR (0x1 << 8 ) /* CLR. Clear an internal interrupt flag. */ - -/* EICLR[IRQ7] - External interrupt 7 clear bit. */ -#define EICLR_IRQ7_BBA (*(volatile unsigned long *) 0x4204861C) -#define EICLR_IRQ7_MSK (0x1 << 7 ) -#define EICLR_IRQ7 (0x1 << 7 ) -#define EICLR_IRQ7_CLR (0x1 << 7 ) /* CLR. Clear an internal interrupt flag. */ - -/* EICLR[IRQ6] - External interrupt 6 clear bit. */ -#define EICLR_IRQ6_BBA (*(volatile unsigned long *) 0x42048618) -#define EICLR_IRQ6_MSK (0x1 << 6 ) -#define EICLR_IRQ6 (0x1 << 6 ) -#define EICLR_IRQ6_CLR (0x1 << 6 ) /* CLR. Clear an internal interrupt flag. */ - -/* EICLR[IRQ5] - External interrupt 5 clear bit. */ -#define EICLR_IRQ5_BBA (*(volatile unsigned long *) 0x42048614) -#define EICLR_IRQ5_MSK (0x1 << 5 ) -#define EICLR_IRQ5 (0x1 << 5 ) -#define EICLR_IRQ5_CLR (0x1 << 5 ) /* CLR. Clear an internal interrupt flag. */ - -/* EICLR[IRQ4] - External interrupt 4 clear bit. */ -#define EICLR_IRQ4_BBA (*(volatile unsigned long *) 0x42048610) -#define EICLR_IRQ4_MSK (0x1 << 4 ) -#define EICLR_IRQ4 (0x1 << 4 ) -#define EICLR_IRQ4_CLR (0x1 << 4 ) /* CLR. Clear an internal interrupt flag. */ - -/* EICLR[IRQ3] - External interrupt 3 clear bit. */ -#define EICLR_IRQ3_BBA (*(volatile unsigned long *) 0x4204860C) -#define EICLR_IRQ3_MSK (0x1 << 3 ) -#define EICLR_IRQ3 (0x1 << 3 ) -#define EICLR_IRQ3_CLR (0x1 << 3 ) /* CLR. Clear an internal interrupt flag. */ - -/* EICLR[IRQ2] - External interrupt 2 clear bit. */ -#define EICLR_IRQ2_BBA (*(volatile unsigned long *) 0x42048608) -#define EICLR_IRQ2_MSK (0x1 << 2 ) -#define EICLR_IRQ2 (0x1 << 2 ) -#define EICLR_IRQ2_CLR (0x1 << 2 ) /* CLR. Clear an internal interrupt flag. */ - -/* EICLR[IRQ1] - External interrupt 1 clear bit. */ -#define EICLR_IRQ1_BBA (*(volatile unsigned long *) 0x42048604) -#define EICLR_IRQ1_MSK (0x1 << 1 ) -#define EICLR_IRQ1 (0x1 << 1 ) -#define EICLR_IRQ1_CLR (0x1 << 1 ) /* CLR. Clear an internal interrupt flag. */ - -/* EICLR[IRQ0] - External interrupt 0 clear bit. */ -#define EICLR_IRQ0_BBA (*(volatile unsigned long *) 0x42048600) -#define EICLR_IRQ0_MSK (0x1 << 0 ) -#define EICLR_IRQ0 (0x1 << 0 ) -#define EICLR_IRQ0_CLR (0x1 << 0 ) /* CLR. Clear an internal interrupt flag. */ - -/* Reset Value for NMICLR*/ -#define NMICLR_RVAL 0x0 - -/* NMICLR[CLEAR] - NMI clear bit. */ -#define NMICLR_CLEAR_BBA (*(volatile unsigned long *) 0x42048680) -#define NMICLR_CLEAR_MSK (0x1 << 0 ) -#define NMICLR_CLEAR (0x1 << 0 ) -#define NMICLR_CLEAR_EN (0x1 << 0 ) /* EN. Clear an internal interrupt flag when the NMI interrupt is set. */ -// ------------------------------------------------------------------------------------------------ -// ----- NVIC ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Nested Vectored Interrupt Controller (pADI_NVIC) - */ - -#if (__NO_MMR_STRUCTS__==0) -#else // (__NO_MMR_STRUCTS__==0) -#define ICTR (*(volatile unsigned long *) 0xE000E004) -#define STCSR (*(volatile unsigned long *) 0xE000E010) -#define STRVR (*(volatile unsigned long *) 0xE000E014) -#define STCVR (*(volatile unsigned long *) 0xE000E018) -#define STCR (*(volatile unsigned long *) 0xE000E01C) -#define ISER0 (*(volatile unsigned long *) 0xE000E100) -#define ISER1 (*(volatile unsigned long *) 0xE000E104) -#define ICER0 (*(volatile unsigned long *) 0xE000E180) -#define ICER1 (*(volatile unsigned long *) 0xE000E184) -#define ISPR0 (*(volatile unsigned long *) 0xE000E200) -#define ISPR1 (*(volatile unsigned long *) 0xE000E204) -#define ICPR0 (*(volatile unsigned long *) 0xE000E280) -#define ICPR1 (*(volatile unsigned long *) 0xE000E284) -#define IABR0 (*(volatile unsigned long *) 0xE000E300) -#define IABR1 (*(volatile unsigned long *) 0xE000E304) -#define IPR0 (*(volatile unsigned long *) 0xE000E400) -#define IPR1 (*(volatile unsigned long *) 0xE000E404) -#define IPR2 (*(volatile unsigned long *) 0xE000E408) -#define IPR3 (*(volatile unsigned long *) 0xE000E40C) -#define IPR4 (*(volatile unsigned long *) 0xE000E410) -#define IPR5 (*(volatile unsigned long *) 0xE000E414) -#define IPR6 (*(volatile unsigned long *) 0xE000E418) -#define IPR7 (*(volatile unsigned long *) 0xE000E41C) -#define IPR8 (*(volatile unsigned long *) 0xE000E420) -#define IPR9 (*(volatile unsigned long *) 0xE000E424) -#define IPR10 (*(volatile unsigned long *) 0xE000E428) -#define CPUID (*(volatile unsigned long *) 0xE000ED00) -#define ICSR (*(volatile unsigned long *) 0xE000ED04) -#define VTOR (*(volatile unsigned long *) 0xE000ED08) -#define AIRCR (*(volatile unsigned long *) 0xE000ED0C) -#define SCR (*(volatile unsigned long *) 0xE000ED10) -#define CCR (*(volatile unsigned long *) 0xE000ED14) -#define SHPR1 (*(volatile unsigned long *) 0xE000ED18) -#define SHPR2 (*(volatile unsigned long *) 0xE000ED1C) -#define SHPR3 (*(volatile unsigned long *) 0xE000ED20) -#define SHCSR (*(volatile unsigned long *) 0xE000ED24) -#define CFSR (*(volatile unsigned long *) 0xE000ED28) -#define HFSR (*(volatile unsigned long *) 0xE000ED2C) -#define MMFAR (*(volatile unsigned long *) 0xE000ED34) -#define BFAR (*(volatile unsigned long *) 0xE000ED38) -#define STIR (*(volatile unsigned long *) 0xE000EF00) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for ICTR*/ -#define ICTR_RVAL 0x1 - -/* ICTR[INTLINESNUM] - Total number of interrupt lines in groups of 32 */ -#define ICTR_INTLINESNUM_MSK (0xF << 0 ) - -/* Reset Value for STCSR*/ -#define STCSR_RVAL 0x0 - -/* STCSR[COUNTFLAG] - Returns 1 if timer counted to 0 since last time this register was read */ -#define STCSR_COUNTFLAG_MSK (0x1 << 16 ) -#define STCSR_COUNTFLAG (0x1 << 16 ) -#define STCSR_COUNTFLAG_DIS (0x0 << 16 ) /* DIS */ -#define STCSR_COUNTFLAG_EN (0x1 << 16 ) /* EN */ - -/* STCSR[CLKSOURCE] - clock source used for SysTick */ -#define STCSR_CLKSOURCE_MSK (0x1 << 2 ) -#define STCSR_CLKSOURCE (0x1 << 2 ) -#define STCSR_CLKSOURCE_DIS (0x0 << 2 ) /* DIS */ -#define STCSR_CLKSOURCE_EN (0x1 << 2 ) /* EN */ - -/* STCSR[TICKINT] - If 1, counting down to 0 will cause the SysTick exception to pended. */ -#define STCSR_TICKINT_MSK (0x1 << 1 ) -#define STCSR_TICKINT (0x1 << 1 ) -#define STCSR_TICKINT_DIS (0x0 << 1 ) /* DIS */ -#define STCSR_TICKINT_EN (0x1 << 1 ) /* EN */ - -/* STCSR[ENABLE] - Enable bit */ -#define STCSR_ENABLE_MSK (0x1 << 0 ) -#define STCSR_ENABLE (0x1 << 0 ) -#define STCSR_ENABLE_DIS (0x0 << 0 ) /* DIS */ -#define STCSR_ENABLE_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for STRVR*/ -#define STRVR_RVAL 0x0 - -/* STRVR[RELOAD] - Value to load into the Current Value register when the counter reaches 0 */ -#define STRVR_RELOAD_MSK (0xFFFFFF << 0 ) - -/* Reset Value for STCVR*/ -#define STCVR_RVAL 0x0 - -/* STCVR[CURRENT] - Current counter value */ -#define STCVR_CURRENT_MSK (0xFFFFFFFF << 0 ) - -/* Reset Value for STCR*/ -#define STCR_RVAL 0x0 - -/* STCR[NOREF] - If reads as 1, the Reference clock is not provided */ -#define STCR_NOREF_MSK (0x1 << 31 ) -#define STCR_NOREF (0x1 << 31 ) -#define STCR_NOREF_DIS (0x0 << 31 ) /* DIS */ -#define STCR_NOREF_EN (0x1 << 31 ) /* EN */ - -/* STCR[SKEW] - If reads as 1, the calibration value for 10ms is inexact */ -#define STCR_SKEW_MSK (0x1 << 30 ) -#define STCR_SKEW (0x1 << 30 ) -#define STCR_SKEW_DIS (0x0 << 30 ) /* DIS */ -#define STCR_SKEW_EN (0x1 << 30 ) /* EN */ - -/* STCR[TENMS] - An optional Reload value to be used for 10ms (100Hz) timing */ -#define STCR_TENMS_MSK (0xFFFFFF << 0 ) - -/* Reset Value for ISER0*/ -#define ISER0_RVAL 0x0 - -/* ISER0[DMAI2CMRX] - */ -#define ISER0_DMAI2CMRX_MSK (0x1 << 30 ) -#define ISER0_DMAI2CMRX (0x1 << 30 ) -#define ISER0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */ -#define ISER0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */ - -/* ISER0[DMAI2CMTX] - */ -#define ISER0_DMAI2CMTX_MSK (0x1 << 29 ) -#define ISER0_DMAI2CMTX (0x1 << 29 ) -#define ISER0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */ -#define ISER0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */ - -/* ISER0[DMAI2CSRX] - */ -#define ISER0_DMAI2CSRX_MSK (0x1 << 28 ) -#define ISER0_DMAI2CSRX (0x1 << 28 ) -#define ISER0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */ -#define ISER0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */ - -/* ISER0[DMAI2CSTX] - */ -#define ISER0_DMAI2CSTX_MSK (0x1 << 27 ) -#define ISER0_DMAI2CSTX (0x1 << 27 ) -#define ISER0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */ -#define ISER0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */ - -/* ISER0[DMAUARTRX] - */ -#define ISER0_DMAUARTRX_MSK (0x1 << 26 ) -#define ISER0_DMAUARTRX (0x1 << 26 ) -#define ISER0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */ -#define ISER0_DMAUARTRX_EN (0x1 << 26 ) /* EN */ - -/* ISER0[DMAUARTTX] - */ -#define ISER0_DMAUARTTX_MSK (0x1 << 25 ) -#define ISER0_DMAUARTTX (0x1 << 25 ) -#define ISER0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */ -#define ISER0_DMAUARTTX_EN (0x1 << 25 ) /* EN */ - -/* ISER0[DMASPI1RX] - */ -#define ISER0_DMASPI1RX_MSK (0x1 << 24 ) -#define ISER0_DMASPI1RX (0x1 << 24 ) -#define ISER0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */ -#define ISER0_DMASPI1RX_EN (0x1 << 24 ) /* EN */ - -/* ISER0[DMASPI1TX] - */ -#define ISER0_DMASPI1TX_MSK (0x1 << 23 ) -#define ISER0_DMASPI1TX (0x1 << 23 ) -#define ISER0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */ -#define ISER0_DMASPI1TX_EN (0x1 << 23 ) /* EN */ - -/* ISER0[DMAERROR] - */ -#define ISER0_DMAERROR_MSK (0x1 << 22 ) -#define ISER0_DMAERROR (0x1 << 22 ) -#define ISER0_DMAERROR_DIS (0x0 << 22 ) /* DIS */ -#define ISER0_DMAERROR_EN (0x1 << 22 ) /* EN */ - -/* ISER0[I2CM] - */ -#define ISER0_I2CM_MSK (0x1 << 20 ) -#define ISER0_I2CM (0x1 << 20 ) -#define ISER0_I2CM_DIS (0x0 << 20 ) /* DIS */ -#define ISER0_I2CM_EN (0x1 << 20 ) /* EN */ - -/* ISER0[I2CS] - */ -#define ISER0_I2CS_MSK (0x1 << 19 ) -#define ISER0_I2CS (0x1 << 19 ) -#define ISER0_I2CS_DIS (0x0 << 19 ) /* DIS */ -#define ISER0_I2CS_EN (0x1 << 19 ) /* EN */ - -/* ISER0[SPI1] - */ -#define ISER0_SPI1_MSK (0x1 << 18 ) -#define ISER0_SPI1 (0x1 << 18 ) -#define ISER0_SPI1_DIS (0x0 << 18 ) /* DIS */ -#define ISER0_SPI1_EN (0x1 << 18 ) /* EN */ - -/* ISER0[SPI0] - */ -#define ISER0_SPI0_MSK (0x1 << 17 ) -#define ISER0_SPI0 (0x1 << 17 ) -#define ISER0_SPI0_DIS (0x0 << 17 ) /* DIS */ -#define ISER0_SPI0_EN (0x1 << 17 ) /* EN */ - -/* ISER0[UART] - */ -#define ISER0_UART_MSK (0x1 << 16 ) -#define ISER0_UART (0x1 << 16 ) -#define ISER0_UART_DIS (0x0 << 16 ) /* DIS */ -#define ISER0_UART_EN (0x1 << 16 ) /* EN */ - -/* ISER0[FEE] - */ -#define ISER0_FEE_MSK (0x1 << 15 ) -#define ISER0_FEE (0x1 << 15 ) -#define ISER0_FEE_DIS (0x0 << 15 ) /* DIS */ -#define ISER0_FEE_EN (0x1 << 15 ) /* EN */ - -/* ISER0[ADC] - */ -#define ISER0_ADC_MSK (0x1 << 14 ) -#define ISER0_ADC (0x1 << 14 ) -#define ISER0_ADC_DIS (0x0 << 14 ) /* DIS */ -#define ISER0_ADC_EN (0x1 << 14 ) /* EN */ - -/* ISER0[T1] - */ -#define ISER0_T1_MSK (0x1 << 13 ) -#define ISER0_T1 (0x1 << 13 ) -#define ISER0_T1_DIS (0x0 << 13 ) /* DIS */ -#define ISER0_T1_EN (0x1 << 13 ) /* EN */ - -/* ISER0[T0] - */ -#define ISER0_T0_MSK (0x1 << 12 ) -#define ISER0_T0 (0x1 << 12 ) -#define ISER0_T0_DIS (0x0 << 12 ) /* DIS */ -#define ISER0_T0_EN (0x1 << 12 ) /* EN */ - -/* ISER0[T3] - */ -#define ISER0_T3_MSK (0x1 << 10 ) -#define ISER0_T3 (0x1 << 10 ) -#define ISER0_T3_DIS (0x0 << 10 ) /* DIS */ -#define ISER0_T3_EN (0x1 << 10 ) /* EN */ - -/* ISER0[EXTINT8] - */ -#define ISER0_EXTINT8_MSK (0x1 << 9 ) -#define ISER0_EXTINT8 (0x1 << 9 ) -#define ISER0_EXTINT8_DIS (0x0 << 9 ) /* DIS */ -#define ISER0_EXTINT8_EN (0x1 << 9 ) /* EN */ - -/* ISER0[EXTINT7] - */ -#define ISER0_EXTINT7_MSK (0x1 << 8 ) -#define ISER0_EXTINT7 (0x1 << 8 ) -#define ISER0_EXTINT7_DIS (0x0 << 8 ) /* DIS */ -#define ISER0_EXTINT7_EN (0x1 << 8 ) /* EN */ - -/* ISER0[EXTINT6] - */ -#define ISER0_EXTINT6_MSK (0x1 << 7 ) -#define ISER0_EXTINT6 (0x1 << 7 ) -#define ISER0_EXTINT6_DIS (0x0 << 7 ) /* DIS */ -#define ISER0_EXTINT6_EN (0x1 << 7 ) /* EN */ - -/* ISER0[EXTINT5] - */ -#define ISER0_EXTINT5_MSK (0x1 << 6 ) -#define ISER0_EXTINT5 (0x1 << 6 ) -#define ISER0_EXTINT5_DIS (0x0 << 6 ) /* DIS */ -#define ISER0_EXTINT5_EN (0x1 << 6 ) /* EN */ - -/* ISER0[EXTINT4] - */ -#define ISER0_EXTINT4_MSK (0x1 << 5 ) -#define ISER0_EXTINT4 (0x1 << 5 ) -#define ISER0_EXTINT4_DIS (0x0 << 5 ) /* DIS */ -#define ISER0_EXTINT4_EN (0x1 << 5 ) /* EN */ - -/* ISER0[EXTINT3] - */ -#define ISER0_EXTINT3_MSK (0x1 << 4 ) -#define ISER0_EXTINT3 (0x1 << 4 ) -#define ISER0_EXTINT3_DIS (0x0 << 4 ) /* DIS */ -#define ISER0_EXTINT3_EN (0x1 << 4 ) /* EN */ - -/* ISER0[EXTINT2] - */ -#define ISER0_EXTINT2_MSK (0x1 << 3 ) -#define ISER0_EXTINT2 (0x1 << 3 ) -#define ISER0_EXTINT2_DIS (0x0 << 3 ) /* DIS */ -#define ISER0_EXTINT2_EN (0x1 << 3 ) /* EN */ - -/* ISER0[EXTINT1] - */ -#define ISER0_EXTINT1_MSK (0x1 << 2 ) -#define ISER0_EXTINT1 (0x1 << 2 ) -#define ISER0_EXTINT1_DIS (0x0 << 2 ) /* DIS */ -#define ISER0_EXTINT1_EN (0x1 << 2 ) /* EN */ - -/* ISER0[EXTINT0] - */ -#define ISER0_EXTINT0_MSK (0x1 << 1 ) -#define ISER0_EXTINT0 (0x1 << 1 ) -#define ISER0_EXTINT0_DIS (0x0 << 1 ) /* DIS */ -#define ISER0_EXTINT0_EN (0x1 << 1 ) /* EN */ - -/* ISER0[T2] - */ -#define ISER0_T2_MSK (0x1 << 0 ) -#define ISER0_T2 (0x1 << 0 ) -#define ISER0_T2_DIS (0x0 << 0 ) /* DIS */ -#define ISER0_T2_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for ISER1*/ -#define ISER1_RVAL 0x0 - -/* ISER1[PWM3] - */ -#define ISER1_PWM3_MSK (0x1 << 9 ) -#define ISER1_PWM3 (0x1 << 9 ) -#define ISER1_PWM3_DIS (0x0 << 9 ) /* DIS */ -#define ISER1_PWM3_EN (0x1 << 9 ) /* EN */ - -/* ISER1[PWM2] - */ -#define ISER1_PWM2_MSK (0x1 << 8 ) -#define ISER1_PWM2 (0x1 << 8 ) -#define ISER1_PWM2_DIS (0x0 << 8 ) /* DIS */ -#define ISER1_PWM2_EN (0x1 << 8 ) /* EN */ - -/* ISER1[PWM1] - */ -#define ISER1_PWM1_MSK (0x1 << 7 ) -#define ISER1_PWM1 (0x1 << 7 ) -#define ISER1_PWM1_DIS (0x0 << 7 ) /* DIS */ -#define ISER1_PWM1_EN (0x1 << 7 ) /* EN */ - -/* ISER1[PWM0] - */ -#define ISER1_PWM0_MSK (0x1 << 6 ) -#define ISER1_PWM0 (0x1 << 6 ) -#define ISER1_PWM0_DIS (0x0 << 6 ) /* DIS */ -#define ISER1_PWM0_EN (0x1 << 6 ) /* EN */ - -/* ISER1[PWMTRIP] - */ -#define ISER1_PWMTRIP_MSK (0x1 << 5 ) -#define ISER1_PWMTRIP (0x1 << 5 ) -#define ISER1_PWMTRIP_DIS (0x0 << 5 ) /* DIS */ -#define ISER1_PWMTRIP_EN (0x1 << 5 ) /* EN */ - -/* ISER1[DMASPI0RX] - */ -#define ISER1_DMASPI0RX_MSK (0x1 << 4 ) -#define ISER1_DMASPI0RX (0x1 << 4 ) -#define ISER1_DMASPI0RX_DIS (0x0 << 4 ) /* DIS */ -#define ISER1_DMASPI0RX_EN (0x1 << 4 ) /* EN */ - -/* ISER1[DMASPI0TX] - */ -#define ISER1_DMASPI0TX_MSK (0x1 << 3 ) -#define ISER1_DMASPI0TX (0x1 << 3 ) -#define ISER1_DMASPI0TX_DIS (0x0 << 3 ) /* DIS */ -#define ISER1_DMASPI0TX_EN (0x1 << 3 ) /* EN */ - -/* ISER1[DMAADC] - */ -#define ISER1_DMAADC_MSK (0x1 << 2 ) -#define ISER1_DMAADC (0x1 << 2 ) -#define ISER1_DMAADC_DIS (0x0 << 2 ) /* DIS */ -#define ISER1_DMAADC_EN (0x1 << 2 ) /* EN */ - -/* Reset Value for ICER0*/ -#define ICER0_RVAL 0x0 - -/* ICER0[DMAI2CMRX] - */ -#define ICER0_DMAI2CMRX_MSK (0x1 << 30 ) -#define ICER0_DMAI2CMRX (0x1 << 30 ) -#define ICER0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */ -#define ICER0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */ - -/* ICER0[DMAI2CMTX] - */ -#define ICER0_DMAI2CMTX_MSK (0x1 << 29 ) -#define ICER0_DMAI2CMTX (0x1 << 29 ) -#define ICER0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */ -#define ICER0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */ - -/* ICER0[DMAI2CSRX] - */ -#define ICER0_DMAI2CSRX_MSK (0x1 << 28 ) -#define ICER0_DMAI2CSRX (0x1 << 28 ) -#define ICER0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */ -#define ICER0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */ - -/* ICER0[DMAI2CSTX] - */ -#define ICER0_DMAI2CSTX_MSK (0x1 << 27 ) -#define ICER0_DMAI2CSTX (0x1 << 27 ) -#define ICER0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */ -#define ICER0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */ - -/* ICER0[DMAUARTRX] - */ -#define ICER0_DMAUARTRX_MSK (0x1 << 26 ) -#define ICER0_DMAUARTRX (0x1 << 26 ) -#define ICER0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */ -#define ICER0_DMAUARTRX_EN (0x1 << 26 ) /* EN */ - -/* ICER0[DMAUARTTX] - */ -#define ICER0_DMAUARTTX_MSK (0x1 << 25 ) -#define ICER0_DMAUARTTX (0x1 << 25 ) -#define ICER0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */ -#define ICER0_DMAUARTTX_EN (0x1 << 25 ) /* EN */ - -/* ICER0[DMASPI1RX] - */ -#define ICER0_DMASPI1RX_MSK (0x1 << 24 ) -#define ICER0_DMASPI1RX (0x1 << 24 ) -#define ICER0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */ -#define ICER0_DMASPI1RX_EN (0x1 << 24 ) /* EN */ - -/* ICER0[DMASPI1TX] - */ -#define ICER0_DMASPI1TX_MSK (0x1 << 23 ) -#define ICER0_DMASPI1TX (0x1 << 23 ) -#define ICER0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */ -#define ICER0_DMASPI1TX_EN (0x1 << 23 ) /* EN */ - -/* ICER0[DMAERROR] - */ -#define ICER0_DMAERROR_MSK (0x1 << 22 ) -#define ICER0_DMAERROR (0x1 << 22 ) -#define ICER0_DMAERROR_DIS (0x0 << 22 ) /* DIS */ -#define ICER0_DMAERROR_EN (0x1 << 22 ) /* EN */ - -/* ICER0[I2CM] - */ -#define ICER0_I2CM_MSK (0x1 << 20 ) -#define ICER0_I2CM (0x1 << 20 ) -#define ICER0_I2CM_DIS (0x0 << 20 ) /* DIS */ -#define ICER0_I2CM_EN (0x1 << 20 ) /* EN */ - -/* ICER0[I2CS] - */ -#define ICER0_I2CS_MSK (0x1 << 19 ) -#define ICER0_I2CS (0x1 << 19 ) -#define ICER0_I2CS_DIS (0x0 << 19 ) /* DIS */ -#define ICER0_I2CS_EN (0x1 << 19 ) /* EN */ - -/* ICER0[SPI1] - */ -#define ICER0_SPI1_MSK (0x1 << 18 ) -#define ICER0_SPI1 (0x1 << 18 ) -#define ICER0_SPI1_DIS (0x0 << 18 ) /* DIS */ -#define ICER0_SPI1_EN (0x1 << 18 ) /* EN */ - -/* ICER0[SPI0] - */ -#define ICER0_SPI0_MSK (0x1 << 17 ) -#define ICER0_SPI0 (0x1 << 17 ) -#define ICER0_SPI0_DIS (0x0 << 17 ) /* DIS */ -#define ICER0_SPI0_EN (0x1 << 17 ) /* EN */ - -/* ICER0[UART] - */ -#define ICER0_UART_MSK (0x1 << 16 ) -#define ICER0_UART (0x1 << 16 ) -#define ICER0_UART_DIS (0x0 << 16 ) /* DIS */ -#define ICER0_UART_EN (0x1 << 16 ) /* EN */ - -/* ICER0[FEE] - */ -#define ICER0_FEE_MSK (0x1 << 15 ) -#define ICER0_FEE (0x1 << 15 ) -#define ICER0_FEE_DIS (0x0 << 15 ) /* DIS */ -#define ICER0_FEE_EN (0x1 << 15 ) /* EN */ - -/* ICER0[ADC] - */ -#define ICER0_ADC_MSK (0x1 << 14 ) -#define ICER0_ADC (0x1 << 14 ) -#define ICER0_ADC_DIS (0x0 << 14 ) /* DIS */ -#define ICER0_ADC_EN (0x1 << 14 ) /* EN */ - -/* ICER0[T1] - */ -#define ICER0_T1_MSK (0x1 << 13 ) -#define ICER0_T1 (0x1 << 13 ) -#define ICER0_T1_DIS (0x0 << 13 ) /* DIS */ -#define ICER0_T1_EN (0x1 << 13 ) /* EN */ - -/* ICER0[T0] - */ -#define ICER0_T0_MSK (0x1 << 12 ) -#define ICER0_T0 (0x1 << 12 ) -#define ICER0_T0_DIS (0x0 << 12 ) /* DIS */ -#define ICER0_T0_EN (0x1 << 12 ) /* EN */ - -/* ICER0[T3] - */ -#define ICER0_T3_MSK (0x1 << 10 ) -#define ICER0_T3 (0x1 << 10 ) -#define ICER0_T3_DIS (0x0 << 10 ) /* DIS */ -#define ICER0_T3_EN (0x1 << 10 ) /* EN */ - -/* ICER0[EXTINT8] - */ -#define ICER0_EXTINT8_MSK (0x1 << 9 ) -#define ICER0_EXTINT8 (0x1 << 9 ) -#define ICER0_EXTINT8_DIS (0x0 << 9 ) /* DIS */ -#define ICER0_EXTINT8_EN (0x1 << 9 ) /* EN */ - -/* ICER0[EXTINT7] - */ -#define ICER0_EXTINT7_MSK (0x1 << 8 ) -#define ICER0_EXTINT7 (0x1 << 8 ) -#define ICER0_EXTINT7_DIS (0x0 << 8 ) /* DIS */ -#define ICER0_EXTINT7_EN (0x1 << 8 ) /* EN */ - -/* ICER0[EXTINT6] - */ -#define ICER0_EXTINT6_MSK (0x1 << 7 ) -#define ICER0_EXTINT6 (0x1 << 7 ) -#define ICER0_EXTINT6_DIS (0x0 << 7 ) /* DIS */ -#define ICER0_EXTINT6_EN (0x1 << 7 ) /* EN */ - -/* ICER0[EXTINT5] - */ -#define ICER0_EXTINT5_MSK (0x1 << 6 ) -#define ICER0_EXTINT5 (0x1 << 6 ) -#define ICER0_EXTINT5_DIS (0x0 << 6 ) /* DIS */ -#define ICER0_EXTINT5_EN (0x1 << 6 ) /* EN */ - -/* ICER0[EXTINT4] - */ -#define ICER0_EXTINT4_MSK (0x1 << 5 ) -#define ICER0_EXTINT4 (0x1 << 5 ) -#define ICER0_EXTINT4_DIS (0x0 << 5 ) /* DIS */ -#define ICER0_EXTINT4_EN (0x1 << 5 ) /* EN */ - -/* ICER0[EXTINT3] - */ -#define ICER0_EXTINT3_MSK (0x1 << 4 ) -#define ICER0_EXTINT3 (0x1 << 4 ) -#define ICER0_EXTINT3_DIS (0x0 << 4 ) /* DIS */ -#define ICER0_EXTINT3_EN (0x1 << 4 ) /* EN */ - -/* ICER0[EXTINT2] - */ -#define ICER0_EXTINT2_MSK (0x1 << 3 ) -#define ICER0_EXTINT2 (0x1 << 3 ) -#define ICER0_EXTINT2_DIS (0x0 << 3 ) /* DIS */ -#define ICER0_EXTINT2_EN (0x1 << 3 ) /* EN */ - -/* ICER0[EXTINT1] - */ -#define ICER0_EXTINT1_MSK (0x1 << 2 ) -#define ICER0_EXTINT1 (0x1 << 2 ) -#define ICER0_EXTINT1_DIS (0x0 << 2 ) /* DIS */ -#define ICER0_EXTINT1_EN (0x1 << 2 ) /* EN */ - -/* ICER0[EXTINT0] - */ -#define ICER0_EXTINT0_MSK (0x1 << 1 ) -#define ICER0_EXTINT0 (0x1 << 1 ) -#define ICER0_EXTINT0_DIS (0x0 << 1 ) /* DIS */ -#define ICER0_EXTINT0_EN (0x1 << 1 ) /* EN */ - -/* ICER0[T2] - */ -#define ICER0_T2_MSK (0x1 << 0 ) -#define ICER0_T2 (0x1 << 0 ) -#define ICER0_T2_DIS (0x0 << 0 ) /* DIS */ -#define ICER0_T2_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for ICER1*/ -#define ICER1_RVAL 0x0 - -/* ICER1[PWM3] - */ -#define ICER1_PWM3_MSK (0x1 << 9 ) -#define ICER1_PWM3 (0x1 << 9 ) -#define ICER1_PWM3_DIS (0x0 << 9 ) /* DIS */ -#define ICER1_PWM3_EN (0x1 << 9 ) /* EN */ - -/* ICER1[PWM2] - */ -#define ICER1_PWM2_MSK (0x1 << 8 ) -#define ICER1_PWM2 (0x1 << 8 ) -#define ICER1_PWM2_DIS (0x0 << 8 ) /* DIS */ -#define ICER1_PWM2_EN (0x1 << 8 ) /* EN */ - -/* ICER1[PWM1] - */ -#define ICER1_PWM1_MSK (0x1 << 7 ) -#define ICER1_PWM1 (0x1 << 7 ) -#define ICER1_PWM1_DIS (0x0 << 7 ) /* DIS */ -#define ICER1_PWM1_EN (0x1 << 7 ) /* EN */ - -/* ICER1[PWM0] - */ -#define ICER1_PWM0_MSK (0x1 << 6 ) -#define ICER1_PWM0 (0x1 << 6 ) -#define ICER1_PWM0_DIS (0x0 << 6 ) /* DIS */ -#define ICER1_PWM0_EN (0x1 << 6 ) /* EN */ - -/* ICER1[PWMTRIP] - */ -#define ICER1_PWMTRIP_MSK (0x1 << 5 ) -#define ICER1_PWMTRIP (0x1 << 5 ) -#define ICER1_PWMTRIP_DIS (0x0 << 5 ) /* DIS */ -#define ICER1_PWMTRIP_EN (0x1 << 5 ) /* EN */ - -/* ICER1[DMASPI0RX] - */ -#define ICER1_DMASPI0RX_MSK (0x1 << 4 ) -#define ICER1_DMASPI0RX (0x1 << 4 ) -#define ICER1_DMASPI0RX_DIS (0x0 << 4 ) /* DIS */ -#define ICER1_DMASPI0RX_EN (0x1 << 4 ) /* EN */ - -/* ICER1[DMASPI0TX] - */ -#define ICER1_DMASPI0TX_MSK (0x1 << 3 ) -#define ICER1_DMASPI0TX (0x1 << 3 ) -#define ICER1_DMASPI0TX_DIS (0x0 << 3 ) /* DIS */ -#define ICER1_DMASPI0TX_EN (0x1 << 3 ) /* EN */ - -/* ICER1[DMAADC] - */ -#define ICER1_DMAADC_MSK (0x1 << 2 ) -#define ICER1_DMAADC (0x1 << 2 ) -#define ICER1_DMAADC_DIS (0x0 << 2 ) /* DIS */ -#define ICER1_DMAADC_EN (0x1 << 2 ) /* EN */ - -/* Reset Value for ISPR0*/ -#define ISPR0_RVAL 0x0 - -/* ISPR0[DMAI2CMRX] - */ -#define ISPR0_DMAI2CMRX_MSK (0x1 << 30 ) -#define ISPR0_DMAI2CMRX (0x1 << 30 ) -#define ISPR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */ -#define ISPR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */ - -/* ISPR0[DMAI2CMTX] - */ -#define ISPR0_DMAI2CMTX_MSK (0x1 << 29 ) -#define ISPR0_DMAI2CMTX (0x1 << 29 ) -#define ISPR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */ -#define ISPR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */ - -/* ISPR0[DMAI2CSRX] - */ -#define ISPR0_DMAI2CSRX_MSK (0x1 << 28 ) -#define ISPR0_DMAI2CSRX (0x1 << 28 ) -#define ISPR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */ -#define ISPR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */ - -/* ISPR0[DMAI2CSTX] - */ -#define ISPR0_DMAI2CSTX_MSK (0x1 << 27 ) -#define ISPR0_DMAI2CSTX (0x1 << 27 ) -#define ISPR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */ -#define ISPR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */ - -/* ISPR0[DMAUARTRX] - */ -#define ISPR0_DMAUARTRX_MSK (0x1 << 26 ) -#define ISPR0_DMAUARTRX (0x1 << 26 ) -#define ISPR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */ -#define ISPR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */ - -/* ISPR0[DMAUARTTX] - */ -#define ISPR0_DMAUARTTX_MSK (0x1 << 25 ) -#define ISPR0_DMAUARTTX (0x1 << 25 ) -#define ISPR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */ -#define ISPR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */ - -/* ISPR0[DMASPI1RX] - */ -#define ISPR0_DMASPI1RX_MSK (0x1 << 24 ) -#define ISPR0_DMASPI1RX (0x1 << 24 ) -#define ISPR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */ -#define ISPR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */ - -/* ISPR0[DMASPI1TX] - */ -#define ISPR0_DMASPI1TX_MSK (0x1 << 23 ) -#define ISPR0_DMASPI1TX (0x1 << 23 ) -#define ISPR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */ -#define ISPR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */ - -/* ISPR0[DMAERROR] - */ -#define ISPR0_DMAERROR_MSK (0x1 << 22 ) -#define ISPR0_DMAERROR (0x1 << 22 ) -#define ISPR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */ -#define ISPR0_DMAERROR_EN (0x1 << 22 ) /* EN */ - -/* ISPR0[I2CM] - */ -#define ISPR0_I2CM_MSK (0x1 << 20 ) -#define ISPR0_I2CM (0x1 << 20 ) -#define ISPR0_I2CM_DIS (0x0 << 20 ) /* DIS */ -#define ISPR0_I2CM_EN (0x1 << 20 ) /* EN */ - -/* ISPR0[I2CS] - */ -#define ISPR0_I2CS_MSK (0x1 << 19 ) -#define ISPR0_I2CS (0x1 << 19 ) -#define ISPR0_I2CS_DIS (0x0 << 19 ) /* DIS */ -#define ISPR0_I2CS_EN (0x1 << 19 ) /* EN */ - -/* ISPR0[SPI1] - */ -#define ISPR0_SPI1_MSK (0x1 << 18 ) -#define ISPR0_SPI1 (0x1 << 18 ) -#define ISPR0_SPI1_DIS (0x0 << 18 ) /* DIS */ -#define ISPR0_SPI1_EN (0x1 << 18 ) /* EN */ - -/* ISPR0[SPI0] - */ -#define ISPR0_SPI0_MSK (0x1 << 17 ) -#define ISPR0_SPI0 (0x1 << 17 ) -#define ISPR0_SPI0_DIS (0x0 << 17 ) /* DIS */ -#define ISPR0_SPI0_EN (0x1 << 17 ) /* EN */ - -/* ISPR0[UART] - */ -#define ISPR0_UART_MSK (0x1 << 16 ) -#define ISPR0_UART (0x1 << 16 ) -#define ISPR0_UART_DIS (0x0 << 16 ) /* DIS */ -#define ISPR0_UART_EN (0x1 << 16 ) /* EN */ - -/* ISPR0[FEE] - */ -#define ISPR0_FEE_MSK (0x1 << 15 ) -#define ISPR0_FEE (0x1 << 15 ) -#define ISPR0_FEE_DIS (0x0 << 15 ) /* DIS */ -#define ISPR0_FEE_EN (0x1 << 15 ) /* EN */ - -/* ISPR0[ADC] - */ -#define ISPR0_ADC_MSK (0x1 << 14 ) -#define ISPR0_ADC (0x1 << 14 ) -#define ISPR0_ADC_DIS (0x0 << 14 ) /* DIS */ -#define ISPR0_ADC_EN (0x1 << 14 ) /* EN */ - -/* ISPR0[T1] - */ -#define ISPR0_T1_MSK (0x1 << 13 ) -#define ISPR0_T1 (0x1 << 13 ) -#define ISPR0_T1_DIS (0x0 << 13 ) /* DIS */ -#define ISPR0_T1_EN (0x1 << 13 ) /* EN */ - -/* ISPR0[T0] - */ -#define ISPR0_T0_MSK (0x1 << 12 ) -#define ISPR0_T0 (0x1 << 12 ) -#define ISPR0_T0_DIS (0x0 << 12 ) /* DIS */ -#define ISPR0_T0_EN (0x1 << 12 ) /* EN */ - -/* ISPR0[T3] - */ -#define ISPR0_T3_MSK (0x1 << 10 ) -#define ISPR0_T3 (0x1 << 10 ) -#define ISPR0_T3_DIS (0x0 << 10 ) /* DIS */ -#define ISPR0_T3_EN (0x1 << 10 ) /* EN */ - -/* ISPR0[EXTINT8] - */ -#define ISPR0_EXTINT8_MSK (0x1 << 9 ) -#define ISPR0_EXTINT8 (0x1 << 9 ) -#define ISPR0_EXTINT8_DIS (0x0 << 9 ) /* DIS */ -#define ISPR0_EXTINT8_EN (0x1 << 9 ) /* EN */ - -/* ISPR0[EXTINT7] - */ -#define ISPR0_EXTINT7_MSK (0x1 << 8 ) -#define ISPR0_EXTINT7 (0x1 << 8 ) -#define ISPR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */ -#define ISPR0_EXTINT7_EN (0x1 << 8 ) /* EN */ - -/* ISPR0[EXTINT6] - */ -#define ISPR0_EXTINT6_MSK (0x1 << 7 ) -#define ISPR0_EXTINT6 (0x1 << 7 ) -#define ISPR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */ -#define ISPR0_EXTINT6_EN (0x1 << 7 ) /* EN */ - -/* ISPR0[EXTINT5] - */ -#define ISPR0_EXTINT5_MSK (0x1 << 6 ) -#define ISPR0_EXTINT5 (0x1 << 6 ) -#define ISPR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */ -#define ISPR0_EXTINT5_EN (0x1 << 6 ) /* EN */ - -/* ISPR0[EXTINT4] - */ -#define ISPR0_EXTINT4_MSK (0x1 << 5 ) -#define ISPR0_EXTINT4 (0x1 << 5 ) -#define ISPR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */ -#define ISPR0_EXTINT4_EN (0x1 << 5 ) /* EN */ - -/* ISPR0[EXTINT3] - */ -#define ISPR0_EXTINT3_MSK (0x1 << 4 ) -#define ISPR0_EXTINT3 (0x1 << 4 ) -#define ISPR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */ -#define ISPR0_EXTINT3_EN (0x1 << 4 ) /* EN */ - -/* ISPR0[EXTINT2] - */ -#define ISPR0_EXTINT2_MSK (0x1 << 3 ) -#define ISPR0_EXTINT2 (0x1 << 3 ) -#define ISPR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */ -#define ISPR0_EXTINT2_EN (0x1 << 3 ) /* EN */ - -/* ISPR0[EXTINT1] - */ -#define ISPR0_EXTINT1_MSK (0x1 << 2 ) -#define ISPR0_EXTINT1 (0x1 << 2 ) -#define ISPR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */ -#define ISPR0_EXTINT1_EN (0x1 << 2 ) /* EN */ - -/* ISPR0[EXTINT0] - */ -#define ISPR0_EXTINT0_MSK (0x1 << 1 ) -#define ISPR0_EXTINT0 (0x1 << 1 ) -#define ISPR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */ -#define ISPR0_EXTINT0_EN (0x1 << 1 ) /* EN */ - -/* ISPR0[T2] - */ -#define ISPR0_T2_MSK (0x1 << 0 ) -#define ISPR0_T2 (0x1 << 0 ) -#define ISPR0_T2_DIS (0x0 << 0 ) /* DIS */ -#define ISPR0_T2_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for ISPR1*/ -#define ISPR1_RVAL 0x0 - -/* ISPR1[PWM3] - */ -#define ISPR1_PWM3_MSK (0x1 << 9 ) -#define ISPR1_PWM3 (0x1 << 9 ) -#define ISPR1_PWM3_DIS (0x0 << 9 ) /* DIS */ -#define ISPR1_PWM3_EN (0x1 << 9 ) /* EN */ - -/* ISPR1[PWM2] - */ -#define ISPR1_PWM2_MSK (0x1 << 8 ) -#define ISPR1_PWM2 (0x1 << 8 ) -#define ISPR1_PWM2_DIS (0x0 << 8 ) /* DIS */ -#define ISPR1_PWM2_EN (0x1 << 8 ) /* EN */ - -/* ISPR1[PWM1] - */ -#define ISPR1_PWM1_MSK (0x1 << 7 ) -#define ISPR1_PWM1 (0x1 << 7 ) -#define ISPR1_PWM1_DIS (0x0 << 7 ) /* DIS */ -#define ISPR1_PWM1_EN (0x1 << 7 ) /* EN */ - -/* ISPR1[PWM0] - */ -#define ISPR1_PWM0_MSK (0x1 << 6 ) -#define ISPR1_PWM0 (0x1 << 6 ) -#define ISPR1_PWM0_DIS (0x0 << 6 ) /* DIS */ -#define ISPR1_PWM0_EN (0x1 << 6 ) /* EN */ - -/* ISPR1[PWMTRIP] - */ -#define ISPR1_PWMTRIP_MSK (0x1 << 5 ) -#define ISPR1_PWMTRIP (0x1 << 5 ) -#define ISPR1_PWMTRIP_DIS (0x0 << 5 ) /* DIS */ -#define ISPR1_PWMTRIP_EN (0x1 << 5 ) /* EN */ - -/* ISPR1[DMASPI0RX] - */ -#define ISPR1_DMASPI0RX_MSK (0x1 << 4 ) -#define ISPR1_DMASPI0RX (0x1 << 4 ) -#define ISPR1_DMASPI0RX_DIS (0x0 << 4 ) /* DIS */ -#define ISPR1_DMASPI0RX_EN (0x1 << 4 ) /* EN */ - -/* ISPR1[DMASPI0TX] - */ -#define ISPR1_DMASPI0TX_MSK (0x1 << 3 ) -#define ISPR1_DMASPI0TX (0x1 << 3 ) -#define ISPR1_DMASPI0TX_DIS (0x0 << 3 ) /* DIS */ -#define ISPR1_DMASPI0TX_EN (0x1 << 3 ) /* EN */ - -/* ISPR1[DMAADC] - */ -#define ISPR1_DMAADC_MSK (0x1 << 2 ) -#define ISPR1_DMAADC (0x1 << 2 ) -#define ISPR1_DMAADC_DIS (0x0 << 2 ) /* DIS */ -#define ISPR1_DMAADC_EN (0x1 << 2 ) /* EN */ - -/* Reset Value for ICPR0*/ -#define ICPR0_RVAL 0x0 - -/* ICPR0[DMAI2CMRX] - */ -#define ICPR0_DMAI2CMRX_MSK (0x1 << 30 ) -#define ICPR0_DMAI2CMRX (0x1 << 30 ) -#define ICPR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */ -#define ICPR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */ - -/* ICPR0[DMAI2CMTX] - */ -#define ICPR0_DMAI2CMTX_MSK (0x1 << 29 ) -#define ICPR0_DMAI2CMTX (0x1 << 29 ) -#define ICPR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */ -#define ICPR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */ - -/* ICPR0[DMAI2CSRX] - */ -#define ICPR0_DMAI2CSRX_MSK (0x1 << 28 ) -#define ICPR0_DMAI2CSRX (0x1 << 28 ) -#define ICPR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */ -#define ICPR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */ - -/* ICPR0[DMAI2CSTX] - */ -#define ICPR0_DMAI2CSTX_MSK (0x1 << 27 ) -#define ICPR0_DMAI2CSTX (0x1 << 27 ) -#define ICPR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */ -#define ICPR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */ - -/* ICPR0[DMAUARTRX] - */ -#define ICPR0_DMAUARTRX_MSK (0x1 << 26 ) -#define ICPR0_DMAUARTRX (0x1 << 26 ) -#define ICPR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */ -#define ICPR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */ - -/* ICPR0[DMAUARTTX] - */ -#define ICPR0_DMAUARTTX_MSK (0x1 << 25 ) -#define ICPR0_DMAUARTTX (0x1 << 25 ) -#define ICPR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */ -#define ICPR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */ - -/* ICPR0[DMASPI1RX] - */ -#define ICPR0_DMASPI1RX_MSK (0x1 << 24 ) -#define ICPR0_DMASPI1RX (0x1 << 24 ) -#define ICPR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */ -#define ICPR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */ - -/* ICPR0[DMASPI1TX] - */ -#define ICPR0_DMASPI1TX_MSK (0x1 << 23 ) -#define ICPR0_DMASPI1TX (0x1 << 23 ) -#define ICPR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */ -#define ICPR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */ - -/* ICPR0[DMAERROR] - */ -#define ICPR0_DMAERROR_MSK (0x1 << 22 ) -#define ICPR0_DMAERROR (0x1 << 22 ) -#define ICPR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */ -#define ICPR0_DMAERROR_EN (0x1 << 22 ) /* EN */ - -/* ICPR0[I2CM] - */ -#define ICPR0_I2CM_MSK (0x1 << 20 ) -#define ICPR0_I2CM (0x1 << 20 ) -#define ICPR0_I2CM_DIS (0x0 << 20 ) /* DIS */ -#define ICPR0_I2CM_EN (0x1 << 20 ) /* EN */ - -/* ICPR0[I2CS] - */ -#define ICPR0_I2CS_MSK (0x1 << 19 ) -#define ICPR0_I2CS (0x1 << 19 ) -#define ICPR0_I2CS_DIS (0x0 << 19 ) /* DIS */ -#define ICPR0_I2CS_EN (0x1 << 19 ) /* EN */ - -/* ICPR0[SPI1] - */ -#define ICPR0_SPI1_MSK (0x1 << 18 ) -#define ICPR0_SPI1 (0x1 << 18 ) -#define ICPR0_SPI1_DIS (0x0 << 18 ) /* DIS */ -#define ICPR0_SPI1_EN (0x1 << 18 ) /* EN */ - -/* ICPR0[SPI0] - */ -#define ICPR0_SPI0_MSK (0x1 << 17 ) -#define ICPR0_SPI0 (0x1 << 17 ) -#define ICPR0_SPI0_DIS (0x0 << 17 ) /* DIS */ -#define ICPR0_SPI0_EN (0x1 << 17 ) /* EN */ - -/* ICPR0[UART] - */ -#define ICPR0_UART_MSK (0x1 << 16 ) -#define ICPR0_UART (0x1 << 16 ) -#define ICPR0_UART_DIS (0x0 << 16 ) /* DIS */ -#define ICPR0_UART_EN (0x1 << 16 ) /* EN */ - -/* ICPR0[FEE] - */ -#define ICPR0_FEE_MSK (0x1 << 15 ) -#define ICPR0_FEE (0x1 << 15 ) -#define ICPR0_FEE_DIS (0x0 << 15 ) /* DIS */ -#define ICPR0_FEE_EN (0x1 << 15 ) /* EN */ - -/* ICPR0[ADC] - */ -#define ICPR0_ADC_MSK (0x1 << 14 ) -#define ICPR0_ADC (0x1 << 14 ) -#define ICPR0_ADC_DIS (0x0 << 14 ) /* DIS */ -#define ICPR0_ADC_EN (0x1 << 14 ) /* EN */ - -/* ICPR0[T1] - */ -#define ICPR0_T1_MSK (0x1 << 13 ) -#define ICPR0_T1 (0x1 << 13 ) -#define ICPR0_T1_DIS (0x0 << 13 ) /* DIS */ -#define ICPR0_T1_EN (0x1 << 13 ) /* EN */ - -/* ICPR0[T0] - */ -#define ICPR0_T0_MSK (0x1 << 12 ) -#define ICPR0_T0 (0x1 << 12 ) -#define ICPR0_T0_DIS (0x0 << 12 ) /* DIS */ -#define ICPR0_T0_EN (0x1 << 12 ) /* EN */ - -/* ICPR0[T3] - */ -#define ICPR0_T3_MSK (0x1 << 10 ) -#define ICPR0_T3 (0x1 << 10 ) -#define ICPR0_T3_DIS (0x0 << 10 ) /* DIS */ -#define ICPR0_T3_EN (0x1 << 10 ) /* EN */ - -/* ICPR0[EXTINT8] - */ -#define ICPR0_EXTINT8_MSK (0x1 << 9 ) -#define ICPR0_EXTINT8 (0x1 << 9 ) -#define ICPR0_EXTINT8_DIS (0x0 << 9 ) /* DIS */ -#define ICPR0_EXTINT8_EN (0x1 << 9 ) /* EN */ - -/* ICPR0[EXTINT7] - */ -#define ICPR0_EXTINT7_MSK (0x1 << 8 ) -#define ICPR0_EXTINT7 (0x1 << 8 ) -#define ICPR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */ -#define ICPR0_EXTINT7_EN (0x1 << 8 ) /* EN */ - -/* ICPR0[EXTINT6] - */ -#define ICPR0_EXTINT6_MSK (0x1 << 7 ) -#define ICPR0_EXTINT6 (0x1 << 7 ) -#define ICPR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */ -#define ICPR0_EXTINT6_EN (0x1 << 7 ) /* EN */ - -/* ICPR0[EXTINT5] - */ -#define ICPR0_EXTINT5_MSK (0x1 << 6 ) -#define ICPR0_EXTINT5 (0x1 << 6 ) -#define ICPR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */ -#define ICPR0_EXTINT5_EN (0x1 << 6 ) /* EN */ - -/* ICPR0[EXTINT4] - */ -#define ICPR0_EXTINT4_MSK (0x1 << 5 ) -#define ICPR0_EXTINT4 (0x1 << 5 ) -#define ICPR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */ -#define ICPR0_EXTINT4_EN (0x1 << 5 ) /* EN */ - -/* ICPR0[EXTINT3] - */ -#define ICPR0_EXTINT3_MSK (0x1 << 4 ) -#define ICPR0_EXTINT3 (0x1 << 4 ) -#define ICPR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */ -#define ICPR0_EXTINT3_EN (0x1 << 4 ) /* EN */ - -/* ICPR0[EXTINT2] - */ -#define ICPR0_EXTINT2_MSK (0x1 << 3 ) -#define ICPR0_EXTINT2 (0x1 << 3 ) -#define ICPR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */ -#define ICPR0_EXTINT2_EN (0x1 << 3 ) /* EN */ - -/* ICPR0[EXTINT1] - */ -#define ICPR0_EXTINT1_MSK (0x1 << 2 ) -#define ICPR0_EXTINT1 (0x1 << 2 ) -#define ICPR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */ -#define ICPR0_EXTINT1_EN (0x1 << 2 ) /* EN */ - -/* ICPR0[EXTINT0] - */ -#define ICPR0_EXTINT0_MSK (0x1 << 1 ) -#define ICPR0_EXTINT0 (0x1 << 1 ) -#define ICPR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */ -#define ICPR0_EXTINT0_EN (0x1 << 1 ) /* EN */ - -/* ICPR0[T2] - */ -#define ICPR0_T2_MSK (0x1 << 0 ) -#define ICPR0_T2 (0x1 << 0 ) -#define ICPR0_T2_DIS (0x0 << 0 ) /* DIS */ -#define ICPR0_T2_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for ICPR1*/ -#define ICPR1_RVAL 0x0 - -/* ICPR1[PWM3] - */ -#define ICPR1_PWM3_MSK (0x1 << 9 ) -#define ICPR1_PWM3 (0x1 << 9 ) -#define ICPR1_PWM3_DIS (0x0 << 9 ) /* DIS */ -#define ICPR1_PWM3_EN (0x1 << 9 ) /* EN */ - -/* ICPR1[PWM2] - */ -#define ICPR1_PWM2_MSK (0x1 << 8 ) -#define ICPR1_PWM2 (0x1 << 8 ) -#define ICPR1_PWM2_DIS (0x0 << 8 ) /* DIS */ -#define ICPR1_PWM2_EN (0x1 << 8 ) /* EN */ - -/* ICPR1[PWM1] - */ -#define ICPR1_PWM1_MSK (0x1 << 7 ) -#define ICPR1_PWM1 (0x1 << 7 ) -#define ICPR1_PWM1_DIS (0x0 << 7 ) /* DIS */ -#define ICPR1_PWM1_EN (0x1 << 7 ) /* EN */ - -/* ICPR1[PWM0] - */ -#define ICPR1_PWM0_MSK (0x1 << 6 ) -#define ICPR1_PWM0 (0x1 << 6 ) -#define ICPR1_PWM0_DIS (0x0 << 6 ) /* DIS */ -#define ICPR1_PWM0_EN (0x1 << 6 ) /* EN */ - -/* ICPR1[PWMTRIP] - */ -#define ICPR1_PWMTRIP_MSK (0x1 << 5 ) -#define ICPR1_PWMTRIP (0x1 << 5 ) -#define ICPR1_PWMTRIP_DIS (0x0 << 5 ) /* DIS */ -#define ICPR1_PWMTRIP_EN (0x1 << 5 ) /* EN */ - -/* ICPR1[DMASPI0RX] - */ -#define ICPR1_DMASPI0RX_MSK (0x1 << 4 ) -#define ICPR1_DMASPI0RX (0x1 << 4 ) -#define ICPR1_DMASPI0RX_DIS (0x0 << 4 ) /* DIS */ -#define ICPR1_DMASPI0RX_EN (0x1 << 4 ) /* EN */ - -/* ICPR1[DMASPI0TX] - */ -#define ICPR1_DMASPI0TX_MSK (0x1 << 3 ) -#define ICPR1_DMASPI0TX (0x1 << 3 ) -#define ICPR1_DMASPI0TX_DIS (0x0 << 3 ) /* DIS */ -#define ICPR1_DMASPI0TX_EN (0x1 << 3 ) /* EN */ - -/* ICPR1[DMAADC] - */ -#define ICPR1_DMAADC_MSK (0x1 << 2 ) -#define ICPR1_DMAADC (0x1 << 2 ) -#define ICPR1_DMAADC_DIS (0x0 << 2 ) /* DIS */ -#define ICPR1_DMAADC_EN (0x1 << 2 ) /* EN */ - -/* Reset Value for IABR0*/ -#define IABR0_RVAL 0x0 - -/* IABR0[DMAI2CMRX] - */ -#define IABR0_DMAI2CMRX_MSK (0x1 << 30 ) -#define IABR0_DMAI2CMRX (0x1 << 30 ) -#define IABR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */ -#define IABR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */ - -/* IABR0[DMAI2CMTX] - */ -#define IABR0_DMAI2CMTX_MSK (0x1 << 29 ) -#define IABR0_DMAI2CMTX (0x1 << 29 ) -#define IABR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */ -#define IABR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */ - -/* IABR0[DMAI2CSRX] - */ -#define IABR0_DMAI2CSRX_MSK (0x1 << 28 ) -#define IABR0_DMAI2CSRX (0x1 << 28 ) -#define IABR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */ -#define IABR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */ - -/* IABR0[DMAI2CSTX] - */ -#define IABR0_DMAI2CSTX_MSK (0x1 << 27 ) -#define IABR0_DMAI2CSTX (0x1 << 27 ) -#define IABR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */ -#define IABR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */ - -/* IABR0[DMAUARTRX] - */ -#define IABR0_DMAUARTRX_MSK (0x1 << 26 ) -#define IABR0_DMAUARTRX (0x1 << 26 ) -#define IABR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */ -#define IABR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */ - -/* IABR0[DMAUARTTX] - */ -#define IABR0_DMAUARTTX_MSK (0x1 << 25 ) -#define IABR0_DMAUARTTX (0x1 << 25 ) -#define IABR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */ -#define IABR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */ - -/* IABR0[DMASPI1RX] - */ -#define IABR0_DMASPI1RX_MSK (0x1 << 24 ) -#define IABR0_DMASPI1RX (0x1 << 24 ) -#define IABR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */ -#define IABR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */ - -/* IABR0[DMASPI1TX] - */ -#define IABR0_DMASPI1TX_MSK (0x1 << 23 ) -#define IABR0_DMASPI1TX (0x1 << 23 ) -#define IABR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */ -#define IABR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */ - -/* IABR0[DMAERROR] - */ -#define IABR0_DMAERROR_MSK (0x1 << 22 ) -#define IABR0_DMAERROR (0x1 << 22 ) -#define IABR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */ -#define IABR0_DMAERROR_EN (0x1 << 22 ) /* EN */ - -/* IABR0[I2CM] - */ -#define IABR0_I2CM_MSK (0x1 << 20 ) -#define IABR0_I2CM (0x1 << 20 ) -#define IABR0_I2CM_DIS (0x0 << 20 ) /* DIS */ -#define IABR0_I2CM_EN (0x1 << 20 ) /* EN */ - -/* IABR0[I2CS] - */ -#define IABR0_I2CS_MSK (0x1 << 19 ) -#define IABR0_I2CS (0x1 << 19 ) -#define IABR0_I2CS_DIS (0x0 << 19 ) /* DIS */ -#define IABR0_I2CS_EN (0x1 << 19 ) /* EN */ - -/* IABR0[SPI1] - */ -#define IABR0_SPI1_MSK (0x1 << 18 ) -#define IABR0_SPI1 (0x1 << 18 ) -#define IABR0_SPI1_DIS (0x0 << 18 ) /* DIS */ -#define IABR0_SPI1_EN (0x1 << 18 ) /* EN */ - -/* IABR0[SPI0] - */ -#define IABR0_SPI0_MSK (0x1 << 17 ) -#define IABR0_SPI0 (0x1 << 17 ) -#define IABR0_SPI0_DIS (0x0 << 17 ) /* DIS */ -#define IABR0_SPI0_EN (0x1 << 17 ) /* EN */ - -/* IABR0[UART] - */ -#define IABR0_UART_MSK (0x1 << 16 ) -#define IABR0_UART (0x1 << 16 ) -#define IABR0_UART_DIS (0x0 << 16 ) /* DIS */ -#define IABR0_UART_EN (0x1 << 16 ) /* EN */ - -/* IABR0[FEE] - */ -#define IABR0_FEE_MSK (0x1 << 15 ) -#define IABR0_FEE (0x1 << 15 ) -#define IABR0_FEE_DIS (0x0 << 15 ) /* DIS */ -#define IABR0_FEE_EN (0x1 << 15 ) /* EN */ - -/* IABR0[ADC] - */ -#define IABR0_ADC_MSK (0x1 << 14 ) -#define IABR0_ADC (0x1 << 14 ) -#define IABR0_ADC_DIS (0x0 << 14 ) /* DIS */ -#define IABR0_ADC_EN (0x1 << 14 ) /* EN */ - -/* IABR0[T1] - */ -#define IABR0_T1_MSK (0x1 << 13 ) -#define IABR0_T1 (0x1 << 13 ) -#define IABR0_T1_DIS (0x0 << 13 ) /* DIS */ -#define IABR0_T1_EN (0x1 << 13 ) /* EN */ - -/* IABR0[T0] - */ -#define IABR0_T0_MSK (0x1 << 12 ) -#define IABR0_T0 (0x1 << 12 ) -#define IABR0_T0_DIS (0x0 << 12 ) /* DIS */ -#define IABR0_T0_EN (0x1 << 12 ) /* EN */ - -/* IABR0[T3] - */ -#define IABR0_T3_MSK (0x1 << 10 ) -#define IABR0_T3 (0x1 << 10 ) -#define IABR0_T3_DIS (0x0 << 10 ) /* DIS */ -#define IABR0_T3_EN (0x1 << 10 ) /* EN */ - -/* IABR0[EXTINT8] - */ -#define IABR0_EXTINT8_MSK (0x1 << 9 ) -#define IABR0_EXTINT8 (0x1 << 9 ) -#define IABR0_EXTINT8_DIS (0x0 << 9 ) /* DIS */ -#define IABR0_EXTINT8_EN (0x1 << 9 ) /* EN */ - -/* IABR0[EXTINT7] - */ -#define IABR0_EXTINT7_MSK (0x1 << 8 ) -#define IABR0_EXTINT7 (0x1 << 8 ) -#define IABR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */ -#define IABR0_EXTINT7_EN (0x1 << 8 ) /* EN */ - -/* IABR0[EXTINT6] - */ -#define IABR0_EXTINT6_MSK (0x1 << 7 ) -#define IABR0_EXTINT6 (0x1 << 7 ) -#define IABR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */ -#define IABR0_EXTINT6_EN (0x1 << 7 ) /* EN */ - -/* IABR0[EXTINT5] - */ -#define IABR0_EXTINT5_MSK (0x1 << 6 ) -#define IABR0_EXTINT5 (0x1 << 6 ) -#define IABR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */ -#define IABR0_EXTINT5_EN (0x1 << 6 ) /* EN */ - -/* IABR0[EXTINT4] - */ -#define IABR0_EXTINT4_MSK (0x1 << 5 ) -#define IABR0_EXTINT4 (0x1 << 5 ) -#define IABR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */ -#define IABR0_EXTINT4_EN (0x1 << 5 ) /* EN */ - -/* IABR0[EXTINT3] - */ -#define IABR0_EXTINT3_MSK (0x1 << 4 ) -#define IABR0_EXTINT3 (0x1 << 4 ) -#define IABR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */ -#define IABR0_EXTINT3_EN (0x1 << 4 ) /* EN */ - -/* IABR0[EXTINT2] - */ -#define IABR0_EXTINT2_MSK (0x1 << 3 ) -#define IABR0_EXTINT2 (0x1 << 3 ) -#define IABR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */ -#define IABR0_EXTINT2_EN (0x1 << 3 ) /* EN */ - -/* IABR0[EXTINT1] - */ -#define IABR0_EXTINT1_MSK (0x1 << 2 ) -#define IABR0_EXTINT1 (0x1 << 2 ) -#define IABR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */ -#define IABR0_EXTINT1_EN (0x1 << 2 ) /* EN */ - -/* IABR0[EXTINT0] - */ -#define IABR0_EXTINT0_MSK (0x1 << 1 ) -#define IABR0_EXTINT0 (0x1 << 1 ) -#define IABR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */ -#define IABR0_EXTINT0_EN (0x1 << 1 ) /* EN */ - -/* IABR0[T2] - */ -#define IABR0_T2_MSK (0x1 << 0 ) -#define IABR0_T2 (0x1 << 0 ) -#define IABR0_T2_DIS (0x0 << 0 ) /* DIS */ -#define IABR0_T2_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for IABR1*/ -#define IABR1_RVAL 0x0 - -/* IABR1[PWM3] - */ -#define IABR1_PWM3_MSK (0x1 << 9 ) -#define IABR1_PWM3 (0x1 << 9 ) -#define IABR1_PWM3_DIS (0x0 << 9 ) /* DIS */ -#define IABR1_PWM3_EN (0x1 << 9 ) /* EN */ - -/* IABR1[PWM2] - */ -#define IABR1_PWM2_MSK (0x1 << 8 ) -#define IABR1_PWM2 (0x1 << 8 ) -#define IABR1_PWM2_DIS (0x0 << 8 ) /* DIS */ -#define IABR1_PWM2_EN (0x1 << 8 ) /* EN */ - -/* IABR1[PWM1] - */ -#define IABR1_PWM1_MSK (0x1 << 7 ) -#define IABR1_PWM1 (0x1 << 7 ) -#define IABR1_PWM1_DIS (0x0 << 7 ) /* DIS */ -#define IABR1_PWM1_EN (0x1 << 7 ) /* EN */ - -/* IABR1[PWM0] - */ -#define IABR1_PWM0_MSK (0x1 << 6 ) -#define IABR1_PWM0 (0x1 << 6 ) -#define IABR1_PWM0_DIS (0x0 << 6 ) /* DIS */ -#define IABR1_PWM0_EN (0x1 << 6 ) /* EN */ - -/* IABR1[PWMTRIP] - */ -#define IABR1_PWMTRIP_MSK (0x1 << 5 ) -#define IABR1_PWMTRIP (0x1 << 5 ) -#define IABR1_PWMTRIP_DIS (0x0 << 5 ) /* DIS */ -#define IABR1_PWMTRIP_EN (0x1 << 5 ) /* EN */ - -/* IABR1[DMASPI0RX] - */ -#define IABR1_DMASPI0RX_MSK (0x1 << 4 ) -#define IABR1_DMASPI0RX (0x1 << 4 ) -#define IABR1_DMASPI0RX_DIS (0x0 << 4 ) /* DIS */ -#define IABR1_DMASPI0RX_EN (0x1 << 4 ) /* EN */ - -/* IABR1[DMASPI0TX] - */ -#define IABR1_DMASPI0TX_MSK (0x1 << 3 ) -#define IABR1_DMASPI0TX (0x1 << 3 ) -#define IABR1_DMASPI0TX_DIS (0x0 << 3 ) /* DIS */ -#define IABR1_DMASPI0TX_EN (0x1 << 3 ) /* EN */ - -/* IABR1[DMAADC] - */ -#define IABR1_DMAADC_MSK (0x1 << 2 ) -#define IABR1_DMAADC (0x1 << 2 ) -#define IABR1_DMAADC_DIS (0x0 << 2 ) /* DIS */ -#define IABR1_DMAADC_EN (0x1 << 2 ) /* EN */ - -/* Reset Value for IPR0*/ -#define IPR0_RVAL 0x0 - -/* IPR0[EXTINT2] - */ -#define IPR0_EXTINT2_MSK (0xFF << 24 ) - -/* IPR0[EXTINT1] - */ -#define IPR0_EXTINT1_MSK (0xFF << 16 ) - -/* IPR0[EXTINT0] - Priority of interrupt number 1 */ -#define IPR0_EXTINT0_MSK (0xFF << 8 ) - -/* IPR0[T2] - Priority of interrupt number 0 */ -#define IPR0_T2_MSK (0xFF << 0 ) - -/* Reset Value for IPR1*/ -#define IPR1_RVAL 0x0 - -/* IPR1[EXTINT6] - */ -#define IPR1_EXTINT6_MSK (0xFF << 24 ) - -/* IPR1[EXTINT5] - */ -#define IPR1_EXTINT5_MSK (0xFF << 16 ) - -/* IPR1[EXTINT4] - */ -#define IPR1_EXTINT4_MSK (0xFF << 8 ) - -/* IPR1[EXTINT3] - */ -#define IPR1_EXTINT3_MSK (0xFF << 0 ) - -/* Reset Value for IPR2*/ -#define IPR2_RVAL 0x0 - -/* IPR2[T3] - */ -#define IPR2_T3_MSK (0xFF << 16 ) - -/* IPR2[EXTINT8] - */ -#define IPR2_EXTINT8_MSK (0xFF << 8 ) - -/* IPR2[EXTINT7] - */ -#define IPR2_EXTINT7_MSK (0xFF << 0 ) - -/* Reset Value for IPR3*/ -#define IPR3_RVAL 0x0 - -/* IPR3[FEE] - */ -#define IPR3_FEE_MSK (0xFF << 24 ) - -/* IPR3[ADC] - */ -#define IPR3_ADC_MSK (0xFF << 16 ) - -/* IPR3[T1] - */ -#define IPR3_T1_MSK (0xFF << 8 ) - -/* IPR3[T0] - */ -#define IPR3_T0_MSK (0xFF << 0 ) - -/* Reset Value for IPR4*/ -#define IPR4_RVAL 0x0 - -/* IPR4[I2CS] - */ -#define IPR4_I2CS_MSK (0xFF << 24 ) - -/* IPR4[SPI1] - */ -#define IPR4_SPI1_MSK (0xFF << 16 ) - -/* IPR4[SPI0] - */ -#define IPR4_SPI0_MSK (0xFF << 8 ) - -/* IPR4[UART] - */ -#define IPR4_UART_MSK (0xFF << 0 ) - -/* Reset Value for IPR5*/ -#define IPR5_RVAL 0x0 - -/* IPR5[DMASPI1TX] - */ -#define IPR5_DMASPI1TX_MSK (0xFF << 24 ) - -/* IPR5[DMAERROR] - */ -#define IPR5_DMAERROR_MSK (0xFF << 16 ) - -/* IPR5[I2CM] - I2CM */ -#define IPR5_I2CM_MSK (0xFF << 0 ) - -/* Reset Value for IPR6*/ -#define IPR6_RVAL 0x0 - -/* IPR6[DMAI2CSTX] - */ -#define IPR6_DMAI2CSTX_MSK (0xFF << 24 ) - -/* IPR6[DMAUARTRX] - */ -#define IPR6_DMAUARTRX_MSK (0xFF << 16 ) - -/* IPR6[DMAUARTTX] - */ -#define IPR6_DMAUARTTX_MSK (0xFF << 8 ) - -/* IPR6[DMASPI1RX] - */ -#define IPR6_DMASPI1RX_MSK (0xFF << 0 ) - -/* Reset Value for IPR7*/ -#define IPR7_RVAL 0x0 - -/* IPR7[DMAI2CMRX] - */ -#define IPR7_DMAI2CMRX_MSK (0xFF << 16 ) - -/* IPR7[DMAI2CMTX] - */ -#define IPR7_DMAI2CMTX_MSK (0xFF << 8 ) - -/* IPR7[DMAI2CSRX] - */ -#define IPR7_DMAI2CSRX_MSK (0xFF << 0 ) - -/* Reset Value for IPR8*/ -#define IPR8_RVAL 0x0 - -/* IPR8[DMASPI0TX] - */ -#define IPR8_DMASPI0TX_MSK (0xFF << 24 ) - -/* IPR8[DMAADC] - */ -#define IPR8_DMAADC_MSK (0xFF << 16 ) - -/* Reset Value for IPR9*/ -#define IPR9_RVAL 0x0 - -/* IPR9[PWM1] - */ -#define IPR9_PWM1_MSK (0xFF << 24 ) - -/* IPR9[PWM0] - */ -#define IPR9_PWM0_MSK (0xFF << 16 ) - -/* IPR9[PWMTRIP] - */ -#define IPR9_PWMTRIP_MSK (0xFF << 8 ) - -/* IPR9[DMASPI0RX] - */ -#define IPR9_DMASPI0RX_MSK (0xFF << 0 ) - -/* Reset Value for IPR10*/ -#define IPR10_RVAL 0x0 - -/* IPR10[PWM3] - */ -#define IPR10_PWM3_MSK (0xFF << 8 ) - -/* IPR10[PWM2] - */ -#define IPR10_PWM2_MSK (0xFF << 0 ) - -/* Reset Value for CPUID*/ -#define CPUID_RVAL 0x412FC230 - -/* CPUID[IMPLEMENTER] - Indicates implementor */ -#define CPUID_IMPLEMENTER_MSK (0xFF << 24 ) - -/* CPUID[VARIANT] - Indicates processor revision */ -#define CPUID_VARIANT_MSK (0xF << 20 ) - -/* CPUID[PARTNO] - Indicates part number */ -#define CPUID_PARTNO_MSK (0xFFF << 4 ) - -/* CPUID[REVISION] - Indicates patch release */ -#define CPUID_REVISION_MSK (0xF << 0 ) - -/* Reset Value for ICSR*/ -#define ICSR_RVAL 0x0 - -/* ICSR[NMIPENDSET] - Setting this bit will activate an NMI */ -#define ICSR_NMIPENDSET_MSK (0x1 << 31 ) -#define ICSR_NMIPENDSET (0x1 << 31 ) -#define ICSR_NMIPENDSET_DIS (0x0 << 31 ) /* DIS */ -#define ICSR_NMIPENDSET_EN (0x1 << 31 ) /* EN */ - -/* ICSR[PENDSVSET] - Set a pending PendSV interrupt */ -#define ICSR_PENDSVSET_MSK (0x1 << 28 ) -#define ICSR_PENDSVSET (0x1 << 28 ) -#define ICSR_PENDSVSET_DIS (0x0 << 28 ) /* DIS */ -#define ICSR_PENDSVSET_EN (0x1 << 28 ) /* EN */ - -/* ICSR[PENDSVCLR] - Clear a pending PendSV interrupt */ -#define ICSR_PENDSVCLR_MSK (0x1 << 27 ) -#define ICSR_PENDSVCLR (0x1 << 27 ) -#define ICSR_PENDSVCLR_DIS (0x0 << 27 ) /* DIS */ -#define ICSR_PENDSVCLR_EN (0x1 << 27 ) /* EN */ - -/* ICSR[PENDSTSET] - Set a pending SysTick. Reads back with current state */ -#define ICSR_PENDSTSET_MSK (0x1 << 26 ) -#define ICSR_PENDSTSET (0x1 << 26 ) -#define ICSR_PENDSTSET_DIS (0x0 << 26 ) /* DIS */ -#define ICSR_PENDSTSET_EN (0x1 << 26 ) /* EN */ - -/* ICSR[PENDSTCLR] - Clear a pending SysTick */ -#define ICSR_PENDSTCLR_MSK (0x1 << 25 ) -#define ICSR_PENDSTCLR (0x1 << 25 ) -#define ICSR_PENDSTCLR_DIS (0x0 << 25 ) /* DIS */ -#define ICSR_PENDSTCLR_EN (0x1 << 25 ) /* EN */ - -/* ICSR[ISRPREEMPT] - If set, a pending exception will be serviced on exit from the debug halt state */ -#define ICSR_ISRPREEMPT_MSK (0x1 << 23 ) -#define ICSR_ISRPREEMPT (0x1 << 23 ) -#define ICSR_ISRPREEMPT_DIS (0x0 << 23 ) /* DIS */ -#define ICSR_ISRPREEMPT_EN (0x1 << 23 ) /* EN */ - -/* ICSR[ISRPENDING] - Indicates if an external configurable is pending */ -#define ICSR_ISRPENDING_MSK (0x1 << 22 ) -#define ICSR_ISRPENDING (0x1 << 22 ) -#define ICSR_ISRPENDING_DIS (0x0 << 22 ) /* DIS */ -#define ICSR_ISRPENDING_EN (0x1 << 22 ) /* EN */ - -/* ICSR[VECTPENDING] - Indicates the exception number for the highest priority pending exception */ -#define ICSR_VECTPENDING_MSK (0x1FF << 12 ) - -/* ICSR[RETTOBASE] - */ -#define ICSR_RETTOBASE_MSK (0x1 << 11 ) -#define ICSR_RETTOBASE (0x1 << 11 ) -#define ICSR_RETTOBASE_DIS (0x0 << 11 ) /* DIS */ -#define ICSR_RETTOBASE_EN (0x1 << 11 ) /* EN */ - -/* ICSR[VECTACTIVE] - Thread mode, or exception number */ -#define ICSR_VECTACTIVE_MSK (0x1FF << 0 ) - -/* Reset Value for VTOR*/ -#define VTOR_RVAL 0x0 - -/* VTOR[TBLBASE] - */ -#define VTOR_TBLBASE_MSK (0x1 << 29 ) -#define VTOR_TBLBASE (0x1 << 29 ) -#define VTOR_TBLBASE_DIS (0x0 << 29 ) /* DIS */ -#define VTOR_TBLBASE_EN (0x1 << 29 ) /* EN */ - -/* VTOR[TBLOFF] - */ -#define VTOR_TBLOFF_MSK (0x3FFFFF << 7 ) - -/* Reset Value for AIRCR*/ -#define AIRCR_RVAL 0xFA050000 - -/* AIRCR[VECTKEYSTAT] - Reads as 0xFA05 */ -#define AIRCR_VECTKEYSTAT_MSK (0xFFFF << 16 ) - -/* AIRCR[ENDIANESS] - This bit is static or configured by a hardware input on reset */ -#define AIRCR_ENDIANESS_MSK (0x1 << 15 ) -#define AIRCR_ENDIANESS (0x1 << 15 ) -#define AIRCR_ENDIANESS_DIS (0x0 << 15 ) /* DIS */ -#define AIRCR_ENDIANESS_EN (0x1 << 15 ) /* EN */ - -/* AIRCR[PRIGROUP] - Priority grouping position */ -#define AIRCR_PRIGROUP_MSK (0x7 << 8 ) - -/* AIRCR[SYSRESETREQ] - System Reset Request */ -#define AIRCR_SYSRESETREQ_MSK (0x1 << 2 ) -#define AIRCR_SYSRESETREQ (0x1 << 2 ) -#define AIRCR_SYSRESETREQ_DIS (0x0 << 2 ) /* DIS */ -#define AIRCR_SYSRESETREQ_EN (0x1 << 2 ) /* EN */ - -/* AIRCR[VECTCLRACTIVE] - Clears all active state information for fixed and configurable exceptions */ -#define AIRCR_VECTCLRACTIVE_MSK (0x1 << 1 ) -#define AIRCR_VECTCLRACTIVE (0x1 << 1 ) -#define AIRCR_VECTCLRACTIVE_DIS (0x0 << 1 ) /* DIS */ -#define AIRCR_VECTCLRACTIVE_EN (0x1 << 1 ) /* EN */ - -/* AIRCR[VECTRESET] - Local system reset */ -#define AIRCR_VECTRESET_MSK (0x1 << 0 ) -#define AIRCR_VECTRESET (0x1 << 0 ) -#define AIRCR_VECTRESET_DIS (0x0 << 0 ) /* DIS */ -#define AIRCR_VECTRESET_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for SCR*/ -#define SCR_RVAL 0x0 - -/* SCR[SEVONPEND] - */ -#define SCR_SEVONPEND_MSK (0x1 << 4 ) -#define SCR_SEVONPEND (0x1 << 4 ) -#define SCR_SEVONPEND_DIS (0x0 << 4 ) /* DIS */ -#define SCR_SEVONPEND_EN (0x1 << 4 ) /* EN */ - -/* SCR[SLEEPDEEP] - Sleep deep bit */ -#define SCR_SLEEPDEEP_MSK (0x1 << 2 ) -#define SCR_SLEEPDEEP (0x1 << 2 ) -#define SCR_SLEEPDEEP_DIS (0x0 << 2 ) /* DIS */ -#define SCR_SLEEPDEEP_EN (0x1 << 2 ) /* EN */ - -/* SCR[SLEEPONEXIT] - Sleep on exit when returning from handler mode to thread mode */ -#define SCR_SLEEPONEXIT_MSK (0x1 << 1 ) -#define SCR_SLEEPONEXIT (0x1 << 1 ) -#define SCR_SLEEPONEXIT_DIS (0x0 << 1 ) /* DIS */ -#define SCR_SLEEPONEXIT_EN (0x1 << 1 ) /* EN */ - -/* Reset Value for CCR*/ -#define CCR_RVAL 0x200 - -/* CCR[STKALIGN] - */ -#define CCR_STKALIGN_MSK (0x1 << 9 ) -#define CCR_STKALIGN (0x1 << 9 ) -#define CCR_STKALIGN_DIS (0x0 << 9 ) /* DIS */ -#define CCR_STKALIGN_EN (0x1 << 9 ) /* EN */ - -/* CCR[BFHFNMIGN] - */ -#define CCR_BFHFNMIGN_MSK (0x1 << 8 ) -#define CCR_BFHFNMIGN (0x1 << 8 ) -#define CCR_BFHFNMIGN_DIS (0x0 << 8 ) /* DIS */ -#define CCR_BFHFNMIGN_EN (0x1 << 8 ) /* EN */ - -/* CCR[DIV0TRP] - */ -#define CCR_DIV0TRP_MSK (0x1 << 4 ) -#define CCR_DIV0TRP (0x1 << 4 ) -#define CCR_DIV0TRP_DIS (0x0 << 4 ) /* DIS */ -#define CCR_DIV0TRP_EN (0x1 << 4 ) /* EN */ - -/* CCR[UNALIGNTRP] - */ -#define CCR_UNALIGNTRP_MSK (0x1 << 3 ) -#define CCR_UNALIGNTRP (0x1 << 3 ) -#define CCR_UNALIGNTRP_DIS (0x0 << 3 ) /* DIS */ -#define CCR_UNALIGNTRP_EN (0x1 << 3 ) /* EN */ - -/* CCR[USERSETMPEND] - */ -#define CCR_USERSETMPEND_MSK (0x1 << 1 ) -#define CCR_USERSETMPEND (0x1 << 1 ) -#define CCR_USERSETMPEND_DIS (0x0 << 1 ) /* DIS */ -#define CCR_USERSETMPEND_EN (0x1 << 1 ) /* EN */ - -/* CCR[NONBASETHRDENA] - */ -#define CCR_NONBASETHRDENA_MSK (0x1 << 0 ) -#define CCR_NONBASETHRDENA (0x1 << 0 ) -#define CCR_NONBASETHRDENA_DIS (0x0 << 0 ) /* DIS */ -#define CCR_NONBASETHRDENA_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for SHPR1*/ -#define SHPR1_RVAL 0x0 - -/* SHPR1[PRI7] - Priority of system handler 7 - reserved */ -#define SHPR1_PRI7_MSK (0xFF << 24 ) - -/* SHPR1[PRI6] - Priority of system handler 6 - UsageFault */ -#define SHPR1_PRI6_MSK (0xFF << 16 ) - -/* SHPR1[PRI5] - Priority of system handler 5 - BusFault */ -#define SHPR1_PRI5_MSK (0xFF << 8 ) - -/* SHPR1[PRI4] - Priority of system handler 4 - MemManage */ -#define SHPR1_PRI4_MSK (0xFF << 0 ) - -/* Reset Value for SHPR2*/ -#define SHPR2_RVAL 0x0 - -/* SHPR2[PRI11] - Priority of system handler 11 - SVCall */ -#define SHPR2_PRI11_MSK (0xFF << 24 ) - -/* SHPR2[PRI10] - Priority of system handler 10 - reserved */ -#define SHPR2_PRI10_MSK (0xFF << 16 ) - -/* SHPR2[PRI9] - Priority of system handler 9 - reserved */ -#define SHPR2_PRI9_MSK (0xFF << 8 ) - -/* SHPR2[PRI8] - Priority of system handler 8 - reserved */ -#define SHPR2_PRI8_MSK (0xFF << 0 ) - -/* Reset Value for SHPR3*/ -#define SHPR3_RVAL 0x0 - -/* SHPR3[PRI15] - Priority of system handler 15 - SysTick */ -#define SHPR3_PRI15_MSK (0xFF << 24 ) - -/* SHPR3[PRI14] - Priority of system handler 14 - PendSV */ -#define SHPR3_PRI14_MSK (0xFF << 16 ) - -/* SHPR3[PRI13] - Priority of system handler 13 - reserved */ -#define SHPR3_PRI13_MSK (0xFF << 8 ) - -/* SHPR3[PRI12] - Priority of system handler 12 - DebugMonitor */ -#define SHPR3_PRI12_MSK (0xFF << 0 ) - -/* Reset Value for SHCSR*/ -#define SHCSR_RVAL 0x0 - -/* SHCSR[USGFAULTENA] - Enable for UsageFault */ -#define SHCSR_USGFAULTENA_MSK (0x1 << 18 ) -#define SHCSR_USGFAULTENA (0x1 << 18 ) -#define SHCSR_USGFAULTENA_DIS (0x0 << 18 ) /* DIS */ -#define SHCSR_USGFAULTENA_EN (0x1 << 18 ) /* EN */ - -/* SHCSR[BUSFAULTENA] - Enable for BusFault. */ -#define SHCSR_BUSFAULTENA_MSK (0x1 << 17 ) -#define SHCSR_BUSFAULTENA (0x1 << 17 ) -#define SHCSR_BUSFAULTENA_DIS (0x0 << 17 ) /* DIS */ -#define SHCSR_BUSFAULTENA_EN (0x1 << 17 ) /* EN */ - -/* SHCSR[MEMFAULTENA] - Enable for MemManage fault. */ -#define SHCSR_MEMFAULTENA_MSK (0x1 << 16 ) -#define SHCSR_MEMFAULTENA (0x1 << 16 ) -#define SHCSR_MEMFAULTENA_DIS (0x0 << 16 ) /* DIS */ -#define SHCSR_MEMFAULTENA_EN (0x1 << 16 ) /* EN */ - -/* SHCSR[SVCALLPENDED] - Reads as 1 if SVCall is Pending */ -#define SHCSR_SVCALLPENDED_MSK (0x1 << 15 ) -#define SHCSR_SVCALLPENDED (0x1 << 15 ) -#define SHCSR_SVCALLPENDED_DIS (0x0 << 15 ) /* DIS */ -#define SHCSR_SVCALLPENDED_EN (0x1 << 15 ) /* EN */ - -/* SHCSR[BUSFAULTPENDED] - Reads as 1 if BusFault is Pending */ -#define SHCSR_BUSFAULTPENDED_MSK (0x1 << 14 ) -#define SHCSR_BUSFAULTPENDED (0x1 << 14 ) -#define SHCSR_BUSFAULTPENDED_DIS (0x0 << 14 ) /* DIS */ -#define SHCSR_BUSFAULTPENDED_EN (0x1 << 14 ) /* EN */ - -/* SHCSR[MEMFAULTPENDED] - Reads as 1 if MemManage is Pending */ -#define SHCSR_MEMFAULTPENDED_MSK (0x1 << 13 ) -#define SHCSR_MEMFAULTPENDED (0x1 << 13 ) -#define SHCSR_MEMFAULTPENDED_DIS (0x0 << 13 ) /* DIS */ -#define SHCSR_MEMFAULTPENDED_EN (0x1 << 13 ) /* EN */ - -/* SHCSR[USGFAULTPENDED] - Reads as 1 if UsageFault is Pending */ -#define SHCSR_USGFAULTPENDED_MSK (0x1 << 12 ) -#define SHCSR_USGFAULTPENDED (0x1 << 12 ) -#define SHCSR_USGFAULTPENDED_DIS (0x0 << 12 ) /* DIS */ -#define SHCSR_USGFAULTPENDED_EN (0x1 << 12 ) /* EN */ - -/* SHCSR[SYSTICKACT] - Reads as 1 if SysTick is Active */ -#define SHCSR_SYSTICKACT_MSK (0x1 << 11 ) -#define SHCSR_SYSTICKACT (0x1 << 11 ) -#define SHCSR_SYSTICKACT_DIS (0x0 << 11 ) /* DIS */ -#define SHCSR_SYSTICKACT_EN (0x1 << 11 ) /* EN */ - -/* SHCSR[PENDSVACT] - Reads as 1 if PendSV is Active */ -#define SHCSR_PENDSVACT_MSK (0x1 << 10 ) -#define SHCSR_PENDSVACT (0x1 << 10 ) -#define SHCSR_PENDSVACT_DIS (0x0 << 10 ) /* DIS */ -#define SHCSR_PENDSVACT_EN (0x1 << 10 ) /* EN */ - -/* SHCSR[MONITORACT] - Reads as 1 if the Monitor is Active */ -#define SHCSR_MONITORACT_MSK (0x1 << 8 ) -#define SHCSR_MONITORACT (0x1 << 8 ) -#define SHCSR_MONITORACT_DIS (0x0 << 8 ) /* DIS */ -#define SHCSR_MONITORACT_EN (0x1 << 8 ) /* EN */ - -/* SHCSR[SVCALLACT] - Reads as 1 if SVCall is Active */ -#define SHCSR_SVCALLACT_MSK (0x1 << 7 ) -#define SHCSR_SVCALLACT (0x1 << 7 ) -#define SHCSR_SVCALLACT_DIS (0x0 << 7 ) /* DIS */ -#define SHCSR_SVCALLACT_EN (0x1 << 7 ) /* EN */ - -/* SHCSR[USGFAULTACT] - Reads as 1 if UsageFault is Active. */ -#define SHCSR_USGFAULTACT_MSK (0x1 << 3 ) -#define SHCSR_USGFAULTACT (0x1 << 3 ) -#define SHCSR_USGFAULTACT_DIS (0x0 << 3 ) /* DIS */ -#define SHCSR_USGFAULTACT_EN (0x1 << 3 ) /* EN */ - -/* SHCSR[BUSFAULTACT] - Reads as 1 if BusFault is Active. */ -#define SHCSR_BUSFAULTACT_MSK (0x1 << 1 ) -#define SHCSR_BUSFAULTACT (0x1 << 1 ) -#define SHCSR_BUSFAULTACT_DIS (0x0 << 1 ) /* DIS */ -#define SHCSR_BUSFAULTACT_EN (0x1 << 1 ) /* EN */ - -/* SHCSR[MEMFAULTACT] - Reads as 1 if MemManage is Active */ -#define SHCSR_MEMFAULTACT_MSK (0x1 << 0 ) -#define SHCSR_MEMFAULTACT (0x1 << 0 ) -#define SHCSR_MEMFAULTACT_DIS (0x0 << 0 ) /* DIS */ -#define SHCSR_MEMFAULTACT_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for CFSR*/ -#define CFSR_RVAL 0x0 - -/* CFSR[DIVBYZERO] - Divide by zero error */ -#define CFSR_DIVBYZERO_MSK (0x1 << 25 ) -#define CFSR_DIVBYZERO (0x1 << 25 ) -#define CFSR_DIVBYZERO_DIS (0x0 << 25 ) /* DIS */ -#define CFSR_DIVBYZERO_EN (0x1 << 25 ) /* EN */ - -/* CFSR[UNALIGNED] - Unaligned access error */ -#define CFSR_UNALIGNED_MSK (0x1 << 24 ) -#define CFSR_UNALIGNED (0x1 << 24 ) -#define CFSR_UNALIGNED_DIS (0x0 << 24 ) /* DIS */ -#define CFSR_UNALIGNED_EN (0x1 << 24 ) /* EN */ - -/* CFSR[NOCP] - Coprocessor access error */ -#define CFSR_NOCP_MSK (0x1 << 19 ) -#define CFSR_NOCP (0x1 << 19 ) -#define CFSR_NOCP_DIS (0x0 << 19 ) /* DIS */ -#define CFSR_NOCP_EN (0x1 << 19 ) /* EN */ - -/* CFSR[INVPC] - Integrity check error on EXC_RETURN */ -#define CFSR_INVPC_MSK (0x1 << 18 ) -#define CFSR_INVPC (0x1 << 18 ) -#define CFSR_INVPC_DIS (0x0 << 18 ) /* DIS */ -#define CFSR_INVPC_EN (0x1 << 18 ) /* EN */ - -/* CFSR[INVSTATE] - Invalid EPSR.T bit or illegal EPSR.IT bits for executing */ -#define CFSR_INVSTATE_MSK (0x1 << 17 ) -#define CFSR_INVSTATE (0x1 << 17 ) -#define CFSR_INVSTATE_DIS (0x0 << 17 ) /* DIS */ -#define CFSR_INVSTATE_EN (0x1 << 17 ) /* EN */ - -/* CFSR[UNDEFINSTR] - Undefined instruction executed */ -#define CFSR_UNDEFINSTR_MSK (0x1 << 16 ) -#define CFSR_UNDEFINSTR (0x1 << 16 ) -#define CFSR_UNDEFINSTR_DIS (0x0 << 16 ) /* DIS */ -#define CFSR_UNDEFINSTR_EN (0x1 << 16 ) /* EN */ - -/* CFSR[BFARVALID] - This bit is set if the BFAR register has valid contents */ -#define CFSR_BFARVALID_MSK (0x1 << 15 ) -#define CFSR_BFARVALID (0x1 << 15 ) -#define CFSR_BFARVALID_DIS (0x0 << 15 ) /* DIS */ -#define CFSR_BFARVALID_EN (0x1 << 15 ) /* EN */ - -/* CFSR[STKERR] - This bit indicates a derived bus fault has occurred on exception entry */ -#define CFSR_STKERR_MSK (0x1 << 12 ) -#define CFSR_STKERR (0x1 << 12 ) -#define CFSR_STKERR_DIS (0x0 << 12 ) /* DIS */ -#define CFSR_STKERR_EN (0x1 << 12 ) /* EN */ - -/* CFSR[UNSTKERR] - This bit indicates a derived bus fault has occurred on exception return */ -#define CFSR_UNSTKERR_MSK (0x1 << 11 ) -#define CFSR_UNSTKERR (0x1 << 11 ) -#define CFSR_UNSTKERR_DIS (0x0 << 11 ) /* DIS */ -#define CFSR_UNSTKERR_EN (0x1 << 11 ) /* EN */ - -/* CFSR[IMPRECISERR] - Imprecise data access error */ -#define CFSR_IMPRECISERR_MSK (0x1 << 10 ) -#define CFSR_IMPRECISERR (0x1 << 10 ) -#define CFSR_IMPRECISERR_DIS (0x0 << 10 ) /* DIS */ -#define CFSR_IMPRECISERR_EN (0x1 << 10 ) /* EN */ - -/* CFSR[PRECISERR] - Precise data access error. The BFAR is written with the faulting address */ -#define CFSR_PRECISERR_MSK (0x1 << 9 ) -#define CFSR_PRECISERR (0x1 << 9 ) -#define CFSR_PRECISERR_DIS (0x0 << 9 ) /* DIS */ -#define CFSR_PRECISERR_EN (0x1 << 9 ) /* EN */ - -/* CFSR[IBUSERR] - This bit indicates a bus fault on an instruction prefetch */ -#define CFSR_IBUSERR_MSK (0x1 << 8 ) -#define CFSR_IBUSERR (0x1 << 8 ) -#define CFSR_IBUSERR_DIS (0x0 << 8 ) /* DIS */ -#define CFSR_IBUSERR_EN (0x1 << 8 ) /* EN */ - -/* CFSR[MMARVALID] - This bit is set if the MMAR register has valid contents. */ -#define CFSR_MMARVALID_MSK (0x1 << 7 ) -#define CFSR_MMARVALID (0x1 << 7 ) -#define CFSR_MMARVALID_DIS (0x0 << 7 ) /* DIS */ -#define CFSR_MMARVALID_EN (0x1 << 7 ) /* EN */ - -/* CFSR[MSTKERR] - A derived MemManage fault has occurred on exception entry */ -#define CFSR_MSTKERR_MSK (0x1 << 4 ) -#define CFSR_MSTKERR (0x1 << 4 ) -#define CFSR_MSTKERR_DIS (0x0 << 4 ) /* DIS */ -#define CFSR_MSTKERR_EN (0x1 << 4 ) /* EN */ - -/* CFSR[MUNSTKERR] - A derived MemManage fault has occurred on exception return */ -#define CFSR_MUNSTKERR_MSK (0x1 << 3 ) -#define CFSR_MUNSTKERR (0x1 << 3 ) -#define CFSR_MUNSTKERR_DIS (0x0 << 3 ) /* DIS */ -#define CFSR_MUNSTKERR_EN (0x1 << 3 ) /* EN */ - -/* CFSR[DACCVIOL] - Data access violation. The MMAR is set to the data address which the load store tried to access. */ -#define CFSR_DACCVIOL_MSK (0x1 << 1 ) -#define CFSR_DACCVIOL (0x1 << 1 ) -#define CFSR_DACCVIOL_DIS (0x0 << 1 ) /* DIS */ -#define CFSR_DACCVIOL_EN (0x1 << 1 ) /* EN */ - -/* CFSR[IACCVIOL] - violation on an instruction fetch. */ -#define CFSR_IACCVIOL_MSK (0x1 << 0 ) -#define CFSR_IACCVIOL (0x1 << 0 ) -#define CFSR_IACCVIOL_DIS (0x0 << 0 ) /* DIS */ -#define CFSR_IACCVIOL_EN (0x1 << 0 ) /* EN */ - -/* Reset Value for HFSR*/ -#define HFSR_RVAL 0x0 - -/* HFSR[DEBUGEVT] - Debug event, and the Debug Fault Status Register has been updated. */ -#define HFSR_DEBUGEVT_MSK (0x1 << 31 ) -#define HFSR_DEBUGEVT (0x1 << 31 ) -#define HFSR_DEBUGEVT_DIS (0x0 << 31 ) /* DIS */ -#define HFSR_DEBUGEVT_EN (0x1 << 31 ) /* EN */ - -/* HFSR[FORCED] - Configurable fault cannot be activated due to priority or it was disabled. Priority escalated to a HardFault. */ -#define HFSR_FORCED_MSK (0x1 << 30 ) -#define HFSR_FORCED (0x1 << 30 ) -#define HFSR_FORCED_DIS (0x0 << 30 ) /* DIS */ -#define HFSR_FORCED_EN (0x1 << 30 ) /* EN */ - -/* HFSR[VECTTBL] - Fault was due to vector table read on exception processing */ -#define HFSR_VECTTBL_MSK (0x1 << 1 ) -#define HFSR_VECTTBL (0x1 << 1 ) -#define HFSR_VECTTBL_DIS (0x0 << 1 ) /* DIS */ -#define HFSR_VECTTBL_EN (0x1 << 1 ) /* EN */ - -/* Reset Value for MMFAR*/ -#define MMFAR_RVAL 0x0 - -/* MMFAR[ADDRESS] - Data address MPU faulted. */ -#define MMFAR_ADDRESS_MSK (0xFFFFFFFF << 0 ) - -/* Reset Value for BFAR*/ -#define BFAR_RVAL 0x0 - -/* BFAR[ADDRESS] - Updated on precise data access faults */ -#define BFAR_ADDRESS_MSK (0xFFFFFFFF << 0 ) - -/* Reset Value for STIR*/ -#define STIR_RVAL 0x0 - -/* STIR[INTID] - The value written in this field is the interrupt to be triggered. */ -#define STIR_INTID_MSK (0x3FF << 0 ) -// ------------------------------------------------------------------------------------------------ -// ----- PWRCTL ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Power Management Unit (pADI_PWRCTL) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_PWRCTL Structure */ - __IO uint16_t PWRMOD; /*!< Power Modes Register */ - __I uint16_t RESERVED0; - __IO uint16_t PWRKEY; /*!< Key Protection for the PWRMOD Register. */ - __I uint16_t RESERVED1; - __IO uint8_t PSMCON; /*!< Power Supply Monitor Control and Status */ - __I uint8_t RESERVED2[111]; - __IO uint8_t SRAMRET; /*!< SRAM Retention Register */ - __I uint8_t RESERVED3[3]; - __IO uint8_t SHUTDOWN; /*!< Shutdown Acknowledge Register */ -} ADI_PWRCTL_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define PWRMOD (*(volatile unsigned short int *) 0x40002400) -#define PWRKEY (*(volatile unsigned short int *) 0x40002404) -#define PSMCON (*(volatile unsigned char *) 0x40002408) -#define SRAMRET (*(volatile unsigned char *) 0x40002478) -#define SHUTDOWN (*(volatile unsigned char *) 0x4000247C) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for PWRMOD*/ -#define PWRMOD_RVAL 0x100 - -/* PWRMOD[WICENACK] - WIC Acknowledge, for cortex M3 deep sleep mode */ -#define PWRMOD_WICENACK_BBA (*(volatile unsigned long *) 0x4204800C) -#define PWRMOD_WICENACK_MSK (0x1 << 3 ) -#define PWRMOD_WICENACK (0x1 << 3 ) -#define PWRMOD_WICENACK_CLR (0x0 << 3 ) /* CLR. Cleared automatically by hardware when the cortex M3 processor is not ready to enter deep sleep mode including if serial wire activity is detected. */ -#define PWRMOD_WICENACK_SET (0x1 << 3 ) /* SET. Set automatically by the cortex M3 processor when ready to enter sleep deep mode. */ - -/* PWRMOD[MOD] - Low Power Mode */ -#define PWRMOD_MOD_MSK (0x7 << 0 ) -#define PWRMOD_MOD_FLEXI (0x0 << 0 ) /* FLEXI. */ -#define PWRMOD_MOD_HIBERNATE (0x5 << 0 ) /* HIBERNATE. */ -#define PWRMOD_MOD_SHUTDOWN (0x6 << 0 ) /* SHUTDOWN. */ - -/* Reset Value for PWRKEY*/ -#define PWRKEY_RVAL 0x0 - -/* PWRKEY[VALUE] - */ -#define PWRKEY_VALUE_MSK (0xFFFF << 0 ) -#define PWRKEY_VALUE_KEY1 (0x4859 << 0 ) /* KEY1 */ -#define PWRKEY_VALUE_KEY2 (0xF27B << 0 ) /* KEY2 */ - -/* Reset Value for PSMCON*/ -#define PSMCON_RVAL 0x3 - -/* PSMCON[PD] - Power Supply Monitor power down bit. */ -#define PSMCON_PD_BBA (*(volatile unsigned long *) 0x42048104) -#define PSMCON_PD_MSK (0x1 << 1 ) -#define PSMCON_PD (0x1 << 1 ) -#define PSMCON_PD_DIS (0x0 << 1 ) /* DIS. Power up the PSM. */ -#define PSMCON_PD_EN (0x1 << 1 ) /* EN. Power down the PSM. */ - -/* Reset Value for SRAMRET*/ -#define SRAMRET_RVAL 0x1 - -/* SRAMRET[RETAIN] - SRAM retention enable bit */ -#define SRAMRET_RETAIN_BBA (*(volatile unsigned long *) 0x42048F00) -#define SRAMRET_RETAIN_MSK (0x1 << 0 ) -#define SRAMRET_RETAIN (0x1 << 0 ) -#define SRAMRET_RETAIN_DIS (0x0 << 0 ) /* DIS. To retain contents of the bottom 8 kB of SRAM only */ -#define SRAMRET_RETAIN_EN (0x1 << 0 ) /* EN. To retain contents of the entire 16 kB of SRAM */ - -/* Reset Value for SHUTDOWN*/ -#define SHUTDOWN_RVAL 0x0 - -/* SHUTDOWN[EINT8] - External Interrupt 8 detected during SHUTDOWN mode */ -#define SHUTDOWN_EINT8_BBA (*(volatile unsigned long *) 0x42048F88) -#define SHUTDOWN_EINT8_MSK (0x1 << 2 ) -#define SHUTDOWN_EINT8 (0x1 << 2 ) -#define SHUTDOWN_EINT8_CLR (0x0 << 2 ) /* CLR. Cleared automatically by hardware when clearing IRQ8 in EICLR. */ -#define SHUTDOWN_EINT8_SET (0x1 << 2 ) /* SET Indicates the interrupt was detected */ - -/* SHUTDOWN[EINT1] - External Interrupt 1 detected during SHUTDOWN mode */ -#define SHUTDOWN_EINT1_BBA (*(volatile unsigned long *) 0x42048F84) -#define SHUTDOWN_EINT1_MSK (0x1 << 1 ) -#define SHUTDOWN_EINT1 (0x1 << 1 ) -#define SHUTDOWN_EINT1_CLR (0x0 << 1 ) /* CLR. Cleared automatically by hardware when clearing IRQ1 in EICLR. */ -#define SHUTDOWN_EINT1_SET (0x1 << 1 ) /* SET Indicates the interrupt was detected */ - -/* SHUTDOWN[EINT0] - External Interrupt 0 detected during SHUTDOWN mode */ -#define SHUTDOWN_EINT0_BBA (*(volatile unsigned long *) 0x42048F80) -#define SHUTDOWN_EINT0_MSK (0x1 << 0 ) -#define SHUTDOWN_EINT0 (0x1 << 0 ) -#define SHUTDOWN_EINT0_CLR (0x0 << 0 ) /* CLR. Cleared automatically by hardware when clearing IRQ0 in EICLR. */ -#define SHUTDOWN_EINT0_SET (0x1 << 0 ) /* SET Indicates the interrupt was detected */ -// ------------------------------------------------------------------------------------------------ -// ----- PWM ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Pulse Width Modulation (pADI_PWM) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_PWM Structure */ - __IO uint16_t PWMCON0; /*!< PWM Control Register */ - __I uint16_t RESERVED0; - __IO uint8_t PWMCON1; /*!< Trip Control Register */ - __I uint8_t RESERVED1[3]; - __IO uint16_t PWMCLRI; /*!< PWM Interrupt Clear */ - __I uint16_t RESERVED2[3]; - __IO uint16_t PWM0COM0; /*!< Compare Register 0 for Pair 0 */ - __I uint16_t RESERVED3; - __IO uint16_t PWM0COM1; /*!< Compare Register 1 for Pair 0 */ - __I uint16_t RESERVED4; - __IO uint16_t PWM0COM2; /*!< Compare Register 2 for Pair 0 */ - __I uint16_t RESERVED5; - __IO uint16_t PWM0LEN; /*!< Period Value Register for Pair 0 */ - __I uint16_t RESERVED6; - __IO uint16_t PWM1COM0; /*!< Compare Register 0 for Pair 1 */ - __I uint16_t RESERVED7; - __IO uint16_t PWM1COM1; /*!< Compare Register 1 for Pair 1 */ - __I uint16_t RESERVED8; - __IO uint16_t PWM1COM2; /*!< Compare Register 2 for Pair 1 */ - __I uint16_t RESERVED9; - __IO uint16_t PWM1LEN; /*!< Period Value Register for Pair 1 */ - __I uint16_t RESERVED10; - __IO uint16_t PWM2COM0; /*!< Compare Register 0 for Pair 2 */ - __I uint16_t RESERVED11; - __IO uint16_t PWM2COM1; /*!< Compare Register 1 for Pair 2 */ - __I uint16_t RESERVED12; - __IO uint16_t PWM2COM2; /*!< Compare Register 2 for Pair 2 */ - __I uint16_t RESERVED13; - __IO uint16_t PWM2LEN; /*!< Period Value Register for Pair 2 */ - __I uint16_t RESERVED14; - __IO uint16_t PWM3COM0; /*!< Compare Register 0 for Pair 3 */ - __I uint16_t RESERVED15; - __IO uint16_t PWM3COM1; /*!< Compare Register 1 for Pair 3 */ - __I uint16_t RESERVED16; - __IO uint16_t PWM3COM2; /*!< Compare Register 2 for Pair 3 */ - __I uint16_t RESERVED17; - __IO uint16_t PWM3LEN; /*!< Period Value Register for Pair 3 */ -} ADI_PWM_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define PWMCON0 (*(volatile unsigned short int *) 0x40001000) -#define PWMCON1 (*(volatile unsigned char *) 0x40001004) -#define PWMCLRI (*(volatile unsigned short int *) 0x40001008) -#define PWM0COM0 (*(volatile unsigned short int *) 0x40001010) -#define PWM0COM1 (*(volatile unsigned short int *) 0x40001014) -#define PWM0COM2 (*(volatile unsigned short int *) 0x40001018) -#define PWM0LEN (*(volatile unsigned short int *) 0x4000101C) -#define PWM1COM0 (*(volatile unsigned short int *) 0x40001020) -#define PWM1COM1 (*(volatile unsigned short int *) 0x40001024) -#define PWM1COM2 (*(volatile unsigned short int *) 0x40001028) -#define PWM1LEN (*(volatile unsigned short int *) 0x4000102C) -#define PWM2COM0 (*(volatile unsigned short int *) 0x40001030) -#define PWM2COM1 (*(volatile unsigned short int *) 0x40001034) -#define PWM2COM2 (*(volatile unsigned short int *) 0x40001038) -#define PWM2LEN (*(volatile unsigned short int *) 0x4000103C) -#define PWM3COM0 (*(volatile unsigned short int *) 0x40001040) -#define PWM3COM1 (*(volatile unsigned short int *) 0x40001044) -#define PWM3COM2 (*(volatile unsigned short int *) 0x40001048) -#define PWM3LEN (*(volatile unsigned short int *) 0x4000104C) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for PWMCON0*/ -#define PWMCON0_RVAL 0x12 - -/* PWMCON0[SYNC] - PWM Synchronization. */ -#define PWMCON0_SYNC_BBA (*(volatile unsigned long *) 0x4202003C) -#define PWMCON0_SYNC_MSK (0x1 << 15 ) -#define PWMCON0_SYNC (0x1 << 15 ) -#define PWMCON0_SYNC_DIS (0x0 << 15 ) /* DIS. Ignore transitions on the PWMSYNC pin. */ -#define PWMCON0_SYNC_EN (0x1 << 15 ) /* EN. All PWM counters are reset on the next clock edge after the detection of a falling edge on the PWMSYNC pin. */ - -/* PWMCON0[PWM7INV] - Inversion of PWM output. Available in standard mode only. */ -#define PWMCON0_PWM7INV_BBA (*(volatile unsigned long *) 0x42020038) -#define PWMCON0_PWM7INV_MSK (0x1 << 14 ) -#define PWMCON0_PWM7INV (0x1 << 14 ) -#define PWMCON0_PWM7INV_DIS (0x0 << 14 ) /* DIS. PWM7 is normal. */ -#define PWMCON0_PWM7INV_EN (0x1 << 14 ) /* EN. Invert PWM7. */ - -/* PWMCON0[PWM5INV] - Inversion of PWM output. Available in standard mode only. */ -#define PWMCON0_PWM5INV_BBA (*(volatile unsigned long *) 0x42020034) -#define PWMCON0_PWM5INV_MSK (0x1 << 13 ) -#define PWMCON0_PWM5INV (0x1 << 13 ) -#define PWMCON0_PWM5INV_DIS (0x0 << 13 ) /* DIS. PWM5 is normal. */ -#define PWMCON0_PWM5INV_EN (0x1 << 13 ) /* EN. Invert PWM5. */ - -/* PWMCON0[PWM3INV] - Inversion of PWM output. Available in standard mode only. */ -#define PWMCON0_PWM3INV_BBA (*(volatile unsigned long *) 0x42020030) -#define PWMCON0_PWM3INV_MSK (0x1 << 12 ) -#define PWMCON0_PWM3INV (0x1 << 12 ) -#define PWMCON0_PWM3INV_DIS (0x0 << 12 ) /* DIS. PWM3 is normal. */ -#define PWMCON0_PWM3INV_EN (0x1 << 12 ) /* EN. Invert PWM3. */ - -/* PWMCON0[PWM1INV] - Inversion of PWM output. Available in standard mode only. */ -#define PWMCON0_PWM1INV_BBA (*(volatile unsigned long *) 0x4202002C) -#define PWMCON0_PWM1INV_MSK (0x1 << 11 ) -#define PWMCON0_PWM1INV (0x1 << 11 ) -#define PWMCON0_PWM1INV_DIS (0x0 << 11 ) /* DIS. PWM1 is normal. */ -#define PWMCON0_PWM1INV_EN (0x1 << 11 ) /* EN. Invert PWM1. */ - -/* PWMCON0[PWMIEN] - Enable PWM interrupts. */ -#define PWMCON0_PWMIEN_BBA (*(volatile unsigned long *) 0x42020028) -#define PWMCON0_PWMIEN_MSK (0x1 << 10 ) -#define PWMCON0_PWMIEN (0x1 << 10 ) -#define PWMCON0_PWMIEN_DIS (0x0 << 10 ) /* DIS. Disable PWM interrupts. */ -#define PWMCON0_PWMIEN_EN (0x1 << 10 ) /* EN. Enable PWM interrupts. */ - -/* PWMCON0[ENA] - Enable PWM outputs. Available in H-Bridge mode only. */ -#define PWMCON0_ENA_BBA (*(volatile unsigned long *) 0x42020024) -#define PWMCON0_ENA_MSK (0x1 << 9 ) -#define PWMCON0_ENA (0x1 << 9 ) -#define PWMCON0_ENA_DIS (0x0 << 9 ) /* DIS. Disable PWM outputs. */ -#define PWMCON0_ENA_EN (0x1 << 9 ) /* EN. Enable PWM outputs. */ - -/* PWMCON0[PWMCP] - PWM Clock Prescaler. Sets UCLK divider. */ -#define PWMCON0_PWMCP_MSK (0x7 << 6 ) -#define PWMCON0_PWMCP_UCLKDIV2 (0x0 << 6 ) /* UCLK/2. */ -#define PWMCON0_PWMCP_UCLKDIV4 (0x1 << 6 ) /* UCLK/4. */ -#define PWMCON0_PWMCP_UCLKDIV8 (0x2 << 6 ) /* UCLK/8. */ -#define PWMCON0_PWMCP_UCLKDIV16 (0x3 << 6 ) /* UCLK/16. */ -#define PWMCON0_PWMCP_UCLKDIV32 (0x4 << 6 ) /* UCLK/32. */ -#define PWMCON0_PWMCP_UCLKDIV64 (0x5 << 6 ) /* UCLK/64. */ -#define PWMCON0_PWMCP_UCLKDIV128 (0x6 << 6 ) /* UCLK/128. */ -#define PWMCON0_PWMCP_UCLKDIV256 (0x7 << 6 ) /* UCLK/256. */ - -/* PWMCON0[POINV] - Invert all PWM outputs. Available in H-Bridge mode only. */ -#define PWMCON0_POINV_BBA (*(volatile unsigned long *) 0x42020014) -#define PWMCON0_POINV_MSK (0x1 << 5 ) -#define PWMCON0_POINV (0x1 << 5 ) -#define PWMCON0_POINV_DIS (0x0 << 5 ) /* DIS. PWM outputs as normal. */ -#define PWMCON0_POINV_EN (0x1 << 5 ) /* EN. Invert all PWM outputs. */ - -/* PWMCON0[HOFF] - High Side Off. Available in H-Bridge mode only. */ -#define PWMCON0_HOFF_BBA (*(volatile unsigned long *) 0x42020010) -#define PWMCON0_HOFF_MSK (0x1 << 4 ) -#define PWMCON0_HOFF (0x1 << 4 ) -#define PWMCON0_HOFF_DIS (0x0 << 4 ) /* DIS. PWM outputs as normal. */ -#define PWMCON0_HOFF_EN (0x1 << 4 ) /* EN. Force PWM0 and PWM2 outputs high and PWM1 and PWM3 low. */ - -/* PWMCON0[LCOMP] - Load Compare Registers. */ -#define PWMCON0_LCOMP_BBA (*(volatile unsigned long *) 0x4202000C) -#define PWMCON0_LCOMP_MSK (0x1 << 3 ) -#define PWMCON0_LCOMP (0x1 << 3 ) -#define PWMCON0_LCOMP_DIS (0x0 << 3 ) /* DIS. Use the values previously stored in the internal compare registers. */ -#define PWMCON0_LCOMP_EN (0x1 << 3 ) /* EN. Load the internal compare registers with the values in PWMxCOMx on the next transition of the PWM timer from 0x00 to 0x01. */ - -/* PWMCON0[DIR] - Direction Control. Available in H-Bridge mode only. */ -#define PWMCON0_DIR_BBA (*(volatile unsigned long *) 0x42020008) -#define PWMCON0_DIR_MSK (0x1 << 2 ) -#define PWMCON0_DIR (0x1 << 2 ) -#define PWMCON0_DIR_DIS (0x0 << 2 ) /* DIS. Enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low. */ -#define PWMCON0_DIR_EN (0x1 << 2 ) /* EN. Enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low. */ - -/* PWMCON0[HMODE] - Enable H-Bridge Mode. */ -#define PWMCON0_HMODE_BBA (*(volatile unsigned long *) 0x42020004) -#define PWMCON0_HMODE_MSK (0x1 << 1 ) -#define PWMCON0_HMODE (0x1 << 1 ) -#define PWMCON0_HMODE_DIS (0x0 << 1 ) /* DIS. The PWM operates in standard mode. */ -#define PWMCON0_HMODE_EN (0x1 << 1 ) /* EN. The PWM is configured in H-Bridge mode. */ - -/* PWMCON0[PWMEN] - Enable all PWM outputs. */ -#define PWMCON0_PWMEN_BBA (*(volatile unsigned long *) 0x42020000) -#define PWMCON0_PWMEN_MSK (0x1 << 0 ) -#define PWMCON0_PWMEN (0x1 << 0 ) -#define PWMCON0_PWMEN_DIS (0x0 << 0 ) /* DIS. Disables all PWM outputs. */ -#define PWMCON0_PWMEN_EN (0x1 << 0 ) /* EN. Enables all PWM outputs. */ - -/* Reset Value for PWMCON1*/ -#define PWMCON1_RVAL 0x0 - -/* PWMCON1[TRIPEN] - Enable PWM trip functionality. */ -#define PWMCON1_TRIPEN_BBA (*(volatile unsigned long *) 0x42020098) -#define PWMCON1_TRIPEN_MSK (0x1 << 6 ) -#define PWMCON1_TRIPEN (0x1 << 6 ) -#define PWMCON1_TRIPEN_DIS (0x0 << 6 ) /* DIS. Disable PWM trip functionality. */ -#define PWMCON1_TRIPEN_EN (0x1 << 6 ) /* EN. Enable PWM trip functionality. */ - -/* Reset Value for PWMCLRI*/ -#define PWMCLRI_RVAL 0x0 - -/* PWMCLRI[TRIP] - Clear the latched trip interrupt. This bit always reads 0. */ -#define PWMCLRI_TRIP_BBA (*(volatile unsigned long *) 0x42020110) -#define PWMCLRI_TRIP_MSK (0x1 << 4 ) -#define PWMCLRI_TRIP (0x1 << 4 ) -#define PWMCLRI_TRIP_EN (0x1 << 4 ) /* EN. Clear the latched PWMTRIP interrupt. */ - -/* PWMCLRI[IRQPWM3] - Clear the latched PWM3 interrupt. This bit always reads 0. */ -#define PWMCLRI_IRQPWM3_BBA (*(volatile unsigned long *) 0x4202010C) -#define PWMCLRI_IRQPWM3_MSK (0x1 << 3 ) -#define PWMCLRI_IRQPWM3 (0x1 << 3 ) -#define PWMCLRI_IRQPWM3_EN (0x1 << 3 ) /* EN. Clear the latched IRQPWM3 interrupt. */ - -/* PWMCLRI[IRQPWM2] - Clear the latched PWM2 interrupt. This bit always reads 0. */ -#define PWMCLRI_IRQPWM2_BBA (*(volatile unsigned long *) 0x42020108) -#define PWMCLRI_IRQPWM2_MSK (0x1 << 2 ) -#define PWMCLRI_IRQPWM2 (0x1 << 2 ) -#define PWMCLRI_IRQPWM2_EN (0x1 << 2 ) /* EN. Clear the latched IRQPWM2 interrupt. */ - -/* PWMCLRI[IRQPWM1] - Clear the latched PWM1 interrupt. This bit always reads 0. */ -#define PWMCLRI_IRQPWM1_BBA (*(volatile unsigned long *) 0x42020104) -#define PWMCLRI_IRQPWM1_MSK (0x1 << 1 ) -#define PWMCLRI_IRQPWM1 (0x1 << 1 ) -#define PWMCLRI_IRQPWM1_EN (0x1 << 1 ) /* EN. Clear the latched IRQPWM1 interrupt. */ - -/* PWMCLRI[IRQPWM0] - Clear the latched PWM0 interrupt. This bit always reads 0. */ -#define PWMCLRI_IRQPWM0_BBA (*(volatile unsigned long *) 0x42020100) -#define PWMCLRI_IRQPWM0_MSK (0x1 << 0 ) -#define PWMCLRI_IRQPWM0 (0x1 << 0 ) -#define PWMCLRI_IRQPWM0_EN (0x1 << 0 ) /* EN. Clear the latched IRQPWM0 interrupt. */ - -/* Reset Value for PWM0COM0*/ -#define PWM0COM0_RVAL 0x0 - -/* PWM0COM0[VALUE] - */ -#define PWM0COM0_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM0COM1*/ -#define PWM0COM1_RVAL 0x0 - -/* PWM0COM1[VALUE] - */ -#define PWM0COM1_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM0COM2*/ -#define PWM0COM2_RVAL 0x0 - -/* PWM0COM2[VALUE] - */ -#define PWM0COM2_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM0LEN*/ -#define PWM0LEN_RVAL 0x0 - -/* PWM0LEN[VALUE] - */ -#define PWM0LEN_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM1COM0*/ -#define PWM1COM0_RVAL 0x0 - -/* PWM1COM0[VALUE] - */ -#define PWM1COM0_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM1COM1*/ -#define PWM1COM1_RVAL 0x0 - -/* PWM1COM1[VALUE] - */ -#define PWM1COM1_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM1COM2*/ -#define PWM1COM2_RVAL 0x0 - -/* PWM1COM2[VALUE] - */ -#define PWM1COM2_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM1LEN*/ -#define PWM1LEN_RVAL 0x0 - -/* PWM1LEN[VALUE] - */ -#define PWM1LEN_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM2COM0*/ -#define PWM2COM0_RVAL 0x0 - -/* PWM2COM0[VALUE] - */ -#define PWM2COM0_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM2COM1*/ -#define PWM2COM1_RVAL 0x0 - -/* PWM2COM1[VALUE] - */ -#define PWM2COM1_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM2COM2*/ -#define PWM2COM2_RVAL 0x0 - -/* PWM2COM2[VALUE] - */ -#define PWM2COM2_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM2LEN*/ -#define PWM2LEN_RVAL 0x0 - -/* PWM2LEN[VALUE] - */ -#define PWM2LEN_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM3COM0*/ -#define PWM3COM0_RVAL 0x0 - -/* PWM3COM0[VALUE] - */ -#define PWM3COM0_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM3COM1*/ -#define PWM3COM1_RVAL 0x0 - -/* PWM3COM1[VALUE] - */ -#define PWM3COM1_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM3COM2*/ -#define PWM3COM2_RVAL 0x0 - -/* PWM3COM2[VALUE] - */ -#define PWM3COM2_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for PWM3LEN*/ -#define PWM3LEN_RVAL 0x0 - -/* PWM3LEN[VALUE] - */ -#define PWM3LEN_VALUE_MSK (0xFFFF << 0 ) -// ------------------------------------------------------------------------------------------------ -// ----- RESET ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Reset (pADI_RESET) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_RESET Structure */ - - union { - __IO uint8_t RSTSTA; /*!< Reset Status */ - __IO uint8_t RSTCLR; /*!< Reset Status Clear */ - } ; -} ADI_RESET_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define RSTSTA (*(volatile unsigned char *) 0x40002440) -#define RSTCLR (*(volatile unsigned char *) 0x40002440) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for RSTSTA*/ -#define RSTSTA_RVAL 0x3 - -/* RSTSTA[SWRST] - Software reset status bit */ -#define RSTSTA_SWRST_BBA (*(volatile unsigned long *) 0x42048810) -#define RSTSTA_SWRST_MSK (0x1 << 4 ) -#define RSTSTA_SWRST (0x1 << 4 ) -#define RSTSTA_SWRST_CLR (0x0 << 4 ) /* CLR. Indicates that no software reset has occurred. */ -#define RSTSTA_SWRST_SET (0x1 << 4 ) /* SET. Indicates that a software reset has occurred. */ - -/* RSTSTA[WDRST] - Watchdog reset status bit */ -#define RSTSTA_WDRST_BBA (*(volatile unsigned long *) 0x4204880C) -#define RSTSTA_WDRST_MSK (0x1 << 3 ) -#define RSTSTA_WDRST (0x1 << 3 ) -#define RSTSTA_WDRST_CLR (0x0 << 3 ) /* CLR. Indicates that no watchdog reset has occurred. */ -#define RSTSTA_WDRST_SET (0x1 << 3 ) /* SET. Indicates that a Watchdog Reset has occurred. */ - -/* RSTSTA[EXTRST] - External reset status bit */ -#define RSTSTA_EXTRST_BBA (*(volatile unsigned long *) 0x42048808) -#define RSTSTA_EXTRST_MSK (0x1 << 2 ) -#define RSTSTA_EXTRST (0x1 << 2 ) -#define RSTSTA_EXTRST_CLR (0x0 << 2 ) /* CLR. Indicates that no external reset has occurred. */ -#define RSTSTA_EXTRST_SET (0x1 << 2 ) /* SET. Indicates an external reset has occurred. */ - -/* RSTSTA[PORHV] - Power-on reset status bit HV */ -#define RSTSTA_PORHV_BBA (*(volatile unsigned long *) 0x42048804) -#define RSTSTA_PORHV_MSK (0x1 << 1 ) -#define RSTSTA_PORHV (0x1 << 1 ) -#define RSTSTA_PORHV_CLR (0x0 << 1 ) /* CLR. Indicates a POR or wake up from SHUTDOWN has not occurred. */ -#define RSTSTA_PORHV_SET (0x1 << 1 ) /* SET. This bit indicates that the AVDD supply has dropped below the POR trip point, causing a Power On Reset. It is also set when waking up from SHUTDOWN mode. */ - -/* RSTSTA[PORLV] - Power-on reset status bit LV */ -#define RSTSTA_PORLV_BBA (*(volatile unsigned long *) 0x42048800) -#define RSTSTA_PORLV_MSK (0x1 << 0 ) -#define RSTSTA_PORLV (0x1 << 0 ) -#define RSTSTA_PORLV_CLR (0x0 << 0 ) /* CLR. Indicates a POR or wake up from SHUTDOWN has not occurred. */ -#define RSTSTA_PORLV_SET (0x1 << 0 ) /* SET. This bit indicates that the AVDD supply has dropped below the POR trip point, causing a Power On Reset. It is also set when waking up from SHUTDOWN mode. */ - -/* Reset Value for RSTCLR*/ -#define RSTCLR_RVAL 0x3 - -/* RSTCLR[SWRST] - Software reset clear status bit */ -#define RSTCLR_SWRST_BBA (*(volatile unsigned long *) 0x42048810) -#define RSTCLR_SWRST_MSK (0x1 << 4 ) -#define RSTCLR_SWRST (0x1 << 4 ) -#define RSTCLR_SWRST_DIS (0x0 << 4 ) /* DIS. Has no effect. */ -#define RSTCLR_SWRST_EN (0x1 << 4 ) /* EN. Clears the SWRST status bit in RSTSTA. */ - -/* RSTCLR[WDRST] - Watchdog reset clear status bit */ -#define RSTCLR_WDRST_BBA (*(volatile unsigned long *) 0x4204880C) -#define RSTCLR_WDRST_MSK (0x1 << 3 ) -#define RSTCLR_WDRST (0x1 << 3 ) -#define RSTCLR_WDRST_DIS (0x0 << 3 ) /* DIS. Has no effect. */ -#define RSTCLR_WDRST_EN (0x1 << 3 ) /* EN. Clears the WDRST status bit in RSTSTA. */ - -/* RSTCLR[EXTRST] - External reset clear status bit */ -#define RSTCLR_EXTRST_BBA (*(volatile unsigned long *) 0x42048808) -#define RSTCLR_EXTRST_MSK (0x1 << 2 ) -#define RSTCLR_EXTRST (0x1 << 2 ) -#define RSTCLR_EXTRST_DIS (0x0 << 2 ) /* DIS. Has no effect. */ -#define RSTCLR_EXTRST_EN (0x1 << 2 ) /* EN. Clears the EXTRST status bit in RSTSTA. */ - -/* RSTCLR[PORHV] - Power on reset clear status bit */ -#define RSTCLR_PORHV_BBA (*(volatile unsigned long *) 0x42048804) -#define RSTCLR_PORHV_MSK (0x1 << 1 ) -#define RSTCLR_PORHV (0x1 << 1 ) -#define RSTCLR_PORHV_DIS (0x0 << 1 ) /* DIS. Has no effect. */ -#define RSTCLR_PORHV_EN (0x1 << 1 ) /* EN. Clears PORLV status bit in RSTSTA. */ - -/* RSTCLR[PORLV] - Power-on reset clear status bit LV */ -#define RSTCLR_PORLV_BBA (*(volatile unsigned long *) 0x42048800) -#define RSTCLR_PORLV_MSK (0x1 << 0 ) -#define RSTCLR_PORLV (0x1 << 0 ) -#define RSTCLR_PORLV_DIS (0x0 << 0 ) /* DIS. Has no effect. */ -#define RSTCLR_PORLV_EN (0x1 << 0 ) /* EN. Clears the PORLV status bit in RSTSTA. */ -// ------------------------------------------------------------------------------------------------ -// ----- SPI0 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Serial Peripheral Interface (pADI_SPI0) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_SPI0 Structure */ - __IO uint16_t SPISTA; /*!< SPI0 Status Register */ - __I uint16_t RESERVED0; - __IO uint8_t SPIRX; /*!< SPI0 Receive Register */ - __I uint8_t RESERVED1[3]; - __IO uint8_t SPITX; /*!< SPI0 Transmit Register */ - __I uint8_t RESERVED2[3]; - __IO uint16_t SPIDIV; /*!< SPI0 Bit Rate Selection Register */ - __I uint16_t RESERVED3; - __IO uint16_t SPICON; /*!< SPI0 Configuration Register */ - __I uint16_t RESERVED4; - __IO uint16_t SPIDMA; /*!< SPI0 DMA Enable Register */ - __I uint16_t RESERVED5; - __IO uint16_t SPICNT; /*!< SPI0 DMA Master Received Byte Count Register */ -} ADI_SPI_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define SPI0STA (*(volatile unsigned short int *) 0x40004000) -#define SPI0RX (*(volatile unsigned char *) 0x40004004) -#define SPI0TX (*(volatile unsigned char *) 0x40004008) -#define SPI0DIV (*(volatile unsigned short int *) 0x4000400C) -#define SPI0CON (*(volatile unsigned short int *) 0x40004010) -#define SPI0DMA (*(volatile unsigned short int *) 0x40004014) -#define SPI0CNT (*(volatile unsigned short int *) 0x40004018) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for SPI0STA*/ -#define SPI0STA_RVAL 0x0 - -/* SPI0STA[CSERR] - CS error status bit. This bit generates an interrupt when detecting an abrupt CS desassertion before the full byte of data is transmitted completely. */ -#define SPI0STA_CSERR_BBA (*(volatile unsigned long *) 0x42080030) -#define SPI0STA_CSERR_MSK (0x1 << 12 ) -#define SPI0STA_CSERR (0x1 << 12 ) -#define SPI0STA_CSERR_CLR (0x0 << 12 ) /* CLR: Cleared when no CS error is detected. Cleared to 0 on a read of SPI0STA register. */ -#define SPI0STA_CSERR_SET (0x1 << 12 ) /* SET: Set when the CS line is deasserted abruptly. */ - -/* SPI0STA[RXS] - Rx FIFO excess bytes present. */ -#define SPI0STA_RXS_BBA (*(volatile unsigned long *) 0x4208002C) -#define SPI0STA_RXS_MSK (0x1 << 11 ) -#define SPI0STA_RXS (0x1 << 11 ) -#define SPI0STA_RXS_CLR (0x0 << 11 ) /* CLR. When the number of bytes in the FIFO is equal or less than the number in SPI0CON[15:14]. This bit is not cleared on a read of SPI0STA register. */ -#define SPI0STA_RXS_SET (0x1 << 11 ) /* SET. When there are more bytes in the Rx FIFO than configured in MOD (SPI0CON[15:14]). For example if MOD = TX1RX1, RXS is set when there are 2 or more bytes in the Rx FIFO. This bit does not dependent on SPI0CON[6] and does not cause an interrupt. */ - -/* SPI0STA[RXFSTA] - Rx FIFO status bits, indicates how many valid bytes are in the Rx FIFO. */ -#define SPI0STA_RXFSTA_MSK (0x7 << 8 ) -#define SPI0STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY. When Rx FIFO is empty. */ -#define SPI0STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE. When 1 valid byte is in the FIFO. */ -#define SPI0STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES. When 2 valid bytes are in the FIFO. */ -#define SPI0STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES. When 3 valid bytes are in the FIFO. */ -#define SPI0STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES. When 4 valid bytes are in the FIFO. */ - -/* SPI0STA[RXOF] - Rx FIFO overflow status bit. This bit generates an interrupt. */ -#define SPI0STA_RXOF_BBA (*(volatile unsigned long *) 0x4208001C) -#define SPI0STA_RXOF_MSK (0x1 << 7 ) -#define SPI0STA_RXOF (0x1 << 7 ) -#define SPI0STA_RXOF_CLR (0x0 << 7 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ -#define SPI0STA_RXOF_SET (0x1 << 7 ) /* SET. Set when the Rx FIFO is already full when new data is loaded to the FIFO. This bit generates an interrupt except when RFLUSH is set. (SPI0CON[12]). */ - -/* SPI0STA[RX] - Rx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */ -#define SPI0STA_RX_BBA (*(volatile unsigned long *) 0x42080018) -#define SPI0STA_RX_MSK (0x1 << 6 ) -#define SPI0STA_RX (0x1 << 6 ) -#define SPI0STA_RX_CLR (0x0 << 6 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ -#define SPI0STA_RX_SET (0x1 << 6 ) /* SET. Set when a receive interrupt occurs. This bit is set when TIM (SPI0CON[6]) is cleared and the required number of bytes have been received. */ - -/* SPI0STA[TX] - Tx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */ -#define SPI0STA_TX_BBA (*(volatile unsigned long *) 0x42080014) -#define SPI0STA_TX_MSK (0x1 << 5 ) -#define SPI0STA_TX (0x1 << 5 ) -#define SPI0STA_TX_CLR (0x0 << 5 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ -#define SPI0STA_TX_SET (0x1 << 5 ) /* SET. Set when a transmit interrupt occurs. This bit is set when TIM (SPI0CON[6]) set and the required number of bytes have been transmitted. */ - -/* SPI0STA[TXUR] - Tx FIFO Underrun. This bit generates an interrupt. */ -#define SPI0STA_TXUR_BBA (*(volatile unsigned long *) 0x42080010) -#define SPI0STA_TXUR_MSK (0x1 << 4 ) -#define SPI0STA_TXUR (0x1 << 4 ) -#define SPI0STA_TXUR_CLR (0x0 << 4 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ -#define SPI0STA_TXUR_SET (0x1 << 4 ) /* SET. Set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when TFLUSH is set in SPI0CON. */ - -/* SPI0STA[TXFSTA] - Tx FIFO status bits, indicates how many valid bytes are in the Tx FIFO. */ -#define SPI0STA_TXFSTA_MSK (0x7 << 1 ) -#define SPI0STA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY. Tx FIFO is empty. */ -#define SPI0STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE. 1 valid byte is in the FIFO. */ -#define SPI0STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES. 2 valid bytes are in the FIFO. */ -#define SPI0STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES. 3 valid bytes are in the FIFO. */ -#define SPI0STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES . 4 valid bytes are in the FIFO. */ - -/* SPI0STA[IRQ] - Interrupt status bit. */ -#define SPI0STA_IRQ_BBA (*(volatile unsigned long *) 0x42080000) -#define SPI0STA_IRQ_MSK (0x1 << 0 ) -#define SPI0STA_IRQ (0x1 << 0 ) -#define SPI0STA_IRQ_CLR (0x0 << 0 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ -#define SPI0STA_IRQ_SET (0x1 << 0 ) /* SET. Set to 1 when an SPI0 based interrupt occurs. */ - -/* Reset Value for SPI0RX*/ -#define SPI0RX_RVAL 0x0 - -/* SPI0RX[VALUE] - 8-bit receive register. A read of the RX FIFO returns the next byte to be read from the FIFO. A read of the FIFO when it is empty returns zero. */ -#define SPI0RX_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for SPI0TX*/ -#define SPI0TX_RVAL 0x0 - -/* SPI0TX[VALUE] - 8-bit transmit register. A write to the Tx FIFO address space writes data to the next available location in the Tx FIFO. If the FIFO is full, the oldest byte of data in the FIFO is overwritten. A read from this address location return zero. */ -#define SPI0TX_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for SPI0DIV*/ -#define SPI0DIV_RVAL 0x0 - -/* SPI0DIV[BCRST] - Configures the behavior of SPI communication after an abrupt deassertion of CS. This bit should be set in slave and master mode. */ -#define SPI0DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208019C) -#define SPI0DIV_BCRST_MSK (0x1 << 7 ) -#define SPI0DIV_BCRST (0x1 << 7 ) -#define SPI0DIV_BCRST_DIS (0x0 << 7 ) /* DIS. Resumes communication from where it stopped when the CS is deasserted. The rest of the bits are then received/ transmitted when CS returns low. User code should ignore the CSERR interrupt. */ -#define SPI0DIV_BCRST_EN (0x1 << 7 ) /* EN. Enabled for a clean restart of SPI transfer after a CSERR condition. User code must also clear the SPI enable bit in SPI0CON during the CSERR interrupt. */ - -/* SPI0DIV[DIV] - Factor used to divide UCLK in the generation of the master mode serial clock. */ -#define SPI0DIV_DIV_MSK (0x3F << 0 ) - -/* Reset Value for SPI0CON*/ -#define SPI0CON_RVAL 0x0 - -/* SPI0CON[MOD] - IRQ mode bits. When TIM is set these bits configure when the Tx/Rx interrupts occur in a transfer. For a DMA Rx transfer, these bits should be 00. */ -#define SPI0CON_MOD_MSK (0x3 << 14 ) -#define SPI0CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1. Tx/Rx interrupt occurs when 1 byte has been transmitted/received from/into the FIFO. */ -#define SPI0CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2. Tx/Rx interrupt occurs when 2 bytes have been transmitted/received from/into the FIFO. */ -#define SPI0CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3. Tx/Rx interrupt occurs when 3 bytes have been transmitted/received from/into the FIFO. */ -#define SPI0CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4. Tx/Rx interrupt occurs when 4 bytes have been transmitted/received from/into the FIFO. */ - -/* SPI0CON[TFLUSH] - Tx FIFO flush enable bit. */ -#define SPI0CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42080234) -#define SPI0CON_TFLUSH_MSK (0x1 << 13 ) -#define SPI0CON_TFLUSH (0x1 << 13 ) -#define SPI0CON_TFLUSH_DIS (0x0 << 13 ) /* DIS. Disable Tx FIFO flushing. */ -#define SPI0CON_TFLUSH_EN (0x1 << 13 ) /* EN. Flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the ZEN bit (SPI0CON[7]). Any writes to the Tx FIFO are ignored while this bit is set. */ - -/* SPI0CON[RFLUSH] - Rx FIFO flush enable bit. */ -#define SPI0CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42080230) -#define SPI0CON_RFLUSH_MSK (0x1 << 12 ) -#define SPI0CON_RFLUSH (0x1 << 12 ) -#define SPI0CON_RFLUSH_DIS (0x0 << 12 ) /* DIS. Disable Rx FIFO flushing. */ -#define SPI0CON_RFLUSH_EN (0x1 << 12 ) /* EN. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and TIM = 0 (SPI0CON[6]), a read of the Rx FIFO initiates a transfer. */ - -/* SPI0CON[CON] - Continuous transfer enable bit. */ -#define SPI0CON_CON_BBA (*(volatile unsigned long *) 0x4208022C) -#define SPI0CON_CON_MSK (0x1 << 11 ) -#define SPI0CON_CON (0x1 << 11 ) -#define SPI0CON_CON_DIS (0x0 << 11 ) /* DIS. Disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPIxTX register, then a new transfer is initiated after a stall period of one serial clock cycle. The CS line is deactivated for this one serial clock cycle. */ -#define SPI0CON_CON_EN (0x1 << 11 ) /* EN. Enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. */ - -/* SPI0CON[LOOPBACK] - Loopback enable bit. */ -#define SPI0CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42080228) -#define SPI0CON_LOOPBACK_MSK (0x1 << 10 ) -#define SPI0CON_LOOPBACK (0x1 << 10 ) -#define SPI0CON_LOOPBACK_DIS (0x0 << 10 ) /* DIS. Normal mode. */ -#define SPI0CON_LOOPBACK_EN (0x1 << 10 ) /* EN. Connect MISO to MOSI, thus, data transmitted from Tx register is looped back to the Rx register. SPI must be configured in master mode. */ - -/* SPI0CON[SOEN] - Slave output enable bit. */ -#define SPI0CON_SOEN_BBA (*(volatile unsigned long *) 0x42080224) -#define SPI0CON_SOEN_MSK (0x1 << 9 ) -#define SPI0CON_SOEN (0x1 << 9 ) -#define SPI0CON_SOEN_DIS (0x0 << 9 ) /* DIS. Disable the output driver on the MISO pin. The MISO pin is open-circuit when this bit is clear. */ -#define SPI0CON_SOEN_EN (0x1 << 9 ) /* EN. MISO operates as normal. */ - -/* SPI0CON[RXOF] - RX overflow overwrite enable bit. */ -#define SPI0CON_RXOF_BBA (*(volatile unsigned long *) 0x42080220) -#define SPI0CON_RXOF_MSK (0x1 << 8 ) -#define SPI0CON_RXOF (0x1 << 8 ) -#define SPI0CON_RXOF_DIS (0x0 << 8 ) /* DIS. The new serial byte received is discarded when there is no space left in the FIFO */ -#define SPI0CON_RXOF_EN (0x1 << 8 ) /* EN. The valid data in the Rx register is overwritten by the new serial byte received when there is no space left in the FIFO. */ - -/* SPI0CON[ZEN] - Transmit underrun: Transmit 0s when the Tx FIFO is empty */ -#define SPI0CON_ZEN_BBA (*(volatile unsigned long *) 0x4208021C) -#define SPI0CON_ZEN_MSK (0x1 << 7 ) -#define SPI0CON_ZEN (0x1 << 7 ) -#define SPI0CON_ZEN_DIS (0x0 << 7 ) /* DIS. The last byte from the previous transmission is shifted out when a transfer is initiated with no valid data in the FIFO. */ -#define SPI0CON_ZEN_EN (0x1 << 7 ) /* EN. Transmit 0x00 when a transfer is initiated with no valid data in the FIFO. */ - -/* SPI0CON[TIM] - Transfer and interrupt mode bit. */ -#define SPI0CON_TIM_BBA (*(volatile unsigned long *) 0x42080218) -#define SPI0CON_TIM_MSK (0x1 << 6 ) -#define SPI0CON_TIM (0x1 << 6 ) -#define SPI0CON_TIM_TXWR (0x1 << 6 ) /* TXWR. Initiate transfer with a write to the SPIxTX register. Interrupt only occurs when Tx is empty. */ -#define SPI0CON_TIM_RXRD (0x0 << 6 ) /* RXRD. Initiate transfer with a read of the SPIxRX register. The read must be done while the SPI interface is idle. Interrupt only occurs when Rx is full. */ - -/* SPI0CON[LSB] - LSB first transfer enable bit. */ -#define SPI0CON_LSB_BBA (*(volatile unsigned long *) 0x42080214) -#define SPI0CON_LSB_MSK (0x1 << 5 ) -#define SPI0CON_LSB (0x1 << 5 ) -#define SPI0CON_LSB_DIS (0x0 << 5 ) /* DIS. MSB is transmitted first. */ -#define SPI0CON_LSB_EN (0x1 << 5 ) /* EN. LSB is transmitted first. */ - -/* SPI0CON[WOM] - Wired OR enable bit. */ -#define SPI0CON_WOM_BBA (*(volatile unsigned long *) 0x42080210) -#define SPI0CON_WOM_MSK (0x1 << 4 ) -#define SPI0CON_WOM (0x1 << 4 ) -#define SPI0CON_WOM_DIS (0x0 << 4 ) /* DIS. Normal driver output operation. */ -#define SPI0CON_WOM_EN (0x1 << 4 ) /* EN. Enable open circuit data output for multimaster/multislave configuration. */ - -/* SPI0CON[CPOL] - Serial clock polarity mode bit. */ -#define SPI0CON_CPOL_BBA (*(volatile unsigned long *) 0x4208020C) -#define SPI0CON_CPOL_MSK (0x1 << 3 ) -#define SPI0CON_CPOL (0x1 << 3 ) -#define SPI0CON_CPOL_LOW (0x0 << 3 ) /* LOW. Serial clock idles low. */ -#define SPI0CON_CPOL_HIGH (0x1 << 3 ) /* HIGH. Serial clock idles high. */ - -/* SPI0CON[CPHA] - Serial clock phase mode bit. */ -#define SPI0CON_CPHA_BBA (*(volatile unsigned long *) 0x42080208) -#define SPI0CON_CPHA_MSK (0x1 << 2 ) -#define SPI0CON_CPHA (0x1 << 2 ) -#define SPI0CON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING. Serial clock pulses at the middle of the first data bit transfer. */ -#define SPI0CON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING. Serial clock pulses at the start of the first data bit. */ - -/* SPI0CON[MASEN] - Master mode enable bit. */ -#define SPI0CON_MASEN_BBA (*(volatile unsigned long *) 0x42080204) -#define SPI0CON_MASEN_MSK (0x1 << 1 ) -#define SPI0CON_MASEN (0x1 << 1 ) -#define SPI0CON_MASEN_DIS (0x0 << 1 ) /* DIS. Configure in slave mode. */ -#define SPI0CON_MASEN_EN (0x1 << 1 ) /* EN. Configure in master mode. */ - -/* SPI0CON[ENABLE] - SPI enable bit. */ -#define SPI0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42080200) -#define SPI0CON_ENABLE_MSK (0x1 << 0 ) -#define SPI0CON_ENABLE (0x1 << 0 ) -#define SPI0CON_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable the SPI. Clearing this bit will also reset all the FIFO related logic to enable a clean start. */ -#define SPI0CON_ENABLE_EN (0x1 << 0 ) /* EN. Enable the SPI. */ - -/* Reset Value for SPI0DMA*/ -#define SPI0DMA_RVAL 0x0 - -/* SPI0DMA[IENRXDMA] - Receive DMA request enable bit. */ -#define SPI0DMA_IENRXDMA_BBA (*(volatile unsigned long *) 0x42080288) -#define SPI0DMA_IENRXDMA_MSK (0x1 << 2 ) -#define SPI0DMA_IENRXDMA (0x1 << 2 ) -#define SPI0DMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS. Disable Rx DMA requests. */ -#define SPI0DMA_IENRXDMA_EN (0x1 << 2 ) /* EN. Enable Rx DMA requests. */ - -/* SPI0DMA[IENTXDMA] - Transmit DMA request enable bit. */ -#define SPI0DMA_IENTXDMA_BBA (*(volatile unsigned long *) 0x42080284) -#define SPI0DMA_IENTXDMA_MSK (0x1 << 1 ) -#define SPI0DMA_IENTXDMA (0x1 << 1 ) -#define SPI0DMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS. Disable Tx DMA requests. */ -#define SPI0DMA_IENTXDMA_EN (0x1 << 1 ) /* EN. Enable Tx DMA requests. */ - -/* SPI0DMA[ENABLE] - DMA data transfer enable bit. */ -#define SPI0DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42080280) -#define SPI0DMA_ENABLE_MSK (0x1 << 0 ) -#define SPI0DMA_ENABLE (0x1 << 0 ) -#define SPI0DMA_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable DMA transfer. This bit needs to be cleared to prevent extra DMA request to the µDMA controller. */ -#define SPI0DMA_ENABLE_EN (0x1 << 0 ) /* EN. Enable a DMA transfer. Starts the transfer of a master configured to initiate transfer on transmit. */ - -/* Reset Value for SPI0CNT*/ -#define SPI0CNT_RVAL 0x0 - -/* SPI0CNT[VALUE] - Number of bytes requested by the SPI master during DMA transfer, when configured to initiate a transfer on a read of SPI0RX. This register is only used in DMA, master, Rx mode. */ -#define SPI0CNT_VALUE_MSK (0xFF << 0 ) -#if (__NO_MMR_STRUCTS__==1) - -#define SPI1STA (*(volatile unsigned short int *) 0x40004400) -#define SPI1RX (*(volatile unsigned char *) 0x40004404) -#define SPI1TX (*(volatile unsigned char *) 0x40004408) -#define SPI1DIV (*(volatile unsigned short int *) 0x4000440C) -#define SPI1CON (*(volatile unsigned short int *) 0x40004410) -#define SPI1DMA (*(volatile unsigned short int *) 0x40004414) -#define SPI1CNT (*(volatile unsigned short int *) 0x40004418) -#endif // (__NO_MMR_STRUCTS__==1) - -/* Reset Value for SPI1STA*/ -#define SPI1STA_RVAL 0x0 - -/* SPI1STA[CSERR] - CS error status bit. This bit generates an interrupt when detecting an abrupt CS desassertion before the full byte of data is transmitted completely. */ -#define SPI1STA_CSERR_BBA (*(volatile unsigned long *) 0x42088030) -#define SPI1STA_CSERR_MSK (0x1 << 12 ) -#define SPI1STA_CSERR (0x1 << 12 ) -#define SPI1STA_CSERR_CLR (0x0 << 12 ) /* CLR: Cleared when no CS error is detected. Cleared to 0 on a read of SPI1STA register. */ -#define SPI1STA_CSERR_SET (0x1 << 12 ) /* SET. Set when the CS line is deasserted abruptly. */ - -/* SPI1STA[RXS] - Rx FIFO excess bytes present. */ -#define SPI1STA_RXS_BBA (*(volatile unsigned long *) 0x4208802C) -#define SPI1STA_RXS_MSK (0x1 << 11 ) -#define SPI1STA_RXS (0x1 << 11 ) -#define SPI1STA_RXS_CLR (0x0 << 11 ) /* CLR. When the number of bytes in the FIFO is equal or less than the number in SPI0CON[15:14]. This bit is not cleared on a read of SPI0STA register. */ -#define SPI1STA_RXS_SET (0x1 << 11 ) /* SET. When there are more bytes in the Rx FIFO than configured in MOD (SPI1CON[15:14]). For example if MOD = TX1RX1, RXS is set when there are 2 or more bytes in the Rx FIFO. This bit does not dependent on SPI1CON[6] and does not cause an interrupt. */ - -/* SPI1STA[RXFSTA] - Rx FIFO status bits, indicates how many valid bytes are in the Rx FIFO. */ -#define SPI1STA_RXFSTA_MSK (0x7 << 8 ) -#define SPI1STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY. When Rx FIFO is empty. */ -#define SPI1STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE. When 1 valid byte is in the FIFO. */ -#define SPI1STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES. When 2 valid bytes are in the FIFO. */ -#define SPI1STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES. When 3 valid bytes are in the FIFO. */ -#define SPI1STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES. When 4 valid bytes are in the FIFO. */ - -/* SPI1STA[RXOF] - Rx FIFO overflow status bit. This bit generates an interrupt. */ -#define SPI1STA_RXOF_BBA (*(volatile unsigned long *) 0x4208801C) -#define SPI1STA_RXOF_MSK (0x1 << 7 ) -#define SPI1STA_RXOF (0x1 << 7 ) -#define SPI1STA_RXOF_CLR (0x0 << 7 ) /* CLR.Cleared to 0 on a read of SPI1STA register. */ -#define SPI1STA_RXOF_SET (0x1 << 7 ) /* SET. Set when the Rx FIFO is already full when new data is loaded to the FIFO. This bit generates an interrupt except when RFLUSH is set. (SPI1CON[12]). */ - -/* SPI1STA[RX] - Rx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */ -#define SPI1STA_RX_BBA (*(volatile unsigned long *) 0x42088018) -#define SPI1STA_RX_MSK (0x1 << 6 ) -#define SPI1STA_RX (0x1 << 6 ) -#define SPI1STA_RX_CLR (0x0 << 6 ) /* CLR. Cleared to 0 on a read of SPI1STA register. */ -#define SPI1STA_RX_SET (0x1 << 6 ) /* SET. Set when a receive interrupt occurs. This bit is set when TIM (SPI1CON[6]) is cleared and the required number of bytes have been received. */ - -/* SPI1STA[TX] - Tx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */ -#define SPI1STA_TX_BBA (*(volatile unsigned long *) 0x42088014) -#define SPI1STA_TX_MSK (0x1 << 5 ) -#define SPI1STA_TX (0x1 << 5 ) -#define SPI1STA_TX_CLR (0x0 << 5 ) /* CLR. Cleared to 0 on a read of SPI1STA register. */ -#define SPI1STA_TX_SET (0x1 << 5 ) /* SET. Set when a transmit interrupt occurs. This bit is set when TIM (SPI1CON[6]) is set and the required number of bytes have been transmitted. */ - -/* SPI1STA[TXUR] - Tx FIFO Underrun. This bit generates an interrupt. */ -#define SPI1STA_TXUR_BBA (*(volatile unsigned long *) 0x42088010) -#define SPI1STA_TXUR_MSK (0x1 << 4 ) -#define SPI1STA_TXUR (0x1 << 4 ) -#define SPI1STA_TXUR_CLR (0x0 << 4 ) /* CLR. Cleared to 0 on a read of SPI1STA register. */ -#define SPI1STA_TXUR_SET (0x1 << 4 ) /* SET. Set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when TFLUSH is set in SPI1CON. */ - -/* SPI1STA[TXFSTA] - Tx FIFO status bits, indicates how many valid bytes are in the Tx FIFO. */ -#define SPI1STA_TXFSTA_MSK (0x7 << 1 ) -#define SPI1STA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY. When Tx FIFO is empty. */ -#define SPI1STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE. 1 valid byte is in the FIFO. */ -#define SPI1STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES. 2 valid bytes are in the FIFO. */ -#define SPI1STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES. 3 valid bytes are in the FIFO. */ -#define SPI1STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES. 4 valid bytes are in the FIFO. */ - -/* SPI1STA[IRQ] - Interrupt status bit. */ -#define SPI1STA_IRQ_BBA (*(volatile unsigned long *) 0x42088000) -#define SPI1STA_IRQ_MSK (0x1 << 0 ) -#define SPI1STA_IRQ (0x1 << 0 ) -#define SPI1STA_IRQ_CLR (0x0 << 0 ) /* CLR. Cleared to 0 on a read of SPI1STA register. */ -#define SPI1STA_IRQ_SET (0x1 << 0 ) /* SET. Set to 1 when an SPI1 based interrupt occurs. */ - -/* Reset Value for SPI1RX*/ -#define SPI1RX_RVAL 0x0 - -/* SPI1RX[VALUE] - 8-bit receive register. A read of the RX FIFO returns the next byte to be read from the FIFO. A read of the FIFO when it is empty returns zero. */ -#define SPI1RX_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for SPI1TX*/ -#define SPI1TX_RVAL 0x0 - -/* SPI1TX[VALUE] - 8-bit transmit register. A write to the Tx FIFO address space writes data to the next available location in the Tx FIFO. If the FIFO is full, the oldest byte of data in the FIFO is overwritten. A read from this address location return zero. */ -#define SPI1TX_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for SPI1DIV*/ -#define SPI1DIV_RVAL 0x0 - -/* SPI1DIV[BCRST] - Configures the behavior of SPI communication after an abrupt deassertion of CS. This bit should be set in slave and master mode. */ -#define SPI1DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208819C) -#define SPI1DIV_BCRST_MSK (0x1 << 7 ) -#define SPI1DIV_BCRST (0x1 << 7 ) -#define SPI1DIV_BCRST_DIS (0x0 << 7 ) /* DIS. Resumes communication from where it stopped when the CS is deasserted. The rest of the bits are then received/ transmitted when CS returns low. User code should ignore the CSERR interrupt. */ -#define SPI1DIV_BCRST_EN (0x1 << 7 ) /* EN. Enabled for a clean restart of SPI transfer after a CSERR condition. User code must also clear the SPI enable bit in SPI1CON during the CSERR interrupt. */ - -/* SPI1DIV[DIV] - Factor used to divide UCLK in the generation of the master mode serial clock. */ -#define SPI1DIV_DIV_MSK (0x3F << 0 ) - -/* Reset Value for SPI1CON*/ -#define SPI1CON_RVAL 0x0 - -/* SPI1CON[MOD] - IRQ mode bits. When TIM is set these bits configure when the Tx/Rx interrupts occur in a transfer. For a DMA Rx transfer, these bits should be 00. */ -#define SPI1CON_MOD_MSK (0x3 << 14 ) -#define SPI1CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1. Tx/Rx interrupt occurs when 1 byte has been transmitted/received from/into the FIFO. */ -#define SPI1CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2. Tx/Rx interrupt occurs when 2 bytes have been transmitted/received from/into the FIFO. */ -#define SPI1CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3. Tx/Rx interrupt occurs when 3 bytes have been transmitted/received from/into the FIFO. */ -#define SPI1CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4. Tx/Rx interrupt occurs when 4 bytes have been transmitted/received from/into the FIFO. */ - -/* SPI1CON[TFLUSH] - Tx FIFO flush enable bit. */ -#define SPI1CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42088234) -#define SPI1CON_TFLUSH_MSK (0x1 << 13 ) -#define SPI1CON_TFLUSH (0x1 << 13 ) -#define SPI1CON_TFLUSH_DIS (0x0 << 13 ) /* DIS. Disable Tx FIFO flushing. */ -#define SPI1CON_TFLUSH_EN (0x1 << 13 ) /* EN. Flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the ZEN bit (SPI1CON[7]). Any writes to the Tx FIFO are ignored while this bit is set. */ - -/* SPI1CON[RFLUSH] - Rx FIFO flush enable bit. */ -#define SPI1CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42088230) -#define SPI1CON_RFLUSH_MSK (0x1 << 12 ) -#define SPI1CON_RFLUSH (0x1 << 12 ) -#define SPI1CON_RFLUSH_DIS (0x0 << 12 ) /* DIS. Disable Rx FIFO flushing. */ -#define SPI1CON_RFLUSH_EN (0x1 << 12 ) /* EN. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and TIM = 0 (SPI1CON[6]), a read of the Rx FIFO initiates a transfer. */ - -/* SPI1CON[CON] - Continuous transfer enable bit. */ -#define SPI1CON_CON_BBA (*(volatile unsigned long *) 0x4208822C) -#define SPI1CON_CON_MSK (0x1 << 11 ) -#define SPI1CON_CON (0x1 << 11 ) -#define SPI1CON_CON_DIS (0x0 << 11 ) /* DIS. Disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPIxTX register, then a new transfer is initiated after a stall period of one serial clock cycle. The CS line is deactivated for this one serial clock cycle. */ -#define SPI1CON_CON_EN (0x1 << 11 ) /* EN. Enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. */ - -/* SPI1CON[LOOPBACK] - Loopback enable bit. */ -#define SPI1CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42088228) -#define SPI1CON_LOOPBACK_MSK (0x1 << 10 ) -#define SPI1CON_LOOPBACK (0x1 << 10 ) -#define SPI1CON_LOOPBACK_DIS (0x0 << 10 ) /* DIS. Normal mode. */ -#define SPI1CON_LOOPBACK_EN (0x1 << 10 ) /* EN. Connect MISO to MOSI, thus, data transmitted from Tx register is looped back to the Rx register. SPI must be configured in master mode. */ - -/* SPI1CON[SOEN] - Slave output enable bit. */ -#define SPI1CON_SOEN_BBA (*(volatile unsigned long *) 0x42088224) -#define SPI1CON_SOEN_MSK (0x1 << 9 ) -#define SPI1CON_SOEN (0x1 << 9 ) -#define SPI1CON_SOEN_DIS (0x0 << 9 ) /* DIS. Disable the output driver on the MISO pin. The MISO pin is open-circuit when this bit is clear. */ -#define SPI1CON_SOEN_EN (0x1 << 9 ) /* EN. MISO operates as normal. */ - -/* SPI1CON[RXOF] - RX overflow overwrite enable bit. */ -#define SPI1CON_RXOF_BBA (*(volatile unsigned long *) 0x42088220) -#define SPI1CON_RXOF_MSK (0x1 << 8 ) -#define SPI1CON_RXOF (0x1 << 8 ) -#define SPI1CON_RXOF_DIS (0x0 << 8 ) /* DIS. The new serial byte received is discarded when there is no space left in the FIFO */ -#define SPI1CON_RXOF_EN (0x1 << 8 ) /* EN. The valid data in the Rx register is overwritten by the new serial byte received when there is no space left in the FIFO. */ - -/* SPI1CON[ZEN] - TX underrun: Transmit 0s when Tx FIFO is empty. */ -#define SPI1CON_ZEN_BBA (*(volatile unsigned long *) 0x4208821C) -#define SPI1CON_ZEN_MSK (0x1 << 7 ) -#define SPI1CON_ZEN (0x1 << 7 ) -#define SPI1CON_ZEN_DIS (0x0 << 7 ) /* DIS. The last byte from the previous transmission is shifted out when a transfer is initiated with no valid data in the FIFO. */ -#define SPI1CON_ZEN_EN (0x1 << 7 ) /* EN. Transmit 0x00 when a transfer is initiated with no valid data in the FIFO. */ - -/* SPI1CON[TIM] - Transfer and interrupt mode bit. */ -#define SPI1CON_TIM_BBA (*(volatile unsigned long *) 0x42088218) -#define SPI1CON_TIM_MSK (0x1 << 6 ) -#define SPI1CON_TIM (0x1 << 6 ) -#define SPI1CON_TIM_TXWR (0x1 << 6 ) /* TXWR. Initiate transfer with a write to the SPIxTX register. Interrupt only occurs when Tx is empty. */ -#define SPI1CON_TIM_RXRD (0x0 << 6 ) /* RXRD. Initiate transfer with a read of the SPIxRX register. The read must be done while the SPI interface is idle. Interrupt only occurs when Rx is full. */ - -/* SPI1CON[LSB] - LSB first transfer enable bit. */ -#define SPI1CON_LSB_BBA (*(volatile unsigned long *) 0x42088214) -#define SPI1CON_LSB_MSK (0x1 << 5 ) -#define SPI1CON_LSB (0x1 << 5 ) -#define SPI1CON_LSB_DIS (0x0 << 5 ) /* DIS. MSB is transmitted first. */ -#define SPI1CON_LSB_EN (0x1 << 5 ) /* EN. LSB is transmitted first. */ - -/* SPI1CON[WOM] - Wired OR enable bit. */ -#define SPI1CON_WOM_BBA (*(volatile unsigned long *) 0x42088210) -#define SPI1CON_WOM_MSK (0x1 << 4 ) -#define SPI1CON_WOM (0x1 << 4 ) -#define SPI1CON_WOM_DIS (0x0 << 4 ) /* DIS. Normal driver output operation. */ -#define SPI1CON_WOM_EN (0x1 << 4 ) /* EN. Enable open circuit data output for multimaster/multislave configuration. */ - -/* SPI1CON[CPOL] - Serial clock polarity mode bit. */ -#define SPI1CON_CPOL_BBA (*(volatile unsigned long *) 0x4208820C) -#define SPI1CON_CPOL_MSK (0x1 << 3 ) -#define SPI1CON_CPOL (0x1 << 3 ) -#define SPI1CON_CPOL_LOW (0x0 << 3 ) /* LOW. Serial clock idles low. */ -#define SPI1CON_CPOL_HIGH (0x1 << 3 ) /* HIGH. Serial clock idles high. */ - -/* SPI1CON[CPHA] - Serial clock phase mode bit. */ -#define SPI1CON_CPHA_BBA (*(volatile unsigned long *) 0x42088208) -#define SPI1CON_CPHA_MSK (0x1 << 2 ) -#define SPI1CON_CPHA (0x1 << 2 ) -#define SPI1CON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING. Serial clock pulses at the middle of the first data bit transfer. */ -#define SPI1CON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING. Serial clock pulses at the start of the first data bit. */ - -/* SPI1CON[MASEN] - Master mode enable bit. */ -#define SPI1CON_MASEN_BBA (*(volatile unsigned long *) 0x42088204) -#define SPI1CON_MASEN_MSK (0x1 << 1 ) -#define SPI1CON_MASEN (0x1 << 1 ) -#define SPI1CON_MASEN_DIS (0x0 << 1 ) /* DIS. Configure in slave mode. */ -#define SPI1CON_MASEN_EN (0x1 << 1 ) /* EN. Configure in master mode. */ - -/* SPI1CON[ENABLE] - SPI enable bit. */ -#define SPI1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42088200) -#define SPI1CON_ENABLE_MSK (0x1 << 0 ) -#define SPI1CON_ENABLE (0x1 << 0 ) -#define SPI1CON_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable the SPI. Clearing this bit will also reset all the FIFO related logic to enable a clean start. */ -#define SPI1CON_ENABLE_EN (0x1 << 0 ) /* EN. Enable the SPI. */ - -/* Reset Value for SPI1DMA*/ -#define SPI1DMA_RVAL 0x0 - -/* SPI1DMA[IENRXDMA] - Receive DMA request enable bit. */ -#define SPI1DMA_IENRXDMA_BBA (*(volatile unsigned long *) 0x42088288) -#define SPI1DMA_IENRXDMA_MSK (0x1 << 2 ) -#define SPI1DMA_IENRXDMA (0x1 << 2 ) -#define SPI1DMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS. Disable Rx DMA requests. */ -#define SPI1DMA_IENRXDMA_EN (0x1 << 2 ) /* EN. Enable Rx DMA requests. */ - -/* SPI1DMA[IENTXDMA] - Transmit DMA request enable bit. */ -#define SPI1DMA_IENTXDMA_BBA (*(volatile unsigned long *) 0x42088284) -#define SPI1DMA_IENTXDMA_MSK (0x1 << 1 ) -#define SPI1DMA_IENTXDMA (0x1 << 1 ) -#define SPI1DMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS. Disable Tx DMA requests. */ -#define SPI1DMA_IENTXDMA_EN (0x1 << 1 ) /* EN. Enable Tx DMA requests. */ - -/* SPI1DMA[ENABLE] - DMA data transfer enable bit. */ -#define SPI1DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42088280) -#define SPI1DMA_ENABLE_MSK (0x1 << 0 ) -#define SPI1DMA_ENABLE (0x1 << 0 ) -#define SPI1DMA_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable DMA transfer. This bit needs to be cleared to prevent extra DMA request to the µDMA controller. */ -#define SPI1DMA_ENABLE_EN (0x1 << 0 ) /* EN. Enable a DMA transfer. Starts the transfer of a master configured to initiate transfer on transmit. */ - -/* Reset Value for SPI1CNT*/ -#define SPI1CNT_RVAL 0x0 - -/* SPI1CNT[VALUE] - Number of bytes requested by the SPI master during DMA transfer, when configured to initiate a transfer on a read of SPI0RX. This register is only used in DMA, master, Rx mode.. */ -#define SPI1CNT_VALUE_MSK (0xFF << 0 ) -// ------------------------------------------------------------------------------------------------ -// ----- T0 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Timer 0 (pADI_TM0) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_TM0 Structure */ - __IO uint16_t LD; /*!< 16-bit Load Value */ - __I uint16_t RESERVED0; - __IO uint16_t VAL; /*!< 16-bit Timer Value */ - __I uint16_t RESERVED1; - __IO uint16_t CON; /*!< Control Register */ - __I uint16_t RESERVED2; - __IO uint16_t CLRI; /*!< Clear Interrupt Register */ - __I uint16_t RESERVED3; - __IO uint16_t CAP; /*!< Capture Register */ - __I uint16_t RESERVED4[5]; - __IO uint16_t STA; /*!< Status Register */ -} ADI_TIMER_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define T0LD (*(volatile unsigned short int *) 0x40000000) -#define T0VAL (*(volatile unsigned short int *) 0x40000004) -#define T0CON (*(volatile unsigned short int *) 0x40000008) -#define T0CLRI (*(volatile unsigned short int *) 0x4000000C) -#define T0CAP (*(volatile unsigned short int *) 0x40000010) -#define T0STA (*(volatile unsigned short int *) 0x4000001C) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for T0LD*/ -#define T0LD_RVAL 0x0 - -/* T0LD[VALUE] - Load value. */ -#define T0LD_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T0VAL*/ -#define T0VAL_RVAL 0x0 - -/* T0VAL[VALUE] - Current counter value. */ -#define T0VAL_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T0CON*/ -#define T0CON_RVAL 0xA - -/* T0CON[EVENTEN] - Enable event bit. */ -#define T0CON_EVENTEN_BBA (*(volatile unsigned long *) 0x42000130) -#define T0CON_EVENTEN_MSK (0x1 << 12 ) -#define T0CON_EVENTEN (0x1 << 12 ) -#define T0CON_EVENTEN_DIS (0x0 << 12 ) /* DIS. Cleared by user. */ -#define T0CON_EVENTEN_EN (0x1 << 12 ) /* EN. Enable time capture of an event. */ - -/* T0CON[EVENT] - Event select bits. Settings not described are reserved and should not be used. */ -#define T0CON_EVENT_MSK (0xF << 8 ) -#define T0CON_EVENT_T2 (0x0 << 8 ) /* T2. Wakeup Timer. */ -#define T0CON_EVENT_EXT0 (0x1 << 8 ) /* EXT0. External interrupt 0. */ -#define T0CON_EVENT_EXT1 (0x2 << 8 ) /* EXT1. External interrupt 1. */ -#define T0CON_EVENT_EXT2 (0x3 << 8 ) /* EXT2. External interrupt 2. */ -#define T0CON_EVENT_EXT3 (0x4 << 8 ) /* EXT3. External interrupt 3. */ -#define T0CON_EVENT_EXT4 (0x5 << 8 ) /* EXT4. External interrupt 4. */ -#define T0CON_EVENT_EXT5 (0x6 << 8 ) /* EXT5. External interrupt 5. */ -#define T0CON_EVENT_EXT6 (0x7 << 8 ) /* EXT6. External interrupt 6. */ -#define T0CON_EVENT_EXT7 (0x8 << 8 ) /* EXT7. External interrupt 7. */ -#define T0CON_EVENT_EXT8 (0x9 << 8 ) /* EXT8. External interrupt 8. */ -#define T0CON_EVENT_T3 (0xA << 8 ) /* T3. Watchdog timer. */ -#define T0CON_EVENT_T1 (0xC << 8 ) /* T1. Timer 1. */ -#define T0CON_EVENT_ADC (0xD << 8 ) /* ADC. Analog to Digital Converter. */ -#define T0CON_EVENT_FEE (0xE << 8 ) /* FEE. Flash Controller. */ -#define T0CON_EVENT_COM (0xF << 8 ) /* COM. UART Peripheral. */ - -/* T0CON[RLD] - Reload control bit for periodic mode. */ -#define T0CON_RLD_BBA (*(volatile unsigned long *) 0x4200011C) -#define T0CON_RLD_MSK (0x1 << 7 ) -#define T0CON_RLD (0x1 << 7 ) -#define T0CON_RLD_DIS (0x0 << 7 ) /* DIS. Reload on a time out. */ -#define T0CON_RLD_EN (0x1 << 7 ) /* EN. Reload the counter on a write to T0CLRI. */ - -/* T0CON[CLK] - Clock select. */ -#define T0CON_CLK_MSK (0x3 << 5 ) -#define T0CON_CLK_UCLK (0x0 << 5 ) /* UCLK. Undivided system clock. */ -#define T0CON_CLK_PCLK (0x1 << 5 ) /* PCLK. Peripheral clock. */ -#define T0CON_CLK_LFOSC (0x2 << 5 ) /* LFOSC. 32 kHz internal oscillator. */ -#define T0CON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL. 32 kHz external crystal. */ - -/* T0CON[ENABLE] - Timer enable bit. */ -#define T0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42000110) -#define T0CON_ENABLE_MSK (0x1 << 4 ) -#define T0CON_ENABLE (0x1 << 4 ) -#define T0CON_ENABLE_DIS (0x0 << 4 ) /* DIS. Disable the timer. Clearing this bit resets the timer, including the T0VAL register. */ -#define T0CON_ENABLE_EN (0x1 << 4 ) /* EN. Enable the timer. The timer starts counting from its initial value, 0 if count-up mode or 0xFFFF if count-down mode. */ - -/* T0CON[MOD] - Timer mode. */ -#define T0CON_MOD_BBA (*(volatile unsigned long *) 0x4200010C) -#define T0CON_MOD_MSK (0x1 << 3 ) -#define T0CON_MOD (0x1 << 3 ) -#define T0CON_MOD_FREERUN (0x0 << 3 ) /* FREERUN. Operate in free running mode. */ -#define T0CON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC. Operate in periodic mode. */ - -/* T0CON[UP] - Count down/up. */ -#define T0CON_UP_BBA (*(volatile unsigned long *) 0x42000108) -#define T0CON_UP_MSK (0x1 << 2 ) -#define T0CON_UP (0x1 << 2 ) -#define T0CON_UP_DIS (0x0 << 2 ) /* DIS. Timer to count down. */ -#define T0CON_UP_EN (0x1 << 2 ) /* EN. Timer to count up. */ - -/* T0CON[PRE] - Prescaler. */ -#define T0CON_PRE_MSK (0x3 << 0 ) -#define T0CON_PRE_DIV1 (0x0 << 0 ) /* DIV1. Source clock/1.If the selected clock source is UCLK or PCLK this setting results in a prescaler of 4. */ -#define T0CON_PRE_DIV16 (0x1 << 0 ) /* DIV16. Source clock/16. */ -#define T0CON_PRE_DIV256 (0x2 << 0 ) /* DIV256. Source clock/256. */ -#define T0CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768. Source clock/32768. */ - -/* Reset Value for T0CLRI*/ -#define T0CLRI_RVAL 0x0 - -/* T0CLRI[CAP] - Clear captured event interrupt. */ -#define T0CLRI_CAP_BBA (*(volatile unsigned long *) 0x42000184) -#define T0CLRI_CAP_MSK (0x1 << 1 ) -#define T0CLRI_CAP (0x1 << 1 ) -#define T0CLRI_CAP_CLR (0x1 << 1 ) /* CLR. Clear a captured event interrupt. This bit always reads 0. */ - -/* T0CLRI[TMOUT] - Clear timeout interrupt. */ -#define T0CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42000180) -#define T0CLRI_TMOUT_MSK (0x1 << 0 ) -#define T0CLRI_TMOUT (0x1 << 0 ) -#define T0CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR. Clear a timeout interrupt. This bit always reads 0. */ - -/* Reset Value for T0CAP*/ -#define T0CAP_RVAL 0x0 - -/* T0CAP[VALUE] - Capture value. */ -#define T0CAP_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T0STA*/ -#define T0STA_RVAL 0x0 - -/* T0STA[CLRI] - T0CLRI write sync in progress.. */ -#define T0STA_CLRI_BBA (*(volatile unsigned long *) 0x4200039C) -#define T0STA_CLRI_MSK (0x1 << 7 ) -#define T0STA_CLRI (0x1 << 7 ) -#define T0STA_CLRI_CLR (0x0 << 7 ) /* CLR. Cleared when the interrupt is cleared in the timer clock domain. */ -#define T0STA_CLRI_SET (0x1 << 7 ) /* SET. Set automatically when the T0CLRI value is being updated in the timer clock domain, indicating that the timer’s configuration is not yet valid. */ - -/* T0STA[CON] - T0CON write sync in progress. */ -#define T0STA_CON_BBA (*(volatile unsigned long *) 0x42000398) -#define T0STA_CON_MSK (0x1 << 6 ) -#define T0STA_CON (0x1 << 6 ) -#define T0STA_CON_CLR (0x0 << 6 ) /* CLR. Timer ready to receive commands to T0CON. The previous change of T0CON has been synchronized in the timer clock domain. */ -#define T0STA_CON_SET (0x1 << 6 ) /* SET. Timer not ready to receive commands to T0CON. Previous change of the T0CON value has not been synchronized in the timer clock domain. */ - -/* T0STA[CAP] - Capture event pending. */ -#define T0STA_CAP_BBA (*(volatile unsigned long *) 0x42000384) -#define T0STA_CAP_MSK (0x1 << 1 ) -#define T0STA_CAP (0x1 << 1 ) -#define T0STA_CAP_CLR (0x0 << 1 ) /* CLR. No capture event is pending. */ -#define T0STA_CAP_SET (0x1 << 1 ) /* SET. Capture event is pending. */ - -/* T0STA[TMOUT] - Time out event occurred. */ -#define T0STA_TMOUT_BBA (*(volatile unsigned long *) 0x42000380) -#define T0STA_TMOUT_MSK (0x1 << 0 ) -#define T0STA_TMOUT (0x1 << 0 ) -#define T0STA_TMOUT_CLR (0x0 << 0 ) /* CLR. No timeout event has occurred. */ -#define T0STA_TMOUT_SET (0x1 << 0 ) /* SET. Timeout event has occurred. For count-up mode, this is when the counter reaches full scale. For count-down mode, this is when the counter reaches 0. */ -#if (__NO_MMR_STRUCTS__==1) - -#define T1LD (*(volatile unsigned short int *) 0x40000400) -#define T1VAL (*(volatile unsigned short int *) 0x40000404) -#define T1CON (*(volatile unsigned short int *) 0x40000408) -#define T1CLRI (*(volatile unsigned short int *) 0x4000040C) -#define T1CAP (*(volatile unsigned short int *) 0x40000410) -#define T1STA (*(volatile unsigned short int *) 0x4000041C) -#endif // (__NO_MMR_STRUCTS__==1) - -/* Reset Value for T1LD*/ -#define T1LD_RVAL 0x0 - -/* T1LD[VALUE] - Load value. */ -#define T1LD_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T1VAL*/ -#define T1VAL_RVAL 0x0 - -/* T1VAL[VALUE] - Current counter value. */ -#define T1VAL_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T1CON*/ -#define T1CON_RVAL 0xA - -/* T1CON[EVENTEN] - Enable event bit. */ -#define T1CON_EVENTEN_BBA (*(volatile unsigned long *) 0x42008130) -#define T1CON_EVENTEN_MSK (0x1 << 12 ) -#define T1CON_EVENTEN (0x1 << 12 ) -#define T1CON_EVENTEN_DIS (0x0 << 12 ) /* DIS. Cleared by user. */ -#define T1CON_EVENTEN_EN (0x1 << 12 ) /* EN. Enable time capture of an event. */ - -/* T1CON[EVENT] - Event select bits. Settings not described are reserved and should not be used. */ -#define T1CON_EVENT_MSK (0xF << 8 ) -#define T1CON_EVENT_T0 (0x0 << 8 ) /* T0. Timer 0. */ -#define T1CON_EVENT_SPI0 (0x1 << 8 ) /* SPI0. SPI0 Peripheral. */ -#define T1CON_EVENT_SPI1 (0x2 << 8 ) /* SPI1. SPI1 Peripheral. */ -#define T1CON_EVENT_I2CS (0x3 << 8 ) /* I2CS. I2C slave peripheral. */ -#define T1CON_EVENT_I2CM (0x4 << 8 ) /* I2CM. I2C master peripheral. */ -#define T1CON_EVENT_DMAERR (0x6 << 8 ) /* DMAERR. DMA error */ -#define T1CON_EVENT_DMADONE (0x7 << 8 ) /* DMADONE. Completion of transfer on any of the DMA channel. */ -#define T1CON_EVENT_EXT1 (0x8 << 8 ) /* EXT1. External interrupt 1. */ -#define T1CON_EVENT_EXT2 (0x9 << 8 ) /* EXT2. External interrupt 2. */ -#define T1CON_EVENT_EXT3 (0xA << 8 ) /* EXT3. External interrupt 3. */ -#define T1CON_EVENT_PWMTRIP (0xB << 8 ) /* PWMTRIP. */ -#define T1CON_EVENT_PWM0 (0xC << 8 ) /* PWM0. PWM pair 0. */ -#define T1CON_EVENT_PWM1 (0xD << 8 ) /* PWM1. PWM pair 1. */ -#define T1CON_EVENT_PWM2 (0xE << 8 ) /* PWM2. PWM pair 2. */ -#define T1CON_EVENT_PWM3 (0xF << 8 ) /* PWM3. PWM pair 3. */ - -/* T1CON[RLD] - Reload control bit for periodic mode. */ -#define T1CON_RLD_BBA (*(volatile unsigned long *) 0x4200811C) -#define T1CON_RLD_MSK (0x1 << 7 ) -#define T1CON_RLD (0x1 << 7 ) -#define T1CON_RLD_DIS (0x0 << 7 ) /* DIS. Reload on a time out. */ -#define T1CON_RLD_EN (0x1 << 7 ) /* EN. Reload the counter on a write to T1CLRI. */ - -/* T1CON[CLK] - Clock select. */ -#define T1CON_CLK_MSK (0x3 << 5 ) -#define T1CON_CLK_UCLK (0x0 << 5 ) /* UCLK. Undivided system clock. */ -#define T1CON_CLK_PCLK (0x1 << 5 ) /* PCLK. Peripheral clock. */ -#define T1CON_CLK_LFOSC (0x2 << 5 ) /* LFOSC. 32 kHz internal oscillator. */ -#define T1CON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL. 32 kHz external crystal. */ - -/* T1CON[ENABLE] - Timer enable bit. */ -#define T1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42008110) -#define T1CON_ENABLE_MSK (0x1 << 4 ) -#define T1CON_ENABLE (0x1 << 4 ) -#define T1CON_ENABLE_DIS (0x0 << 4 ) /* DIS. Disable the timer. Clearing this bit resets the timer, including the T1VAL register. */ -#define T1CON_ENABLE_EN (0x1 << 4 ) /* EN. Enable the timer. The timer starts counting from its initial value, 0 if count-up mode or 0xFFFF if count-down mode. */ - -/* T1CON[MOD] - Timer mode. */ -#define T1CON_MOD_BBA (*(volatile unsigned long *) 0x4200810C) -#define T1CON_MOD_MSK (0x1 << 3 ) -#define T1CON_MOD (0x1 << 3 ) -#define T1CON_MOD_FREERUN (0x0 << 3 ) /* FREERUN. Operate in free running mode. */ -#define T1CON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC. Operate in periodic mode. */ - -/* T1CON[UP] - Count down/up. */ -#define T1CON_UP_BBA (*(volatile unsigned long *) 0x42008108) -#define T1CON_UP_MSK (0x1 << 2 ) -#define T1CON_UP (0x1 << 2 ) -#define T1CON_UP_DIS (0x0 << 2 ) /* DIS. Timer to count down. */ -#define T1CON_UP_EN (0x1 << 2 ) /* EN. Timer to count up. */ - -/* T1CON[PRE] - Prescaler. */ -#define T1CON_PRE_MSK (0x3 << 0 ) -#define T1CON_PRE_DIV1 (0x0 << 0 ) /* DIV1. Source clock/1.If the selected clock source is UCLK or PCLK this setting results in a prescaler of 4. */ -#define T1CON_PRE_DIV16 (0x1 << 0 ) /* DIV16. Source clock/16. */ -#define T1CON_PRE_DIV256 (0x2 << 0 ) /* DIV256. Source clock/256. */ -#define T1CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768. Source clock/32768. */ - -/* Reset Value for T1CLRI*/ -#define T1CLRI_RVAL 0x0 - -/* T1CLRI[CAP] - Clear captured event interrupt. */ -#define T1CLRI_CAP_BBA (*(volatile unsigned long *) 0x42008184) -#define T1CLRI_CAP_MSK (0x1 << 1 ) -#define T1CLRI_CAP (0x1 << 1 ) -#define T1CLRI_CAP_CLR (0x1 << 1 ) /* CLR. Clear a captured event interrupt. This bit always reads 0. */ - -/* T1CLRI[TMOUT] - Clear timeout interrupt. */ -#define T1CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42008180) -#define T1CLRI_TMOUT_MSK (0x1 << 0 ) -#define T1CLRI_TMOUT (0x1 << 0 ) -#define T1CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR. Clear a timeout interrupt. This bit always reads 0. */ - -/* Reset Value for T1CAP*/ -#define T1CAP_RVAL 0x0 - -/* T1CAP[VALUE] - Capture value. */ -#define T1CAP_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T1STA*/ -#define T1STA_RVAL 0x0 - -/* T1STA[CLRI] - T1CLRI write sync in progress. */ -#define T1STA_CLRI_BBA (*(volatile unsigned long *) 0x4200839C) -#define T1STA_CLRI_MSK (0x1 << 7 ) -#define T1STA_CLRI (0x1 << 7 ) -#define T1STA_CLRI_CLR (0x0 << 7 ) /* CLR. Cleared when the interrupt is cleared in the timer clock domain. */ -#define T1STA_CLRI_SET (0x1 << 7 ) /* SET. Set automatically when the T1CLRI value is being updated in the timer clock domain, indicating that the timer’s configuration is not yet valid. */ - -/* T1STA[CON] - T1CON write sync in progress. */ -#define T1STA_CON_BBA (*(volatile unsigned long *) 0x42008398) -#define T1STA_CON_MSK (0x1 << 6 ) -#define T1STA_CON (0x1 << 6 ) -#define T1STA_CON_CLR (0x0 << 6 ) /* CLR. Timer ready to receive commands to T1CON. The previous change of T1CON has been synchronized in the timer clock domain. */ -#define T1STA_CON_SET (0x1 << 6 ) /* SET. Timer not ready to receive commands to T1CON. Previous change of the T1CON value has not been synchronized in the timer clock domain. */ - -/* T1STA[CAP] - Capture event pending. */ -#define T1STA_CAP_BBA (*(volatile unsigned long *) 0x42008384) -#define T1STA_CAP_MSK (0x1 << 1 ) -#define T1STA_CAP (0x1 << 1 ) -#define T1STA_CAP_CLR (0x0 << 1 ) /* CLR. No capture event is pending. */ -#define T1STA_CAP_SET (0x1 << 1 ) /* SET. Capture event is pending. */ - -/* T1STA[TMOUT] - Time out event occurred. */ -#define T1STA_TMOUT_BBA (*(volatile unsigned long *) 0x42008380) -#define T1STA_TMOUT_MSK (0x1 << 0 ) -#define T1STA_TMOUT (0x1 << 0 ) -#define T1STA_TMOUT_CLR (0x0 << 0 ) /* CLR. No timeout event has occurred. */ -#define T1STA_TMOUT_SET (0x1 << 0 ) /* SET. Timeout event has occurred. For count-up mode, this is when the counter reaches full scale. For count-down mode, this is when the counter reaches 0. */ -// ------------------------------------------------------------------------------------------------ -// ----- UART ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief UART (pADI_UART) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_UART Structure */ - - union { - __IO uint8_t COMTX; /*!< Transmit Holding Register */ - __IO uint8_t COMRX; /*!< Receive Buffer Register */ - } ; - __I uint8_t RESERVED0[3]; - __IO uint8_t COMIEN; /*!< Interrupt Enable Register */ - __I uint8_t RESERVED1[3]; - __IO uint8_t COMIIR; /*!< Interrupt Identification Register */ - __I uint8_t RESERVED2[3]; - __IO uint8_t COMLCR; /*!< Line Control Register */ - __I uint8_t RESERVED3[3]; - __IO uint8_t COMMCR; /*!< Module Control Register */ - __I uint8_t RESERVED4[3]; - __IO uint8_t COMLSR; /*!< Line Status Register */ - __I uint8_t RESERVED5[3]; - __IO uint8_t COMMSR; /*!< Modem Status Register */ - __I uint8_t RESERVED6[11]; - __IO uint16_t COMFBR; /*!< Fractional Baud Rate Register. */ - __I uint16_t RESERVED7; - __IO uint16_t COMDIV; /*!< Baud Rate Divider Register */ -} ADI_UART_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define COMTX (*(volatile unsigned char *) 0x40005000) -#define COMRX (*(volatile unsigned char *) 0x40005000) -#define COMIEN (*(volatile unsigned char *) 0x40005004) -#define COMIIR (*(volatile unsigned char *) 0x40005008) -#define COMLCR (*(volatile unsigned char *) 0x4000500C) -#define COMMCR (*(volatile unsigned char *) 0x40005010) -#define COMLSR (*(volatile unsigned char *) 0x40005014) -#define COMMSR (*(volatile unsigned char *) 0x40005018) -#define COMFBR (*(volatile unsigned short int *) 0x40005024) -#define COMDIV (*(volatile unsigned short int *) 0x40005028) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for COMTX*/ -#define COMTX_RVAL 0x0 - -/* COMTX[VALUE] - Transmit Holding Register */ -#define COMTX_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for COMRX*/ -#define COMRX_RVAL 0x0 - -/* COMRX[VALUE] - Receive Buffer Register */ -#define COMRX_VALUE_MSK (0xFF << 0 ) - -/* Reset Value for COMIEN*/ -#define COMIEN_RVAL 0x0 - -/* COMIEN[EDMAR] - DMA requests in transmit mode */ -#define COMIEN_EDMAR_BBA (*(volatile unsigned long *) 0x420A0094) -#define COMIEN_EDMAR_MSK (0x1 << 5 ) -#define COMIEN_EDMAR (0x1 << 5 ) -#define COMIEN_EDMAR_DIS (0x0 << 5 ) /* DIS. Disable. */ -#define COMIEN_EDMAR_EN (0x1 << 5 ) /* EN. Enable. */ - -/* COMIEN[EDMAT] - DMA requests in receive mode */ -#define COMIEN_EDMAT_BBA (*(volatile unsigned long *) 0x420A0090) -#define COMIEN_EDMAT_MSK (0x1 << 4 ) -#define COMIEN_EDMAT (0x1 << 4 ) -#define COMIEN_EDMAT_DIS (0x0 << 4 ) /* DIS. Disable. */ -#define COMIEN_EDMAT_EN (0x1 << 4 ) /* EN. Enable. */ - -/* COMIEN[EDSSI] - Modem status interrupt */ -#define COMIEN_EDSSI_BBA (*(volatile unsigned long *) 0x420A008C) -#define COMIEN_EDSSI_MSK (0x1 << 3 ) -#define COMIEN_EDSSI (0x1 << 3 ) -#define COMIEN_EDSSI_DIS (0x0 << 3 ) /* DIS. Disable. */ -#define COMIEN_EDSSI_EN (0x1 << 3 ) /* EN. Enable. */ - -/* COMIEN[ELSI] - Rx status interrupt */ -#define COMIEN_ELSI_BBA (*(volatile unsigned long *) 0x420A0088) -#define COMIEN_ELSI_MSK (0x1 << 2 ) -#define COMIEN_ELSI (0x1 << 2 ) -#define COMIEN_ELSI_DIS (0x0 << 2 ) /* DIS. Disable. */ -#define COMIEN_ELSI_EN (0x1 << 2 ) /* EN. Enable. */ - -/* COMIEN[ETBEI] - Transmit buffer empty interrupt */ -#define COMIEN_ETBEI_BBA (*(volatile unsigned long *) 0x420A0084) -#define COMIEN_ETBEI_MSK (0x1 << 1 ) -#define COMIEN_ETBEI (0x1 << 1 ) -#define COMIEN_ETBEI_DIS (0x0 << 1 ) /* DIS. Disable. */ -#define COMIEN_ETBEI_EN (0x1 << 1 ) /* EN. Enable the transmit interrupt. An interrupt is generated when the COMTX register is empty. Note that if the COMTX is already empty when enabling this bit, an interrupt is generated immediately. */ - -/* COMIEN[ERBFI] - Receive buffer full interrupt */ -#define COMIEN_ERBFI_BBA (*(volatile unsigned long *) 0x420A0080) -#define COMIEN_ERBFI_MSK (0x1 << 0 ) -#define COMIEN_ERBFI (0x1 << 0 ) -#define COMIEN_ERBFI_DIS (0x0 << 0 ) /* DIS. Disable. */ -#define COMIEN_ERBFI_EN (0x1 << 0 ) /* EN. Enable the receive interrupt. An interrupt is generated when the COMRX register is loaded with the received data. Note that if the COMRX is already full when enabling this bit, an interrupt is generated immediately. */ - -/* Reset Value for COMIIR*/ -#define COMIIR_RVAL 0x1 - -/* COMIIR[STA] - Status bits. */ -#define COMIIR_STA_MSK (0x3 << 1 ) -#define COMIIR_STA_MODEMSTATUS (0x0 << 1 ) /* MODEMSTATUS. Modem status interrupt. */ -#define COMIIR_STA_TXBUFEMPTY (0x1 << 1 ) /* TXBUFEMPTY. Transmit buffer empty interrupt. */ -#define COMIIR_STA_RXBUFFULL (0x2 << 1 ) /* RXBUFFULL. Receive buffer full interrupt. Read COMRX register to clear. */ -#define COMIIR_STA_RXLINESTATUS (0x3 << 1 ) /* RXLINESTATUS. Receive line status interrupt. Read COMLSR register to clear. */ - -/* COMIIR[NINT] - Interrupt flag. */ -#define COMIIR_NINT_BBA (*(volatile unsigned long *) 0x420A0100) -#define COMIIR_NINT_MSK (0x1 << 0 ) -#define COMIIR_NINT (0x1 << 0 ) -#define COMIIR_NINT_CLR (0x0 << 0 ) /* CLR. Indicates any of the following: receive buffer full, transmit buffer empty, line status, or modem status interrupt occurred. */ -#define COMIIR_NINT_SET (0x1 << 0 ) /* SET. There is no interrupt (default). */ - -/* Reset Value for COMLCR*/ -#define COMLCR_RVAL 0x0 - -/* COMLCR[BRK] - Set Break. */ -#define COMLCR_BRK_BBA (*(volatile unsigned long *) 0x420A0198) -#define COMLCR_BRK_MSK (0x1 << 6 ) -#define COMLCR_BRK (0x1 << 6 ) -#define COMLCR_BRK_DIS (0x0 << 6 ) /* DIS to operate in normal mode. */ -#define COMLCR_BRK_EN (0x1 << 6 ) /* EN to force TxD to 0. */ - -/* COMLCR[SP] - Stick Parity. */ -#define COMLCR_SP_BBA (*(volatile unsigned long *) 0x420A0194) -#define COMLCR_SP_MSK (0x1 << 5 ) -#define COMLCR_SP (0x1 << 5 ) -#define COMLCR_SP_DIS (0x0 << 5 ) /* DIS. Parity is not forced based on EPS and PEN values. */ -#define COMLCR_SP_EN (0x1 << 5 ) /* EN. Force parity to defined values based on EPS and PEN values. EPS = 1 and PEN = 1, parity forced to 1 EPS = 0 and PEN = 1, parity forced to 0 EPS = X and PEN = 0, no parity transmitted. */ - -/* COMLCR[EPS] - Even Parity Select Bit. */ -#define COMLCR_EPS_BBA (*(volatile unsigned long *) 0x420A0190) -#define COMLCR_EPS_MSK (0x1 << 4 ) -#define COMLCR_EPS (0x1 << 4 ) -#define COMLCR_EPS_DIS (0x0 << 4 ) /* DIS. Odd parity. */ -#define COMLCR_EPS_EN (0x1 << 4 ) /* EN. Even parity. */ - -/* COMLCR[PEN] - Parity Enable Bit. */ -#define COMLCR_PEN_BBA (*(volatile unsigned long *) 0x420A018C) -#define COMLCR_PEN_MSK (0x1 << 3 ) -#define COMLCR_PEN (0x1 << 3 ) -#define COMLCR_PEN_DIS (0x0 << 3 ) /* DIS. No parity transmission or checking. */ -#define COMLCR_PEN_EN (0x1 << 3 ) /* EN. Transmit and check the parity bit. */ - -/* COMLCR[STOP] - Stop Bit. */ -#define COMLCR_STOP_BBA (*(volatile unsigned long *) 0x420A0188) -#define COMLCR_STOP_MSK (0x1 << 2 ) -#define COMLCR_STOP (0x1 << 2 ) -#define COMLCR_STOP_DIS (0x0 << 2 ) /* DIS. Generate one stop bit in the transmitted data. */ -#define COMLCR_STOP_EN (0x1 << 2 ) /* EN. Transmit 1.5 stop bits if the word length is 5 bits, or 2 stop bits if the word length is 6, 7, or 8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. */ - -/* COMLCR[WLS] - Word Length Select Bits. */ -#define COMLCR_WLS_MSK (0x3 << 0 ) -#define COMLCR_WLS_5BITS (0x0 << 0 ) /* 5BITS. 5 bits. */ -#define COMLCR_WLS_6BITS (0x1 << 0 ) /* 6BITS. 6 bits. */ -#define COMLCR_WLS_7BITS (0x2 << 0 ) /* 7BITS. 7 bits. */ -#define COMLCR_WLS_8BITS (0x3 << 0 ) /* 8BITS. 8 bits. */ - -/* Reset Value for COMMCR*/ -#define COMMCR_RVAL 0x0 - -/* COMMCR[LOOPBACK] - Loop Back. */ -#define COMMCR_LOOPBACK_BBA (*(volatile unsigned long *) 0x420A0210) -#define COMMCR_LOOPBACK_MSK (0x1 << 4 ) -#define COMMCR_LOOPBACK (0x1 << 4 ) -#define COMMCR_LOOPBACK_DIS (0x0 << 4 ) /* DIS. Normal mode. */ -#define COMMCR_LOOPBACK_EN (0x1 << 4 ) /* EN. Enable loopback mode. */ - -/* COMMCR[RTS] - Request To Send output control bit. */ -#define COMMCR_RTS_BBA (*(volatile unsigned long *) 0x420A0204) -#define COMMCR_RTS_MSK (0x1 << 1 ) -#define COMMCR_RTS (0x1 << 1 ) -#define COMMCR_RTS_DIS (0x0 << 1 ) /* DIS. Force the RTS output to 1. */ -#define COMMCR_RTS_EN (0x1 << 1 ) /* EN. Force the RTS output to 0. */ - -/* Reset Value for COMLSR*/ -#define COMLSR_RVAL 0x60 - -/* COMLSR[TEMT] - COMTX and Shift Register Empty Status Bit. */ -#define COMLSR_TEMT_BBA (*(volatile unsigned long *) 0x420A0298) -#define COMLSR_TEMT_MSK (0x1 << 6 ) -#define COMLSR_TEMT (0x1 << 6 ) -#define COMLSR_TEMT_CLR (0x0 << 6 ) /* CLR. Cleared when writing to COMTX. */ -#define COMLSR_TEMT_SET (0x1 << 6 ) /* SET. If COMTX and the shift register are empty, this bit indicates that the data has been transmitted, that is, it is no longer present in the shift register (default). */ - -/* COMLSR[THRE] - COMTX Empty Status Bit. */ -#define COMLSR_THRE_BBA (*(volatile unsigned long *) 0x420A0294) -#define COMLSR_THRE_MSK (0x1 << 5 ) -#define COMLSR_THRE (0x1 << 5 ) -#define COMLSR_THRE_CLR (0x0 << 5 ) /* CLR. Cleared when writing to COMTX. */ -#define COMLSR_THRE_SET (0x1 << 5 ) /* SET. If COMTX is empty, COMTX can be written as soon as this bit is set. The previous data may not have been transmitted yet and can still be present in the shift register (default). */ - -/* COMLSR[BI] - Break Indicator. */ -#define COMLSR_BI_BBA (*(volatile unsigned long *) 0x420A0290) -#define COMLSR_BI_MSK (0x1 << 4 ) -#define COMLSR_BI (0x1 << 4 ) -#define COMLSR_BI_CLR (0x0 << 4 ) /* CLR. Cleared automatically. */ -#define COMLSR_BI_SET (0x1 << 4 ) /* SET. Set when UART RXD is held low for more than the maximum word length. */ - -/* COMLSR[FE] - Framing Error. */ -#define COMLSR_FE_BBA (*(volatile unsigned long *) 0x420A028C) -#define COMLSR_FE_MSK (0x1 << 3 ) -#define COMLSR_FE (0x1 << 3 ) -#define COMLSR_FE_CLR (0x0 << 3 ) /* CLR. Cleared automatically. */ -#define COMLSR_FE_SET (0x1 << 3 ) /* SET. Set when the stop bit is invalid. */ - -/* COMLSR[PE] - Parity Error. */ -#define COMLSR_PE_BBA (*(volatile unsigned long *) 0x420A0288) -#define COMLSR_PE_MSK (0x1 << 2 ) -#define COMLSR_PE (0x1 << 2 ) -#define COMLSR_PE_CLR (0x0 << 2 ) /* CLR. Cleared automatically. */ -#define COMLSR_PE_SET (0x1 << 2 ) /* SET. Set when a parity error occurs. */ - -/* COMLSR[OE] - Overrun Error. */ -#define COMLSR_OE_BBA (*(volatile unsigned long *) 0x420A0284) -#define COMLSR_OE_MSK (0x1 << 1 ) -#define COMLSR_OE (0x1 << 1 ) -#define COMLSR_OE_CLR (0x0 << 1 ) /* CLR. Cleared automatically. */ -#define COMLSR_OE_SET (0x1 << 1 ) /* SET. Set automatically if data is overwritten before being read. */ - -/* COMLSR[DR] - Data Ready. */ -#define COMLSR_DR_BBA (*(volatile unsigned long *) 0x420A0280) -#define COMLSR_DR_MSK (0x1 << 0 ) -#define COMLSR_DR (0x1 << 0 ) -#define COMLSR_DR_CLR (0x0 << 0 ) /* CLR. Cleared by reading COMRX. */ -#define COMLSR_DR_SET (0x1 << 0 ) /* SET. Set automatically when COMRX is full. */ - -/* Reset Value for COMMSR*/ -#define COMMSR_RVAL 0x0 - -/* COMMSR[CTS] - Clear To Send signal status bit. */ -#define COMMSR_CTS_BBA (*(volatile unsigned long *) 0x420A0310) -#define COMMSR_CTS_MSK (0x1 << 4 ) -#define COMMSR_CTS (0x1 << 4 ) -#define COMMSR_CTS_CLR (0x0 << 4 ) /* CLR. Cleared to 0 when CTS input is logic high. */ -#define COMMSR_CTS_SET (0x1 << 4 ) /* SET. Set to 1 when CTS input is logic low. */ - -/* COMMSR[DCTS] - Delta CTS */ -#define COMMSR_DCTS_BBA (*(volatile unsigned long *) 0x420A0300) -#define COMMSR_DCTS_MSK (0x1 << 0 ) -#define COMMSR_DCTS (0x1 << 0 ) -#define COMMSR_DCTS_DIS (0x0 << 0 ) /* DIS. Cleared automatically by reading COMMSR. */ -#define COMMSR_DCTS_EN (0x1 << 0 ) /* EN. Set automatically if CTS changed state since COMMSR last read. */ - -/* Reset Value for COMFBR*/ -#define COMFBR_RVAL 0x0 - -/* COMFBR[ENABLE] - Fractional baud rate generator enable bit. Used for more accurate baud rate generation. */ -#define COMFBR_ENABLE_BBA (*(volatile unsigned long *) 0x420A04BC) -#define COMFBR_ENABLE_MSK (0x1 << 15 ) -#define COMFBR_ENABLE (0x1 << 15 ) -#define COMFBR_ENABLE_DIS (0x0 << 15 ) /* DIS. Disable. */ -#define COMFBR_ENABLE_EN (0x1 << 15 ) /* EN. Enable. */ - -/* COMFBR[DIVM] - Fractional baud rate M divide bits (1 to 3). These bits should not be set to 0. */ -#define COMFBR_DIVM_MSK (0x3 << 11 ) - -/* COMFBR[DIVN] - Fractional baud rate N divide bits (0 to 2047). */ -#define COMFBR_DIVN_MSK (0x7FF << 0 ) - -/* Reset Value for COMDIV*/ -#define COMDIV_RVAL 0x1 - -/* COMDIV[VALUE] - Sets the baud rate. The COMDIV register should not be 0. */ -#define COMDIV_VALUE_MSK (0xFFFF << 0 ) -// ------------------------------------------------------------------------------------------------ -// ----- WUT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief WakeUp Timer (pADI_WUT) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_WUT Structure */ - __IO uint16_t T2VAL0; /*!< Current Wake-Up Timer Value LSB */ - __I uint16_t RESERVED0; - __IO uint16_t T2VAL1; /*!< Current Wake-Up Timer Value MSB */ - __I uint16_t RESERVED1; - __IO uint16_t T2CON; /*!< Control Register */ - __I uint16_t RESERVED2; - __IO uint16_t T2INC; /*!< 12-bit Interval Register for Wake-Up Field A */ - __I uint16_t RESERVED3; - __IO uint16_t T2WUFB0; /*!< Wake-Up Field B LSB */ - __I uint16_t RESERVED4; - __IO uint16_t T2WUFB1; /*!< Wake-Up Field B MSB */ - __I uint16_t RESERVED5; - __IO uint16_t T2WUFC0; /*!< Wake-Up Field C LSB */ - __I uint16_t RESERVED6; - __IO uint16_t T2WUFC1; /*!< Wake-Up Field C MSB */ - __I uint16_t RESERVED7; - __IO uint16_t T2WUFD0; /*!< Wake-UpField D LSB */ - __I uint16_t RESERVED8; - __IO uint16_t T2WUFD1; /*!< Wake-Up Field D MSB */ - __I uint16_t RESERVED9; - __IO uint16_t T2IEN; /*!< Interrupt Enable */ - __I uint16_t RESERVED10; - __IO uint16_t T2STA; /*!< Status */ - __I uint16_t RESERVED11; - __IO uint16_t T2CLRI; /*!< Clear Interrupts */ - __I uint16_t RESERVED12[5]; - __IO uint16_t T2WUFA0; /*!< Wake-Up Field A LSB */ - __I uint16_t RESERVED13; - __IO uint16_t T2WUFA1; /*!< Wake-Up Field A MSB */ -} ADI_WUT_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define T2VAL0 (*(volatile unsigned short int *) 0x40002500) -#define T2VAL1 (*(volatile unsigned short int *) 0x40002504) -#define T2CON (*(volatile unsigned short int *) 0x40002508) -#define T2INC (*(volatile unsigned short int *) 0x4000250C) -#define T2WUFB0 (*(volatile unsigned short int *) 0x40002510) -#define T2WUFB1 (*(volatile unsigned short int *) 0x40002514) -#define T2WUFC0 (*(volatile unsigned short int *) 0x40002518) -#define T2WUFC1 (*(volatile unsigned short int *) 0x4000251C) -#define T2WUFD0 (*(volatile unsigned short int *) 0x40002520) -#define T2WUFD1 (*(volatile unsigned short int *) 0x40002524) -#define T2IEN (*(volatile unsigned short int *) 0x40002528) -#define T2STA (*(volatile unsigned short int *) 0x4000252C) -#define T2CLRI (*(volatile unsigned short int *) 0x40002530) -#define T2WUFA0 (*(volatile unsigned short int *) 0x4000253C) -#define T2WUFA1 (*(volatile unsigned short int *) 0x40002540) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for T2VAL0*/ -#define T2VAL0_RVAL 0x0 - -/* T2VAL0[VALUE] - Current Wake-Up timer value (bits 15 to 0). */ -#define T2VAL0_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T2VAL1*/ -#define T2VAL1_RVAL 0x0 - -/* T2VAL1[VALUE] - Current Wake-Up timer value (bits 31 to 16). */ -#define T2VAL1_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T2CON*/ -#define T2CON_RVAL 0x40 - -/* T2CON[STOPINC] - Allows the user to update the interval register safely. */ -#define T2CON_STOPINC_BBA (*(volatile unsigned long *) 0x4204A12C) -#define T2CON_STOPINC_MSK (0x1 << 11 ) -#define T2CON_STOPINC (0x1 << 11 ) -#define T2CON_STOPINC_DIS (0x0 << 11 ) /* DIS. Allows the wake-up field A to be updated by hardware. */ -#define T2CON_STOPINC_EN (0x1 << 11 ) /* EN. Prevents wake-up field A being automatically updated by hardware.This allows user software to update the T2INC register value. */ - -/* T2CON[CLK] - Clock select. */ -#define T2CON_CLK_MSK (0x3 << 9 ) -#define T2CON_CLK_PCLK (0x0 << 9 ) /* PCLK. Peripheral clock. */ -#define T2CON_CLK_LFXTAL (0x1 << 9 ) /* LFXTAL. 32 kHz external crystal. */ -#define T2CON_CLK_LFOSC (0x2 << 9 ) /* LFOSC. 32 kHz internal oscillator. */ -#define T2CON_CLK_EXTCLK (0x3 << 9 ) /* EXTCLK. External clock applied on P0.5. */ - -/* T2CON[WUEN] - Wake-up enable bits for time field values. */ -#define T2CON_WUEN_BBA (*(volatile unsigned long *) 0x4204A120) -#define T2CON_WUEN_MSK (0x1 << 8 ) -#define T2CON_WUEN (0x1 << 8 ) -#define T2CON_WUEN_DIS (0x0 << 8 ) /* DIS. Disable asynchronous Wake-Up timer. Interrupt conditions will not wake-up the part from sleep mode. */ -#define T2CON_WUEN_EN (0x1 << 8 ) /* EN. Enable asynchronous Wake-Up timer even when the core clock is off. Once the timer value equals any of the interrupt enabled compare field, a wake-up signal is generated. */ - -/* T2CON[ENABLE] - Timer enable bit. */ -#define T2CON_ENABLE_BBA (*(volatile unsigned long *) 0x4204A11C) -#define T2CON_ENABLE_MSK (0x1 << 7 ) -#define T2CON_ENABLE (0x1 << 7 ) -#define T2CON_ENABLE_DIS (0x0 << 7 ) /* DIS. Disable the timer. */ -#define T2CON_ENABLE_EN (0x1 << 7 ) /* EN. Enable the timer. When enabled wait for T2STA[8] to clear before continuing. */ - -/* T2CON[MOD] - Timer free run enable. */ -#define T2CON_MOD_BBA (*(volatile unsigned long *) 0x4204A118) -#define T2CON_MOD_MSK (0x1 << 6 ) -#define T2CON_MOD (0x1 << 6 ) -#define T2CON_MOD_PERIODIC (0x0 << 6 ) /* PERIODIC. Operate in periodic mode. Counts up to the value in T2WUFD */ -#define T2CON_MOD_FREERUN (0x1 << 6 ) /* FREERUN. Operate in free running mode (default). Counts from 0 to FFFF FFFF and starts again at 0. */ - -/* T2CON[FREEZE] - Freeze enable bit. */ -#define T2CON_FREEZE_BBA (*(volatile unsigned long *) 0x4204A10C) -#define T2CON_FREEZE_MSK (0x1 << 3 ) -#define T2CON_FREEZE (0x1 << 3 ) -#define T2CON_FREEZE_DIS (0x0 << 3 ) /* DIS. Disable this feature. */ -#define T2CON_FREEZE_EN (0x1 << 3 ) /* EN. Enable the freeze of the high 16 bits after the lower bits have been read from T2VAL0. This ensures that the software reads an atomic shot of the timer. The entire T2VAL register unfreezes after the high bits (T2VAL1) have been read. */ - -/* T2CON[PRE] - Prescaler. */ -#define T2CON_PRE_MSK (0x3 << 0 ) -#define T2CON_PRE_DIV1 (0x0 << 0 ) /* DIV1. Source clock/1. If the selected clock source is PCLK this setting results in a prescaler of 4. */ -#define T2CON_PRE_DIV16 (0x1 << 0 ) /* DIV16. Source clock/16. */ -#define T2CON_PRE_DIV256 (0x2 << 0 ) /* DIV256. Source clock/256. */ -#define T2CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768. Source clock/32768. */ - -/* Reset Value for T2INC*/ -#define T2INC_RVAL 0xC8 - -/* T2INC[VALUE] - Wake-up interval */ -#define T2INC_VALUE_MSK (0xFFF << 0 ) - -/* Reset Value for T2WUFB0*/ -#define T2WUFB0_RVAL 0x1FFF - -/* T2WUFB0[VALUE] - Lower 16 bits of Wake-Up Field B */ -#define T2WUFB0_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T2WUFB1*/ -#define T2WUFB1_RVAL 0x0 - -/* T2WUFB1[VALUE] - Upper 16 bits of Wake-Up Field B */ -#define T2WUFB1_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T2WUFC0*/ -#define T2WUFC0_RVAL 0x2FFF - -/* T2WUFC0[VALUE] - Lower 16 bits of Wake-Up Field C */ -#define T2WUFC0_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T2WUFC1*/ -#define T2WUFC1_RVAL 0x0 - -/* T2WUFC1[VALUE] - Upper 16 bits of Wake-Up Field C */ -#define T2WUFC1_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T2WUFD0*/ -#define T2WUFD0_RVAL 0x3FFF - -/* T2WUFD0[VALUE] - Lower 16 bits of Wake-Up Field D */ -#define T2WUFD0_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T2WUFD1*/ -#define T2WUFD1_RVAL 0x0 - -/* T2WUFD1[VALUE] - Upper 16 bits of Wake-Up Field D */ -#define T2WUFD1_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T2IEN*/ -#define T2IEN_RVAL 0x0 - -/* T2IEN[ROLL] - Interrupt enable bit when the counter rolls over. Only occurs in free running mode. */ -#define T2IEN_ROLL_BBA (*(volatile unsigned long *) 0x4204A510) -#define T2IEN_ROLL_MSK (0x1 << 4 ) -#define T2IEN_ROLL (0x1 << 4 ) -#define T2IEN_ROLL_DIS (0x0 << 4 ) /* DIS. Disable the roll over interrupt. */ -#define T2IEN_ROLL_EN (0x1 << 4 ) /* EN. Generate an interrupt when Timer2 rolls over. */ - -/* T2IEN[WUFD] - T2WUFD interrupt enable */ -#define T2IEN_WUFD_BBA (*(volatile unsigned long *) 0x4204A50C) -#define T2IEN_WUFD_MSK (0x1 << 3 ) -#define T2IEN_WUFD (0x1 << 3 ) -#define T2IEN_WUFD_DIS (0x0 << 3 ) /* DIS. Disable T2WUFD interrupt. */ -#define T2IEN_WUFD_EN (0x1 << 3 ) /* EN. Generate an interrupt when T2VAL reaches T2WUFD. */ - -/* T2IEN[WUFC] - T2WUFC interrupt enable */ -#define T2IEN_WUFC_BBA (*(volatile unsigned long *) 0x4204A508) -#define T2IEN_WUFC_MSK (0x1 << 2 ) -#define T2IEN_WUFC (0x1 << 2 ) -#define T2IEN_WUFC_DIS (0x0 << 2 ) /* DIS. Disable T2WUFC interrupt. */ -#define T2IEN_WUFC_EN (0x1 << 2 ) /* EN. Generate an interrupt when T2VAL reaches T2WUFC. */ - -/* T2IEN[WUFB] - T2WUFB interrupt enable */ -#define T2IEN_WUFB_BBA (*(volatile unsigned long *) 0x4204A504) -#define T2IEN_WUFB_MSK (0x1 << 1 ) -#define T2IEN_WUFB (0x1 << 1 ) -#define T2IEN_WUFB_DIS (0x0 << 1 ) /* DIS. Disable T2WUFB interrupt. */ -#define T2IEN_WUFB_EN (0x1 << 1 ) /* EN. Generate an interrupt when T2VAL reaches T2WUFB. */ - -/* T2IEN[WUFA] - T2WUFA interrupt enable */ -#define T2IEN_WUFA_BBA (*(volatile unsigned long *) 0x4204A500) -#define T2IEN_WUFA_MSK (0x1 << 0 ) -#define T2IEN_WUFA (0x1 << 0 ) -#define T2IEN_WUFA_DIS (0x0 << 0 ) /* DIS. Disable T2WUFA interrupt. */ -#define T2IEN_WUFA_EN (0x1 << 0 ) /* EN. Generate an interrupt when T2VAL reaches T2WUFA. */ - -/* Reset Value for T2STA*/ -#define T2STA_RVAL 0x0 - -/* T2STA[CON] - Indicates when a change in the enable bit is synchronized to the 32 kHz clock domain (Done automatically) */ -#define T2STA_CON_BBA (*(volatile unsigned long *) 0x4204A5A0) -#define T2STA_CON_MSK (0x1 << 8 ) -#define T2STA_CON (0x1 << 8 ) -#define T2STA_CON_CLR (0x0 << 8 ) /* CLR. It returns low when the change in the Enable bit has been synchronised to the 32 kHz clock domain. */ -#define T2STA_CON_SET (0x1 << 8 ) /* SET. This bit is set high when the Enable bit (bit 5) in the Control register is set or cleared and it is not synchronised to tthe 32 kHz clock. */ - -/* T2STA[FREEZE] - Status of T2VAL freeze */ -#define T2STA_FREEZE_BBA (*(volatile unsigned long *) 0x4204A59C) -#define T2STA_FREEZE_MSK (0x1 << 7 ) -#define T2STA_FREEZE (0x1 << 7 ) -#define T2STA_FREEZE_CLR (0x0 << 7 ) /* CLR. Reset low when T2VAL1 is read, indicating T2VAL is unfrozen. */ -#define T2STA_FREEZE_SET (0x1 << 7 ) /* SET. Set high when the T2VAL0 is read, indicating T2VAL is frozen. */ - -/* T2STA[ROLL] - Interrupt status bit for instances when counter rolls over. Only occurs in free running mode. */ -#define T2STA_ROLL_BBA (*(volatile unsigned long *) 0x4204A590) -#define T2STA_ROLL_MSK (0x1 << 4 ) -#define T2STA_ROLL (0x1 << 4 ) -#define T2STA_ROLL_CLR (0x0 << 4 ) /* CLR. Indicate that the timer has not rolled over. */ -#define T2STA_ROLL_SET (0x1 << 4 ) /* SET. Set high when enabled in the interrupt enable register and the T2VALS counter register is equal to all 1s */ - -/* T2STA[WUFD] - T2WUFD interrupt flag */ -#define T2STA_WUFD_BBA (*(volatile unsigned long *) 0x4204A58C) -#define T2STA_WUFD_MSK (0x1 << 3 ) -#define T2STA_WUFD (0x1 << 3 ) -#define T2STA_WUFD_CLR (0x0 << 3 ) /* CLR. Cleared after a write to the corresponding bit in T2CLRI. */ -#define T2STA_WUFD_SET (0x1 << 3 ) /* SET. Indicates that a comparator interrupt has occurred. */ - -/* T2STA[WUFC] - T2WUFC interrupt flag */ -#define T2STA_WUFC_BBA (*(volatile unsigned long *) 0x4204A588) -#define T2STA_WUFC_MSK (0x1 << 2 ) -#define T2STA_WUFC (0x1 << 2 ) -#define T2STA_WUFC_CLR (0x0 << 2 ) /* CLR. Cleared after a write to the corresponding bit in T2CLRI. */ -#define T2STA_WUFC_SET (0x1 << 2 ) /* SET. Indicates that a comparator interrupt has occurred. */ - -/* T2STA[WUFB] - T2WUFB interrupt flag */ -#define T2STA_WUFB_BBA (*(volatile unsigned long *) 0x4204A584) -#define T2STA_WUFB_MSK (0x1 << 1 ) -#define T2STA_WUFB (0x1 << 1 ) -#define T2STA_WUFB_CLR (0x0 << 1 ) /* CLR. Cleared after a write to the corresponding bit in T2CLRI. */ -#define T2STA_WUFB_SET (0x1 << 1 ) /* SET. Indicates that a comparator interrupt has occurred. */ - -/* T2STA[WUFA] - T2WUFA interrupt flag */ -#define T2STA_WUFA_BBA (*(volatile unsigned long *) 0x4204A580) -#define T2STA_WUFA_MSK (0x1 << 0 ) -#define T2STA_WUFA (0x1 << 0 ) -#define T2STA_WUFA_CLR (0x0 << 0 ) /* CLR. Cleared after a write to the corresponding bit in T2CLRI. */ -#define T2STA_WUFA_SET (0x1 << 0 ) /* SET. Indicates that a comparator interrupt has occurred. */ - -/* Reset Value for T2CLRI*/ -#define T2CLRI_RVAL 0x0 - -/* T2CLRI[ROLL] - Clear interrupt on Rollover. Only occurs in free running mode. */ -#define T2CLRI_ROLL_BBA (*(volatile unsigned long *) 0x4204A610) -#define T2CLRI_ROLL_MSK (0x1 << 4 ) -#define T2CLRI_ROLL (0x1 << 4 ) -#define T2CLRI_ROLL_CLR (0x1 << 4 ) /* CLR. Interrupt clear bit for when counter rolls over. */ - -/* T2CLRI[WUFD] - T2WUFD interrupt flag. Cleared automatically after synchronization. */ -#define T2CLRI_WUFD_BBA (*(volatile unsigned long *) 0x4204A60C) -#define T2CLRI_WUFD_MSK (0x1 << 3 ) -#define T2CLRI_WUFD (0x1 << 3 ) -#define T2CLRI_WUFD_CLR (0x1 << 3 ) /* CLR. Clear the T2WUFD interrupt flag. */ - -/* T2CLRI[WUFC] - T2WUFC interrupt flag. Cleared automatically after synchronization. */ -#define T2CLRI_WUFC_BBA (*(volatile unsigned long *) 0x4204A608) -#define T2CLRI_WUFC_MSK (0x1 << 2 ) -#define T2CLRI_WUFC (0x1 << 2 ) -#define T2CLRI_WUFC_CLR (0x1 << 2 ) /* CLR. Clear the T2WUFC interrupt flag. */ - -/* T2CLRI[WUFB] - T2WUFB interrupt flag. Cleared automatically after synchronization. */ -#define T2CLRI_WUFB_BBA (*(volatile unsigned long *) 0x4204A604) -#define T2CLRI_WUFB_MSK (0x1 << 1 ) -#define T2CLRI_WUFB (0x1 << 1 ) -#define T2CLRI_WUFB_CLR (0x1 << 1 ) /* CLR. Clear the T2WUFB interrupt flag. */ - -/* T2CLRI[WUFA] - T2WUFA interrupt flag. Cleared automatically after synchronization. */ -#define T2CLRI_WUFA_BBA (*(volatile unsigned long *) 0x4204A600) -#define T2CLRI_WUFA_MSK (0x1 << 0 ) -#define T2CLRI_WUFA (0x1 << 0 ) -#define T2CLRI_WUFA_CLR (0x1 << 0 ) /* CLR. Clear the T2WUFA interrupt flag. */ - -/* Reset Value for T2WUFA0*/ -#define T2WUFA0_RVAL 0x1900 - -/* T2WUFA0[VALUE] - Lower 16 bits of Compare Register A */ -#define T2WUFA0_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T2WUFA1*/ -#define T2WUFA1_RVAL 0x0 - -/* T2WUFA1[VALUE] - Upper 16 bits of Compare Register A */ -#define T2WUFA1_VALUE_MSK (0xFFFF << 0 ) -// ------------------------------------------------------------------------------------------------ -// ----- WDT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Watchdog Timer (pADI_WDT) - */ - -#if (__NO_MMR_STRUCTS__==0) -typedef struct { /*!< pADI_WDT Structure */ - __IO uint16_t T3LD; /*!< 16-bit Load Value */ - __I uint16_t RESERVED0; - __IO uint16_t T3VAL; /*!< 16-bit Timer Value */ - __I uint16_t RESERVED1; - __IO uint16_t T3CON; /*!< Control Register */ - __I uint16_t RESERVED2; - __IO uint16_t T3CLRI; /*!< Clear Interrupt Register */ - __I uint16_t RESERVED3[5]; - __IO uint16_t T3STA; /*!< Status Register */ -} ADI_WDT_TypeDef; -#else // (__NO_MMR_STRUCTS__==0) -#define T3LD (*(volatile unsigned short int *) 0x40002580) -#define T3VAL (*(volatile unsigned short int *) 0x40002584) -#define T3CON (*(volatile unsigned short int *) 0x40002588) -#define T3CLRI (*(volatile unsigned short int *) 0x4000258C) -#define T3STA (*(volatile unsigned short int *) 0x40002598) -#endif // (__NO_MMR_STRUCTS__==0) - -/* Reset Value for T3LD*/ -#define T3LD_RVAL 0x1000 - -/* T3LD[VALUE] - Load value. */ -#define T3LD_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T3VAL*/ -#define T3VAL_RVAL 0x1000 - -/* T3VAL[VALUE] - Current counter value. */ -#define T3VAL_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T3CON*/ -#define T3CON_RVAL 0xE9 - -/* T3CON[MOD] - Timer Mode */ -#define T3CON_MOD_BBA (*(volatile unsigned long *) 0x4204B118) -#define T3CON_MOD_MSK (0x1 << 6 ) -#define T3CON_MOD (0x1 << 6 ) -#define T3CON_MOD_Reserved (0x0 << 6 ) /* Reserved */ -#define T3CON_MOD_PERIODIC (0x1 << 6 ) /* PERIODIC: Operate in periodic mode. */ - -/* T3CON[ENABLE] - Timer enable bit. */ -#define T3CON_ENABLE_BBA (*(volatile unsigned long *) 0x4204B114) -#define T3CON_ENABLE_MSK (0x1 << 5 ) -#define T3CON_ENABLE (0x1 << 5 ) -#define T3CON_ENABLE_DIS (0x0 << 5 ) /* DIS. Disable the timer. Clearing this bit resets the timer, including the T0VAL register. */ -#define T3CON_ENABLE_EN (0x1 << 5 ) /* EN. Enable the timer. The timer starts counting from its initial value. */ - -/* T3CON[PRE] - Prescaler. */ -#define T3CON_PRE_MSK (0x3 << 2 ) -#define T3CON_PRE_DIV1 (0x0 << 2 ) /* DIV1. Source clock/1. */ -#define T3CON_PRE_DIV16 (0x1 << 2 ) /* DIV16. Source clock/16. */ -#define T3CON_PRE_DIV256 (0x2 << 2 ) /* DIV256. Source clock/256. */ -#define T3CON_PRE_DIV4096 (0x3 << 2 ) /* DIV4096. Source clock/4096. */ - -/* T3CON[IRQ] - Timer interrupt. */ -#define T3CON_IRQ_BBA (*(volatile unsigned long *) 0x4204B104) -#define T3CON_IRQ_MSK (0x1 << 1 ) -#define T3CON_IRQ (0x1 << 1 ) -#define T3CON_IRQ_DIS (0x0 << 1 ) /* DIS. Generate a reset on a timeout. */ -#define T3CON_IRQ_EN (0x1 << 1 ) /* EN. Generate an interrupt when the timer times out. This feature is available in active mode only and can be used to debug the watchdog timeout events. */ - -/* T3CON[PD] - Stop count in hibernate mode. */ -#define T3CON_PD_BBA (*(volatile unsigned long *) 0x4204B100) -#define T3CON_PD_MSK (0x1 << 0 ) -#define T3CON_PD (0x1 << 0 ) -#define T3CON_PD_DIS (0x0 << 0 ) /* DIS. The timer continues to count when in hibernate mode. */ -#define T3CON_PD_EN (0x1 << 0 ) /* EN. The timer stops counting when in hibernate mode. */ - -/* Reset Value for T3CLRI*/ -#define T3CLRI_RVAL 0x0 - -/* T3CLRI[VALUE] - Clear watchdog. */ -#define T3CLRI_VALUE_MSK (0xFFFF << 0 ) - -/* Reset Value for T3STA*/ -#define T3STA_RVAL 0x20 - -/* T3STA[LOCK] - Lock status bit. */ -#define T3STA_LOCK_BBA (*(volatile unsigned long *) 0x4204B310) -#define T3STA_LOCK_MSK (0x1 << 4 ) -#define T3STA_LOCK (0x1 << 4 ) -#define T3STA_LOCK_CLR (0x0 << 4 ) /* CLR. Cleared after any reset and until user code sets T3CON[5]. */ -#define T3STA_LOCK_SET (0x1 << 4 ) /* SET. Set automatically in hardware when user code sets T3CON[5]. */ - -/* T3STA[CON] - T3CON write sync in progress. */ -#define T3STA_CON_BBA (*(volatile unsigned long *) 0x4204B30C) -#define T3STA_CON_MSK (0x1 << 3 ) -#define T3STA_CON (0x1 << 3 ) -#define T3STA_CON_CLR (0x0 << 3 ) /* CLR. Timer ready to receive commands to T3CON. The previous change of T3CON has been synchronized in the timer clock domain. */ -#define T3STA_CON_SET (0x1 << 3 ) /* SET. Timer not ready to receive commands to T3CON. Previous change of the T3CON value has not been synchronized in the timer clock domain. */ - -/* T3STA[LD] - T3LD write sync in progress. */ -#define T3STA_LD_BBA (*(volatile unsigned long *) 0x4204B308) -#define T3STA_LD_MSK (0x1 << 2 ) -#define T3STA_LD (0x1 << 2 ) -#define T3STA_LD_CLR (0x0 << 2 ) /* CLR. The previous change of T3LD has been synchronized in the timer clock domain. */ -#define T3STA_LD_SET (0x1 << 2 ) /* SET. Previous change of the T3LD value has not been synchronized in the timer clock domain. */ - -/* T3STA[CLRI] - T3CLRI write sync in progress. */ -#define T3STA_CLRI_BBA (*(volatile unsigned long *) 0x4204B304) -#define T3STA_CLRI_MSK (0x1 << 1 ) -#define T3STA_CLRI (0x1 << 1 ) -#define T3STA_CLRI_CLR (0x0 << 1 ) /* CLR. Cleared when the interrupt is cleared in the timer clock domain. */ -#define T3STA_CLRI_SET (0x1 << 1 ) /* SET. Set automatically when the T3CLRI value is being updated in the timer clock domain, indicating that the timer’s configuration is not yet valid. */ - -/* T3STA[IRQ] - Interrupt pending. */ -#define T3STA_IRQ_BBA (*(volatile unsigned long *) 0x4204B300) -#define T3STA_IRQ_MSK (0x1 << 0 ) -#define T3STA_IRQ (0x1 << 0 ) -#define T3STA_IRQ_CLR (0x0 << 0 ) /* CLR. No timeout event has occurred. */ -#define T3STA_IRQ_SET (0x1 << 0 ) /* SET. A timeout event has occurred. */ - - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif -/******************************************** -** Miscellaneous Definitions ** -*********************************************/ - -//iEiNr in EiCfg() -#define EXTINT0 0x0 -#define EXTINT1 0x1 -#define EXTINT2 0x2 -#define EXTINT3 0x3 -#define EXTINT4 0x4 -#define EXTINT5 0x5 -#define EXTINT6 0x6 -#define EXTINT7 0x7 -#define EXTINT8 0x8 - -//iEnable in EiCfg() -#define INT_DIS 0x0 -#define INT_EN 0x1 - -//iMode in EiCfg() -#define INT_RISE 0x0 -#define INT_FALL 0x1 -#define INT_EDGES 0x2 -#define INT_HIGH 0x3 -#define INT_LOW 0x4 - -//Bit values. -#define BIT0 1 -#define BIT1 2 -#define BIT2 4 -#define BIT3 8 -#define BIT4 0x10 -#define BIT5 0x20 -#define BIT6 0x40 -#define BIT7 0x80 - - -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -#define ADI_ADC0_ADDR 0x40050000UL -#define ADI_CLKCTL_ADDR 0x40002000UL -#define ADI_DMA_ADDR 0x40010000UL -#define ADI_FEE_ADDR 0x40002800UL -#define ADI_GP0_ADDR 0x40006000UL -#define ADI_GP1_ADDR 0x40006030UL -#define ADI_GP2_ADDR 0x40006060UL -#define ADI_GP3_ADDR 0x40006090UL -#define ADI_GP4_ADDR 0x400060C0UL -#define ADI_GPIOCMN_ADDR 0x400060F0UL -#define ADI_MISC_ADDR 0x40008820UL -#define ADI_I2C_ADDR 0x40003000UL -#define ADI_INTERRUPT_ADDR 0x40002420UL -#define ADI_IDENT_ADDR 0x40002020UL -#define ADI_NVIC_ADDR 0xE000E000UL -#define ADI_PWRCTL_ADDR 0x40002400UL -#define ADI_PWM_ADDR 0x40001000UL -#define ADI_RESET_ADDR 0x40002440UL -#define ADI_SPI0_ADDR 0x40004000UL -#define ADI_SPI1_ADDR 0x40004400UL -#define ADI_TM0_ADDR 0x40000000UL -#define ADI_TM1_ADDR 0x40000400UL -#define ADI_UART_ADDR 0x40005000UL -#define ADI_WUT_ADDR 0x40002500UL -#define ADI_WDT_ADDR 0x40002580UL - - -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define pADI_ADC0 ((ADI_ADC_TypeDef *)ADI_ADC0_ADDR) -#define pADI_CLKCTL ((ADI_CLKCTL_TypeDef *)ADI_CLKCTL_ADDR) -#define pADI_DMA ((ADI_DMA_TypeDef *)ADI_DMA_ADDR) -#define pADI_FEE ((ADI_FEE_TypeDef *)ADI_FEE_ADDR) -#define pADI_GP0 ((ADI_GPIO_TypeDef *)ADI_GP0_ADDR) -#define pADI_GP1 ((ADI_GPIO_TypeDef *)ADI_GP1_ADDR) -#define pADI_GP2 ((ADI_GPIO_TypeDef *)ADI_GP2_ADDR) -#define pADI_GP3 ((ADI_GPIO_TypeDef *)ADI_GP3_ADDR) -#define pADI_GP4 ((ADI_GPIO_TypeDef *)ADI_GP4_ADDR) -#define pADI_GPIOCMN ((ADI_GPIOCMN_TypeDef *)ADI_GPIOCMN_ADDR) -#define pADI_MISC ((ADI_MISC_TypeDef *)ADI_MISC_ADDR) -#define pADI_I2C ((ADI_I2C_TypeDef *)ADI_I2C_ADDR) -#define pADI_INTERRUPT ((ADI_INTERRUPT_TypeDef *)ADI_INTERRUPT_ADDR) -#define pADI_PWRCTL ((ADI_PWRCTL_TypeDef *)ADI_PWRCTL_ADDR) -#define pADI_PWM ((ADI_PWM_TypeDef *)ADI_PWM_ADDR) -#define pADI_RESET ((ADI_RESET_TypeDef *)ADI_RESET_ADDR) -#define pADI_SPI0 ((ADI_SPI_TypeDef *)ADI_SPI0_ADDR) -#define pADI_SPI1 ((ADI_SPI_TypeDef *)ADI_SPI1_ADDR) -#define pADI_TM0 ((ADI_TIMER_TypeDef *)ADI_TM0_ADDR) -#define pADI_TM1 ((ADI_TIMER_TypeDef *)ADI_TM1_ADDR) -#define pADI_UART ((ADI_UART_TypeDef *)ADI_UART_ADDR) -#define pADI_WUT ((ADI_WUT_TypeDef *)ADI_WUT_ADDR) -#define pADI_WDT ((ADI_WDT_TypeDef *)ADI_WDT_ADDR) - -/** @} */ /* End of group Device_Peripheral_Registers *//** @} */ /* End of group ADUCRF101 */ -/** @} */ /* End of group CMSIS */ - -#ifdef __cplusplus -} -#endif - - -#endif // __ADUCRF101_H__ - diff --git a/drivers/cpu/arm/aducrf101/Common/GCC/ADuCRF101.ld b/drivers/cpu/arm/aducrf101/Common/GCC/ADuCRF101.ld deleted file mode 100644 index a6effb701..000000000 --- a/drivers/cpu/arm/aducrf101/Common/GCC/ADuCRF101.ld +++ /dev/null @@ -1,108 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) - -ENTRY(Reset_Handler) - -MEMORY -{ - flash (rx) : org = 0x00000000, len = 128k - ram (rwx) : org = 0x20000000, len = 16k -} - -SECTIONS -{ - .vectors : { - __vectors_start = .; - KEEP(*(.vectors)) - . = ALIGN(4); - } >flash - - .text : { - . = ALIGN(4); - *(.text) - *(.text.*) - etext = .; - } >flash - - .ARM.ex : { - *(.ARM.extab* .gnu.linkonce.armextab.*) - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } >flash - - .rodata : { - . = ALIGN(4); - *(.rodata) - *(.rodata.*) - . = ALIGN(4); - __rodata_end = .; - } >flash - - .data : { - /* Initialized data is placed in flash, and will get - copied to RAM by crt0.S */ - . = ALIGN(4); - __data_flash_start = LOADADDR(.data); - __data_start = .; - *(.data) - *(.data.*) - - /* Code that goes into RAM also ends up here, and - gets copied along with the data section. */ - *(.ramtext*) - - __data_end = .; - edata = .; - } > ram AT > flash - - .bss : { - . = ALIGN(8); - __bss_start = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end = .; - end = .; - } > ram - - /* Heap grows up from "end" (after bss), and stack grows down from - the end of RAM. */ - . = ORIGIN(ram) + LENGTH(ram); - stack_end = .; -} diff --git a/drivers/cpu/arm/aducrf101/Common/GCC/crt0.S b/drivers/cpu/arm/aducrf101/Common/GCC/crt0.S deleted file mode 100644 index 04b868448..000000000 --- a/drivers/cpu/arm/aducrf101/Common/GCC/crt0.S +++ /dev/null @@ -1,173 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -.equ SCB_VTOR, 0xE000ED08 - -/* Vector table */ - .macro handler name - .long \name\() - .weak \name\() - .set \name\(), unhandled_vector - .endm - - .macro handler_reserved - .long 0 - .endm - - .section .vectors, "a", %progbits -vectors: - .long stack_end - .long Reset_Handler - - /* Cortex-M3 core interrupts */ - handler NMI_Handler - handler HardFault_Handler - handler MemManage_Handler - handler BusFault_Handler - handler UsageFault_Handler - handler_reserved - handler_reserved - handler_reserved - handler_reserved - handler SVC_Handler - handler DebugMon_Handler - handler_reserved - handler PendSV_Handler - handler SysTick_Handler - - /* ADuCRF101 external interrupts */ - handler WakeUp_Int_Handler - handler Ext_Int0_Handler - handler Ext_Int1_Handler - handler Ext_Int2_Handler - handler Ext_Int3_Handler - handler Ext_Int4_Handler - handler Ext_Int5_Handler - handler Ext_Int6_Handler - handler Ext_Int7_Handler - handler Ext_Int8_Handler - handler WDog_Tmr_Int_Handler - handler_reserved - handler GP_Tmr0_Int_Handler - handler GP_Tmr1_Int_Handler - handler ADC0_Int_Handler - handler Flsh_Int_Handler - handler UART_Int_Handler - handler SPI0_Int_Handler - handler SPI1_Int_Handler - handler I2C0_Slave_Int_Handler - handler I2C0_Master_Int_Handler - handler_reserved - handler_reserved - handler DMA_Err_Int_Handler - handler DMA_SPI1_TX_Int_Handler - handler DMA_SPI1_RX_Int_Handler - handler DMA_UART_TX_Int_Handler - handler DMA_UART_RX_Int_Handler - handler DMA_I2C0_STX_Int_Handler - handler DMA_I2C0_SRX_Int_Handler - handler DMA_I2C0_MTX_Int_Handler - handler DMA_I2C0_MRX_Int_Handler - handler_reserved - handler_reserved - handler_reserved - handler DMA_ADC_Int_Handler - handler DMA_SPI0_TX_Int_Handler - handler DMA_SPI0_RX_Int_Handler - handler PWMTrip_Int_Handler - handler PWM0_Int_Handler - handler PWM1_Int_Handler - handler PWM2_Int_Handler - handler PWM3_Int_Handler - -/* Reset handler */ - .section .text - .syntax unified - .code 16 - .global Reset_Handler - .thumb_func -Reset_Handler: - /* Set up some basics, in case we came here from a call - rather than system reset. */ - - /* Disable interrupts */ - cpsid i - - /* Privileged mode, main stack, no floating point */ - mov r0, #0 - msr control, r0 - isb - - /* Point vector table to the right place */ - ldr r0, =__vectors_start - ldr r1, =SCB_VTOR - str r0, [r1] - - /* Load initial stack pointer */ - ldr r0, =stack_end - mov sp, r0 - isb - - /* Clear BSS */ - mov r0, #0 - ldr r1, =__bss_start - ldr r2, =__bss_end -zero_bss_loop: - cmp r1, r2 - it lt - strlt r0, [r1], #4 - blt zero_bss_loop - - /* Copy initialized data from flash to RAM */ - ldr r0, =__data_flash_start - ldr r1, =__data_start - ldr r2, =__data_end -copy_data_loop: - ldr r3, [r0], #4 - cmp r1, r2 - it lt - strlt r3, [r1], #4 - blt copy_data_loop - - /* We can run C code now */ - bl main - - /* If main returned, just loop */ - b . - -/* Handler for otherwise unhandled vectors */ - .section .text,"ax",%progbits - .thumb_func -unhandled_vector: - b unhandled_vector diff --git a/drivers/cpu/arm/aducrf101/Common/IAR/ADUCRF101.icf b/drivers/cpu/arm/aducrf101/Common/IAR/ADUCRF101.icf deleted file mode 100644 index 9ebe02a5a..000000000 --- a/drivers/cpu/arm/aducrf101/Common/IAR/ADUCRF101.icf +++ /dev/null @@ -1,67 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; -do not initialize { section .mainstackarea }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place at address mem:0x1FC { readonly section .PageZeroCheckSum }; -place at address mem:0x1FFEC { readonly section .sigprot }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; diff --git a/drivers/cpu/arm/aducrf101/Common/IAR/Retarget.c b/drivers/cpu/arm/aducrf101/Common/IAR/Retarget.c deleted file mode 100644 index 0006d5a05..000000000 --- a/drivers/cpu/arm/aducrf101/Common/IAR/Retarget.c +++ /dev/null @@ -1,99 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - Module : Retarget.c - Description : uart interface - Date : December 2012 - Version : v2.00 - Changelog : v1.00 Initial - v2.00 use of UrtLib functions -*/ -#include -#include "UrtLib.h" -#include -#include -#include - -#define CR 0x0D - - - -/*************************************************************************/ -/* size_t __read(int handle,unsigned char *buf,size_t bufSize) */ -/* Write data to a stream */ -/* Needed for retargetting the IAR DLIB library for the ADUCRF101 */ -/*************************************************************************/ -size_t __read(int handle,unsigned char *buf,size_t bufSize) -{ - size_t i; - for (i=0x0; iCOMLSR & COMLSR_DR))); - buf[i] = pADI_UART->COMRX; - } - return i; -} - -/*************************************************************************/ -/* __write(int handle,const unsigned char *buf,size_t bufSize) */ -/* Read data from a stream */ -/* Needed for retargetting the IAR DLIB library for the ADUCRF101 */ -/*************************************************************************/ -size_t __write(int handle,const unsigned char *buf,size_t bufSize) -{ - size_t i; - for (i=0x0; i -#include -#include - -#pragma import(__use_no_semihosting_swi) - - #define CR 0x0D -struct __FILE { int handle; /* Add whatever you need here */ }; -FILE __stdout; -FILE __stdin; - - -// Re-targetting the Realview library functions -/* - * writes the character specified by c (converted to an unsigned char) to - * the output stream pointed to by stream, at the position indicated by the - * asociated file position indicator (if defined), and advances the - * indicator appropriately. If the file position indicator is not defined, - * the character is appended to the output stream. - * Returns: the character written. If a write error occurs, the error - * indicator is set and fputc returns EOF. - */ -int fputc(int ch, FILE * stream ) -{ - if(ch == '\n') - while(!(COMLSR_THRE==(UrtLinSta(0) & COMLSR_THRE))); - UrtTx(0, CR); /* output CR */ - while(!(COMLSR_THRE==(UrtLinSta(0) & COMLSR_THRE))); - UrtTx(0, ch); - return(ch); -} - -int __backspace(FILE *stream) -{ - return 0x0; - -} -/* - * obtains the next character (if present) as an unsigned char converted to - * an int, from the input stream pointed to by stream, and advances the - * associated file position indicator (if defined). - * Returns: the next character from the input stream pointed to by stream. - * If the stream is at end-of-file, the end-of-file indicator is - * set and fgetc returns EOF. If a read error occurs, the error - * indicator is set and fgetc returns EOF. - */ -int fgetc(FILE * stream) -{ - return (UrtRx(0)); -} - - -int ferror(FILE *f) { - /* Your implementation of ferror */ - return EOF; -} - - -void _ttywrch(int ch) { UrtTx(0, ch); } - - -void _sys_exit(int return_code) { -label: goto label; /* endless loop */ -} diff --git a/drivers/cpu/arm/aducrf101/Common/aducrf101-include.h b/drivers/cpu/arm/aducrf101/Common/aducrf101-include.h deleted file mode 100644 index 1d250d121..000000000 --- a/drivers/cpu/arm/aducrf101/Common/aducrf101-include.h +++ /dev/null @@ -1,61 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - @module include.h - @brief Main Include file - @version V0.2 - @author PAD CSE group, Analog Devices Inc - @date January 2013 - - @par Revision History: - - V0.1, February 2012: initial version. - - V0.2, January 2013: addition of PwmLib, FeeLib and DmaLib - remove uart.h -**/ - -#ifndef __INCLUDE_H -#define __INCLUDE_H - -#include -#include -#include -#include -#include -#include - -#include - -#include "radioeng.h" - -#endif // __INCLUDE_H diff --git a/drivers/cpu/arm/aducrf101/Common/defs.h b/drivers/cpu/arm/aducrf101/Common/defs.h deleted file mode 100644 index e129c7e58..000000000 --- a/drivers/cpu/arm/aducrf101/Common/defs.h +++ /dev/null @@ -1,42 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - @file defs.h - @brief Global definitions. - @version V0.1 - @author PAD CSE group, Analog Devices Inc - @date January 2012 -**/ - -typedef enum {FALSE = 0, TRUE = !FALSE} boolean; diff --git a/drivers/cpu/arm/aducrf101/Common/radioeng.c b/drivers/cpu/arm/aducrf101/Common/radioeng.c deleted file mode 100644 index d6ee03c0f..000000000 --- a/drivers/cpu/arm/aducrf101/Common/radioeng.c +++ /dev/null @@ -1,1790 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - @file radioeng.c - @brief Radio Interface Engine Functions - @version v1.0 - @author PAD CSE group, Analog Devices Inc - @date May 08th 2013 -**/ - -#include "aducrf101-include.h" - -// 1.0 of the Engine -#define RIE_ENGINE_MAJOR_VERSION 1UL -#define RIE_ENGINE_MINOR_VERSION 0UL - - -#define RADIO_SPI_CLK_FREQ 4000000 // 4 MHz SPI CLK for radio interface -#define SYSTEM_UCLK 16000000 // 16 MHz UCLK -// Default Radio Parameters -#define DEFAULT_CHNL_FREQ 915000000 -#define FREQ_CNVRT_VAL 0.00252061538 -// Defines for radio memory mapped areas -#define PACKETRAM_START 0x10 -#define PACKETRAM_LEN 240 -#define BBRAM_START 0x100 -#define PR_var_tx_mode_ADR 0x00D - -// PrF Table 35 -#define PARAM_TX_NORMAL_PACKET 0 -#define PARAM_TX_PREAMBLE_FOREVER 2 -#define PARAM_TX_CARRIER_FOREVER 3 - -#define gpio_configure_sport_mode_0 0xA0 -#define gpio_configure_default 0x00 -#define MCR_pa_level_mcr_Adr 0x307 -#define MCR_rssi_readback_Adr 0x312 -#define MCR_gpio_configure_Adr 0x3fa -#define MCR_ext_uc_clk_divide_Adr 0x32e -#define MCR_interrupt_source_0_Adr 0x336 -#define MCR_interrupt_source_1_Adr 0x337 - -// Macros for manual GPIO checking of Radio MISO pin P2.0 (SPI0) -#define RADIO_MISO_IN GP2IN_IN0_BBA -// Macros for manual GPIO control of P2.3 (Radio SPI CS) (SPI0) -#define RADIO_CSN_DEASSERT (pADI_GP2->GPSET = GP2SET_SET3) -#define RADIO_CSN_ASSERT (pADI_GP2->GPCLR = GP2CLR_CLR3) -// Macros for Sending\Receiving single bytes via SPI -#define SEND_SPI(x) pADI_SPI0->SPITX = x -#define WAIT_SPI_RX while((pADI_SPI0->SPISTA & SPISTA_RXFSTA_MSK) == 0x0); -#define READ_SPI pADI_SPI0->SPIRX - -// Bit Manipulation Macros -#define MSKSET_VAL(byte,numbits,offset,value) ((byte & ~(((0x1 << numbits)-1) << offset)) | value) - - - -/*************************************************************************/ -/* Local Types */ -/*************************************************************************/ -/*************************************************************************/ -/* Radio Command Codes */ -/*************************************************************************/ -typedef enum -{ - CMD_SYNC = 0xA2, // Synchronizatio - CMD_PHY_OFF = 0xB0, // Transition to state PHY_OFF - CMD_PHY_ON = 0xB1, // transition to state PHY_ON - CMD_PHY_RX = 0xB2, // transition to state PHY_RX - CMD_PHY_TX = 0xB5, // transition to state PHY_TX - CMD_PHY_SLEEP = 0xBA, // transition to state PHY_SLEEP - CMD_CONFIG_DEV = 0xBB, // Apply Radio Configuration - CMD_GET_RSSI = 0xBC, // Performs an RSSI measurement - CMD_HW_RESET = 0xC8, // Power Down radio - SPI_MEM_WR = 0x18, // Sequential SPI Write - SPI_MEM_RD = 0x38, // Sequential SPI Read - SPI_NOP = 0xFF // No operation -} Radio_CmdCodes; -/*************************************************************************/ -/* Firmware States */ -/*************************************************************************/ -typedef enum -{ - FW_INIT = 0x0F, // Radio Starting Up - FW_BUSY = 0x00, // Radio not completed current operation - FW_RSSI = 0x05, // Performing CMD_GET_RSSI - FW_OFF = 0x11, // Radio is OFF - FW_ON = 0x12, // Radio is ON - FW_RX = 0x13, // Radio is in receive mode - FW_TX = 0x14, // Radio is in transmit mode - -} RadioState; -/*************************************************************************/ -/* Status Byte Masks */ -/*************************************************************************/ -#define STATUS_BYTE_FW_STATE (0x1F << 0) -#define STATUS_BYTE_CMD_READY (0x1 << 5) -#define STATUS_BYTE_IRQ_STATUS (0x1 << 6) -#define STATUS_BYTE_SPI_READY (0x1 << 7) -/*************************************************************************/ -/* SPI Memory Access Defs */ -/*************************************************************************/ -#define SPI_MEMCMD_BYTE0_ADR_MSK (0x3 << 0) -#define SPI_MEMCMD_BYTE0_CMD_BITOFFSET 3 -#define SPI_MEMCMD_BYTE0_CMD_MSK (0x1F << SPI_MEMCMD_BYTE0_CMD_BITOFFSET) -/*************************************************************************/ -/* Radio Configuration Structure */ -/*************************************************************************/ -/** - \internal Hide from Doxegen - \var TyRadioConfiguration - **/ -typedef struct -{ - RIE_U8 interrupt_mask_0_r; // 0x100 - RIE_U8 cfg_101_r; // 0x101 - RIE_U8 cfg_102_r; // 0x102 - RIE_U8 cfg_103_r; // 0x103 - RIE_U8 cfg_104_r; // 0x104 - RIE_U8 cfg_105_r; // 0x105 - RIE_U8 cfg_106_r; // 0x106 - RIE_U8 cfg_107_r; // 0x107 - RIE_U8 cfg_108_r; // 0x108 - RIE_U8 channel_freq_0_r; // 0x109 - RIE_U8 channel_freq_1_r; // 0x10A - RIE_U8 channel_freq_2_r; // 0x10B - RIE_U8 cfg_10C_r; // 0x10C - RIE_U8 cfg_10D_r; // 0x10D - RIE_U8 cfg_10E_r; // 0x10E - RIE_U8 cfg_10F_r; // 0x10F - RIE_U8 cfg_110_r; // 0x110 - RIE_U8 cfg_111_r; // 0x111 - RIE_U8 cfg_112_r; // 0x112 - RIE_U8 cfg_113_r; // 0x113 - RIE_U8 radio_cfg_8_r; // 0x114 - RIE_U8 radio_cfg_9_r; // 0x115 - RIE_U8 cfg_116_r; // 0x116 - RIE_U8 cfg_117_r; // 0x117 - RIE_U8 image_reject_cal_phase_r; // 0x118 - RIE_U8 image_reject_cal_amplitude_r; // 0x119 - RIE_U8 cfg_11A_r; // 0x11A - RIE_U8 cfg_11B_r; // 0x11B - RIE_U8 symbol_mode_r; // 0x11C - RIE_U8 cfg_11D_r; // 0x11D - RIE_U8 cfg_11E_r; // 0x11E - RIE_U8 cfg_11F_r; // 0x11F - RIE_U8 cfg_120_r; // 0x120 - RIE_U8 cfg_121_r; // 0x121 - RIE_U8 cfg_122_r; // 0x122 - RIE_U8 cfg_123_r; // 0x123 - RIE_U8 tx_base_adr_r; // 0x124 - RIE_U8 rx_base_adr_r; // 0x125 - RIE_U8 packet_length_control_r; // 0x126 - RIE_U8 packet_length_max_r; // 0x127 - RIE_U8 cfg_128_r; // 0x128 - RIE_U8 cfg_129_r; // 0x129 - RIE_U8 cfg_12A_r; // 0x12A - RIE_U8 cfg_12B_r; // 0x12B - RIE_U8 cfg_12C_r; // 0x12C - RIE_U8 cfg_12D_r; // 0x12D - RIE_U8 cfg_12E_r; // 0x12E - RIE_U8 cfg_12F_r; // 0x12F - RIE_U8 cfg_130_r; // 0x130 - RIE_U8 cfg_131_r; // 0x131 - RIE_U8 cfg_132_r; // 0x132 - RIE_U8 cfg_133_r; // 0x133 - RIE_U8 cfg_134_r; // 0x134 - RIE_U8 cfg_135_r; // 0x135 - RIE_U8 cfg_136_r; // 0x136 - RIE_U8 cfg_137_r; // 0x137 - RIE_U8 cfg_138_r; // 0x138 - RIE_U8 cfg_139_r; // 0x139 - RIE_U8 cfg_13A_r; // 0x13A - RIE_U8 cfg_13B_r; // 0x13B - RIE_U8 cfg_13C_r; // 0x13C - RIE_U8 cfg_13D_r; // 0x13D - RIE_U8 cfg_13E_r; // 0x13E - RIE_U8 cfg_13F_r; // 0x13F -} TyRadioConfiguration; -/*************************************************************************/ -/* Radio Configuration Constants */ -/*************************************************************************/ -#define interrupt_mask_0_interrupt_tx_eof (0x1 << 4) -#define interrupt_mask_0_interrupt_crc_correct (0x1 << 2) - -#define packet_length_control_length_offset_offset (0) -#define packet_length_control_length_offset_minus0 (0x4 << packet_length_control_length_offset_offset) -#define packet_length_control_data_mode_offset (3) -#define packet_length_control_data_mode_packet (0x0 << packet_length_control_data_mode_offset) -#define packet_length_control_crc_en_yes (0x1 << 5) -#define packet_length_control_packet_len_variable (0x0 << 6) -#define packet_length_control_packet_len_fixed (0x1 << 6) -#define packet_length_control_data_byte_lsb (0x0 << 7) - -#define symbol_mode_symbol_length_8_bit (0 << 0) -#define symbol_mode_data_whitening_disabled (0 << 3) -#define symbol_mode_data_whitening_enabled (1 << 3) -#define symbol_mode_eight_ten_enc_disabled (0 << 4 ) -#define symbol_mode_prog_crc_en_disabled (0 << 5) -#define symbol_mode_manchester_enc_enabled (1 << 6) - -#define radio_cfg_8_pa_single_diff_sel_single_ended (0x0 << 7) -#define radio_cfg_8_pa_single_diff_sel_differential (0x1 << 7) -#define radio_cfg_8_pa_power_numbits (4) -#define radio_cfg_8_pa_power_offset (3) -#define radio_cfg_8_pa_power_setting_63 (0xF << radio_cfg_8_pa_power_offset) -#define radio_cfg_8_pa_ramp_numbits (3) -#define radio_cfg_8_pa_ramp_offset (0) -#define radio_cfg_8_pa_ramp_16 (0x5 << radio_cfg_8_pa_ramp_offset) - -#define radio_cfg_9_demod_scheme_offset (0) -#define radio_cfg_9_demod_scheme_FSK (0x0 << radio_cfg_9_demod_scheme_offset) -#define radio_cfg_9_mod_scheme_numbits (3) -#define radio_cfg_9_mod_scheme_offset (3) -#define radio_cfg_9_mod_scheme_2_level_FSK (0x0 << radio_cfg_9_mod_scheme_offset) -#define radio_cfg_9_mod_scheme_2_level_GFSK (0x1 << radio_cfg_9_mod_scheme_offset) -#define radio_cfg_9_ifbw_numbits (2) -#define radio_cfg_9_ifbw_offset (6) -#define radio_cfg_9_ifbw_100kHz (0x0 << radio_cfg_9_ifbw_offset) -#define radio_cfg_9_ifbw_150kHz (0x1 << radio_cfg_9_ifbw_offset) -#define radio_cfg_9_ifbw_200kHz (0x2 << radio_cfg_9_ifbw_offset) -#define radio_cfg_9_ifbw_300kHz (0x3 << radio_cfg_9_ifbw_offset) - -/*************************************************************************/ -/* Local Variables */ -/*************************************************************************/ -static TyRadioConfiguration RadioConfiguration; -static RIE_BOOL bRadioConfigurationChanged = RIE_FALSE; -static RIE_BOOL bTestModeEnabled = RIE_FALSE; -static RIE_U32 DataRate = 38400; -static volatile RIE_BOOL bPacketTx = RIE_FALSE; -static volatile RIE_BOOL bPacketRx = RIE_FALSE; - -const RIE_U8 DR_38_4kbps_Dev20kHz_Configuration[] = -{ - 0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0x76,0x62,0x21, - -// 0 1 2 3 4 5 6 7 8 9 A B - 0x80,0x01,0xC8,0x20,0x0E,0x00,0x00,0x00,0xFD,0x00,0x0B,0x37, - 0x16,0x07, - - 0x40,0x0C,0x00,0x0C,0x00,0x00, - 0x10,0x00,0xC3,0x36,0x10,0x10,0x24,0xF0,0x2A,0x00,0x2F,0x19,0x5E,0x46,0x5F,0x78, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 -}; - - -const RIE_U8 DR_300_0kbps_Dev75_0kHz_Configuration[] = -{ - 0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0x76,0x62,0x21, - -// 0 1 2 3 4 5 6 7 8 9 A B - 0xB8,0x2B,0xEE,0x0B,0x70,0x00,0x03,0x00,0xFD,0xC0,0x0B,0x37, - 0x16,0x07, - - 0x40,0x0C,0x00,0x0C,0x00,0x00, - 0x10,0x00,0xC3,0x36,0x10,0x10,0x24,0xF0,0x2A,0x00,0x2F,0x19,0x5E,0x46,0x5F,0x78, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 -}; - - - -const RIE_U8 DR_1_0kbps_Dev10_0kHz_Configuration[] = -{ - 0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0x76,0x62,0x21, -// 0 1 2 3 4 5 6 7 8 9 A B - 0x0A,0x00,0x64,0x41,0x01,0x00,0x02,0x00,0xFD,0x00,0x0B,0x37, - 0x16,0x07, - - 0x40,0x0C,0x00,0x0C,0x00,0x00, - 0x10,0x00,0xC3,0x36,0x10,0x10,0x24,0xF0,0x2A,0x00,0x2F,0x19,0x5E,0x46,0x5F,0x78, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 -}; - -/*************************************************************************/ -/* Local Functions */ -/*************************************************************************/ -static RIE_Responses RadioSPIXferByte (RIE_U8 ucByte, - RIE_U8 * pData); -static RIE_Responses RadioSendCommandBytes (RIE_U8 * pCmdBytes, - RIE_U8 NumBytes); -static RIE_Responses RadioSendCommandNoWait (Radio_CmdCodes CmdCode); -static RIE_Responses RadioSendCommandWait (Radio_CmdCodes CmdCode); -static RIE_Responses RadioMMapRead (RIE_U32 ulAdr, - RIE_U32 ulLen, - RIE_U8 * pData); -static RIE_Responses RadioMMapWrite (RIE_U32 ulAdr, - RIE_U32 ulLen, - RIE_U8 * pData); -static RIE_Responses RadioReadState (RadioState * pState); -static RIE_Responses RadioWaitOnState (RadioState FinalState); -static RIE_Responses RadioWaitForPowerUp (void); -static RIE_Responses RadioSyncComms (void); -static RIE_Responses SetRadioConfiguration (RIE_BaseConfigs BaseConfig); -static RIE_Responses RadioCommitRadioConfig (void); -static RIE_Responses RadioConfigure (void); -static RIE_Responses RadioToOnMode (void); -static RIE_Responses RadioToOffMode (void); -static RIE_Responses RadioWaitOnCmdLdr (void); -/*************************************************************************/ -/* Functions Implementations - Start */ -/*************************************************************************/ - -/** - @fn RIE_Responses RadioGetAPIVersion(RIE_U32 *pVersion) - @brief Return the Radio Interface Engine API Version - @param pVersion :{} - pVersion Storage for Radio Interface Engine API version. - @code - RIE_U32 Version; - Response = RadioGetAPIVersion(&Version); - @endcode - @return RIE_Responses Error code. -**/ - -RIE_Responses RadioGetAPIVersion(RIE_U32 *pVersion) -{ - RIE_Responses Response = RIE_Success; - - if (pVersion) - *pVersion = RIE_ENGINE_MINOR_VERSION | (RIE_ENGINE_MAJOR_VERSION << 8); - return Response; -} - - -/** - @fn RIE_U32 RadioSwitchConfig(RIE_BaseConfigs BaseConfig) - @brief Change the Radio to using specified configuration. - @param BaseConfig :{DR_1_0kbps_Dev10_0kHz, DR_38_4kbps_Dev20kHz, DR_300_0kbps_Dev75_0kHz} - - DR_1_0kbps_Dev10_0kHz Base configuration of 1 kbps datarate, 10.0 kHz frequency deviation. - - DR_38_4kbps_Dev20kHz Base configuration of 38.4 kbps datarate, 20 kHz frequency deviation. - - DR_300_0kbps_Dev75_0kHz Base configuration of 300 kbps datarate, 75 kHz frequency deviation. - @pre - RadioInit() must be called before this function is called. - @return RIE_Responses Error code. -**/ - -RIE_Responses RadioSwitchConfig(RIE_BaseConfigs BaseConfig) -{ - RIE_Responses Response = RIE_Success; - if(Response == RIE_Success) - Response = RadioToOffMode(); - if(Response == RIE_Success) - Response = SetRadioConfiguration(BaseConfig); - if(Response == RIE_Success) - Response = RadioCommitRadioConfig(); - if(Response == RIE_Success) - Response = RadioToOnMode(); - return Response; -} - - -/** - @fn RIE_U32 RadioInit(RIE_BaseConfigs BaseConfig) - @brief Initialise the Radio, using specified configuration. - @param BaseConfig :{DR_1_0kbps_Dev10_0kHz , DR_38_4kbps_Dev20kHz ,DR_300_0kbps_Dev75_0kHz } - - DR_1_0kbps_Dev10_0kHz Base configuration of 1 kbps datarate, 10.0 kHz frequency deviation. - - DR_38_4kbps_Dev20kHz Base configuration of 38.4 kbps datarate, 20 kHz frequency deviation. - - DR_300_0kbps_Dev75_0kHz Base configuration of 300 kbps datarate, 75 kHz frequency deviation. - @note - This must be called before any other function is called. - @return RIE_Responses Error code. -**/ - -RIE_Responses RadioInit(RIE_BaseConfigs BaseConfig) -{ - RIE_Responses Response = RIE_Success; - - // Disable the radio interrupt until we have initialised the radio - NVIC_DisableIRQ(UHFTRX_IRQn); - - // Initialise GPIO Port 2 for Radio Use - pADI_GP2->GPCON = GP2CON_CON0_SPI0MISO | GP2CON_CON1_SPI0SCLK | - GP2CON_CON2_SPI0MOSI | GP2CON_CON3_GPIO | - GP2CON_CON4_IRQ8 | GP2CON_CON5_GPIO | - GP2CON_CON6_GPIO | GP2CON_CON7_GPIOIRQ7; - - pADI_GP2->GPOEN = GP2OEN_OEN0_IN | GP2OEN_OEN1_IN | - GP2OEN_OEN2_IN | GP2OEN_OEN3_OUT | - GP2OEN_OEN4_IN | GP2OEN_OEN5_IN | - GP2OEN_OEN6_IN | GP2OEN_OEN7_IN; - - // Disable the PULL-Up on P2.4 which is connected to the radio - GP2PUL_PUL4_BBA = 0x0; - - // Configure the SPI Interface to the Radio and flush it - pADI_SPI0->SPIDIV = ((SYSTEM_UCLK/RADIO_SPI_CLK_FREQ)/2)-0x1; - pADI_SPI0->SPICON = SPICON_MASEN | // Master mode - SPICON_TIM | // Interrupt on transmit - SPICON_TFLUSH | // Flush FIFO - SPICON_RFLUSH | // Flush FIFO - SPICON_ENABLE; - pADI_SPI0->SPICON = SPICON_MASEN | // Master mode - SPICON_TIM | // Interrupt on transmit - SPICON_ENABLE; - - // Initialise the chip select line to starting position - RADIO_CSN_DEASSERT; - - - // Power it down and up again to return to a known state - // which will be PHY_OFF. - // This will clear any pre-existing radio interrupt before - // we enable the Cortex interrupt handling of it - if(Response == RIE_Success) - Response = RadioPowerOff(); - // Configure a "high level" radio interrupt ... - pADI_INTERRUPT->EI2CFG = EI2CFG_IRQ8MDE_HIGHLEVEL | EI2CFG_IRQ8EN; - // ... and set it up in the NVIC so that our interrupt handler is called - // when the radio wants our attention. Clear any pre-existing condition - // before enabling the interrupt. - pADI_INTERRUPT->EICLR = EICLR_IRQ8; - NVIC_ClearPendingIRQ(UHFTRX_IRQn); - NVIC_SetPriority (UHFTRX_IRQn,0x0); - NVIC_EnableIRQ (UHFTRX_IRQn); - - if(Response == RIE_Success) - Response = RadioWaitForPowerUp(); - if(Response == RIE_Success) - Response = RadioSyncComms(); - if(Response == RIE_Success) - Response = RadioToOffMode(); - if(Response == RIE_Success) - Response = SetRadioConfiguration(BaseConfig); - if(Response == RIE_Success) - Response = RadioCommitRadioConfig(); - if(Response == RIE_Success) - Response = RadioToOnMode(); - return Response; -} - -/** - @fn RIE_U32 RadioDeInit(void) - @brief Deinitialise the Radio, and power it down. - @note - This can be called independently of all other functions to power down - the radio - @return RIE_Responses Error code. -**/ - -RIE_Responses RadioDeInit(void) -{ - RIE_Responses Response = RIE_Success; - - // Disable the radio interrupt - NVIC_DisableIRQ(UHFTRX_IRQn); - - // Initialise GPIO Port 2 for Radio Use - pADI_GP2->GPCON = GP2CON_CON0_SPI0MISO | GP2CON_CON1_SPI0SCLK | - GP2CON_CON2_SPI0MOSI | GP2CON_CON3_GPIO | - GP2CON_CON4_IRQ8 | GP2CON_CON5_GPIO | - GP2CON_CON6_GPIO | GP2CON_CON7_GPIOIRQ7; - - pADI_GP2->GPOEN = GP2OEN_OEN0_IN | GP2OEN_OEN1_IN | - GP2OEN_OEN2_IN | GP2OEN_OEN3_OUT | - GP2OEN_OEN4_IN | GP2OEN_OEN5_IN | - GP2OEN_OEN6_IN | GP2OEN_OEN7_IN; - - // Enable the pull-up as we are powering down the radion - GP2PUL_PUL4_BBA = 0x1; - - // Configure the SPI Interface to the Radio and flush it - pADI_SPI0->SPIDIV = ((SYSTEM_UCLK/RADIO_SPI_CLK_FREQ)/2)-0x1; - pADI_SPI0->SPICON = SPICON_MASEN | // Master mode - SPICON_TIM | // Interrupt on transmit - SPICON_TFLUSH | // Flush FIFO - SPICON_RFLUSH | // Flush FIFO - SPICON_ENABLE; - pADI_SPI0->SPICON = SPICON_MASEN | // Master mode - SPICON_TIM | // Interrupt on transmit - SPICON_ENABLE; - - // Initialise the chip select line to starting position - RADIO_CSN_DEASSERT; - - // Power it down - Response = RadioSendCommandNoWait(CMD_HW_RESET); - - return Response; -} - -/** - @fn RIE_Responses RadioPowerOff(void) - @brief Shutdown the radio and place it in its lowest power sleep mode. - @pre - RadioInit() must be called before this function is called. - @return RIE_Response Error code. -**/ - -RIE_Responses RadioPowerOff(void) -{ - volatile RIE_U32 ulDelay; - RIE_Responses Response = RIE_Success; - - Response = RadioSendCommandNoWait(CMD_HW_RESET); - - // Delay for approximately 1 ms - ulDelay = 0x1000; - while (ulDelay--); - - return Response; -} - -/** - @fn RIE_Responses RadioTerminateRadioOp(void) - @brief Terminate a currently running radio RX or TX operation. - @pre RadioInit() must be called before this function is called. - @code - if (RIE_Response == RIE_Success) - RIE_Response = RadioRxPacketFixedLen(12); - // Delay for a while waiting for a packet - if (RIE_Response == RIE_Success) - { - // Abort the waiting - RIE_Response = RadioTerminateRadioOp(); - } - @endcode - @return RIE_Responses Error code -**/ -RIE_Responses RadioTerminateRadioOp (void) -{ - RIE_Responses Response = RIE_Success; - - Response = RadioToOnMode(); - - return Response; -} - -/** - @fn RIE_Responses RadioSetFrequency(RIE_U32 Frequency) - @brief Set frequency for radio communications - @param Frequency :{431000000-928000000} - - This must be within the available bands of the radio: - - 431000000Hz to 464000000Hz and - - 862000000Hz to 928000000Hz. - @pre RadioInit() must be called before this function is called. - @code - if (RIE_Response == RIE_Success) - RIE_Response = RadioSetFrequency(915000000); - @endcode - @return RIE_Responses Error code -**/ -RIE_Responses RadioSetFrequency(RIE_U32 Frequency) -{ - RIE_Responses Response = RIE_Success; - RIE_U32 EncodedFrequency; - - bRadioConfigurationChanged = RIE_TRUE; - - EncodedFrequency = (RIE_U32)(Frequency * FREQ_CNVRT_VAL); - RadioConfiguration.channel_freq_0_r = (EncodedFrequency >> 0) & 0xFF; - RadioConfiguration.channel_freq_1_r = (EncodedFrequency >> 8) & 0xFF; - RadioConfiguration.channel_freq_2_r = (EncodedFrequency >> 16)& 0xFF; - if (Frequency >= 862000000) - { - RadioConfiguration.image_reject_cal_amplitude_r = 0x07; - RadioConfiguration.image_reject_cal_phase_r = 0x16; - } - else - { - RadioConfiguration.image_reject_cal_amplitude_r = 0x03; - RadioConfiguration.image_reject_cal_phase_r = 0x08; - } - return Response; -} - -/** - @fn RIE_Responses RadioSetModulationType(RIE_ModulationTypes ModulationType) - @brief Set the Radio Transmitter Modulation Type. Can be FSK_Modulation or GFSK_Modulation. - @param ModulationType :{DR_1_0kbps_Dev10_0kHz , DR_38_4kbps_Dev20kHz ,DR_300_0kbps_Dev75_0kHz } - - DR_1_0kbps_Dev10_0kHz Base configuration of 1 kbps datarate, 10.0 kHz frequency deviation. - - DR_38_4kbps_Dev20kHz Base configuration of 38.4 kbps datarate, 20 kHz frequency deviation. - - DR_300_0kbps_Dev75_0kHz Base configuration of 300 kbps datarate, 75 kHz frequency deviation. - @pre RadioInit() must be called before this function is called. - @code - Response = RadioSetModulationType(GFSK_Modulation); - @endcode - @note FSK_Modulation is used by default. - @return RIE_Responses Error code -**/ -RIE_Responses RadioSetModulationType(RIE_ModulationTypes ModulationType) -{ - RIE_Responses Response = RIE_Success; - RIE_U8 ucNewCode; - RIE_U8 ucNewRegVal = RadioConfiguration.radio_cfg_9_r; - - switch (ModulationType) - { - case FSK_Modulation: - ucNewCode = radio_cfg_9_mod_scheme_2_level_FSK; - break; - case GFSK_Modulation: - ucNewCode = radio_cfg_9_mod_scheme_2_level_GFSK; - break; - default: - Response = RIE_UnsupportedRadioConfig; - break; - } - if(Response == RIE_Success) - { - ucNewRegVal = MSKSET_VAL(RadioConfiguration.radio_cfg_9_r, - radio_cfg_9_mod_scheme_numbits, - radio_cfg_9_mod_scheme_offset, - ucNewCode); - if (ucNewRegVal != RadioConfiguration.radio_cfg_9_r ) - { - bRadioConfigurationChanged = RIE_TRUE; - RadioConfiguration.radio_cfg_9_r = ucNewRegVal; - } - - } - return Response; -} - -/** - @fn RIE_Responses RadioPayldManchesterEncode(RIE_BOOL bEnable) - @brief Enable or Disable Manchester Encoding of payload data. - - Manchester encoding can be used to ensure a dc-free (zero mean) - transmission. - - A Binary 0 is mapped to 10, and a Binary 1 is mapped to 01. - - Manchester encoding and decoding are applied to the payload data - and the CRC. - - @param bEnable :{RIE_FALSE,RIE_TRUE} - - RIE_TRUE if Manchester Encoding is to be enabled. - - RIE_FALSE if disabled. - - @pre RadioInit() must be called before this function is called. - @code - Response = RadioPayldManchesterEncode(RIE_TRUE); - - @endcode - @note Manchester Encoding is disabled by default. - @return RIE_Responses Error code -**/ -RIE_Responses RadioPayldManchesterEncode(RIE_BOOL bEnable) -{ - RIE_Responses Response = RIE_Success; - RIE_U8 ucNewRegVal = RadioConfiguration.symbol_mode_r; - - switch (bEnable) - { - case RIE_FALSE: - ucNewRegVal &= ~symbol_mode_manchester_enc_enabled; - break; - case RIE_TRUE: - ucNewRegVal |= symbol_mode_manchester_enc_enabled; - break; - default: - Response = RIE_UnsupportedRadioConfig; - break; - } - if(Response == RIE_Success) - { - if (ucNewRegVal != RadioConfiguration.symbol_mode_r ) - { - bRadioConfigurationChanged = RIE_TRUE; - RadioConfiguration.symbol_mode_r = ucNewRegVal; - } - } - return Response; -} -/** - @fn RIE_Responses RadioPayldDataWhitening(RIE_BOOL bEnable) - @brief Enable or Disable Data Whitening of payload data. - - Data whitening can be employed to avoid long runs of 1s or 0s - in the transmitted data stream. - - This ensures sufficient bit transitions in the packet, which - aids in receiver clock and data recovery because the encoding - breaks up long runs of 1s or 0s in the transmit packet. - - The data, excluding the preamble and sync word, is automatically - whitened before transmission by XORing the data with an 8-bit - pseudorandom sequence. - - At the receiver, the data is XORed with the same pseudorandom - sequence, thereby reversing the whitening. - - The linear feedback shift register polynomial used is x7 + x1 + 1. - - @param bEnable :{RIE_FALSE, RIE_TRUE} - - RIE_TRUE if Manchester Encoding is to be enabled. - - RIE_FALSE if disabled. - - @pre RadioInit() must be called before this function is called. - @code - Response = RadioPayldDataWhitening(RIE_TRUE); - - @endcode - @note Data Whitening is disabled by default. - @return RIE_Responses Error code -**/ -RIE_Responses RadioPayldDataWhitening(RIE_BOOL bEnable) -{ - RIE_Responses Response = RIE_Success; - RIE_U8 ucNewRegVal = RadioConfiguration.symbol_mode_r; - - switch (bEnable) - { - case RIE_FALSE: - ucNewRegVal &= ~symbol_mode_data_whitening_enabled; - break; - case RIE_TRUE: - ucNewRegVal |= symbol_mode_data_whitening_enabled; - break; - default: - Response = RIE_UnsupportedRadioConfig; - break; - } - if(Response == RIE_Success) - { - if (ucNewRegVal != RadioConfiguration.symbol_mode_r ) - { - bRadioConfigurationChanged = RIE_TRUE; - RadioConfiguration.symbol_mode_r = ucNewRegVal; - } - } - return Response; -} - -/** - @fn RIE_Responses RadioTxPacketFixedLen(RIE_U8 Len, RIE_U8 *pData) - @brief Transmit a fixed length packet. - @param Len :{1-240} Length of packet to be transmitted. - @param pData :{} Data bytes to be transmitted. - @pre RadioInit() must be called before this function is called. - @code - if (RIE_Response == RIE_Success) - RIE_Response = RadioTxSetPA(DifferentialPA,PowerLevel15); - if (RIE_Response == RIE_Success) - RIE_Response = RadioTxPacketFixedLen(12, "HELLO WORLD"); - while (!RadioTxPacketComplete()); - @endcode - @return RIE_Responses Error code -**/ -RIE_Responses RadioTxPacketFixedLen(RIE_U8 Len, RIE_U8 *pData) -{ - RIE_Responses Response = RIE_Success; - - bPacketTx = RIE_FALSE; - if (Len > PACKETRAM_LEN) - Response = RIE_InvalidParamter; - if (Response == RIE_Success) - Response = RadioToOnMode(); - if (Response == RIE_Success) - Response = RadioMMapWrite(PACKETRAM_START, Len, pData); - if (Response == RIE_Success) - { - RadioConfiguration.packet_length_max_r = Len; - RadioConfiguration.packet_length_control_r |= packet_length_control_packet_len_fixed; - } - if(Response == RIE_Success) - Response = RadioCommitRadioConfig(); - if (Response == RIE_Success) - Response = RadioToOnMode(); - if (Response == RIE_Success) - Response = RadioSendCommandWait(CMD_PHY_TX); - - return Response; -} - -/** - @fn RIE_Responses RadioTxPacketVariableLen(RIE_U8 Len, RIE_U8 *pData) - @brief Transmit a Variable length packet. - @param Len :{1-240} Length of packet to be transmitted. - @param pData :{} Data bytes to be transmitted. - @pre RadioInit() must be called before this function is called. - @code - if (RIE_Response == RIE_Success) - RIE_Response = RadioTxSetPA(DifferentialPA,PowerLevel15); - if (RIE_Response == RIE_Success) - RIE_Response = RadioTxPacketVariableLen(12, "HELLO WORLD"); - while (!RadioTxPacketComplete()); - @endcode - @return RIE_Responses Error code -**/ -RIE_Responses RadioTxPacketVariableLen(RIE_U8 Len, RIE_U8 *pData) -{ - RIE_Responses Response = RIE_Success; - - bPacketTx = RIE_FALSE; - - Len += 0x1; - if (Len > PACKETRAM_LEN) - Response = RIE_InvalidParamter; - if (Response == RIE_Success) - Response = RadioToOnMode(); - if (Response == RIE_Success) - Response = RadioMMapWrite(PACKETRAM_START, 0x1, &Len); - if (Response == RIE_Success) - Response = RadioMMapWrite(PACKETRAM_START+0x1, Len-1, pData); - if (Response == RIE_Success) - { - RadioConfiguration.packet_length_max_r = PACKETRAM_LEN; - RadioConfiguration.packet_length_control_r &= ~packet_length_control_packet_len_fixed; - } - if(Response == RIE_Success) - Response = RadioCommitRadioConfig(); - if (Response == RIE_Success) - Response = RadioToOnMode(); - if (Response == RIE_Success) - Response = RadioSendCommandWait(CMD_PHY_TX); - - return Response; -} - - -/** - @fn RIE_BOOL RadioTxPacketComplete(void) - @brief Checks if a packet has finished transmitting - @pre RadioInit() must be called before this function is called. - @pre RadioRxPacketFixedLen() or equivalent should be called first. - @code - if (RIE_Response == RIE_Success) - RIE_Response = RadioTxSetPA(DifferentialPA,PowerLevel15); - if (RIE_Response == RIE_Success) - RIE_Response = RadioTxPacketFixedLen(12, "HELLO WORLD"); - while (!RadioTxPacketComplete()); - @endcode - @return RIE_BOOL RIE_TRUE if packet has finished transmitting, else RIE_FALSE -**/ -RIE_BOOL RadioTxPacketComplete (void) -{ - return bPacketTx; -} - -/** - @fn RIE_Responses RadioTxSetPA(RIE_PATypes PAType,RIE_PAPowerLevel Power) - @brief Set PA Type and the Transmit Power Level for Radio Transmission. - @param PAType :{DifferentialPA, SingleEndedPA} Select Single Ended or Differential PA Type - @param Power :{PowerLevel0 ,PowerLevel1 ,PowerLevel2 ,PowerLevel3, - PowerLevel4 ,PowerLevel5 ,PowerLevel6 ,PowerLevel7, - PowerLevel8 ,PowerLevel9 ,PowerLevel10,PowerLevel11, - PowerLevel12,PowerLevel13,PowerLevel14,PowerLevel15} - @pre RadioInit() must be called before this function is called. - @code - Response = RadioTxSetPA(SingleEndedPA,PowerLevel8); - @endcode - @note Differential PA is enabled by default. - @note Max TX Power is used by default. - @return RIE_Responses Error code -**/ -RIE_Responses RadioTxSetPA(RIE_PATypes PAType,RIE_PAPowerLevel Power) -{ - RIE_Responses Response = RIE_Success; - RIE_U8 ucNewRegVal = 0x0; - unsigned long pa_level_mcr,pa_ramp, codes_per_bit,min_codes_per_bit; - - switch (PAType) - { - case DifferentialPA: - ucNewRegVal |= radio_cfg_8_pa_single_diff_sel_differential; - break; - case SingleEndedPA: - ucNewRegVal |= radio_cfg_8_pa_single_diff_sel_single_ended; - break; - default: - Response = RIE_UnsupportedRadioConfig; - break; - } - if(Response == RIE_Success) - { - switch (Power) - { - case PowerLevel0 : - case PowerLevel1 : - case PowerLevel2 : - case PowerLevel3 : - case PowerLevel4 : - case PowerLevel5 : - case PowerLevel6 : - case PowerLevel7 : - case PowerLevel8 : - case PowerLevel9 : - case PowerLevel10: - case PowerLevel11: - case PowerLevel12: - case PowerLevel13: - case PowerLevel14: - case PowerLevel15: - ucNewRegVal |= ((RIE_U8)Power << radio_cfg_8_pa_power_offset); - // Calculate the minimum allowable codes per bit - pa_level_mcr = (((RIE_U8)Power)* 4) + 0x3; - min_codes_per_bit = (pa_level_mcr * 2500)/(DataRate/100); - pa_ramp = 0x1; - codes_per_bit = 256; - while (codes_per_bit > min_codes_per_bit) - { - pa_ramp++; - codes_per_bit = 512 >> pa_ramp; - if (pa_ramp >= 7) - break; // This is the maximum - } - ucNewRegVal |= ((RIE_U8)pa_ramp << radio_cfg_8_pa_ramp_offset); - break; - default: - Response = RIE_UnsupportedRadioConfig; - break; - } - } - - if(Response == RIE_Success) - { - if (ucNewRegVal != RadioConfiguration.radio_cfg_8_r ) - { - bRadioConfigurationChanged = RIE_TRUE; - RadioConfiguration.radio_cfg_8_r = ucNewRegVal; - } - } - return Response; -} -/** - @fn RIE_Responses RadioTxCarrier(void) - @brief Transmit a carrier tone - using the current radio configuration. - @pre RadioInit() must be called before this function is called. - @code - Response = RadioTxCarrier(); - @endcode - @note Terminate this mode by calling RadioTerminateRadioOp(); - @return RIE_Responses Error code -**/ -RIE_Responses RadioTxCarrier (void) -{ - RIE_Responses Response = RIE_Success; - RIE_U8 ParamTX = PARAM_TX_CARRIER_FOREVER; - - if(Response == RIE_Success) - Response = RadioCommitRadioConfig(); - bTestModeEnabled = RIE_TRUE; - if (Response == RIE_Success) - Response = RadioToOnMode(); - // Mode needs to be set, before entry to PHY_TX - if (Response == RIE_Success) - Response = RadioMMapWrite(PR_var_tx_mode_ADR,sizeof(ParamTX),&ParamTX); - if (Response == RIE_Success) - Response = RadioSendCommandWait(CMD_PHY_TX); - return Response; -} -/** - @fn RIE_Responses RadioTxPreamble(void) - @brief Transmit a pre-amble (alternating ones and zeros) - using the current radio configuration. - @pre RadioInit() must be called before this function is called. - @code - Response = RadioTxPreamble(); - @endcode - @note Terminate this mode by calling RadioTerminateRadioOp(); - @return RIE_Responses Error code -**/ -RIE_Responses RadioTxPreamble (void) -{ - RIE_Responses Response = RIE_Success; - RIE_U8 ParamTX = PARAM_TX_PREAMBLE_FOREVER; - - if(Response == RIE_Success) - Response = RadioCommitRadioConfig(); - if (Response == RIE_Success) - Response = RadioToOnMode(); - bTestModeEnabled = RIE_TRUE; - // Mode needs to be set, before entry to PHY_TX - if (Response == RIE_Success) - Response = RadioMMapWrite(PR_var_tx_mode_ADR,sizeof(ParamTX),&ParamTX); - if (Response == RIE_Success) - Response = RadioSendCommandWait(CMD_PHY_TX); - return Response; -} - -/** - @fn RIE_Responses RadioRxPacketFixedLen(RIE_U8 Len) - @brief Enter receive mode and wait for a packet to be received. - - Radio will stay in Receive Mode until - 1) A packet is received. - 2) User manually exits Receive Mode with a call to RadioTerminateRadioOp() - - @param Len :{1-240} Fixed Length of packet to be received. - @pre RadioInit() must be called before this function is called. - @return RIE_Responses Error code -**/ -RIE_Responses RadioRxPacketFixedLen(RIE_U8 Len) -{ - RIE_Responses Response = RIE_Success; - - bPacketRx = RIE_FALSE; - if (Len > PACKETRAM_LEN) - Response = RIE_InvalidParamter; - - if (Response == RIE_Success) - { - RadioConfiguration.packet_length_max_r = Len; - RadioConfiguration.packet_length_control_r |= packet_length_control_packet_len_fixed; - } - if(Response == RIE_Success) - Response = RadioCommitRadioConfig(); - if (Response == RIE_Success) - Response = RadioToOnMode(); - if (Response == RIE_Success) - Response = RadioSendCommandWait(CMD_PHY_RX); - return Response; -} - -/** - @fn RIE_Responses RadioRxPacketVariableLen(void) - @brief Enter receive mode and wait for a packet to be received. - - Radio will stay in Receive Mode until - 1) A packet is received. - 2) User manually exits Receive Mode with a call to RadioTerminateRadioOp() - - @pre RadioInit() must be called before this function is called. - @return RIE_Responses Error code -**/ -RIE_Responses RadioRxPacketVariableLen(void) -{ - RIE_Responses Response = RIE_Success; - - bPacketRx = RIE_FALSE; - - if (Response == RIE_Success) - { - RadioConfiguration.packet_length_max_r = PACKETRAM_LEN; - RadioConfiguration.packet_length_control_r &= ~packet_length_control_packet_len_fixed; - } - if(Response == RIE_Success) - Response = RadioCommitRadioConfig(); - if (Response == RIE_Success) - Response = RadioToOnMode(); - if (Response == RIE_Success) - Response = RadioSendCommandWait(CMD_PHY_RX); - return Response; -} - -/** - @fn RIE_BOOL RadioRxPacketAvailable(void) - @brief Checks if a packet has been received. - @pre RadioInit() must be called before this function is called. - @pre RadioRxPacketFixedLen() or equivalent should be called first. - @code - if (RIE_Response == RIE_Success) - RIE_Response = RadioRxPacketFixedLen(12); - if (RIE_Response == RIE_Success) - { - while (!RadioRxPacketAvailable()); - } - if (RIE_Response == RIE_Success) - { - unsigned char Buffer[0x20]; - RIE_U8 PktLen; - RIE_S8 RSSI; - RIE_Response = RadioRxPacketRead(sizeof(Buffer),&PktLen,Buffer,&RSSI); - } - @endcode - @return RIE_BOOL RIE_TRUE if packet received, else RIE_FALSE -**/ -RIE_BOOL RadioRxPacketAvailable(void) -{ - return bPacketRx; - -} - -/** - @fn RIE_Responses RadioRxPacketRead(RIE_U8 BufferLen,RIE_U8 *pPktLen,RIE_U8 *pData,RIE_S8 *pRSSIdBm) - @brief Read the packet that was received by the radio. - @param BufferLen :{1-240} Size of passed in buffer - @param pPktLen :{1-240} Storage for size of actual received packet - @param pData :{} Received Packet will be stored here. - @param pRSSIdBm :{} RSSI of received packet in dBm. - @pre RadioInit() must be called before this function is called. - @pre RadioRxPacketFixedLen() or equivalent should be called first. - @code - if (RIE_Response == RIE_Success) - RIE_Response = RadioRxPacketFixedLen(12); - if (RIE_Response == RIE_Success) - { - while (!RadioRxPacketAvailable()); - } - if (RIE_Response == RIE_Success) - { - unsigned char Buffer[0x20]; - RIE_U8 PktLen; - RIE_S8 RSSI; - RIE_Response = RadioRxPacketRead(sizeof(Buffer),&PktLen,Buffer,&RSSI); - } - @endcode - @note Check for the presence of a packet by calling RadioRxPacketAvailable(); - @return RIE_Responses Error code -**/ -RIE_Responses RadioRxPacketRead(RIE_U8 BufferLen,RIE_U8 *pPktLen,RIE_U8 *pData,RIE_S8 *pRSSIdBm) -{ - RIE_Responses Response = RIE_Success; - - if (RadioRxPacketAvailable()) - { - RIE_U8 RdLen; - if(RadioConfiguration.packet_length_control_r & packet_length_control_packet_len_fixed) - { - if (pPktLen) - *pPktLen = RadioConfiguration.packet_length_max_r; - RdLen = RadioConfiguration.packet_length_max_r; - if (RdLen > BufferLen) - RdLen = BufferLen; - if (Response == RIE_Success) - Response = RadioMMapRead(PACKETRAM_START,RdLen, pData); - } - else - { - if (Response == RIE_Success) - Response = RadioMMapRead(PACKETRAM_START,0x1, &RdLen); - RdLen -= 0x1; - if (pPktLen) - *pPktLen = RdLen; - if (RdLen > BufferLen) - RdLen = BufferLen; - if (Response == RIE_Success) - Response = RadioMMapRead(PACKETRAM_START+0x1,RdLen, pData); - } - - if (pRSSIdBm) - { - if (Response == RIE_Success) - Response = RadioMMapRead(MCR_rssi_readback_Adr,0x1, (RIE_U8 *)pRSSIdBm); - - *pRSSIdBm -= 107; // Convert to dBm - } - - } - else - { - if (pPktLen) - *pPktLen = 0x0; - } - - return Response; -} - -/** - @fn RIE_Responses RadioRxBERTestMode(void) - @brief Enter receiver Bit Error Rate (BER) test mode where the - clock and data appear on GPIO pins. - Clock on P0.6 and Data on P2.6 - @pre RadioInit() must be called before this function is called. - @code - Response = RadioRxBERTestMode(); - @endcode - @note Terminate this mode by calling RadioTerminateRadioOp(); - @return RIE_Responses Error code -**/ -RIE_Responses RadioRxBERTestMode(void) -{ - RIE_Responses Response = RIE_Success; - RIE_U8 Data; - // Enables internal radio signals on external pins - // but overrides some of the standard GPIO muxed - // functionality (UART?) - pADI_MISC->RFTST = 0x7E1; - - if(Response == RIE_Success) - Response = RadioCommitRadioConfig(); - - bTestModeEnabled = RIE_TRUE; - // Enable the RX signals on GPIO pins - Data = gpio_configure_sport_mode_0; - if (Response == RIE_Success) - Response = RadioMMapWrite(MCR_gpio_configure_Adr, 0x1, (RIE_U8 *)&Data); - - // disable ext_uc_clk on GP5 - Data = 0; - if (Response == RIE_Success) - Response = RadioMMapWrite(MCR_ext_uc_clk_divide_Adr, - 0x1, - (RIE_U8 *)&Data); - if (Response == RIE_Success) - Response = RadioSendCommandWait(CMD_PHY_RX); - return Response; -} - -/** - @internal Hide from Doxegen - @fn RIE_Responses RadioCommitRadioConfig(void) - @brief Configures the radio if any changes were made - since the last time. - @return RIE_Responses Error code -**/ -static RIE_Responses RadioCommitRadioConfig(void) -{ - RIE_Responses Response = RIE_Success; - - if(bTestModeEnabled) - { - RIE_U8 Data; - Data = gpio_configure_default; - if (Response == RIE_Success) - Response = RadioMMapWrite(MCR_gpio_configure_Adr, 0x1, (RIE_U8 *)&Data); - Data = 4; - if (Response == RIE_Success) - Response = RadioMMapWrite(MCR_ext_uc_clk_divide_Adr, - 0x1, - (RIE_U8 *)&Data); - - Data = PARAM_TX_NORMAL_PACKET; - if (Response == RIE_Success) - Response = RadioMMapWrite(PR_var_tx_mode_ADR,sizeof(Data),&Data); - bTestModeEnabled = RIE_FALSE; - } - if (bRadioConfigurationChanged) - { - Response = RadioConfigure(); - if(Response == RIE_Success) - bRadioConfigurationChanged = RIE_FALSE; - } - return Response; -} -/** - @fn RIE_Responses RadioReadState(RadioState *pState) - @brief Read the current state - @param pState Pointer to return storage of state - @return RIE_Responses Error code -**/ -static RIE_Responses RadioReadState(RadioState *pState) -{ - RIE_Responses Response = RIE_Success; - RIE_U8 StatusByte; - - NVIC_DisableIRQ(UHFTRX_IRQn); - RADIO_CSN_ASSERT; - if (Response == RIE_Success) - Response = RadioSPIXferByte(SPI_NOP,NULL); - if (Response == RIE_Success) - Response = RadioSPIXferByte(SPI_NOP,&StatusByte); - RADIO_CSN_DEASSERT; - NVIC_EnableIRQ (UHFTRX_IRQn); - if ((Response == RIE_Success) && pState) - *pState = (RadioState)(StatusByte & STATUS_BYTE_FW_STATE); - return Response; -} - -/** - @fn RIE_Responses RadioWaitOnState(RadioState FinalState) - @brief Wait for Final State to be reached - @param FinalState State to wait on - @return RIE_Responses Error code -**/ -static RIE_Responses RadioWaitOnState(RadioState FinalState) -{ - RIE_Responses Response = RIE_Success; - RadioState CurrState; - do - { - Response = RadioReadState(&CurrState); - } - while((Response == RIE_Success) && (CurrState != FinalState)); - return Response; -} - -/** - @fn RIE_Responses RadioWaitOnCmdLdr(void) - @brief Wait for Final State to be reached - @return RIE_Responses Error code -**/ -static RIE_Responses RadioWaitOnCmdLdr(void) -{ - RIE_Responses Response = RIE_Success; - do - { - RIE_U8 StatusByte; - NVIC_DisableIRQ(UHFTRX_IRQn); - RADIO_CSN_ASSERT; - if (Response == RIE_Success) - Response = RadioSPIXferByte(SPI_NOP,NULL); - if (Response == RIE_Success) - Response = RadioSPIXferByte(SPI_NOP,&StatusByte); - RADIO_CSN_DEASSERT; - NVIC_EnableIRQ (UHFTRX_IRQn); - if ((Response == RIE_Success)) - if(StatusByte & STATUS_BYTE_CMD_READY) - break; - } - while((Response == RIE_Success)); - return Response; -} - -/** - @internal Hide from Doxegen - @fn RIE_Responses RadioToOnMode(void) - @brief Transition to On Mode - - Handle all possible states that the radio could be in - and brings it back to PHY_ON state - @param None - @return RIE_Responses Error code -**/ -static RIE_Responses RadioToOnMode(void) -{ - RIE_Responses Response = RIE_Success; - RadioState FwState; - - if (Response == RIE_Success) - Response = RadioReadState(&FwState); - - while ((FwState != FW_ON) && (Response == RIE_Success)) - { - switch (FwState) - { - case FW_BUSY: - break; - case FW_TX: - if(Response == RIE_Success) - Response = RadioSendCommandNoWait(CMD_PHY_ON); - if (Response == RIE_Success) - Response = RadioWaitOnState (FW_ON); - break; - case FW_RX: - if(Response == RIE_Success) - Response = RadioSendCommandNoWait(CMD_PHY_ON); - if (Response == RIE_Success) - Response = RadioWaitOnState (FW_ON); - break; - default: - if(Response == RIE_Success) - Response = RadioSendCommandNoWait(CMD_PHY_ON); - if (Response == RIE_Success) - Response = RadioWaitOnState (FW_ON); - break; - } - if (Response == RIE_Success) - Response = RadioReadState(&FwState); - } - return Response; -} -/** - @internal Hide from Doxegen - @fn RIE_Responses RadioToOffMode(void) - @brief Transition to Off Mode - - Handle all possible states that the radio could be in - and bring it back to PHY_OFF state. - - @param None - @return RIE_Responses Error code -**/ -static RIE_Responses RadioToOffMode(void) -{ - RIE_Responses Response = RIE_Success; - RadioState FwState; - - if (Response == RIE_Success) - Response = RadioReadState(&FwState); - - while ((FwState != FW_OFF) && (Response == RIE_Success)) - { - switch (FwState) - { - case FW_BUSY: - break; - case FW_TX: - if(Response == RIE_Success) - Response = RadioSendCommandNoWait(CMD_PHY_ON); - if (Response == RIE_Success) - Response = RadioWaitOnState (FW_ON); - break; - case FW_RX: - if(Response == RIE_Success) - Response = RadioSendCommandNoWait(CMD_PHY_ON); - if (Response == RIE_Success) - Response = RadioWaitOnState (FW_ON); - break; - default: - if(Response == RIE_Success) - Response = RadioSendCommandNoWait(CMD_PHY_OFF); - if (Response == RIE_Success) - Response = RadioWaitOnState (FW_OFF); - break; - } - if (Response == RIE_Success) - Response = RadioReadState(&FwState); - } - return Response; -} -/** - @internal Hide from Doxegen - @fn RIE_Responses RadioSyncComms (void) - @brief Sync comms with the radio - @param None - @return RIE_Responses Error code -**/ -static RIE_Responses RadioSyncComms (void) -{ - RIE_Responses Response = RIE_Success; - if (Response == RIE_Success) - Response = RadioSendCommandWait(CMD_SYNC); - if (Response == RIE_Success) - Response = RadioWaitOnCmdLdr(); - return Response; -} -/** - @fn RIE_Responses RadioWaitForPowerUp(void) - @brief Wake Up the Part - - Assert SPI chip select which will wake up the radio if asleep - Wait for MISO line to go high indicating SPI comms now possible - - @return RIE_Responses Error code -**/ -static RIE_Responses RadioWaitForPowerUp(void) -{ - RIE_Responses Response = RIE_Success; - int i = 0x0; - RADIO_CSN_ASSERT; - while (!RADIO_MISO_IN && (i < 1000)) - i++; - if (1000 == i)// Timed out waiting for MISO high? - Response = RIE_RadioSPICommsFail; - RADIO_CSN_DEASSERT; - return Response; -} - -/** - \internal Hide from Doxegen - \fn void Ext_Int8_Handler(void) - \brief Radio Interrupt Handler -**/ -extern void aducrf101_rx_packet_hook(void); -void Ext_Int8_Handler (void) -{ - RIE_Responses Response = RIE_Success; - RIE_U8 ucInt0; - RIE_U8 ucInt1; - - if (Response == RIE_Success) - Response = RadioMMapRead(MCR_interrupt_source_0_Adr,0x1, &ucInt0); - if (Response == RIE_Success) - Response = RadioMMapRead(MCR_interrupt_source_1_Adr,0x1,&ucInt1); - if (ucInt0 & interrupt_mask_0_interrupt_tx_eof) - bPacketTx = RIE_TRUE; - if (ucInt0 & interrupt_mask_0_interrupt_crc_correct) { - bPacketRx = RIE_TRUE; - aducrf101_rx_packet_hook(); - } - // Clear all the interrupts that we have just handleed - if (Response == RIE_Success) - Response = RadioMMapWrite(MCR_interrupt_source_0_Adr,0x1, &ucInt0); - if (Response == RIE_Success) - Response = RadioMMapWrite(MCR_interrupt_source_1_Adr,0x1,&ucInt1); - // Clear the interrupt - pADI_INTERRUPT->EICLR = EICLR_IRQ8; -} -/** - \internal Hide from Doxegen - \fn void RadioSPIXferByte(RIE_U8 ucByte,RIE_U8 *pData) - \brief Transfer a byte via SPI to the radio and optionally return - received byte. - Chip Select is manually controlled elsewhere. - \param ucByte Command or data byte to be transferred. - \param pData NULL, or storage for response - \return RIE_Responses Error code -**/ -static RIE_Responses RadioSPIXferByte(RIE_U8 ucByte,RIE_U8 *pData) -{ - RIE_Responses Response = RIE_Success; - - SEND_SPI(ucByte); // Send byte - WAIT_SPI_RX; // wait for data received status bit - if(pData) - *pData = READ_SPI; - else - (void)READ_SPI; - return Response; -} -/** - \internal Hide from Doxegen - \fn RIE_Responses RadioSendCommandBytes(RIE_U8 *pCmdBytes,RIE_U8 NumBytes) - \brief Send a complete command to the radio. - - It is neccessary to disable the radio interrupt when doing this - as a command in progress must finish before a radio interrupt - can be handled. - - \param pCmdBytes Pointer to a number of bytes to be transferred. - \param NumBytes Number of bytes to transfer - - \return RIE_Responses Error code -**/ -static RIE_Responses RadioSendCommandBytes(RIE_U8 *pCmdBytes,RIE_U8 NumBytes) -{ - RIE_Responses Response = RIE_Success; - - NVIC_DisableIRQ(UHFTRX_IRQn); - RADIO_CSN_ASSERT; - while ((NumBytes--) && (Response == RIE_Success)) - Response = RadioSPIXferByte(*(pCmdBytes++),NULL); // Send Command - RADIO_CSN_DEASSERT; // De-assert SPI chip select - NVIC_EnableIRQ (UHFTRX_IRQn); - - return Response; -} -/** - \internal Hide from Doxegen - \fn RIE_Responses RadioSendCommandNoWait (Radio_CmdCodes CmdCode ) - \brief Send a single byte command to the radio. - \param CmdCode Command code to be sent - \return RIE_Responses Error code -**/ -static RIE_Responses RadioSendCommandNoWait (Radio_CmdCodes CmdCode ) -{ - RIE_U8 Command = (RIE_U8)CmdCode; - return RadioSendCommandBytes(&Command,0x1); -} -/** - \internal Hide from Doxegen - \fn RIE_Responses RadioSendCommandWait (Radio_CmdCodes CmdCode ) - \brief Send a single byte command to the radio. - \param CmdCode Command code to be sent - \return RIE_Responses Error code -**/ -static RIE_Responses RadioSendCommandWait (Radio_CmdCodes CmdCode ) -{ - RIE_Responses Response = RIE_Success; - RIE_U8 Command = (RIE_U8)CmdCode; - - if (Response == RIE_Success) - Response = RadioWaitOnCmdLdr(); - if (Response == RIE_Success) - Response = RadioSendCommandBytes(&Command,0x1); - return Response; -} -/** - \fn RIE_Responses RadioMMapRead(RIE_U32 ulAdr, RIE_U32 ulLen, RIE_U8 *pData) - \brief Read bytes from specified memory map address - \param ulAdr Address to read at. - \param ulLen Length of data to read. - \param pData Pointer to location to stored read data. - \return RIE_Responses Error code -**/ -static RIE_Responses RadioMMapRead(RIE_U32 ulAdr, RIE_U32 ulLen, RIE_U8 *pData) -{ - RIE_Responses Response = RIE_Success; - - NVIC_DisableIRQ(UHFTRX_IRQn); - RADIO_CSN_ASSERT; - - if(Response == RIE_Success) // Send first byte (SPI_MEMR_RD + Bytes) - Response = RadioSPIXferByte(SPI_MEM_RD | ((ulAdr & 0x700) >> 8),NULL); - if(Response == RIE_Success)// Send Second byte remainder of address - Response = RadioSPIXferByte((RIE_U8)(ulAdr & 0xFF),NULL); - if(Response == RIE_Success) - Response = RadioSPIXferByte((RIE_U8)SPI_NOP,NULL); - while(ulLen-- && (Response == RIE_Success)) - Response = RadioSPIXferByte(SPI_NOP,pData++); - RADIO_CSN_DEASSERT; - NVIC_EnableIRQ (UHFTRX_IRQn); - - return Response; -} -/** - \fn RIE_Responses RadioMMapWrite(RIE_U32 ulAdr, RIE_U32 ulLen, RIE_U8 *pData) - \brief Read bytes from specified memory map address - \param ulAdr Address to read at. - \param ulLen Length of data to read. - \param pData Pointer to location of data to write. - \return RIE_Responses Error code -**/ -static RIE_Responses RadioMMapWrite(RIE_U32 ulAdr,RIE_U32 ulLen,RIE_U8 * pData) -{ - RIE_Responses Response = RIE_Success; - - NVIC_DisableIRQ(UHFTRX_IRQn); - RADIO_CSN_ASSERT; - if(Response == RIE_Success) // Send first byte (SPI_MEMR_WR + Bytes) - Response = RadioSPIXferByte(SPI_MEM_WR | ((ulAdr & 0x700) >> 8),NULL); - if(Response == RIE_Success) // Send Second byte remainder of addrress - Response = RadioSPIXferByte((RIE_U8)(ulAdr & 0xFF),NULL); - while(ulLen-- && (Response == RIE_Success)) - Response = RadioSPIXferByte(*(pData++),NULL); - RADIO_CSN_DEASSERT; - NVIC_EnableIRQ (UHFTRX_IRQn); - - return Response; -} - -/** - \internal Hide from Doxegen - \fn void SetRadioConfiguration(void) - \brief Create a default radio configuration that all base configurations - are derived from. - - \return RIE_Responses Error code -**/ -static RIE_Responses SetRadioConfiguration(RIE_BaseConfigs BaseConfig) -{ - RIE_Responses Response = RIE_Success; - - bRadioConfigurationChanged = RIE_TRUE; - switch (BaseConfig) - { - case DR_1_0kbps_Dev10_0kHz: - memcpy((void *)&RadioConfiguration, - (void *)DR_1_0kbps_Dev10_0kHz_Configuration, - sizeof(TyRadioConfiguration)); - DataRate = 1000; - break; - case DR_38_4kbps_Dev20kHz: - memcpy((void *)&RadioConfiguration, - (void *)DR_38_4kbps_Dev20kHz_Configuration, - sizeof(TyRadioConfiguration)); - DataRate = 38400; - break; - case DR_300_0kbps_Dev75_0kHz: - memcpy((void *)&RadioConfiguration, - (void *)DR_300_0kbps_Dev75_0kHz_Configuration, - sizeof(TyRadioConfiguration)); - DataRate = 300000; - break; - default: - Response = RIE_UnsupportedRadioConfig; - break; - } - return Response; -} -/** - @internal Hide from Doxegen - @fn RIE_Responses RadioConfigure (void) - @brief Configure the Radio as per the current configuration - @return RIE_Responses Error code -**/ -RIE_Responses RadioConfigure (void) -{ - RIE_Responses Response = RIE_Success; - if(Response == RIE_Success) - Response = RadioToOffMode(); - if(Response == RIE_Success) // Write the configuration to the radio memory - Response = RadioMMapWrite(BBRAM_START, - sizeof(TyRadioConfiguration), - (RIE_U8 *)&RadioConfiguration); - if(Response == RIE_Success) // Apply that configuration to the radio - Response = RadioSendCommandWait(CMD_CONFIG_DEV); - if(Response == RIE_Success) - Response = RadioToOnMode(); - return Response; -} - - -/** - @fn RIE_Responses RadioRadioGetRSSI (RIE_S8 *pRSSIdBm) - @brief Return a Received Signal Strength Indicator value - @param pRSSIdBm :{} detected RSSI in dBm. - @pre RadioInit() must be called before this function is called. - @code - RIE_S8 RSSIdBm; - if (RIE_Response == RIE_Success) - RIE_Response = RadioRadioGetRSSI(&RSSIdBm); - @endcode - @return RIE_Responses Error code -**/ -RIE_Responses RadioRadioGetRSSI (RIE_S8 *pRSSIdBm) -{ - RIE_Responses Response = RIE_Success; - - if(Response == RIE_Success) - Response = RadioCommitRadioConfig(); - if (Response == RIE_Success) - Response = RadioToOnMode(); - if (Response == RIE_Success) - Response = RadioSendCommandWait(CMD_GET_RSSI); - if (Response == RIE_Success) - Response = RadioSyncComms(); // - if (pRSSIdBm) - { - if (Response == RIE_Success) - Response = RadioMMapRead(MCR_rssi_readback_Adr,0x1, (RIE_U8 *)pRSSIdBm); - *pRSSIdBm -= 107; // Convert to dBm - } - return Response; -} - -/** - @fn RIE_Responses RadioTxSetPower(RIE_PAPowerLevel Power) - @brief Set the Transmit Power Level for Radio Transmission. - @param Power :{PowerLevel0 ,PowerLevel1 ,PowerLevel2 ,PowerLevel3, - PowerLevel4 ,PowerLevel5 ,PowerLevel6 ,PowerLevel7, - PowerLevel8 ,PowerLevel9 ,PowerLevel10,PowerLevel11, - PowerLevel12,PowerLevel13,PowerLevel14,PowerLevel15} - @pre RadioInit() must be called before this function is called. - @code - Response = RadioTxSetPower(PowerLevel8); - @endcode - @note Max TX Power is used by default. - @return RIE_Responses Error code -*/ -RIE_Responses RadioTxSetPower (RIE_PAPowerLevel Power) -{ - RIE_Responses Response = RIE_Success; - RIE_U8 ucNewRegVal = RadioConfiguration.radio_cfg_8_r; - unsigned long pa_level_mcr,pa_ramp, codes_per_bit,min_codes_per_bit; - - if (RadioConfiguration.radio_cfg_8_r & radio_cfg_8_pa_single_diff_sel_differential) - ucNewRegVal = radio_cfg_8_pa_single_diff_sel_differential; - else - ucNewRegVal = radio_cfg_8_pa_single_diff_sel_single_ended; - - if(Response == RIE_Success) - { - switch (Power) - { - case PowerLevel0 : - case PowerLevel1 : - case PowerLevel2 : - case PowerLevel3 : - case PowerLevel4 : - case PowerLevel5 : - case PowerLevel6 : - case PowerLevel7 : - case PowerLevel8 : - case PowerLevel9 : - case PowerLevel10: - case PowerLevel11: - case PowerLevel12: - case PowerLevel13: - case PowerLevel14: - case PowerLevel15: - ucNewRegVal |= ((RIE_U8)Power << radio_cfg_8_pa_power_offset); - // Calculate the minimum allowable codes per bit - pa_level_mcr = (((RIE_U8)Power)* 4) + 0x3; - min_codes_per_bit = (pa_level_mcr * 2500)/(DataRate/100); - pa_ramp = 0x1; - codes_per_bit = 256; - while (codes_per_bit > min_codes_per_bit) - { - pa_ramp++; - codes_per_bit = 512 >> pa_ramp; - if (pa_ramp >= 7) - break; // This is the maximum - } - ucNewRegVal |= ((RIE_U8)pa_ramp << radio_cfg_8_pa_ramp_offset); - break; - default: - Response = RIE_UnsupportedRadioConfig; - break; - } - } - - if(Response == RIE_Success) - { - if (ucNewRegVal != RadioConfiguration.radio_cfg_8_r ) - { - // Write directly to the MCR in this case and avoid a reconfigure - if (Response == RIE_Success) - Response = RadioMMapWrite(MCR_pa_level_mcr_Adr, 0x1, (RIE_U8 *)&ucNewRegVal); - RadioConfiguration.radio_cfg_8_r = ucNewRegVal; - } - } - return Response; -} - diff --git a/drivers/cpu/arm/aducrf101/Common/radioeng.h b/drivers/cpu/arm/aducrf101/Common/radioeng.h deleted file mode 100644 index 22f68cc63..000000000 --- a/drivers/cpu/arm/aducrf101/Common/radioeng.h +++ /dev/null @@ -1,174 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** -@file radioeng.h -@brief Radio Interface Engine Functions -@version v1.0 -@author PAD CSE group, Analog Devices Inc -@date May 08th 2013 -**/ - -#define RIE_U32 unsigned long -#define RIE_U16 unsigned short int -#define RIE_U8 unsigned char -#define RIE_S8 signed char - -/*! \enum RIE_BaseConfigs - * Variables of this type are used to define the Base Configuration - */ -/*! \var RIE_BaseConfigs DR_1_0kbps_Dev10_0kHz - * Base configuration of 1 kbps datarate, 10.0 kHz frequency deviation. - Use for achieving longer distances. - */ -/*! \var RIE_BaseConfigs DR_38_4kbps_Dev20kHz - * Base configuration of 38.4 kbps datarate, 20 kHz frequency deviation. - Use as a compromise of distance and power. - */ -/*! \var RIE_BaseConfigs DR_300_0kbps_Dev75_0kHz - * Base configuration of 300 kbps datarate, 75 kHz frequency deviation. - Use for achieving faster transmission times hence lower power. - */ -typedef enum -{ - DR_1_0kbps_Dev10_0kHz = 0x0, - DR_38_4kbps_Dev20kHz = 0x1, - DR_300_0kbps_Dev75_0kHz = 0x2, - UnsupportedDRDev -} RIE_BaseConfigs; - -/*! \enum RIE_ModulationTypes - * Variables of this type are used to define a tx modulation type - */ -/*! \var RIE_ModulationTypes FSK_Modulation - * FSK Modulation - */ -/*! \var RIE_ModulationTypes GFSK_Modulation - * GFSK Modulation - */ -typedef enum {FSK_Modulation = 0, GFSK_Modulation = 1} RIE_ModulationTypes; - -/*! \enum RIE_PATypes - * Variables of this type are used to define a PA type - */ -/*! \var RIE_PATypes DifferentialPA - * Differential PA - */ -/*! \var RIE_PATypes SingleEndedPA - * Single Ended PA - */ -typedef enum {DifferentialPA = 0, SingleEndedPA = 1} RIE_PATypes; - - - -typedef enum {PowerLevel0 ,PowerLevel1 ,PowerLevel2 ,PowerLevel3, - PowerLevel4 ,PowerLevel5 ,PowerLevel6 ,PowerLevel7, - PowerLevel8 ,PowerLevel9 ,PowerLevel10,PowerLevel11, - PowerLevel12,PowerLevel13,PowerLevel14,PowerLevel15 - } RIE_PAPowerLevel; - - -/*! \enum RIE_BOOL - * Variables of this type are used to define a TRUE or FALSE condition - */ -/*! \var RIE_BOOL RIE_TRUE - * TRUE condition - */ -/*! \var RIE_BOOL RIE_FALSE - * FALSE condition - */ -typedef enum {RIE_FALSE = 0, RIE_TRUE = !RIE_FALSE} RIE_BOOL; - - -/*! \enum RIE_Responses - * Variables of this type are used to define the return value from functions - */ -/*! \var RIE_Responses RIE_Success - * Successful completion - */ -/*! \var RIE_Responses RIE_RadioSPICommsFail - * SPI communications with the radio failure. - */ -/*! \var RIE_Responses RIE_UnsupportedRadioConfig - * This is an unsupported radio configuration - */ -/*! \var RIE_Responses RIE_Unimplemented - * This feature has not been implemented - */ -/*! \var RIE_Responses RIE_InvalidParamter - * An invaild parameter was passed - */ -typedef enum -{ - RIE_Success = 0x0, - RIE_RadioSPICommsFail = 0x1, - RIE_UnsupportedRadioConfig = 0x2, - RIE_Unimplemented = 0x3, - RIE_InvalidParamter = 0x4, -} RIE_Responses; - -// Added in Radio Interface Engine v0.1 -RIE_Responses RadioGetAPIVersion (RIE_U32 *pVersion); -RIE_Responses RadioInit (RIE_BaseConfigs BaseConfig); -RIE_Responses RadioPowerOff (void); -RIE_Responses RadioTerminateRadioOp (void); -RIE_Responses RadioSetFrequency (RIE_U32 Frequency); -RIE_Responses RadioSetModulationType (RIE_ModulationTypes ModulationType); -RIE_Responses RadioPayldManchesterEncode(RIE_BOOL bEnable); -RIE_Responses RadioPayldDataWhitening (RIE_BOOL bEnable); -RIE_Responses RadioTxPacketFixedLen (RIE_U8 Len, RIE_U8 *pData); -RIE_BOOL RadioTxPacketComplete (void); -RIE_Responses RadioTxSetPA (RIE_PATypes PAType,RIE_PAPowerLevel Power); -RIE_Responses RadioTxCarrier (void); -RIE_Responses RadioTxPreamble (void); -RIE_Responses RadioRxPacketFixedLen (RIE_U8 Len); -RIE_BOOL RadioRxPacketAvailable (void); -RIE_Responses RadioRxPacketRead (RIE_U8 BufferLen,RIE_U8 *pPktLen,RIE_U8 *pData,RIE_S8 *pRSSIdBm); -RIE_Responses RadioRxBERTestMode (void); - -// Added in Radio Interface Engine v0.2 -RIE_Responses RadioSwitchConfig (RIE_BaseConfigs BaseConfig); -RIE_Responses RadioRadioGetRSSI (RIE_S8 *pRSSIdBm); -RIE_Responses RadioTxSetPower (RIE_PAPowerLevel Power); - -// Added in Radio Interface Engine v0.3 -RIE_Responses RadioTxPacketVariableLen (RIE_U8 Len, RIE_U8 *pData); -RIE_Responses RadioRxPacketVariableLen (void); - -// Added in Radio Interface Engine v0.5 -RIE_Responses RadioDeInit (void); - - - - - diff --git a/drivers/cpu/arm/aducrf101/Common/system_ADuCRF101.c b/drivers/cpu/arm/aducrf101/Common/system_ADuCRF101.c deleted file mode 100644 index f6abc0a98..000000000 --- a/drivers/cpu/arm/aducrf101/Common/system_ADuCRF101.c +++ /dev/null @@ -1,178 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** -@file system_ADuCRF101.c -@brief CMSIS Cortex-M3 Device Peripheral Access Layer Implementation File - for the ADuCRF101 -@version v1.0 -@author PAD CSE group, Analog Devices Inc -@date January 14th 2013 -**/ - -#include -#include "ADuCRF101.h" - - -/*---------------------------------------------------------------------------- - DEFINES - *---------------------------------------------------------------------------*/ - -/* Extract the Clock Divider */ -#define __CCLK_DIV (1 << (pADI_CLKCTL->CLKCON & CLKCON_CD_MSK) ) - -/* define the clock multiplexer input frequencies */ -#define __HFOSC 16000000 -#define __LFXTAL 32768 -#define __LFOSC 32768 - -/*---------------------------------------------------------------------------- - Internal Clock Variables - *---------------------------------------------------------------------------*/ -static uint32_t uClk = 0; /* Undivided System Clock Frequency (UCLK) */ -static uint32_t uClkDiv = 0; /* Divided System Clock Frequency (UCLK_DIV) */ - -/* Frequency of the external clock source connected to P0.5 */ -static uint32_t SystemExtClock = 0; - -/*---------------------------------------------------------------------------- - Clock functions - *---------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ -/* pre-processor verification that clock mux mask and allowed values agree */ -#if ((CLKCON_CLKMUX_HFOSC \ - | CLKCON_CLKMUX_LFXTAL \ - | CLKCON_CLKMUX_LFOSC \ - | CLKCON_CLKMUX_EXTP05) \ - == CLKCON_CLKMUX_MSK) - - /* update the system core clock according the the current clock mux setting */ - switch (pADI_CLKCTL->CLKCON & CLKCON_CLKMUX_MSK ) { - - case CLKCON_CLKMUX_HFOSC: - uClk = __HFOSC; - break; - case CLKCON_CLKMUX_LFXTAL: - uClk = __LFXTAL; - break; - case CLKCON_CLKMUX_LFOSC: - uClk = __LFOSC; - break; - case CLKCON_CLKMUX_ECLKIN: - uClk = SystemExtClock; - break; - /* no need to catch default case due to pre-processor test */ - } - - /* update the divided system clock */ - uClkDiv = uClk / __CCLK_DIV; - -#else -#error "Clock mux mask and allowed value mismatch!" -#endif -} - -/** - * Initialize the system - * - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemFrequency variable. - */ -void SystemInit (void) -{ - /* reset CLKCON register */ - pADI_CLKCTL->CLKCON = CLKCON_RVAL; - - /* reset XOSCCON register */ - pADI_CLKCTL->XOSCCON = XOSCCON_RVAL; - - /* compute internal clocks */ - SystemCoreClockUpdate(); -} - -/** - * @brief Sets the system external clock frequency - * - * @param ExtClkFreq External clock frequency in Hz - * @return none - * - * Sets the clock frequency of the source connected to P0.5 clock input source - */ -void SetSystemExtClkFreq (uint32_t ExtClkFreq) -{ - SystemExtClock = ExtClkFreq; -} - -/** - * @brief Gets the system external clock frequency - * - * @return External Clock frequency - * - * Gets the clock frequency of the source connected to P0.5 clock input source - */ -uint32_t GetSystemExtClkFreq (void) -{ - return SystemExtClock; -} - - -/* set the system clock dividers */ -void SystemSetClockDivider(uint16_t div) -{ - /* critical region */ - __disable_irq(); - - /* read-modify-write without any interrupts */ - - pADI_CLKCTL->CLKCON &= ~(CLKCON_CD_MSK); /* keep everything else */ - pADI_CLKCTL->CLKCON |= div; /* set new value */ - - /* end critical region */ - __enable_irq(); - - /* refresh internal clock variables */ - SystemCoreClockUpdate(); -} - - -uint32_t SystemGetClockFrequency(void) -{ - return uClkDiv; -} - - - - diff --git a/drivers/cpu/arm/aducrf101/Common/system_ADuCRF101.h b/drivers/cpu/arm/aducrf101/Common/system_ADuCRF101.h deleted file mode 100644 index 241e3b062..000000000 --- a/drivers/cpu/arm/aducrf101/Common/system_ADuCRF101.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** -@file system_ADuCRF101.h -@brief: CMSIS Cortex-M3 Device Peripheral Access Layer Header File - for the ADuCRF101 -@version v0.2 -@author PAD CSE group, Analog Devices Inc -@date March 09th 2012 -**/ - - -#ifndef __SYSTEM_ADUCRF101_H__ -#define __SYSTEM_ADUCRF101_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/** - * @brief Initialize the system - * - * @return none - * - * Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * @brief Update internal SystemCoreClock variable - * - * @return none - * - * Updates the internal SystemCoreClock with current core - * Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - - -/** - * @brief Sets the system external clock frequency - * - * @param ExtClkFreq External clock frequency in Hz - * @return none - * - * Sets the clock frequency of the source connected to P0.5 clock input source - */ -extern void SetSystemExtClkFreq (uint32_t ExtClkFreq); - - -/** - * @brief Gets the system external clock frequency - * - * @return External Clock frequency - * - * Gets the clock frequency of the source connected to P0.5 clock input source - */ -extern uint32_t GetSystemExtClkFreq (void); - - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_ADUCRF101_H__ */ - diff --git a/drivers/cpu/arm/aducrf101/Makefile.aducrf101 b/drivers/cpu/arm/aducrf101/Makefile.aducrf101 deleted file mode 100644 index 48c01a7d5..000000000 --- a/drivers/cpu/arm/aducrf101/Makefile.aducrf101 +++ /dev/null @@ -1,75 +0,0 @@ -# -*- makefile -*- - -# Copyright (c) 2014, Analog Devices, Inc. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted (subject to the limitations in the -# disclaimer below) provided that the following conditions are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the -# distribution. -# -# - Neither the name of Analog Devices, Inc. nor the names of its -# contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -# GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -# HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -# Author: Jim Paris - -CONTIKI_CPU = $(CONTIKI)/drivers/cpu/arm/aducrf101 - -ifdef IAR -include $(CONTIKI_CPU)/Makefile.aducrf101.iar -else -include $(CONTIKI_CPU)/Makefile.aducrf101.gnu -endif - -ifdef SERIAL_ID - CFLAGS += -DSERIAL_ID='$(SERIAL_ID)' -endif - -ifdef __STACK_SIZE - CFLAGS += -D__STACK_SIZE=$(__STACK_SIZE) -endif - -ifdef RF_CHANNEL - CFLAGS += -DRF_CHANNEL=$(RF_CHANNEL) -endif - -# HSI internal oscillator by default -CFLAGS += -DF_CPU=16000000 - -### CPU-dependent directories and source files -CONTIKI_CPU_DIRS += ../common/CMSIS - -CONTIKI_CPU_DIRS += . -CONTIKI_SOURCEFILES += slip-arch.c -CONTIKI_SOURCEFILES += rtimer-arch.c - -CONTIKI_CPU_DIRS += dev -CONTIKI_SOURCEFILES += uart.c -CONTIKI_SOURCEFILES += clock.c -CONTIKI_SOURCEFILES += watchdog.c -CONTIKI_SOURCEFILES += radio.c - -CONTIKI_CPU_DIRS += Common -CONTIKI_SOURCEFILES += system_ADuCRF101.c -CONTIKI_SOURCEFILES += radioeng.c diff --git a/drivers/cpu/arm/aducrf101/Makefile.aducrf101.gnu b/drivers/cpu/arm/aducrf101/Makefile.aducrf101.gnu deleted file mode 100644 index bafb06aa9..000000000 --- a/drivers/cpu/arm/aducrf101/Makefile.aducrf101.gnu +++ /dev/null @@ -1,86 +0,0 @@ -# -*- makefile -*- - -# Copyright (c) 2014, Analog Devices, Inc. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted (subject to the limitations in the -# disclaimer below) provided that the following conditions are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the -# distribution. -# -# - Neither the name of Analog Devices, Inc. nor the names of its -# contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -# GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -# HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -# Author: Jim Paris - -CROSS_COMPILE = arm-none-eabi- - -CC = $(CROSS_COMPILE)gcc -LD = $(CROSS_COMPILE)gcc -AS = $(CROSS_COMPILE)gcc -AR = $(CROSS_COMPILE)gcc-ar -NM = $(CROSS_COMPILE)gcc-nm -OBJCOPY = $(CROSS_COMPILE)objcopy -OBJDUMP = $(CROSS_COMPILE)objdump -STRIP = $(CROSS_COMPILE)strip - -CFLAGS_OPT ?= -Os -CFLAGS_DEBUG ?= -ggdb3 -fomit-frame-pointer -CFLAGS += $(CFLAGS_OPT) $(CFLAGS_DEBUG) -CFLAGS += -std=gnu99 -CFLAGS += -ffreestanding -mcpu=cortex-m3 -mthumb -mno-thumb-interwork -CFLAGS += -ffunction-sections -fdata-sections -fno-common -fno-builtin -CFLAGS += -flto - -ifdef WERROR - CFLAGS += -Wall -Werror - # These warnings are triggered by existing Contiki code - CFLAGS += -Wno-error=pointer-sign - CFLAGS += -Wno-error=char-subscripts - CFLAGS += -Wno-error=unused-variable - CFLAGS += -Wno-error=unused-but-set-variable -endif - -# UIP code does not follow C aliasing rules -CFLAGS += -fno-strict-aliasing - -LDFLAGS = $(CFLAGS) -LDFLAGS += -specs=nosys.specs -nostartfiles - -# TODO: When it becomes more commonly available, switch to newlib-nano -# for significant size reduction, by uncommenting this: -# LDFLAGS += -specs=nano.specs - -LDFLAGS += -Wl,--gc-sections -LDFLAGS += -Wl,-T$(CONTIKI_CPU)/Common/GCC/ADuCRF101.ld - -ASFLAGS += -c $(CFLAGS) - -# Compiler-specific startup code -CONTIKI_CPU_DIRS += Common/GCC -CONTIKI_SOURCEFILES += crt0.S - -# Rules -%.hex: % - $(OBJCOPY) -O ihex $^ $@ \ No newline at end of file diff --git a/drivers/cpu/arm/aducrf101/Makefile.aducrf101.iar b/drivers/cpu/arm/aducrf101/Makefile.aducrf101.iar deleted file mode 100644 index 08f46be85..000000000 --- a/drivers/cpu/arm/aducrf101/Makefile.aducrf101.iar +++ /dev/null @@ -1,94 +0,0 @@ -# -*- makefile -*- - -# Copyright (c) 2014, Analog Devices, Inc. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted (subject to the limitations in the -# disclaimer below) provided that the following conditions are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the -# distribution. -# -# - Neither the name of Analog Devices, Inc. nor the names of its -# contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -# GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -# HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -# Author: Jim Paris - -# Filename quoting here is very tricky, and probably depends on which Windows -# build of "make" is being used. This works for mingw32-make. - -ifeq ($(IAR_PATH),) - IAR_SUBPATH := $(shell ls "${PROGRAMFILES}\IAR Systems" 2>/dev/null | tail -1) - ifeq ($(IAR_SUBPATH),) - define iar_error - -Unable to find the IAR installation path. Please specify IAR_PATH. -For example: $(MAKE) IAR_PATH="C:\\Program Files (x86)\\IAR Systems\\Embedded Workbench 7.0\\arm" - endef - $(error $(iar_error)) - endif - IAR_PATH := ${PROGRAMFILES}\IAR Systems\${IAR_SUBPATH}\arm -endif - -CC := "$(IAR_PATH)""\\bin\iccarm" -LD := "$(IAR_PATH)""\\bin\ilinkarm" -AS := "$(IAR_PATH)""\\bin\iasmarm" -AR := "$(IAR_PATH)""\\bin\iarchive" -OBJCOPY := "$(IAR_PATH)""\\bin\ielftool" - -CFLAGS += -Ohz -CFLAGS += --silent -CFLAGS += --debug -CFLAGS += --endian=little -CFLAGS += --cpu=Cortex-M3 -CFLAGS += -I"$(IAR_PATH)""\\inc" -CFLAGS += -D__ICCARM__ - -AROPTS = --create -ASFLAGS = -S -s+ -w+ --cpu Cortex-M3 - -LDFLAGS += --config $(CONTIKI_CPU)/Common/IAR/ADUCRF101.icf - -# Compiler-specific startup code -CONTIKI_CPU_DIRS += Common/IAR -CONTIKI_SOURCEFILES += startup_ADuCRF101.S - -# Rules - -CUSTOM_RULE_C_TO_OBJECTDIR_O = 1 -$(OBJECTDIR)/%.o: %.c | $(OBJECTDIR) - $(TRACE_CC) - $(Q)$(CC) $(CFLAGS) $< --dependencies=m $(@:.o=.d) -o $@ - -CUSTOM_RULE_C_TO_O = 1 -%.co: %.c - $(TRACE_CC) - $(Q)$(CC) $(CFLAGS) $< -o $@ - -CUSTOM_RULE_C_TO_CO = 1 -%.co: %.c - $(TRACE_CC) - $(Q)$(CC) $(CFLAGS) -DAUTOSTART_ENABLE $< -o $@ - -%.hex: % - $(OBJCOPY) --silent --ihex $^ $@ diff --git a/drivers/cpu/arm/aducrf101/aducrf101-contiki.h b/drivers/cpu/arm/aducrf101/aducrf101-contiki.h deleted file mode 100644 index 4610c49d6..000000000 --- a/drivers/cpu/arm/aducrf101/aducrf101-contiki.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - * \author Jim Paris - */ - -#ifndef ADUCRF101_CONTIKI_H -#define ADUCRF101_CONTIKI_H - -#include - -#include - -typedef uint32_t clock_time_t; -typedef uint16_t uip_stats_t; - -typedef uint32_t rtimer_clock_t; -#define RTIMER_CLOCK_DIFF(a, b) ((int32_t)((a) - (b))) -rtimer_clock_t rtimer_arch_now(void); - -#endif diff --git a/drivers/cpu/arm/aducrf101/clock.c b/drivers/cpu/arm/aducrf101/clock.c deleted file mode 100644 index e1feab63f..000000000 --- a/drivers/cpu/arm/aducrf101/clock.c +++ /dev/null @@ -1,107 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - * \author Jim Paris - */ - -#include -#include -#include - -static volatile clock_time_t current_clock = 0; -static volatile unsigned long current_seconds = 0; -static unsigned int second_countdown = CLOCK_SECOND; - -#define SAMPLE_STACK_POINTER -#ifdef SAMPLE_STACK_POINTER -volatile uint32_t *__min_sampled_sp = (uint32_t *)0xFFFFFFFF; -#endif - -void -SysTick_Handler(void) -{ -#ifdef SAMPLE_STACK_POINTER - /* Take note of the lowest stack pointer we ever saw. - When compiling against newlib, the total free bytes of - RAM not ever used by heap or stack can be found via GDB: - (gdb) p (char *)__min_sampled_sp - (char *)_sbrk(0) - */ - uint32_t *sp = (uint32_t *)&sp; - if (sp < __min_sampled_sp) - __min_sampled_sp = sp; -#endif - - current_clock++; - if(etimer_pending()) { - etimer_request_poll(); - } - if(--second_countdown == 0) { - current_seconds++; - second_countdown = CLOCK_SECOND; - } -} -/*---------------------------------------------------------------------------*/ -void -clock_init() -{ - SysTick_Config(F_CPU / CLOCK_SECOND); -} -/*---------------------------------------------------------------------------*/ -clock_time_t -clock_time(void) -{ - return current_clock; -} -/*---------------------------------------------------------------------------*/ -unsigned long -clock_seconds(void) -{ - return current_seconds; -} -/*---------------------------------------------------------------------------*/ -void -clock_delay_usec(uint16_t usec) -{ - /* Delay by watching the SysTick value change. */ - int32_t remaining = (int32_t)usec * F_CPU / 1000000; - int32_t old = SysTick->VAL; - while(remaining > 0) { - int32_t new = SysTick->VAL; - if(new > old) { /* wraparound */ - old += SysTick->LOAD; - } - remaining -= (old - new); - old = new; - } -} diff --git a/drivers/cpu/arm/aducrf101/dev/radio.c b/drivers/cpu/arm/aducrf101/dev/radio.c deleted file mode 100644 index 608e57614..000000000 --- a/drivers/cpu/arm/aducrf101/dev/radio.c +++ /dev/null @@ -1,397 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - * \author Jim Paris - */ - -#include -#include - -#include - -#include "contiki.h" -#include "contiki-net.h" -#include "net/netstack.h" -#include "radio.h" - -#define MAX_PACKET_LEN 240 - -static uint8_t tx_buf[MAX_PACKET_LEN]; - -#ifndef ADUCRF101_RADIO_BASE_CONFIG -#define ADUCRF101_RADIO_BASE_CONFIG DR_38_4kbps_Dev20kHz -#endif - -static RIE_BaseConfigs base_config = ADUCRF101_RADIO_BASE_CONFIG; -static int current_channel = 915000000; -static int current_power = 31; -static int radio_is_on = 0; -/*---------------------------------------------------------------------------*/ -/* "Channel" is really frequency, and can be within the bands: - 431000000 Hz to 464000000 Hz - 862000000 Hz to 928000000 Hz - */ -#define MIN_CHANNEL 431000000 -#define MAX_CHANNEL 928000000 -static int -_set_channel(int freq) -{ - if(freq < 431000000) { - freq = 431000000; - } else if(freq > 464000000 && freq < 663000000) { - freq = 464000000; - } else if(freq >= 663000000 && freq < 862000000) { - freq = 862000000; - } else if(freq > 928000000) { - freq = 928000000; - } - current_channel = freq; - if(RadioSetFrequency(freq) != RIE_Success) { - return RADIO_RESULT_ERROR; - } - return RADIO_RESULT_OK; -} -/*---------------------------------------------------------------------------*/ -/* "Power" covers both PA type and power level: - 0 through 15 means single-ended, power level 0 through 15 - 16 through 31 means differential, power level 0 through 15 */ -#define MIN_POWER 0 -#define MAX_POWER 31 -static int -_set_power(int power) -{ - RIE_Responses ret; - if(power < 0) { - power = 0; - } - if(power > 31) { - power = 31; - } - if(power <= 15) { - ret = RadioTxSetPA(SingleEndedPA, power); - } else { - ret = RadioTxSetPA(DifferentialPA, power - 16); - } - current_power = power; - if(ret != RIE_Success) { - return RADIO_RESULT_ERROR; - } - return RADIO_RESULT_OK; -} -/*---------------------------------------------------------------------------*/ -PROCESS(aducrf101_rf_process, "ADuCRF101 RF driver"); -/*---------------------------------------------------------------------------*/ -/** Turn the radio on. */ -static int -on(void) -{ - if(radio_is_on) { - return 1; - } - - /* Power radio on */ - if(RadioInit(base_config) != RIE_Success) { - return 0; - } - - /* Ensure channel and power are set */ - if(_set_channel(current_channel) != RADIO_RESULT_OK) { - return 0; - } - if(_set_power(current_power) != RADIO_RESULT_OK) { - return 0; - } - - /* Enter receive mode */ - RadioRxPacketVariableLen(); - - radio_is_on = 1; - return 1; -} -/*---------------------------------------------------------------------------*/ -/** Turn the radio off. */ -static int -off(void) -{ - if(!radio_is_on) { - return 1; - } - if(RadioPowerOff() != RIE_Success) { - return 0; - } - radio_is_on = 0; - return 1; -} -/*---------------------------------------------------------------------------*/ -static int -init(void) -{ - off(); - on(); - process_start(&aducrf101_rf_process, NULL); - return 1; -} -/*---------------------------------------------------------------------------*/ -/** Prepare the radio with a packet to be sent. */ -static int -prepare(const void *payload, unsigned short payload_len) -{ - /* Truncate long packets */ - if(payload_len > MAX_PACKET_LEN) { - payload_len = MAX_PACKET_LEN; - } - memcpy(tx_buf, payload, payload_len); - return 0; -} -/*---------------------------------------------------------------------------*/ -/** Send the packet that has previously been prepared. */ -static int -transmit(unsigned short transmit_len) -{ - if(!radio_is_on) - return RADIO_TX_ERR; - - /* Transmit the packet */ - if(transmit_len > MAX_PACKET_LEN) { - transmit_len = MAX_PACKET_LEN; - } - if(RadioTxPacketVariableLen(transmit_len, tx_buf) != RIE_Success) { - return RADIO_TX_ERR; - } - while(!RadioTxPacketComplete()) - continue; - - /* Enter receive mode immediately after transmitting a packet */ - RadioRxPacketVariableLen(); - - return RADIO_TX_OK; -} -/*---------------------------------------------------------------------------*/ -/** Prepare & transmit a packet. */ -static int -send(const void *payload, unsigned short payload_len) -{ - prepare(payload, payload_len); - return transmit(payload_len); -} -/*---------------------------------------------------------------------------*/ -/** Read a received packet into a buffer. */ -static int -read(void *buf, unsigned short buf_len) -{ - uint8_t packet_len; - int8_t rssi; - - if(!radio_is_on) - return 0; - - if(buf_len > MAX_PACKET_LEN) { - buf_len = MAX_PACKET_LEN; - } - - /* Read already-received packet */ - if(RadioRxPacketRead(buf_len, &packet_len, buf, &rssi) != RIE_Success) { - return 0; - } - - if(packet_len > buf_len) { - packet_len = buf_len; - } - - /* Re-enter receive mode immediately after receiving a packet */ - RadioRxPacketVariableLen(); - - return packet_len; -} -/*---------------------------------------------------------------------------*/ -/** Perform a Clear-Channel Assessment (CCA) to find out if there is - a packet in the air or not. */ -static int -channel_clear(void) -{ - /* Not implemented; assume clear */ - return 1; -} -/*---------------------------------------------------------------------------*/ -/** Check if the radio driver is currently receiving a packet */ -static int -receiving_packet(void) -{ - /* Not implemented; assume no. */ - return 0; -} -/*---------------------------------------------------------------------------*/ -/** Check if the radio driver has just received a packet */ -static int -pending_packet(void) -{ - if(RadioRxPacketAvailable()) { - return 1; - } - return 0; -} -/*---------------------------------------------------------------------------*/ -/** Get a radio parameter value. */ -static radio_result_t -get_value(radio_param_t param, radio_value_t *value) -{ - if(!value) { - return RADIO_RESULT_INVALID_VALUE; - } - - switch(param) { - case RADIO_PARAM_RSSI: - { - int8_t dbm; - if(!radio_is_on || RadioRadioGetRSSI(&dbm) != RIE_Success) { - return RADIO_RESULT_ERROR; - } - *value = dbm; - return RADIO_RESULT_OK; - } - - case RADIO_PARAM_CHANNEL: - *value = current_channel; - return RADIO_RESULT_OK; - case RADIO_CONST_CHANNEL_MIN: - *value = MIN_CHANNEL; - return RADIO_RESULT_OK; - case RADIO_CONST_CHANNEL_MAX: - *value = MAX_CHANNEL; - return RADIO_RESULT_OK; - - case RADIO_PARAM_TXPOWER: - *value = current_power; - return RADIO_RESULT_OK; - case RADIO_CONST_TXPOWER_MIN: - *value = MIN_POWER; - return RADIO_RESULT_OK; - case RADIO_CONST_TXPOWER_MAX: - *value = MAX_POWER; - return RADIO_RESULT_OK; - - default: - return RADIO_RESULT_NOT_SUPPORTED; - } -} -/*---------------------------------------------------------------------------*/ -/** Set a radio parameter value. */ -static radio_result_t -set_value(radio_param_t param, radio_value_t value) -{ - switch(param) { - case RADIO_PARAM_CHANNEL: - return _set_channel(value); - - case RADIO_PARAM_TXPOWER: - return _set_power(value); - - default: - return RADIO_RESULT_NOT_SUPPORTED; - } -} -/*---------------------------------------------------------------------------*/ -/** - * Get a radio parameter object. The argument 'dest' must point to a - * memory area of at least 'size' bytes, and this memory area will - * contain the parameter object if the function succeeds. - */ -static radio_result_t -get_object(radio_param_t param, void *dest, size_t size) -{ - return RADIO_RESULT_NOT_SUPPORTED; -} -/*---------------------------------------------------------------------------*/ -/** - * Set a radio parameter object. The memory area referred to by the - * argument 'src' will not be accessed after the function returns. - */ -static radio_result_t -set_object(radio_param_t param, const void *src, size_t size) -{ - return RADIO_RESULT_NOT_SUPPORTED; -} -/*---------------------------------------------------------------------------*/ -/** - * \brief Implementation of the ADuCRF101 RF driver process - * - * This process is started by init(). It waits for events triggered - * by packet reception. - */ -PROCESS_THREAD(aducrf101_rf_process, ev, data) -{ - int len; - PROCESS_BEGIN(); - - while(1) { - PROCESS_YIELD_UNTIL(ev == PROCESS_EVENT_POLL); - - packetbuf_clear(); - len = read(packetbuf_dataptr(), PACKETBUF_SIZE); - - if(len > 0) { - packetbuf_set_datalen(len); - - NETSTACK_MAC.input(); - } - } - - PROCESS_END(); -} -/*---------------------------------------------------------------------------*/ -/** - * \brief Trigger function called by ADI radio engine upon packet RX. - */ -void -aducrf101_rx_packet_hook(void) -{ - process_poll(&aducrf101_rf_process); -} -/*---------------------------------------------------------------------------*/ -const struct radio_driver aducrf101_radio_driver = { - .init = init, - .prepare = prepare, - .transmit = transmit, - .send = send, - .read = read, - .channel_clear = channel_clear, - .receiving_packet = receiving_packet, - .pending_packet = pending_packet, - .on = on, - .off = off, - .get_value = get_value, - .set_value = set_value, - .get_object = get_object, - .set_object = set_object, -}; diff --git a/drivers/cpu/arm/aducrf101/dev/uart.c b/drivers/cpu/arm/aducrf101/dev/uart.c deleted file mode 100644 index 569e54fdd..000000000 --- a/drivers/cpu/arm/aducrf101/dev/uart.c +++ /dev/null @@ -1,124 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - * \author Jim Paris - */ - -#include - -static int (*uart_input_handler)(unsigned char c); -static int stdout_enabled; - -void -uart_init(int baud) -{ - /* P1.0 is UARTRXD, P1.1 is UARTTXD */ - pADI_GP1->GPCON &= ~(GP1CON_CON0_MSK | GP1CON_CON1_MSK); - pADI_GP1->GPCON |= GP1CON_CON0_UART0RXD | GP1CON_CON1_UART0TXD; - - /* Set P1.1 as output */ - GP1OEN_OEN1_BBA = 1; - - /* Set baudrate */ - int div = (F_CPU / 32) / baud; - pADI_UART->COMDIV = div; - pADI_UART->COMFBR = 0x8800 | ((((64 * F_CPU) / div) / baud) - 2048); - pADI_UART->COMIEN = 0; - pADI_UART->COMLCR = 3; - - /* Set up RX IRQ */ - pADI_UART->COMIEN = COMIEN_ERBFI_EN; - NVIC_EnableIRQ(UART_IRQn); - __enable_irq(); - - uart_input_handler = NULL; - stdout_enabled = 1; -} -/*---------------------------------------------------------------------------*/ -void -uart_put(unsigned char x) -{ - while(!(pADI_UART->COMLSR & COMLSR_THRE)) - continue; - pADI_UART->COMTX = x; -} -/*---------------------------------------------------------------------------*/ -void -UART_Int_Handler(void) -{ - if(pADI_UART->COMIIR & COMIIR_STA_RXBUFFULL) { - unsigned char x = pADI_UART->COMRX; - if(uart_input_handler) { - uart_input_handler(x); - } - } -} -/*---------------------------------------------------------------------------*/ -void -uart_set_input(int (*input)(unsigned char c)) -{ - uart_input_handler = input; -} -void -uart_enable_stdout(int enabled) -{ - stdout_enabled = enabled; -} -/*---------------------------------------------------------------------------*/ -/* Connect newlib's _write function to the UART. */ -int -_write(int fd, const void *buf, size_t len) -{ - if(stdout_enabled == 0) { - return -1; - } - - if(fd == 1 || fd == 2) { - int n = len; - const unsigned char *p = buf; - while(n--) - uart_put(*p++); - return len; - } - return -1; -} -/*---------------------------------------------------------------------------*/ -#ifdef __ICCARM__ -/* Connect IAR's __write function to the UART. */ -size_t -__write(int fd, const unsigned char *buf, size_t count) -{ - return _write(fd, buf, count); -} -#endif diff --git a/drivers/cpu/arm/aducrf101/dev/uart.h b/drivers/cpu/arm/aducrf101/dev/uart.h deleted file mode 100644 index deaec627c..000000000 --- a/drivers/cpu/arm/aducrf101/dev/uart.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - * \author Jim Paris - */ - -#ifndef UART_H -#define UART_H - -void uart_init(int baud); -void uart_put(unsigned char x); -void uart_set_input(int (*input)(unsigned char c)); - -void uart_enable_stdout(int enabled); - -#endif diff --git a/drivers/cpu/arm/aducrf101/dev/uart0.h b/drivers/cpu/arm/aducrf101/dev/uart0.h deleted file mode 100644 index 2f8670044..000000000 --- a/drivers/cpu/arm/aducrf101/dev/uart0.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - * \author Jim Paris - * - * \file - * This file exists only because some examples rely on it. - */ - -#ifndef UART1_H -#define UART1_H - -#include "dev/uart.h" -#undef BAUD2UBR -#define BAUD2UBR(x) (x) -#define uart1_set_input(f) uart_set_input(f) - -#endif /* UART1_H */ diff --git a/drivers/cpu/arm/aducrf101/dev/uart1.h b/drivers/cpu/arm/aducrf101/dev/uart1.h deleted file mode 100644 index 6b7ca27df..000000000 --- a/drivers/cpu/arm/aducrf101/dev/uart1.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - * \author Jim Paris - * - * \file - * This file exists only because some examples rely on it. - */ - -#ifndef UART0_H -#define UART0_H - -#include "dev/uart.h" -#undef BAUD2UBR -#define BAUD2UBR(x) (x) -#define uart0_set_input(f) uart_set_input(f) - -#endif /* UART0_H */ diff --git a/drivers/cpu/arm/aducrf101/dev/watchdog.c b/drivers/cpu/arm/aducrf101/dev/watchdog.c deleted file mode 100644 index 3c5cb4e49..000000000 --- a/drivers/cpu/arm/aducrf101/dev/watchdog.c +++ /dev/null @@ -1,67 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - * \author Jim Paris - */ - -#include -#include - -void -watchdog_init(void) -{ - /* Start disabled. */ - T3CON_ENABLE_BBA = 0; -} -/*---------------------------------------------------------------------------*/ -void -watchdog_start(void) -{ - /* 32 second timeout. This also locks the watchdog configuration. */ - pADI_WDT->T3CON = 0x00E9; - pADI_WDT->T3LD = 0x1000; - pADI_WDT->T3VAL = 0x1000; -} -/*---------------------------------------------------------------------------*/ -void -watchdog_stop(void) -{ - /* Not possible to stop, once enabled */ -} -/*---------------------------------------------------------------------------*/ -void -watchdog_periodic(void) -{ - pADI_WDT->T3CLRI = 0xcccc; -} diff --git a/drivers/cpu/arm/aducrf101/mtarch.h b/drivers/cpu/arm/aducrf101/mtarch.h deleted file mode 100644 index e968158c0..000000000 --- a/drivers/cpu/arm/aducrf101/mtarch.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - * \author Jim Paris - */ - -#ifndef MTARCH_H_ -#define MTARCH_H_ - -/* Multithreading is currently unimplemented for ARM Cortex-M3 */ - -struct mtarch_thread { - short mt_thread; -}; - -#endif /* MTARCH_H_ */ diff --git a/drivers/cpu/arm/aducrf101/rtimer-arch.c b/drivers/cpu/arm/aducrf101/rtimer-arch.c deleted file mode 100644 index 4f6b3caa3..000000000 --- a/drivers/cpu/arm/aducrf101/rtimer-arch.c +++ /dev/null @@ -1,138 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - * \author Jim Paris - */ - -#include -#include "rtimer-arch.h" -#include "aducrf101-contiki.h" - -/* rtimer on the ADuCRF101 is implemented with the "wakeup" timer. - (timer 2). It should be clocked from an external crystal, - but if that doesn't seem to be present, this code will select the - imprecise internal 32.768 KHz oscillator instead. */ - -static void -_timer2_enable(int enable) -{ - T2CON_ENABLE_BBA = enable; - clock_time_t now = clock_time(); - while(T2STA_CON_BBA) { - /* Synchronizing settings may fail if the chosen clock isn't running; - wait no more than 1ms for it */ - if((clock_time() - now) > (CLOCK_SECOND / 1000)) { - break; - } - } -} -static uint32_t -_timer2_val(void) -{ - /* This is atomic because the FREEZE bit is set in T2CON. */ - uint32_t now; - now = pADI_WUT->T2VAL0; - now |= pADI_WUT->T2VAL1 << 16; - return now; -} -static uint32_t -_timer2_measure_freq(void) -{ - const int test_usec = 10000; - uint32_t now = _timer2_val(); - clock_delay_usec(test_usec); - return (_timer2_val() - now) * (1000000 / test_usec); -} -void -rtimer_arch_init(void) -{ - uint32_t freq; - const char *timer = "LFXTAL"; - - _timer2_enable(0); - pADI_WUT->T2CON = T2CON_PRE_DIV1 | T2CON_MOD_FREERUN | T2CON_FREEZE_EN | - T2CON_WUEN_EN; - - /* Try 32.768 KHz crystal */ - pADI_WUT->T2CON |= T2CON_CLK_LFXTAL; - _timer2_enable(1); - freq = _timer2_measure_freq(); - - if(freq < 20000 || freq > 40000) { - /* No good; use 32.768 KHz internal oscillator */ - _timer2_enable(0); - pADI_WUT->T2CON &= ~T2CON_CLK_MSK; - pADI_WUT->T2CON |= T2CON_CLK_LFOSC; - _timer2_enable(1); - freq = _timer2_measure_freq(); - timer = "LFOSC"; - } - - printf("Using %s for rtimer (%ld Hz)\n", timer, freq); - - /* Enable interrupt in NVIC, but disable in WUT for now. */ - pADI_WUT->T2IEN = 0; - NVIC_EnableIRQ(WUT_IRQn); -} -rtimer_clock_t -rtimer_arch_now(void) -{ - /* This is atomic because the FREEZE bit is set in T2CON. */ - return _timer2_val(); -} -void -rtimer_arch_schedule(rtimer_clock_t t) -{ - uint32_t now = _timer2_val(); - - /* Minimum of 5 wakeup timer ticks */ - if((int32_t)(t - now) < 5) { - t = now + 5; - } - - /* Set T2WUFB to match at target time */ - T2IEN_WUFB_BBA = 0; - pADI_WUT->T2WUFB0 = (t & 0xffff); - pADI_WUT->T2WUFB1 = (t >> 16); - T2IEN_WUFB_BBA = 1; -} -void -WakeUp_Int_Handler(void) -{ - /* clear interrupt */ - T2CLRI_WUFB_BBA = 1; - /* disable T2WUFB match */ - T2IEN_WUFB_BBA = 0; - rtimer_run_next(); -} diff --git a/drivers/cpu/arm/aducrf101/rtimer-arch.h b/drivers/cpu/arm/aducrf101/rtimer-arch.h deleted file mode 100644 index ec28dcf7d..000000000 --- a/drivers/cpu/arm/aducrf101/rtimer-arch.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - * \author Jim Paris - */ - -#ifndef __RTIMER_ARCH_H__ -#define __RTIMER_ARCH_H__ - -#include - -#define RTIMER_ARCH_SECOND (32768) - -#include "sys/rtimer.h" - -#endif /* __RTIMER_ARCH_H__ */ diff --git a/drivers/cpu/arm/aducrf101/slip-arch.c b/drivers/cpu/arm/aducrf101/slip-arch.c deleted file mode 100644 index 523e30313..000000000 --- a/drivers/cpu/arm/aducrf101/slip-arch.c +++ /dev/null @@ -1,60 +0,0 @@ -/** - * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted (subject to the limitations in the - * disclaimer below) provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * - Neither the name of Analog Devices, Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE - * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** - * \author Jim Paris - */ - -#include - -#include "contiki.h" -#include "dev/slip.h" -#include "uart.h" - -/*---------------------------------------------------------------------------*/ -void -slip_arch_writeb(unsigned char c) -{ - uart_put(c); -} -/*---------------------------------------------------------------------------*/ -/** - * Initalize the RS232 port and the SLIP driver. - * - */ -void -slip_arch_init(unsigned long ubr) -{ - uart_set_input(slip_input_byte); -} -/*---------------------------------------------------------------------------*/ diff --git a/drivers/cpu/arm/at91sam7s/AT91SAM7S-ROM.ld b/drivers/cpu/arm/at91sam7s/AT91SAM7S-ROM.ld deleted file mode 100644 index 05eba5b06..000000000 --- a/drivers/cpu/arm/at91sam7s/AT91SAM7S-ROM.ld +++ /dev/null @@ -1,175 +0,0 @@ -/***********************************************************************/ -/* */ -/* Linker Script File for the AT91SAM7S64 - Code in ROM */ -/* */ -/***********************************************************************/ -/* modified for arm-elf-gcc by Martin Thomas */ -/* extensions: - Section for Functions in RAM, */ -/* Exeception-Vector remapping */ -/* modifications Copyright Martin Thomas 2005 */ -/* */ -/* */ -/* Based on file that has been a part of the uVision/ARM development */ -/* tools, Copyright KEIL ELEKTRONIK GmbH 2002-2004 */ -/***********************************************************************/ - - - -/* Section Definitions */ - -SECTIONS -{ - - /* first section is .text which is used for code */ - -.vectrom : -{ - KEEP(*(.vectrom)) -} >CODE =0 - .text : - { -/* *startup.o (.text) */ /* Startup code */ - KEEP(*(.init)) - *(.text .text.*) - *(.gnu.linkonce.t.*) - *(.glue_7t .glue_7) - KEEP(*(.fini)) - *(.gcc_except_table) - } >CODE =0 - - . = ALIGN(4); - - /* .ctors .dtors are used for c++ constructors/destructors */ - /* added by mthomas, based on an Anglia-Designs example for STR7 */ - - .ctors : - { - PROVIDE(__ctors_start__ = .); - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - } >CODE - - .dtors : - { - PROVIDE(__dtors_start__ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(__dtors_end__ = .); - } >CODE - - /* .rodata section which is used for read-only data (constants) */ - - .rodata : - { - *(.rodata .rodata.*) - *(.gnu.linkonce.r.*) - } >CODE - - . = ALIGN(4); - _etext = . ; - PROVIDE (etext = .); - - .data : AT (_etext) - { - _data = . ; - KEEP(*(.vectram)) /* added by mthomas */ - *(.data) - SORT(CONSTRUCTORS) - . = ALIGN(4); - *(.fastrun) /* "RAM-Functions" */ /* added by mthomas */ - } >DATA - . = ALIGN(4); - - _edata = . ; - PROVIDE (edata = .); - - /* .bss section which is used for uninitialized data */ - - .bss : - { - __bss_start = . ; - __bss_start__ = . ; - *(.bss) - *(COMMON) - } >DATA - . = ALIGN(4); - __bss_end = . ; - __bss_end__ = . ; - _end = .; - PROVIDE (end = .); - - -UND_Stack_Size = 0x00000004; -SVC_Stack_Size = 0x00000200; -ABT_Stack_Size = 0x00000004; -FIQ_Stack_Size = 0x00000100; -IRQ_Stack_Size = 0x00000300; -USR_Stack_Size = 0x00000400; - -Stack_Size = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size; - .stack ORIGIN(DATA) + LENGTH(DATA) - Stack_Size : - { - __stack_start__ = . ; - USR_Stack_Start = . ; - . += USR_Stack_Size; - USR_Stack_End = . ; - IRQ_Stack_Start = . ; - . += IRQ_Stack_Size; - IRQ_Stack_End = . ; - FIQ_Stack_Start = . ; - . += FIQ_Stack_Size; - FIQ_Stack_End = . ; - ABT_Stack_Start = . ; - . += ABT_Stack_Size; - ABT_Stack_End = . ; - SVC_Stack_Start = . ; - . += SVC_Stack_Size; - SVC_Stack_End = . ; - UND_Stack_Start = . ; - . += UND_Stack_Size; - UND_Stack_End = . ; - . = ALIGN(4); - __stack_end__ = . ; - Top_Stack = .; - } >DATA - - - - __heap_start__ = __bss_end__ ; - __heap_end__ = __stack_start__ ; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/drivers/cpu/arm/at91sam7s/AT91SAM7S128-ROM.ld b/drivers/cpu/arm/at91sam7s/AT91SAM7S128-ROM.ld deleted file mode 100644 index 7d1173916..000000000 --- a/drivers/cpu/arm/at91sam7s/AT91SAM7S128-ROM.ld +++ /dev/null @@ -1,9 +0,0 @@ -/* Memory Definitions */ - -MEMORY -{ - CODE (rx) : ORIGIN = 0x00100000, LENGTH = 128K - DATA (rw) : ORIGIN = 0x00200000, LENGTH = 32K -} - -INCLUDE AT91SAM7S-ROM.ld diff --git a/drivers/cpu/arm/at91sam7s/AT91SAM7S128.h b/drivers/cpu/arm/at91sam7s/AT91SAM7S128.h deleted file mode 100644 index 5eb3450ef..000000000 --- a/drivers/cpu/arm/at91sam7s/AT91SAM7S128.h +++ /dev/null @@ -1,2229 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// Copyright (c) 2006, Atmel Corporation -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the disclaimer below. -// -// Atmel's name may not be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S128.h -// Object : AT91SAM7S128 definitions -// Generated : AT91 SW Application Group 07/07/2008 (16:12:49) -// -// CVS Reference : /AT91SAM7S128.pl/1.12/Wed Aug 30 14:08:34 2006// -// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// -// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006// -// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// -// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// -// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// -// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// -// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// -// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7S128_H -#define AT91SAM7S128_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG;// Hardware register definition -#define AT91_CAST(a) (a) -#else -#define AT91_CAST(a) -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[469]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved13[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved14[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved15[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved16[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved17[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved18[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved19[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved20[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; -#else - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; -#else -#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register -#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register -#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register -#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register -#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register -#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register -#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register -#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register -#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register -#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register -#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register -#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register -#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register -#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register -#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) -#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register -#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register -#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register - -#endif -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; -#else -#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register -#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register -#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register -#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register -#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register -#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register -#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register -#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register -#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register -#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register - -#endif -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; -#else -#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register -#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register -#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register -#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register -#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register -#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register -#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register -#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register -#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register -#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register -#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register -#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register - -#endif -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; -#else -#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register -#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register -#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register -#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register -#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr -#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register -#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register -#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register -#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register -#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register -#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register -#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register -#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register -#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register -#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register -#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register -#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register -#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register -#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register -#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register -#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register -#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register -#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register -#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register -#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register -#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register -#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register -#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register -#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; -#else -#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register -#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register -#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register - -#endif -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved4[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; -#else -#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register -#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register -#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register -#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register -#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register -#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register -#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register -#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register -#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register -#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register -#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register -#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register - -#endif -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; -#else -#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register -#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register -#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register - -#endif -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; -#else -#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register -#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register -#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register -#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register - -#endif -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; -#else -#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register -#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register -#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register -#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register - -#endif -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; -#else -#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register -#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register -#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register - -#endif -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; -#else -#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register - -#endif -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; -#else -#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register -#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register -#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register -#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register -#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register -#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register - -#endif -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; -#else -#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register -#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register -#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register -#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register -#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register -#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register -#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register -#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register -#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register - -#endif -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; -#else -#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register -#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register -#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register -#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register -#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register -#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register -#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register -#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register -#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register -#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register -#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 -#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 -#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 -#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 -#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 -#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 -#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 -#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 - -#endif -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; -#else -#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register -#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register -#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister -#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register -#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register -#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register -#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register -#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register -#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register -#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register -#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register -#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register -#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register -#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register - -#endif -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; -#else -#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register -#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register -#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register -#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register -#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register -#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register -#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register -#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register -#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register -#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register -#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register -#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register -#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register -#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register - -#endif -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register - AT91_REG Reserved2[50]; // - AT91_REG TWI_RPR; // Receive Pointer Register - AT91_REG TWI_RCR; // Receive Counter Register - AT91_REG TWI_TPR; // Transmit Pointer Register - AT91_REG TWI_TCR; // Transmit Counter Register - AT91_REG TWI_RNPR; // Receive Next Pointer Register - AT91_REG TWI_RNCR; // Receive Next Counter Register - AT91_REG TWI_TNPR; // Transmit Next Pointer Register - AT91_REG TWI_TNCR; // Transmit Next Counter Register - AT91_REG TWI_PTCR; // PDC Transfer Control Register - AT91_REG TWI_PTSR; // PDC Transfer Status Register -} AT91S_TWI, *AT91PS_TWI; -#else -#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register -#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register -#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register -#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register -#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register -#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register -#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register -#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register -#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register -#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register - -#endif -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) -#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) -#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) -#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; -#else -#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register -#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value -#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A -#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B -#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C -#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register -#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register -#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register -#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register - -#endif -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; -#else -#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register -#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register - -#endif -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; -#else -#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register -#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register -#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register -#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register -#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register -#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved - -#endif -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; -#else -#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register -#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register -#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register -#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register -#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register -#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register -#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register -#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register -#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register - -#endif -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register - AT91_REG Reserved3[4]; // - AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register - AT91_REG Reserved4[5]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; -#else -#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register -#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register -#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register -#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register -#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register -#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register -#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register -#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register -#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register -#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register -#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register -#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register - -#endif -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S128 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S128 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S128 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ( 3) // Reserved -#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_15_Reserved (15) // Reserved -#define AT91C_ID_16_Reserved (16) // Reserved -#define AT91C_ID_17_Reserved (17) // Reserved -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S128 -// ***************************************************************************** -#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S128 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbytes) -// IFLASH -#define AT91C_IFLASH (0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE (0x00020000) // Internal FLASH size in byte (128 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (8) // Internal FLASH Number of Lock Bits: 8 bytes - -#endif diff --git a/drivers/cpu/arm/at91sam7s/AT91SAM7S256.h b/drivers/cpu/arm/at91sam7s/AT91SAM7S256.h deleted file mode 100644 index 812f3fae3..000000000 --- a/drivers/cpu/arm/at91sam7s/AT91SAM7S256.h +++ /dev/null @@ -1,2229 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// Copyright (c) 2006, Atmel Corporation -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the disclaimer below. -// -// Atmel's name may not be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S256.h -// Object : AT91SAM7S256 definitions -// Generated : AT91 SW Application Group 07/07/2008 (16:12:57) -// -// CVS Reference : /AT91SAM7S256.pl/1.12/Wed Aug 30 14:08:39 2006// -// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// -// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006// -// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// -// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// -// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// -// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// -// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// -// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7S256_H -#define AT91SAM7S256_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG;// Hardware register definition -#define AT91_CAST(a) (a) -#else -#define AT91_CAST(a) -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[469]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved13[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved14[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved15[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved16[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved17[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved18[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved19[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved20[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; -#else - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; -#else -#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register -#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register -#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register -#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register -#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register -#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register -#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register -#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register -#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register -#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register -#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register -#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register -#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register -#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register -#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) -#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register -#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register -#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register - -#endif -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; -#else -#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register -#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register -#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register -#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register -#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register -#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register -#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register -#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register -#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register -#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register - -#endif -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; -#else -#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register -#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register -#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register -#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register -#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register -#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register -#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register -#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register -#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register -#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register -#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register -#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register - -#endif -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; -#else -#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register -#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register -#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register -#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register -#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr -#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register -#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register -#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register -#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register -#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register -#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register -#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register -#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register -#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register -#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register -#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register -#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register -#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register -#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register -#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register -#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register -#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register -#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register -#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register -#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register -#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register -#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register -#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register -#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; -#else -#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register -#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register -#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register - -#endif -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved4[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; -#else -#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register -#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register -#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register -#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register -#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register -#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register -#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register -#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register -#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register -#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register -#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register -#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register - -#endif -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; -#else -#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register -#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register -#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register - -#endif -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; -#else -#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register -#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register -#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register -#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register - -#endif -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; -#else -#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register -#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register -#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register -#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register - -#endif -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; -#else -#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register -#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register -#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register - -#endif -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; -#else -#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register - -#endif -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; -#else -#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register -#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register -#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register -#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register -#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register -#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register - -#endif -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; -#else -#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register -#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register -#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register -#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register -#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register -#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register -#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register -#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register -#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register - -#endif -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; -#else -#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register -#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register -#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register -#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register -#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register -#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register -#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register -#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register -#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register -#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register -#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 -#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 -#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 -#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 -#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 -#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 -#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 -#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 - -#endif -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; -#else -#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register -#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register -#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister -#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register -#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register -#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register -#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register -#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register -#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register -#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register -#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register -#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register -#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register -#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register - -#endif -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; -#else -#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register -#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register -#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register -#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register -#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register -#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register -#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register -#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register -#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register -#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register -#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register -#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register -#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register -#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register - -#endif -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register - AT91_REG Reserved2[50]; // - AT91_REG TWI_RPR; // Receive Pointer Register - AT91_REG TWI_RCR; // Receive Counter Register - AT91_REG TWI_TPR; // Transmit Pointer Register - AT91_REG TWI_TCR; // Transmit Counter Register - AT91_REG TWI_RNPR; // Receive Next Pointer Register - AT91_REG TWI_RNCR; // Receive Next Counter Register - AT91_REG TWI_TNPR; // Transmit Next Pointer Register - AT91_REG TWI_TNCR; // Transmit Next Counter Register - AT91_REG TWI_PTCR; // PDC Transfer Control Register - AT91_REG TWI_PTSR; // PDC Transfer Status Register -} AT91S_TWI, *AT91PS_TWI; -#else -#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register -#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register -#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register -#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register -#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register -#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register -#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register -#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register -#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register -#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register - -#endif -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) -#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) -#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) -#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; -#else -#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register -#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value -#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A -#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B -#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C -#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register -#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register -#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register -#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register - -#endif -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; -#else -#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register -#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register - -#endif -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; -#else -#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register -#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register -#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register -#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register -#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register -#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved - -#endif -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; -#else -#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register -#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register -#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register -#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register -#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register -#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register -#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register -#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register -#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register - -#endif -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register - AT91_REG Reserved3[4]; // - AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register - AT91_REG Reserved4[5]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; -#else -#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register -#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register -#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register -#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register -#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register -#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register -#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register -#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register -#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register -#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register -#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register -#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register - -#endif -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S256 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S256 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ( 3) // Reserved -#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_15_Reserved (15) // Reserved -#define AT91C_ID_16_Reserved (16) // Reserved -#define AT91C_ID_17_Reserved (17) // Reserved -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S256 -// ***************************************************************************** -#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S256 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes) -// IFLASH -#define AT91C_IFLASH (0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes - -#endif diff --git a/drivers/cpu/arm/at91sam7s/AT91SAM7S64-ROM.ld b/drivers/cpu/arm/at91sam7s/AT91SAM7S64-ROM.ld deleted file mode 100644 index be0405814..000000000 --- a/drivers/cpu/arm/at91sam7s/AT91SAM7S64-ROM.ld +++ /dev/null @@ -1,9 +0,0 @@ -/* Memory Definitions */ - -MEMORY -{ - CODE (rx) : ORIGIN = 0x00100000, LENGTH = 64K - DATA (rw) : ORIGIN = 0x00200000, LENGTH = 16K -} -INCLUDE AT91SAM7S-ROM.ld - diff --git a/drivers/cpu/arm/at91sam7s/AT91SAM7S64.h b/drivers/cpu/arm/at91sam7s/AT91SAM7S64.h deleted file mode 100644 index af386a7b7..000000000 --- a/drivers/cpu/arm/at91sam7s/AT91SAM7S64.h +++ /dev/null @@ -1,2229 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// Copyright (c) 2006, Atmel Corporation -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the disclaimer below. -// -// Atmel's name may not be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S64.h -// Object : AT91SAM7S64 definitions -// Generated : AT91 SW Application Group 07/07/2008 (16:13:29) -// -// CVS Reference : /AT91SAM7S64.pl/1.23/Wed Aug 30 14:08:51 2006// -// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005// -// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006// -// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// -// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005// -// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006// -// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// -// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// -// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7S64_H -#define AT91SAM7S64_H - -#ifndef __ASSEMBLY__ -typedef volatile unsigned int AT91_REG;// Hardware register definition -#define AT91_CAST(a) (a) -#else -#define AT91_CAST(a) -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[469]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved13[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved14[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved15[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved16[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved17[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved18[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved19[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved20[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; -#else - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; -#else -#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register -#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register -#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register -#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register -#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register -#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register -#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register -#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register -#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register -#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register -#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register -#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register -#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register -#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register -#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) -#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register -#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register -#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register - -#endif -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; -#else -#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register -#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register -#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register -#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register -#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register -#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register -#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register -#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register -#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register -#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register - -#endif -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; -#else -#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register -#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register -#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register -#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register -#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register -#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register -#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register -#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register -#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register -#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register -#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register -#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register - -#endif -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; -#else -#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register -#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register -#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register -#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register -#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr -#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register -#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register -#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register -#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register -#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register -#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register -#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register -#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register -#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register -#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register -#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register -#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register -#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register -#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register -#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register -#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register -#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register -#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register -#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register -#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register -#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register -#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register -#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register -#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; -#else -#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register -#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register -#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register - -#endif -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved4[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; -#else -#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register -#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register -#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register -#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register -#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register -#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register -#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register -#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register -#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register -#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register -#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register -#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register - -#endif -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; -#else -#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register -#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register -#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register - -#endif -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; -#else -#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register -#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register -#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register -#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register - -#endif -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; -#else -#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register -#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register -#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register -#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register - -#endif -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; -#else -#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register -#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register -#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register - -#endif -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; -#else -#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register - -#endif -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; -#else -#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register -#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register -#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register -#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register -#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register -#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register - -#endif -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; -#else -#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register -#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register -#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register -#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register -#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register -#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register -#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register -#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register -#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register - -#endif -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; -#else -#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register -#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register -#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register -#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register -#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register -#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register -#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register -#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register -#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register -#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register -#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 -#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 -#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 -#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 -#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 -#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 -#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 -#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 - -#endif -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; -#else -#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register -#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register -#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister -#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register -#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register -#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register -#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register -#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register -#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register -#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register -#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register -#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register -#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register -#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register - -#endif -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; -#else -#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register -#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register -#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register -#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register -#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register -#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register -#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register -#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register -#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register -#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register -#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register -#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register -#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register -#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register - -#endif -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register - AT91_REG Reserved2[50]; // - AT91_REG TWI_RPR; // Receive Pointer Register - AT91_REG TWI_RCR; // Receive Counter Register - AT91_REG TWI_TPR; // Transmit Pointer Register - AT91_REG TWI_TCR; // Transmit Counter Register - AT91_REG TWI_RNPR; // Receive Next Pointer Register - AT91_REG TWI_RNCR; // Receive Next Counter Register - AT91_REG TWI_TNPR; // Transmit Next Pointer Register - AT91_REG TWI_TNCR; // Transmit Next Counter Register - AT91_REG TWI_PTCR; // PDC Transfer Control Register - AT91_REG TWI_PTSR; // PDC Transfer Status Register -} AT91S_TWI, *AT91PS_TWI; -#else -#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register -#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register -#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register -#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register -#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register -#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register -#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register -#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register -#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register -#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register - -#endif -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) -#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) -#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) -#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; -#else -#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register -#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value -#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A -#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B -#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C -#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register -#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register -#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register -#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register - -#endif -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; -#else -#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register -#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register - -#endif -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; -#else -#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register -#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register -#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register -#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register -#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register -#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved - -#endif -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; -#else -#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register -#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register -#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register -#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register -#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register -#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register -#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register -#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register -#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register - -#endif -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register - AT91_REG Reserved3[4]; // - AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register - AT91_REG Reserved4[5]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; -#else -#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register -#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register -#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register -#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register -#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register -#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register -#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register -#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register -#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register -#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register -#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register -#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register - -#endif -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ( 3) // Reserved -#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_15_Reserved (15) // Reserved -#define AT91C_ID_16_Reserved (16) // Reserved -#define AT91C_ID_17_Reserved (17) // Reserved -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbytes) -// IFLASH -#define AT91C_IFLASH (0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE (0x00010000) // Internal FLASH size in byte (64 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE (128) // Internal FLASH Page Size: 128 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE (4096) // Internal FLASH Lock Region Size: 4 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes - -#endif diff --git a/drivers/cpu/arm/at91sam7s/Makefile.at91sam7s b/drivers/cpu/arm/at91sam7s/Makefile.at91sam7s deleted file mode 100644 index ea6aba0fb..000000000 --- a/drivers/cpu/arm/at91sam7s/Makefile.at91sam7s +++ /dev/null @@ -1,182 +0,0 @@ -# Adapted from Makefile.msp430 - -# Default to AT91SAM7S64 -SUBTARGET = 64 - -### Code common for all ARM CPUs - -CONTIKI_CPU_ARM=$(CONTIKI)/drivers/cpu/arm/ -CONTIKI_CPU_ARM_COMMON=$(CONTIKI_CPU_ARM)/common - -### Defin the CPU directory -CONTIKI_CPU=$(CONTIKI_CPU_ARM)/at91sam7s - -### Define the source files we have in the AT91SAM7S port - -CONTIKI_CPU_DIRS = . ../common/dbg-io ../common/usb - -AT91SAM7S = clock.c debug-uart.c interrupt-utils.c newlib-syscalls.c sys-interrupt.c rtimer-arch.c rtimer-arch-interrupt.c uip-log.c - -SYSAPPS = codeprop-otf.c - - -include $(CONTIKI_CPU_ARM_COMMON)/usb/Makefile.usb - -USB += usb-interrupt.c - -include $(CONTIKI_CPU_ARM_COMMON)/SD-card/Makefile.sdcard - -TARGETLIBS = random.c dbg-printf.c dbg-puts.c dbg-putchar.c dbg-sprintf.c dbg-snprintf.c strformat.c - -CONTIKI_TARGET_SOURCEFILES += $(AT91SAM7S) $(SYSAPPS) \ - $(TARGETLIBS) $(UIPDRIVERS) $(USB) - -CONTIKI_SOURCEFILES += $(CONTIKI_TARGET_SOURCEFILES) - - -THREADS = - -### Compiler definitions -CC = arm-elf-gcc -LD = arm-elf-ld -AS = arm-elf-as -AR = arm-elf-ar -NM = arm-elf-nm -OBJCOPY = arm-elf-objcopy -STRIP = arm-elf-strip - -XSLTPROC=xsltproc - -PROJECT_OBJECTFILES += ${addprefix $(OBJECTDIR)/,$(CONTIKI_TARGET_MAIN:.c=.o)} - -LINKERSCRIPT = $(CONTIKI_CPU)/AT91SAM7S$(SUBTARGET)-ROM.ld - -STARTUP=${addprefix $(OBJECTDIR)/,startup-SAM7S-arm.o} - -# JTAG program upload -OPENOCD = openocd -OPENOCD_DIR = $(CONTIKI_CPU)/openocd/ -OPENOCD_CFG = arm7_wig.cfg - -OPENOCD_FLASH_CFG = arm7_wig_flash.cfg - -# USB program upload -SAMIAM=Sam_I_Am -SAMIAM_TTY=/dev/ttyACM0 - -ARCH_FLAGS= -mcpu=arm7tdmi -mthumb-interwork -THUMB_FLAGS=-mthumb -ARM_FLAGS= - - -CFLAGSNO = -I. -I$(CONTIKI)/core -I$(CONTIKI_CPU) \ - -I$(CONTIKI_CPU)/dbg-io \ - -I$(CONTIKI)/drivers/platform/$(TARGET) \ - ${addprefix -I,$(APPDIRS)} \ - -DWITH_ASCII -DMCK=$(MCK) \ - -Wall $(ARCH_FLAGS) -g -D SUBTARGET=$(SUBTARGET) - -CFLAGS += $(CFLAGSNO) -O -DRUN_AS_SYSTEM -DROM_RUN -LDFLAGS += -L $(CONTIKI_CPU) -T $(LINKERSCRIPT) -nostartfiles - -CDEPFLAGS = $(CFLAGS) -D __MAKING_DEPS__ - - - - -### Setup directory search path for source files - -CUSTOM_RULE_C_TO_OBJECTDIR_O=yes -CUSTOM_RULE_C_TO_O=yes - -%-interrupt.o: %-interrupt.c - $(CC) $(CFLAGS) $(ARM_FLAGS) $< -c - -$(OBJECTDIR)/%-interrupt.o: %-interrupt.c | $(OBJECTDIR) - $(CC) $(CFLAGS) $(ARM_FLAGS) -c $< -o $@ - -%-arm.o: %-arm.c - $(CC) $(CFLAGS) $(ARM_FLAGS) $< -c - -$(OBJECTDIR)/%-arm.o: %-arm.c | $(OBJECTDIR) - $(CC) $(CFLAGS) $(ARM_FLAGS) -c $< -o $@ - -$(OBJECTDIR)/interrupt-utils.o: interrupt-utils.c | $(OBJECTDIR) - $(CC) $(CFLAGS) $(ARM_FLAGS) $< -c -o $@ - -%.o: %.c - $(CC) $(CFLAGS) $(THUMB_FLAGS) $< -c - -$(OBJECTDIR)/%.o: %.c | $(OBJECTDIR) - $(CC) $(CFLAGS) $(THUMB_FLAGS) -c $< -o $@ - -CUSTOM_RULE_S_TO_OBJECTDIR_O = yes -%.o: %.S - $(CC) $(CFLAGS) $(ARM_FLAGS) $< -c - -$(OBJECTDIR)/%.o: %.S | $(OBJECTDIR) - $(CC) $(CFLAGS) $(ARM_FLAGS) $< -c -o $@ - - -CUSTOM_RULE_C_TO_CO=yes - -%.co: %.c - $(CC) $(CFLAGS) $(THUMB_FLAGS) $< -c -o $@ - -CUSTOM_RULE_C_TO_CE=yes - -%.ce: %.o - $(LD) $(LDFLAGS) --relocatable -T $(CONTIKI_CPU)/merge-rodata.ld $< -o $@ - $(STRIP) -K _init -K _fini --strip-unneeded -g -x $@ - -CUSTOM_RULE_LINK=yes - -%-stripped.o: %.c - $(CC) $(CFLAGS) -c $< -o $@ - $(STRIP) --strip-unneeded -g -x $@ - -%-stripped.o: %.o - $(STRIP) --strip-unneeded -g -x -o $@ $< - -%-nosyms.$(TARGET): %.co $(PROJECT_OBJECTFILES) contiki-$(TARGET).a $(STARTUP) - $(CC) $(LDFLAGS) $(CFLAGS) -nostartfiles -o $@ $(filter-out %.a,$^) $(filter %.a,$^) -lc $(filter %.a,$^) - - -%.ihex: %.$(TARGET) - $(OBJCOPY) $^ -O ihex $@ - -%.bin: %.$(TARGET) - $(OBJCOPY) -O binary $< $@ - -ifdef CORE -%.$(TARGET): %.co $(PROJECT_OBJECTFILES) contiki-$(TARGET).a $(STARTUP) - $(CC) $(LDFLAGS) $(CFLAGS) -nostartfiles -o $@ $(filter-out %.a,$^) $(filter %.a,$^) -lc $(filter %.a,$^) - -else -%.$(TARGET): %-nosyms.$(TARGET) - ln -sf $< $@ -endif - -upload_ocd_%: %.bin - # Clear lock bits - $(OPENOCD) -s $(OPENOCD_DIR) -f $(OPENOCD_CFG) -c init -c "halt;mww 0xffffff64 0x5a000004;sleep 250;mww 0xffffff64 0x5a002004; sleep 250;flash probe 0;flash write_bank 0 $< 0x0;reset run;sleep 500;exit" - - - -upload_%: %.ihex - # Clear lock bits - $(SAMIAM) "open $(SAMIAM_TTY) , writew 0xffffff64 5a000004" - $(SAMIAM) "open $(SAMIAM_TTY) , writew 0xffffff64 5a002004" - $(SAMIAM) "open $(SAMIAM_TTY) , flash $< , go" - -ocd_reset: - cd $(CONTIKI_CPU)/openocd;$(OPENOCD) -f $(OPENOCD_CFG) -c init -c reset -c exit - -clean: clean_cpu - -.PHONY: clean_cpu - -clean_cpu: - -rm -rf $(BUILTSRCDIR) - -.PRECIOUS: %-nosyms.$(TARGET) diff --git a/drivers/cpu/arm/at91sam7s/builtins.awk b/drivers/cpu/arm/at91sam7s/builtins.awk deleted file mode 100644 index 367014e38..000000000 --- a/drivers/cpu/arm/at91sam7s/builtins.awk +++ /dev/null @@ -1,4 +0,0 @@ -BEGIN { - builtin["_exit"] = "void _exit()"; - builtin["strlen"] = "unsigned long strlen()"; -} diff --git a/drivers/cpu/arm/at91sam7s/cfs-sdcard-arch.c b/drivers/cpu/arm/at91sam7s/cfs-sdcard-arch.c deleted file mode 100644 index 262646e81..000000000 --- a/drivers/cpu/arm/at91sam7s/cfs-sdcard-arch.c +++ /dev/null @@ -1,183 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include - - - -process_event_t sdcard_inserted_event; - -process_event_t sdcard_removed_event; - -static struct process *event_process = NULL; - - -#define MAX_FDS 4 - -static File file_descriptors[MAX_FDS]; - -static int -find_free_fd() -{ - int fd; - for (fd = 0; fd < MAX_FDS; fd++) { - if (!file_getAttr(&file_descriptors[fd], FILE_STATUS_OPEN)) { - return fd; - } - } - return -1; -} - -static File * -get_file(int fd) -{ - if (!sdcard_ready()) return 0; - if (fd >= MAX_FDS || fd < 0) return NULL; - if (!file_getAttr(&file_descriptors[fd], FILE_STATUS_OPEN)) return NULL; - return &file_descriptors[fd]; -} - -int -cfs_open (const char *name, int flags) -{ - eint8 mode; - int fd; - if (!sdcard_ready()) return -1; - fd = find_free_fd(); - if (fd < 0) return -1; - if (flags == CFS_READ) { - mode = MODE_READ; - } else { - mode = MODE_APPEND; - } - if (file_fopen(&file_descriptors[fd], &sdcard_efs.myFs, - (char*)name, mode) < 0) { - return -1; - } - return fd; -} - -void -cfs_close(int fd) -{ - File *file = get_file(fd); - if (!file) return; - file_fclose(file); - fs_flushFs(efs_sdcard_get_fs()); -} - -int -cfs_read (int fd, void *buf, unsigned int len) -{ - File *file = get_file(fd); - if (!file) return 0; - return file_read(file, len, (euint8*)buf); -} - -int -cfs_write (int fd, const void *buf, unsigned int len) -{ - File *file = get_file(fd); - if (!file) return 0; - return file_write(file, len, (euint8*)buf); -} - -cfs_offset_t -cfs_seek (int fd, cfs_offset_t offset, int whence) -{ - File *file; - if (whence != CFS_SEEK_SET) return -1; - file = get_file(fd); - if (!file) return 0; - if (file_setpos(file, offset) != 0) return -1; - return file->FilePtr; -} - - -/* Cause a compile time error if expr is false */ -#ifdef __GNUC__ -#define COMPILE_TIME_CHECK(expr) \ -(void) (__builtin_choose_expr ((expr), 0, ((void)0))+3) -#else -#define COMPILE_TIME_CHECK(expr) -#endif - -#define MAX_DIR_LISTS 4 -DirList dir_lists[MAX_DIR_LISTS]; - -static DirList * -find_free_dir_list() -{ - unsigned int l; - for(l = 0; l < MAX_DIR_LISTS; l++) { - if (dir_lists[l].fs == NULL) { - return &dir_lists[l]; - } - } - return NULL; -} - -int -cfs_opendir (struct cfs_dir *dirp, const char *name) -{ - DirList *dirs; - COMPILE_TIME_CHECK(sizeof(DirList*) <= sizeof(struct cfs_dir)); - if (!sdcard_ready()) return -1; - dirs = find_free_dir_list(); - if (!dirs) return -1; - if (ls_openDir(dirs, efs_sdcard_get_fs(), (eint8*)name) != 0) { - dirs->fs = NULL; - return -1; - } - *(DirList**)dirp = dirs; - return 0; -} - -int -cfs_readdir (struct cfs_dir *dirp, struct cfs_dirent *dirent) -{ - euint8 *start; - euint8 *end; - char *to = dirent->name; - DirList *dirs = *(DirList**)dirp; - if (!sdcard_ready()) return 1; - if (ls_getNext(dirs) != 0) return 1; - start = dirs->currentEntry.FileName; - end = start + 7; - while(end > start) { - if (*end > ' ') { - end++; - break; - } - end--; - } - while(start < end) { - *to++ = *start++; - } - start = dirs->currentEntry.FileName + 8; - end = start + 3; - if (*start > ' ') { - *to++ = '.'; - *to++ = *start++; - while(start < end && *start > ' ') { - *to++ = *start++; - } - } - *to = '\0'; - if (dirs->currentEntry.Attribute & ATTR_DIRECTORY) { - dirent->size = 0; - } else { - dirent->size = dirs->currentEntry.FileSize; - } - return 0; -} - -void -cfs_closedir (struct cfs_dir *dirp) -{ - (*(DirList**)dirp)->fs = NULL; -} diff --git a/drivers/cpu/arm/at91sam7s/clock.c b/drivers/cpu/arm/at91sam7s/clock.c deleted file mode 100644 index 3febce712..000000000 --- a/drivers/cpu/arm/at91sam7s/clock.c +++ /dev/null @@ -1,74 +0,0 @@ -#include -#include -#include -#include - -#include -#include - -#define PIV ((MCK/CLOCK_SECOND/16)-1) - -static volatile clock_time_t current_clock = 0; -static volatile unsigned long current_seconds = 0; -static unsigned int second_countdown = CLOCK_SECOND; - - -static int pit_handler_func() -{ - if (!(*AT91C_PITC_PISR & AT91C_PITC_PITS)) return 0; /* Check PIT - Interrupt */ - current_clock++; - if(etimer_pending() && etimer_next_expiration_time() <= current_clock) { - etimer_request_poll(); - /* dbg_printf("%d,%d\n", clock_time(),etimer_next_expiration_time ()); */ - - } - if (--second_countdown == 0) { - current_seconds++; - second_countdown = CLOCK_SECOND; - } - (void)*AT91C_PITC_PIVR; - return 1; -} - -static SystemInterruptHandler pit_handler = {NULL, pit_handler_func}; - -void -clock_init() -{ - sys_interrupt_append_handler(&pit_handler); - *AT91C_PITC_PIMR = (AT91C_PITC_PITIEN | /* PIT Interrupt Enable */ - AT91C_PITC_PITEN | /* PIT Enable */ - PIV); - sys_interrupt_enable(); -} - -clock_time_t -clock_time(void) -{ - return current_clock; -} - -/* The inner loop takes 4 cycles. The outer 5+SPIN_COUNT*4. */ - -#define SPIN_TIME 2 /* us */ -#define SPIN_COUNT (((MCK*SPIN_TIME/1000000)-5)/4) - -#ifndef __MAKING_DEPS__ - -void -clock_delay(unsigned int t) -{ -#ifdef __THUMBEL__ - asm volatile("1: mov r1,%2\n2:\tsub r1,#1\n\tbne 2b\n\tsub %0,#1\n\tbne 1b\n":"=l"(t):"0"(t),"l"(SPIN_COUNT)); -#else -#error Must be compiled in thumb mode -#endif -} - -unsigned long -clock_seconds(void) -{ - return current_seconds; -} -#endif /* __MAKING_DEPS__ */ diff --git a/drivers/cpu/arm/at91sam7s/debug-uart.c b/drivers/cpu/arm/at91sam7s/debug-uart.c deleted file mode 100644 index a077e366a..000000000 --- a/drivers/cpu/arm/at91sam7s/debug-uart.c +++ /dev/null @@ -1,196 +0,0 @@ -#include -#include -/* #include */ -#include -#include -#include - -#ifndef DBG_XMIT_BUFFER_LEN -#define DBG_XMIT_BUFFER_LEN 3024 -#endif -#ifndef DBG_RECV_BUFFER_LEN -#define DBG_RECV_BUFFER_LEN 256 -#endif - -static unsigned char dbg_xmit_buffer[DBG_XMIT_BUFFER_LEN]; -static unsigned char dbg_recv_buffer[DBG_RECV_BUFFER_LEN]; -static unsigned int dbg_recv_buffer_len = 0; - -void -dbg_setup_uart() -{ - /* Setup PIO ports */ - *AT91C_PIOA_OER = AT91C_PA10_DTXD; - *AT91C_PIOA_ODR = AT91C_PA9_DRXD; - *AT91C_PIOA_ASR = AT91C_PA10_DTXD | AT91C_PA9_DRXD; - *AT91C_PIOA_PDR = AT91C_PA10_DTXD | AT91C_PA9_DRXD; - - *AT91C_DBGU_MR = AT91C_US_PAR_NONE | AT91C_US_CHMODE_NORMAL; - *AT91C_DBGU_IDR= 0xffffffff; - - *AT91C_DBGU_BRGR = MCK / (115200 * 16); - *AT91C_DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN; - - *AT91C_DBGU_TPR = (unsigned int)dbg_xmit_buffer; - *AT91C_DBGU_TNPR = (unsigned int)dbg_xmit_buffer; - - -} - -static void (*input_func)(const char *inp, unsigned int len) = NULL; - -static int dbg_recv_handler_func() -{ - if (!(*AT91C_DBGU_CSR & AT91C_US_RXRDY)) return 0; - unsigned char c = *AT91C_DBGU_RHR; - /* Leave one byte for '\0' */ - if (dbg_recv_buffer_len < (DBG_RECV_BUFFER_LEN -1)) { - dbg_recv_buffer[dbg_recv_buffer_len++] = c; - } - if (c == '\n') { - dbg_recv_buffer[dbg_recv_buffer_len] = '\0'; - if (input_func) input_func((char*)dbg_recv_buffer, dbg_recv_buffer_len); - dbg_recv_buffer_len = 0; - } - return 1; -} - -static SystemInterruptHandler dbg_recv_handler = {NULL, dbg_recv_handler_func}; - -void -dbg_set_input_handler(void (*handler)(const char *inp, unsigned int len)) -{ - input_func = handler; - sys_interrupt_append_handler(&dbg_recv_handler); - sys_interrupt_enable(); - *AT91C_DBGU_IER = AT91C_US_RXRDY; -} -static volatile unsigned char mutex = 0; - -unsigned int -dbg_send_bytes(const unsigned char *seq, unsigned int len) -{ - unsigned short next_count; - unsigned short current_count; - unsigned short left; - unsigned int save = disableIRQ(); - if (mutex) { - restoreIRQ(save); - return 0; /* Buffer being updated */ - } - mutex = 1; /* Prevent interrupts from messing up the transmission */ - *AT91C_DBGU_PTCR =AT91C_PDC_TXTDIS; /* Stop transmitting */ - while(*AT91C_DBGU_PTSR & AT91C_PDC_TXTEN); /* Wait until stopped */ - next_count = *AT91C_DBGU_TNCR; - current_count = *AT91C_DBGU_TCR; - - left = DBG_XMIT_BUFFER_LEN - next_count - current_count; - if (left > 0) { - if (left < len) len = left; - if (next_count > 0) { - /* Buffer is wrapped */ - memcpy(&dbg_xmit_buffer[next_count], seq, len); - *AT91C_DBGU_TNCR = next_count + len; - } else { - unsigned char *to = ((unsigned char*)*AT91C_DBGU_TPR) + current_count; - left = &dbg_xmit_buffer[DBG_XMIT_BUFFER_LEN] - to; - if (len > left) { - unsigned int wrapped = len - left; - memcpy(to, seq, left); - memcpy(dbg_xmit_buffer, &seq[left], wrapped); - *AT91C_DBGU_TCR = current_count + left; - *AT91C_DBGU_TNCR = wrapped; - } else { - memcpy(to, seq, len); - *AT91C_DBGU_TCR = current_count + len; - } - } - } else { - len = 0; - } - - *AT91C_DBGU_PTCR =AT91C_PDC_TXTEN; /* Restart transmission */ - mutex = 0; - restoreIRQ(save); - return len; -} -static unsigned char dbg_write_overrun = 0; - -void -dbg_putchar(const char ch) -{ - if (dbg_write_overrun) { - if (dbg_send_bytes((const unsigned char*)"^",1) != 1) return; - } - dbg_write_overrun = 0; - if (dbg_send_bytes((const unsigned char*)&ch,1) != 1) { - dbg_write_overrun = 1; - } -} - -void -dbg_blocking_putchar(const char ch) -{ - if (dbg_write_overrun) { - while (dbg_send_bytes((const unsigned char*)"^",1) != 1); - } - dbg_write_overrun = 0; - while (dbg_send_bytes((const unsigned char*)&ch,1) != 1); -} - -#if 0 -static StrFormatResult -dbg_write_cb(void *user_data, const char *data, unsigned int len) -{ - if (dbg_send_bytes((const unsigned char*)data, len) != len) { - dbg_write_overrun = 1; - return STRFORMAT_FAILED; - } - return STRFORMAT_OK; -} - -void -dbg_printf(const char *format, ...) -{ - static const StrFormatContext ctxt = {dbg_write_cb, NULL}; - va_list ap; - if (dbg_write_overrun) { - if (dbg_send_bytes((const unsigned char*)"^",1) != 1) return; - } - dbg_write_overrun = 0; - va_start(ap, format); - format_str_v(&ctxt, format, ap); - va_end(ap); -} - -static StrFormatResult -dbg_write_blocking_cb(void *user_data, const char *data, unsigned int len) -{ - unsigned int left = len; - while(left > 0) { - unsigned int sent = dbg_send_bytes((const unsigned char*)data, left); - left -= sent; - data += sent; - } - return STRFORMAT_OK; -} - -void -dbg_blocking_printf(const char *format, ...) -{ - static const StrFormatContext ctxt = {dbg_write_blocking_cb, NULL}; - va_list ap; - if (dbg_write_overrun) { - while (dbg_send_bytes((const unsigned char*)"^",1) != 1); - } - dbg_write_overrun = 0; - va_start(ap, format); - format_str_v(&ctxt, format, ap); - va_end(ap); -} -#endif -void -dbg_drain() -{ - while(!(*AT91C_DBGU_CSR & AT91C_US_TXBUFE)); -} diff --git a/drivers/cpu/arm/at91sam7s/debug-uart.h b/drivers/cpu/arm/at91sam7s/debug-uart.h deleted file mode 100644 index c322de89e..000000000 --- a/drivers/cpu/arm/at91sam7s/debug-uart.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef DEBUG_UART_H_1V2039076V__ -#define DEBUG_UART_H_1V2039076V__ - - -void -dbg_setup_uart(); - -void -dbg_set_input_handler(void (*handler)(const char *inp, unsigned int len)); - -unsigned int -dbg_send_bytes(const unsigned char *seq, unsigned int len); - -#if 0 -void -dbg_printf(const char *format, ...) - __attribute__ ((__format__ (__printf__, 1,2))); - -void -dbg_blocking_printf(const char *format, ...) - __attribute__ ((__format__ (__printf__, 1,2))); -#endif - -void -dbg_putchar(const char ch); - -void -dbg_blocking_putchar(const char ch); - -void -dbg_drain(); - -#endif /* DEBUG_UART_H_1V2039076V__ */ diff --git a/drivers/cpu/arm/at91sam7s/efs-sdcard-arch.c b/drivers/cpu/arm/at91sam7s/efs-sdcard-arch.c deleted file mode 100644 index d2562cbb2..000000000 --- a/drivers/cpu/arm/at91sam7s/efs-sdcard-arch.c +++ /dev/null @@ -1,195 +0,0 @@ -#include -#include -#include -#include -#include - -#define SPI_SPEED 10000000 /* 10MHz clock*/ - -#define SPI_TRANSFER (AT91C_PA12_MISO | AT91C_PA13_MOSI | AT91C_PA14_SPCK) - -#define SPI_CS (AT91C_PA11_NPCS0) - -static struct process *event_process = NULL; - -static void -init_spi() -{ - *AT91C_SPI_CR = AT91C_SPI_SPIDIS | AT91C_SPI_SWRST; - *AT91C_PMC_PCER = (1 << AT91C_ID_SPI); - *AT91C_PIOA_ASR = SPI_TRANSFER | SPI_CS; - *AT91C_PIOA_PDR = SPI_TRANSFER | SPI_CS; - *AT91C_PIOA_PPUER = AT91C_PA12_MISO | SPI_CS; - *AT91C_SPI_MR = (AT91C_SPI_MSTR | AT91C_SPI_PS_FIXED - | AT91C_SPI_MODFDIS); - - /* It seems necessary to set the clock speed for chip select 0 - even if it's not used. */ - - AT91C_SPI_CSR[0] = - ((((MCK+SPI_SPEED/2)/SPI_SPEED)<<8) | AT91C_SPI_CPOL - | AT91C_SPI_BITS_8 | AT91C_SPI_CSAAT); - *AT91C_SPI_CR = AT91C_SPI_SPIEN; - -} - -void -if_spiInit(hwInterface *iface) -{ - unsigned int i; - *AT91C_PIOA_SODR = AT91C_PA11_NPCS0; - *AT91C_PIOA_PER = AT91C_PA11_NPCS0; - for(i=0;i<20;i++) { - if_spiSend(iface, 0xff); - } - *AT91C_PIOA_PDR = AT91C_PA11_NPCS0; -} - -/* Borrowed from at91_spi.c (c)2006 Martin Thomas */ - -esint8 -if_initInterface(hwInterface* file, eint8* opts) -{ - euint32 sc; - - if_spiInit(file); - if(sd_Init(file)<0) { - DBG((TXT("Card failed to init, breaking up...\n"))); - return(-1); - } - - if(sd_State(file)<0){ - DBG((TXT("Card didn't return the ready state, breaking up...\n") - )); - return(-2); - } - - - - sd_getDriveSize(file, &sc); - file->sectorCount = sc/512; - if( (sc%512) != 0) { - file->sectorCount--; - } - DBG((TXT("Card Capacity is %lu Bytes (%lu Sectors)\n"), sc, file->sectorCount)); - - - return(0); -} - -/* Borrowed from lpc2000_spi.c (c)2005 Martin Thomas */ - -esint8 -if_readBuf(hwInterface* file,euint32 address,euint8* buf) -{ - return(sd_readSector(file,address,buf,512)); -} - -esint8 -if_writeBuf(hwInterface* file,euint32 address,euint8* buf) -{ - return(sd_writeSector(file,address, buf)); -} - -esint8 -if_setPos(hwInterface* file,euint32 address) -{ - return(0); -} - - -euint8 -if_spiSend(hwInterface *iface, euint8 outgoing) -{ - euint8 ingoing; - *AT91C_SPI_TDR = outgoing; - while(!(*AT91C_SPI_SR & AT91C_SPI_RDRF)); - ingoing = *AT91C_SPI_RDR; - /* printf(">%02x <%02x\n", outgoing, ingoing); */ - return ingoing; -} - -static EmbeddedFileSystem sdcard_efs; - -PROCESS(sdcard_process, "SD card process"); - -PROCESS_THREAD(sdcard_process, ev , data) -{ - static struct etimer timer; - PROCESS_BEGIN(); - *AT91C_PIOA_PER = AT91C_PIO_PA20 | AT91C_PIO_PA1; - *AT91C_PIOA_ODR = AT91C_PIO_PA20 | AT91C_PIO_PA1; - - - /* Card not inserted */ - sdcard_efs.myCard.sectorCount = 0; - init_spi(); - - while(1) { - if (!(*AT91C_PIOA_PDSR & AT91C_PA20_IRQ0)) { - if (sdcard_efs.myCard.sectorCount == 0) { - if (efs_init(&sdcard_efs,0) == 0) { - if (event_process) { - process_post(event_process, sdcard_inserted_event, NULL); - } - printf("SD card inserted\n"); - } else { - printf("SD card insertion failed\n"); - } - } - } else { - if (sdcard_efs.myCard.sectorCount != 0) { - /* Card removed */ - fs_umount(&sdcard_efs.myFs); - sdcard_efs.myCard.sectorCount = 0; - if (event_process) { - process_post(event_process, sdcard_removed_event, NULL); - } - printf("SD card removed\n"); - } - } - - etimer_set(&timer, CLOCK_SECOND); - PROCESS_WAIT_EVENT_UNTIL(ev == PROCESS_EVENT_EXIT || - ev == PROCESS_EVENT_TIMER); - if (ev == PROCESS_EVENT_EXIT) break; - if (!(*AT91C_PIOA_PDSR & AT91C_PA20_IRQ0)) { - /* Wait for card to be preperly inserted */ - etimer_set(&timer,CLOCK_SECOND/2); - PROCESS_WAIT_EVENT_UNTIL(ev== PROCESS_EVENT_TIMER); - } - - } - PROCESS_END(); -} - -FileSystem * -efs_sdcard_get_fs() -{ - efs_sdcard_init(); - return &sdcard_efs.myFs; -} - -void -efs_sdcard_init() -{ - static int initialized = 0; - if (!initialized) { - sdcard_inserted_event = process_alloc_event(); - sdcard_removed_event = process_alloc_event(); - process_start(&sdcard_process, NULL); - initialized = 1; - } -} - -int -sdcard_ready() -{ - return sdcard_efs.myCard.sectorCount > 0; -} - -void -sdcard_event_process(struct process *p) -{ - event_process = p; -} diff --git a/drivers/cpu/arm/at91sam7s/interrupt-utils.c b/drivers/cpu/arm/at91sam7s/interrupt-utils.c deleted file mode 100644 index 6ddf5f42f..000000000 --- a/drivers/cpu/arm/at91sam7s/interrupt-utils.c +++ /dev/null @@ -1,84 +0,0 @@ -/****************************************************************************** - * - * $RCSfile: interrupt-utils.c,v $ - * $Revision: 1.2 $ - * - * This module provides the interface routines for setting up and - * controlling the various interrupt modes present on the ARM processor. - * Copyright 2004, R O SoftWare - * No guarantees, warrantees, or promises, implied or otherwise. - * May be used for hobby or commercial purposes provided copyright - * notice remains intact. - * - *****************************************************************************/ -#include "interrupt-utils.h" - -#define IRQ_MASK 0x00000080 -#define FIQ_MASK 0x00000040 -#define INT_MASK (IRQ_MASK | FIQ_MASK) - -static inline unsigned __get_cpsr(void) -{ - unsigned long retval; - asm volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ ); - return retval; -} - -static inline void __set_cpsr(unsigned val) -{ - asm volatile (" msr cpsr_c, %0" : /* no outputs */ : "r" (val) ); -} - -unsigned disableIRQ(void) -{ - unsigned _cpsr; - - _cpsr = __get_cpsr(); - __set_cpsr(_cpsr | IRQ_MASK); - return _cpsr; -} - -unsigned restoreIRQ(unsigned oldCPSR) -{ - unsigned _cpsr; - - _cpsr = __get_cpsr(); - __set_cpsr((_cpsr & ~IRQ_MASK) | (oldCPSR & IRQ_MASK)); - return _cpsr; -} - -unsigned enableIRQ(void) -{ - unsigned _cpsr; - - _cpsr = __get_cpsr(); - __set_cpsr(_cpsr & ~IRQ_MASK); - return _cpsr; -} - -unsigned disableFIQ(void) -{ - unsigned _cpsr; - - _cpsr = __get_cpsr(); - __set_cpsr(_cpsr | FIQ_MASK); - return _cpsr; -} - -unsigned restoreFIQ(unsigned oldCPSR) -{ - unsigned _cpsr; - - _cpsr = __get_cpsr(); - __set_cpsr((_cpsr & ~FIQ_MASK) | (oldCPSR & FIQ_MASK)); - return _cpsr; -} - -unsigned enableFIQ(void) -{ - unsigned _cpsr; - - _cpsr = __get_cpsr(); - __set_cpsr(_cpsr & ~FIQ_MASK); - return _cpsr; -} diff --git a/drivers/cpu/arm/at91sam7s/interrupt-utils.h b/drivers/cpu/arm/at91sam7s/interrupt-utils.h deleted file mode 100644 index 536556827..000000000 --- a/drivers/cpu/arm/at91sam7s/interrupt-utils.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Defines and Macros for Interrupt-Service-Routines - * collected and partly created by - * Martin Thomas - * - * Copyright 2005 M. Thomas - * No guarantees, warrantees, or promises, implied or otherwise. - * May be used for hobby or commercial purposes provided copyright - * notice remains intact. - */ - -#ifndef interrupt_utils_ -#define interrupt_utils_ - -/* - The following defines are usefull for - interrupt service routine declarations. -*/ - -/* - RAMFUNC - Attribute which defines a function to be located - in memory section .fastrun and called via "long calls". - See linker-skript and startup-code to see how the - .fastrun-section is handled. - The definition is not only useful for ISRs but since - ISRs should be executed fast the macro is defined in - this header. -*/ -#define RAMFUNC __attribute__ ((long_call, section (".fastrun"))) - - -/* - INTFUNC - standard attribute for arm-elf-gcc which marks - a function as ISR (for the VIC). Since gcc seems - to produce wrong code if this attribute is used in - thumb/thumb-interwork the attribute should only be - used for "pure ARM-mode" binaries. -*/ -#define INTFUNC __attribute__ ((interrupt("IRQ"))) - - -/* - NACKEDFUNC - gcc will not add any code to a function declared - "nacked". The user has to take care to save registers - and add the needed code for ISR functions. Some - macros for this tasks are provided below. -*/ -#define NACKEDFUNC __attribute__((naked)) - - -/****************************************************************************** - * - * MACRO Name: ISR_STORE() - * - * Description: - * This MACRO is used upon entry to an ISR with interrupt nesting. - * Should be used together with ISR_ENABLE_NEST(). The MACRO - * performs the following steps: - * - * 1 - Save the non-banked registers r0-r12 and lr onto the IRQ stack. - * - *****************************************************************************/ -#define ISR_STORE() asm volatile( \ - "STMDB SP!,{R0-R12,LR}\n" ) - - /****************************************************************************** - * - * MACRO Name: ISR_RESTORE() - * - * Description: - * This MACRO is used upon exit from an ISR with interrupt nesting. - * Should be used together with ISR_DISABLE_NEST(). The MACRO - * performs the following steps: - * - * 1 - Load the non-banked registers r0-r12 and lr from the IRQ stack. - * 2 - Adjusts resume adress - * - *****************************************************************************/ -#define ISR_RESTORE() asm volatile( \ - "LDMIA SP!,{R0-R12,LR}\n" \ - "SUBS R15,R14,#0x0004\n" ) - -/****************************************************************************** - * - * MACRO Name: ISR_ENABLE_NEST() - * - * Description: - * This MACRO is used upon entry from an ISR with interrupt nesting. - * Should be used after ISR_STORE. - * - *****************************************************************************/ - -#define ISR_ENABLE_NEST() asm volatile( \ - "MRS LR, SPSR \n" \ - "STMFD SP!, {LR} \n" \ - "MSR CPSR_c, #0x1f \n" \ - "STMFD SP!, {LR} " ) - -/****************************************************************************** - * - * MACRO Name: ISR_DISABLE_NEST() - * - * Description: - * This MACRO is used upon entry from an ISR with interrupt nesting. - * Should be used before ISR_RESTORE. - * - *****************************************************************************/ - -#define ISR_DISABLE_NEST() asm volatile( \ - "LDMFD SP!, {LR} \n" \ - "MSR CPSR_c, #0x92 \n" \ - "LDMFD SP!, {LR} \n" \ - "MSR SPSR_cxsf, LR \n" ) - - - -/* - * The following marcos are from the file "armVIC.h" by: - * - * Copyright 2004, R O SoftWare - * No guarantees, warrantees, or promises, implied or otherwise. - * May be used for hobby or commercial purposes provided copyright - * notice remains intact. - * - */ - -/****************************************************************************** - * - * MACRO Name: ISR_ENTRY() - * - * Description: - * This MACRO is used upon entry to an ISR. The current version of - * the gcc compiler for ARM does not produce correct code for - * interrupt routines to operate properly with THUMB code. The MACRO - * performs the following steps: - * - * 1 - Adjust address at which execution should resume after servicing - * ISR to compensate for IRQ entry - * 2 - Save the non-banked registers r0-r12 and lr onto the IRQ stack. - * 3 - Get the status of the interrupted program is in SPSR. - * 4 - Push it onto the IRQ stack as well. - * - *****************************************************************************/ -#define ISR_ENTRY() asm volatile(" sub lr, lr,#4\n" \ - " stmfd sp!,{r0-r12,lr}\n" \ - " mrs r1, spsr\n" \ - " stmfd sp!,{r1}") - -/****************************************************************************** - * - * MACRO Name: ISR_EXIT() - * - * Description: - * This MACRO is used to exit an ISR. The current version of the gcc - * compiler for ARM does not produce correct code for interrupt - * routines to operate properly with THUMB code. The MACRO performs - * the following steps: - * - * 1 - Recover SPSR value from stack - * 2 - and restore its value - * 3 - Pop the return address & the saved general registers from - * the IRQ stack & return - * - *****************************************************************************/ -#define ISR_EXIT() asm volatile(" ldmfd sp!,{r1}\n" \ - " msr spsr_c,r1\n" \ - " ldmfd sp!,{r0-r12,pc}^") - -/****************************************************************************** - * - * Function Name: disableIRQ() - * - * Description: - * This function sets the IRQ disable bit in the status register - * - * Calling Sequence: - * void - * - * Returns: - * previous value of CPSR - * - *****************************************************************************/ -unsigned disableIRQ(void); - -/****************************************************************************** - * - * Function Name: enableIRQ() - * - * Description: - * This function clears the IRQ disable bit in the status register - * - * Calling Sequence: - * void - * - * Returns: - * previous value of CPSR - * - *****************************************************************************/ -unsigned enableIRQ(void); - -/****************************************************************************** - * - * Function Name: restoreIRQ() - * - * Description: - * This function restores the IRQ disable bit in the status register - * to the value contained within passed oldCPSR - * - * Calling Sequence: - * void - * - * Returns: - * previous value of CPSR - * - *****************************************************************************/ -unsigned restoreIRQ(unsigned oldCPSR); - -/****************************************************************************** - * - * Function Name: disableFIQ() - * - * Description: - * This function sets the FIQ disable bit in the status register - * - * Calling Sequence: - * void - * - * Returns: - * previous value of CPSR - * - *****************************************************************************/ -unsigned disableFIQ(void); - -/****************************************************************************** - * - * Function Name: enableFIQ() - * - * Description: - * This function clears the FIQ disable bit in the status register - * - * Calling Sequence: - * void - * - * Returns: - * previous value of CPSR - * - *****************************************************************************/ -unsigned enableFIQ(void); - -/****************************************************************************** - * - * Function Name: restoreFIQ() - * - * Description: - * This function restores the FIQ disable bit in the status register - * to the value contained within passed oldCPSR - * - * Calling Sequence: - * void - * - * Returns: - * previous value of CPSR - * - *****************************************************************************/ -unsigned restoreFIQ(unsigned oldCPSR); - - -#endif - diff --git a/drivers/cpu/arm/at91sam7s/io.h b/drivers/cpu/arm/at91sam7s/io.h deleted file mode 100644 index b08ff144b..000000000 --- a/drivers/cpu/arm/at91sam7s/io.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef IO_H_7UTLUP9AG6__ -#define IO_H_7UTLUP9AG6__ - -#include - - -#ifndef BV -#define BV(x) (1<<(x)) -#endif - -int splhigh(void); - -void splx(int saved); - -#endif /* IO_H_7UTLUP9AG6__ */ diff --git a/drivers/cpu/arm/at91sam7s/merge-rodata.ld b/drivers/cpu/arm/at91sam7s/merge-rodata.ld deleted file mode 100644 index a02479537..000000000 --- a/drivers/cpu/arm/at91sam7s/merge-rodata.ld +++ /dev/null @@ -1,8 +0,0 @@ -SECTIONS -{ - .text : - { - *(.text) - *(.rodata.* .rodata) - } -} diff --git a/drivers/cpu/arm/at91sam7s/newlib-syscalls.c b/drivers/cpu/arm/at91sam7s/newlib-syscalls.c deleted file mode 100644 index b765cbb38..000000000 --- a/drivers/cpu/arm/at91sam7s/newlib-syscalls.c +++ /dev/null @@ -1,124 +0,0 @@ -#include -#include -#include -#include - -int -_open(const char *name, int flags, int mode) { - errno = ENOENT; - return -1; -} - -int -_close(int file) -{ - if (file == 1 || file == 2) { - dbg_drain(); - return 0; - } - errno = EBADF; - return -1; -} - -int -isatty(int file) -{ - if (file >= 0 && file <= 2) return 1; - return 0; -} - -int -_read(int file, char *ptr, int len){ - return 0; -} - - - -int -_write(int file, const char *ptr, int len){ - int sent = -1; - if (file == 1 || file == 2) { - sent = dbg_send_bytes((const unsigned char*)ptr, len); - } - return sent; -} - -int -_lseek(int file, int ptr, int dir){ - return 0; -} - -int -_fstat(int file, struct stat *st) { - if (file >= 0 && file <= 2) { - st->st_mode = S_IFCHR; - return 0; - } - errno = EBADF; - return -1; -} - -int -_stat(char *file, struct stat *st) { - errno = ENOENT; - return -1; -} - -caddr_t -_sbrk(int incr) -{ - extern char __heap_start__; /* Defined by the linker */ - extern char __heap_end__; /* Defined by the linker */ - static char *heap_end = &__heap_start__; - char *prev_heap_end; - - prev_heap_end = heap_end; - if (heap_end + incr > &__heap_end__) { - printf("Heap full (requested %d, available %d)\n", - incr, (int)(&__heap_end__ - heap_end)); - errno = ENOMEM; - return (caddr_t)-1; - } - - heap_end += incr; - return (caddr_t) prev_heap_end; -} - -int -fsync(int fd) -{ - if (fd == 1 || fd == 2) { - dbg_drain(); - return 0; - } - if (fd == 0) return 0; - errno = EBADF; - return -1; -} - -void -_exit(int status) -{ - while(1); -} - -void -_abort() -{ - while(1); -} - -void -_kill() -{ - while(1); -} - -pid_t -_getpid(void) -{ - return 1; -} - -const unsigned long -bkpt_instr = 0xe1200070; diff --git a/drivers/cpu/arm/at91sam7s/openocd/AT91SAM7x_init.script b/drivers/cpu/arm/at91sam7s/openocd/AT91SAM7x_init.script deleted file mode 100644 index b21e278fa..000000000 --- a/drivers/cpu/arm/at91sam7s/openocd/AT91SAM7x_init.script +++ /dev/null @@ -1 +0,0 @@ -arm7_9 force_hw_bkpts enable diff --git a/drivers/cpu/arm/at91sam7s/openocd/arm7_wig.cfg b/drivers/cpu/arm/at91sam7s/openocd/arm7_wig.cfg deleted file mode 100644 index d640f83e5..000000000 --- a/drivers/cpu/arm/at91sam7s/openocd/arm7_wig.cfg +++ /dev/null @@ -1,18 +0,0 @@ - - -# Change the default telnet port... -telnet_port 4444 -# GDB connects here -gdb_port 3333 -# GDB can also flash my flash! -gdb_memory_map enable -gdb_flash_program enable - -# Wiggler interface -interface parport -parport_port 0 -parport_cable wiggler -jtag_speed 0 -set CPUTAPID 0x3f0f0f0f -source [find target/sam7s.cfg] - diff --git a/drivers/cpu/arm/at91sam7s/openocd/arm7_wig_flash.cfg b/drivers/cpu/arm/at91sam7s/openocd/arm7_wig_flash.cfg deleted file mode 100644 index 818665fe2..000000000 --- a/drivers/cpu/arm/at91sam7s/openocd/arm7_wig_flash.cfg +++ /dev/null @@ -1,30 +0,0 @@ -#daemon configuration -telnet_port 4444 -gdb_port 3333 - -#interface -interface parport -parport_port 0 -parport_cable wiggler -jtag_speed 0 -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config srst_only - -#jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe - -#target configuration -daemon_startup reset -#target -#target arm7tdmi -target arm7tdmi little run_and_init 0 arm7tdmi_r4 -#target_script 0 reset h2294_init.script -target_script 0 reset openocd_flash -run_and_halt_time 0 30 -working_area 0 0x40000000 0x4000 nobackup - -#flash configuration -#flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14765 calc_checksum -#flash bank cfi 0x80000000 0x400000 2 2 0 -flash bank at91sam7 0 0 0 0 0 diff --git a/drivers/cpu/arm/at91sam7s/openocd/arm7_wig_reset.cfg b/drivers/cpu/arm/at91sam7s/openocd/arm7_wig_reset.cfg deleted file mode 100644 index c21e46067..000000000 --- a/drivers/cpu/arm/at91sam7s/openocd/arm7_wig_reset.cfg +++ /dev/null @@ -1,30 +0,0 @@ -#daemon configuration -telnet_port 4444 -gdb_port 3333 - -#interface -interface parport -parport_port 0 -parport_cable wiggler -jtag_speed 0 -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config srst_only - -#jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe - -#target configuration -daemon_startup reset -#target -#target arm7tdmi -target arm7tdmi little run_and_init 0 arm7tdmi_r4 -#target_script 0 reset h2294_init.script -target_script 0 reset openocd_reset -run_and_halt_time 0 30 -working_area 0 0x40000000 0x4000 nobackup - -#flash configuration -#flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14765 calc_checksum -#flash bank cfi 0x80000000 0x400000 2 2 0 -flash bank at91sam7 0 0 0 0 0 diff --git a/drivers/cpu/arm/at91sam7s/openocd/openocd_flash b/drivers/cpu/arm/at91sam7s/openocd/openocd_flash deleted file mode 100644 index 60ad35f10..000000000 --- a/drivers/cpu/arm/at91sam7s/openocd/openocd_flash +++ /dev/null @@ -1,10 +0,0 @@ -poll -mww 0xffffff64 0x5a000004 -sleep 250 -mww 0xffffff64 0x5a002004 -sleep 250 -flash probe 0 -flash write 0 /tmp/openocd_write.bin 0x0 -reset run -sleep 500 -shutdown diff --git a/drivers/cpu/arm/at91sam7s/openocd/openocd_reset b/drivers/cpu/arm/at91sam7s/openocd/openocd_reset deleted file mode 100644 index 6c138449e..000000000 --- a/drivers/cpu/arm/at91sam7s/openocd/openocd_reset +++ /dev/null @@ -1,4 +0,0 @@ -poll -reset run -sleep 500 -shutdown diff --git a/drivers/cpu/arm/at91sam7s/openocd/target/sam7s.cfg b/drivers/cpu/arm/at91sam7s/openocd/target/sam7s.cfg deleted file mode 100644 index 9b6b68b51..000000000 --- a/drivers/cpu/arm/at91sam7s/openocd/target/sam7s.cfg +++ /dev/null @@ -1,36 +0,0 @@ -# ATMEL sam7s - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME sam7s -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - # force an error till we get a good number - set _CPUTAPID 0xffffffff -} - -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config srst_only - -#jtag scan chain -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -# The target -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi - -$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 - -flash bank at91sam7 0 0 0 0 0 - - diff --git a/drivers/cpu/arm/at91sam7s/pit-interrupt.h b/drivers/cpu/arm/at91sam7s/pit-interrupt.h deleted file mode 100644 index 7cd88cc93..000000000 --- a/drivers/cpu/arm/at91sam7s/pit-interrupt.h +++ /dev/null @@ -1,22 +0,0 @@ -volatile unsigned int pit_count = 0; - -static void NACKEDFUNC ATTR system_int (void) { /* System Interrupt Handler */ - - ISR_ENTRY(); - - if (*AT91C_PITC_PISR & AT91C_PITC_PITS) { /* Check PIT Interrupt */ - pit_count++; - /* - if ((pit_count % 100) == 0) { - unsigned int led_state = (pit_count % 300) / 100; - *AT91C_PIOA_ODSR = ~(1< -#include - -#define DEBUG 1 -#if DEBUG -#include -#define PRINTF(...) printf(__VA_ARGS__) -#else -#define PRINTF(...) -#endif - -/* Here we have a proper stack frame and can use local variables */ -static void rtimer_int_safe() __attribute((noinline)); -static void -rtimer_int_safe() -{ - unsigned int status; - status = RTIMER_ARCH_TIMER_BASE->TC_SR; - if (status & AT91C_TC_CPAS) { - rtimer_run_next(); - } - *AT91C_AIC_EOICR = 0; -} - -void NACKEDFUNC -rtimer_interrupt (void) { - ISR_STORE(); - ISR_ENABLE_NEST(); - rtimer_int_safe(); - ISR_DISABLE_NEST(); - ISR_RESTORE(); -} diff --git a/drivers/cpu/arm/at91sam7s/rtimer-arch-interrupt.h b/drivers/cpu/arm/at91sam7s/rtimer-arch-interrupt.h deleted file mode 100644 index 97ea3671d..000000000 --- a/drivers/cpu/arm/at91sam7s/rtimer-arch-interrupt.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef RTIMER_ARCH_INTERRUPT_H_P0PXG70757__ -#define RTIMER_ARCH_INTERRUPT_H_P0PXG70757__ - -void rtimer_interrupt (void); - -#endif /* RTIMER_ARCH_INTERRUPT_H_P0PXG70757__ */ diff --git a/drivers/cpu/arm/at91sam7s/rtimer-arch.c b/drivers/cpu/arm/at91sam7s/rtimer-arch.c deleted file mode 100644 index 24fe11c08..000000000 --- a/drivers/cpu/arm/at91sam7s/rtimer-arch.c +++ /dev/null @@ -1,49 +0,0 @@ -#include "rtimer-arch.h" -#include -#include "rtimer-arch-interrupt.h" - -#define DEBUG 1 -#if DEBUG -#include -#define PRINTF(...) printf(__VA_ARGS__) -#else -#define PRINTF(...) -#endif - -static rtimer_clock_t offset; - -void -rtimer_arch_init(void) -{ - offset = 0; - RTIMER_ARCH_TIMER_BASE->TC_CMR = - (AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP | AT91C_TC_CLKS_TIMER_DIV5_CLOCK); - RTIMER_ARCH_TIMER_BASE->TC_RA = 0xffff; - RTIMER_ARCH_TIMER_BASE->TC_IER = AT91C_TC_CPAS; - *AT91C_PMC_PCER = (1 << RTIMER_ARCH_TIMER_ID); - AT91C_AIC_SMR[RTIMER_ARCH_TIMER_ID] = - AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE | 6; - AT91C_AIC_SVR[RTIMER_ARCH_TIMER_ID] = (unsigned long)rtimer_interrupt; - *AT91C_AIC_IECR = (1 << RTIMER_ARCH_TIMER_ID); - RTIMER_ARCH_TIMER_BASE->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN; - PRINTF("rtimer_arch_init: Done\n"); -} - -void -rtimer_arch_schedule(rtimer_clock_t t) -{ - RTIMER_ARCH_TIMER_BASE->TC_RA = t + offset; - PRINTF("rtimer_arch_schedule: %d\n",t); -} - -void -rtimer_arch_set(rtimer_clock_t t) -{ - offset = t - RTIMER_ARCH_TIMER_BASE->TC_CV; -} - -rtimer_clock_t -rtimer_arch_now(void) -{ - return RTIMER_ARCH_TIMER_BASE->TC_CV + offset; -} diff --git a/drivers/cpu/arm/at91sam7s/rtimer-arch.h b/drivers/cpu/arm/at91sam7s/rtimer-arch.h deleted file mode 100644 index bacf656e7..000000000 --- a/drivers/cpu/arm/at91sam7s/rtimer-arch.h +++ /dev/null @@ -1,22 +0,0 @@ -/** - * \file - * Header file for the AT91SAM7S-specific rtimer code - * \author - * Simon Berg - */ - -#ifndef RTIMER_ARCH_H_ -#define RTIMER_ARCH_H_ - -#include "sys/rtimer.h" - -#define RTIMER_ARCH_TIMER_ID AT91C_ID_TC1 -#define RTIMER_ARCH_TIMER_BASE AT91C_BASE_TC1 - -#define RTIMER_ARCH_SECOND (MCK/1024) - -void rtimer_arch_set(rtimer_clock_t t); - -rtimer_clock_t rtimer_arch_now(void); - -#endif /* RTIMER_ARCH_H_ */ diff --git a/drivers/cpu/arm/at91sam7s/sdcard-arch.c b/drivers/cpu/arm/at91sam7s/sdcard-arch.c deleted file mode 100644 index 262646e81..000000000 --- a/drivers/cpu/arm/at91sam7s/sdcard-arch.c +++ /dev/null @@ -1,183 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include - - - -process_event_t sdcard_inserted_event; - -process_event_t sdcard_removed_event; - -static struct process *event_process = NULL; - - -#define MAX_FDS 4 - -static File file_descriptors[MAX_FDS]; - -static int -find_free_fd() -{ - int fd; - for (fd = 0; fd < MAX_FDS; fd++) { - if (!file_getAttr(&file_descriptors[fd], FILE_STATUS_OPEN)) { - return fd; - } - } - return -1; -} - -static File * -get_file(int fd) -{ - if (!sdcard_ready()) return 0; - if (fd >= MAX_FDS || fd < 0) return NULL; - if (!file_getAttr(&file_descriptors[fd], FILE_STATUS_OPEN)) return NULL; - return &file_descriptors[fd]; -} - -int -cfs_open (const char *name, int flags) -{ - eint8 mode; - int fd; - if (!sdcard_ready()) return -1; - fd = find_free_fd(); - if (fd < 0) return -1; - if (flags == CFS_READ) { - mode = MODE_READ; - } else { - mode = MODE_APPEND; - } - if (file_fopen(&file_descriptors[fd], &sdcard_efs.myFs, - (char*)name, mode) < 0) { - return -1; - } - return fd; -} - -void -cfs_close(int fd) -{ - File *file = get_file(fd); - if (!file) return; - file_fclose(file); - fs_flushFs(efs_sdcard_get_fs()); -} - -int -cfs_read (int fd, void *buf, unsigned int len) -{ - File *file = get_file(fd); - if (!file) return 0; - return file_read(file, len, (euint8*)buf); -} - -int -cfs_write (int fd, const void *buf, unsigned int len) -{ - File *file = get_file(fd); - if (!file) return 0; - return file_write(file, len, (euint8*)buf); -} - -cfs_offset_t -cfs_seek (int fd, cfs_offset_t offset, int whence) -{ - File *file; - if (whence != CFS_SEEK_SET) return -1; - file = get_file(fd); - if (!file) return 0; - if (file_setpos(file, offset) != 0) return -1; - return file->FilePtr; -} - - -/* Cause a compile time error if expr is false */ -#ifdef __GNUC__ -#define COMPILE_TIME_CHECK(expr) \ -(void) (__builtin_choose_expr ((expr), 0, ((void)0))+3) -#else -#define COMPILE_TIME_CHECK(expr) -#endif - -#define MAX_DIR_LISTS 4 -DirList dir_lists[MAX_DIR_LISTS]; - -static DirList * -find_free_dir_list() -{ - unsigned int l; - for(l = 0; l < MAX_DIR_LISTS; l++) { - if (dir_lists[l].fs == NULL) { - return &dir_lists[l]; - } - } - return NULL; -} - -int -cfs_opendir (struct cfs_dir *dirp, const char *name) -{ - DirList *dirs; - COMPILE_TIME_CHECK(sizeof(DirList*) <= sizeof(struct cfs_dir)); - if (!sdcard_ready()) return -1; - dirs = find_free_dir_list(); - if (!dirs) return -1; - if (ls_openDir(dirs, efs_sdcard_get_fs(), (eint8*)name) != 0) { - dirs->fs = NULL; - return -1; - } - *(DirList**)dirp = dirs; - return 0; -} - -int -cfs_readdir (struct cfs_dir *dirp, struct cfs_dirent *dirent) -{ - euint8 *start; - euint8 *end; - char *to = dirent->name; - DirList *dirs = *(DirList**)dirp; - if (!sdcard_ready()) return 1; - if (ls_getNext(dirs) != 0) return 1; - start = dirs->currentEntry.FileName; - end = start + 7; - while(end > start) { - if (*end > ' ') { - end++; - break; - } - end--; - } - while(start < end) { - *to++ = *start++; - } - start = dirs->currentEntry.FileName + 8; - end = start + 3; - if (*start > ' ') { - *to++ = '.'; - *to++ = *start++; - while(start < end && *start > ' ') { - *to++ = *start++; - } - } - *to = '\0'; - if (dirs->currentEntry.Attribute & ATTR_DIRECTORY) { - dirent->size = 0; - } else { - dirent->size = dirs->currentEntry.FileSize; - } - return 0; -} - -void -cfs_closedir (struct cfs_dir *dirp) -{ - (*(DirList**)dirp)->fs = NULL; -} diff --git a/drivers/cpu/arm/at91sam7s/startup-SAM7S-arm.c b/drivers/cpu/arm/at91sam7s/startup-SAM7S-arm.c deleted file mode 100644 index bb3c5f391..000000000 --- a/drivers/cpu/arm/at91sam7s/startup-SAM7S-arm.c +++ /dev/null @@ -1,233 +0,0 @@ -#include -#include - -#define USED __attribute__((used)) -#define USED_NAKED __attribute__((used,naked)) -#define USED_INT(type) __attribute__((used,interrupt(#type))) -#if MCK > 30000000 -#define FLASH_CYCLES AT91C_MC_FWS_1FWS -#else -#define FLASH_CYCLES AT91C_MC_FWS_0FWS -#endif - -#ifndef MAIN_OSC_FREQ -#define MAIN_OSC_FREQ 18432000 -#endif - -#if MAIN_OSC_FREQ != 18432000 -#error Unsupported main oscilator frequency -#endif - -#if MCK == 23961600 -#define PLL_DIV 5 -#define PLL_MUL 26 -#define PLL_USBDIV_EXP 1 -#define MCK_DIV_EXP 2 -#elif MCK == 47923200 -#define PLL_DIV 5 -#define PLL_MUL 26 -#define PLL_USBDIV_EXP 1 -#define MCK_DIV_EXP 1 -#else -#error "Unsupported main clock frequency" -#endif - -#define PLL_FREQ ((MAIN_OSC_FREQ * PLL_MUL) / PLL_DIV) - -#if PLL_FREQ > 180000000 -#error "PLL frequency too high" -#elif PLL_FREQ < 80000000 -#error "PLL frequency too low" -#endif - -#if PLL_FREQ > 155000000 -#define PLL_RANGE AT91C_CKGR_OUT_2 -#else -#define PLL_RANGE AT91C_CKGR_OUT_0 -#endif - -#if PLL_USBDIV > 2 -#error "PLL frequency too high for USB" -#endif - -#define USB_FREQ (PLL_FREQ / (1< 48120000 || USB_FREQ < 47880000 -#warning "USB frequency outside limits" -#endif - -#if MCK * (1< -#include -#include - -#define ATTR - -#ifndef NULL -#define NULL 0 -#endif - - -static SystemInterruptHandler *handlers = NULL; - -static void -system_int_safe (void) __attribute__((noinline)); - -static void -system_int_safe (void) -{ - SystemInterruptHandler *h; - h = handlers; - while (h) { - if (h->handler()) break; - h = h->next; - } -} - -static void NACKEDFUNC ATTR -system_int (void) /* System Interrupt Handler */ -{ - ISR_ENTRY(); - system_int_safe(); - *AT91C_AIC_EOICR = 0; /* End of Interrupt */ - ISR_EXIT(); -} - -static unsigned int enabled = 0; /* Number of times the system - interrupt has been enabled */ - -#define DIS_INT *AT91C_AIC_IDCR = (1 << AT91C_ID_SYS) -#define EN_INT if (enabled > 0) *AT91C_AIC_IECR = (1 << AT91C_ID_SYS) - -void -sys_interrupt_enable() -{ - if (enabled++ == 0) { - /* Level trigged at priority 5 */ - AT91C_AIC_SMR[AT91C_ID_SYS] = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | 5; - /* Interrupt vector */ - AT91C_AIC_SVR[AT91C_ID_SYS] = (unsigned long) system_int; - /* Enable */ - EN_INT; - } -} - - -void -sys_interrupt_disable() -{ - if (--enabled == 0) { - DIS_INT; - } -} - -void -sys_interrupt_append_handler(SystemInterruptHandler *handler) -{ - SystemInterruptHandler **h = &handlers; - while(*h) { - h = &(*h)->next; - } - DIS_INT; - *h = handler; - handler->next = NULL; - EN_INT; -} - -void -sys_interrupt_prepend_handler(SystemInterruptHandler *handler) -{ - DIS_INT; - handler->next = handlers; - handlers = handler; - EN_INT; -} - -void -sys_interrupt_remove_handler(SystemInterruptHandler *handler) -{ - SystemInterruptHandler **h = &handlers; - while(*h) { - if (*h == handler) { - DIS_INT; - *h = handler->next; - EN_INT; - break; - } - h = &(*h)->next; - } -} diff --git a/drivers/cpu/arm/at91sam7s/sys-interrupt.h b/drivers/cpu/arm/at91sam7s/sys-interrupt.h deleted file mode 100644 index 738d336b1..000000000 --- a/drivers/cpu/arm/at91sam7s/sys-interrupt.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef SYS_INTERRUPT_H_QIHZ66NP8K__ -#define SYS_INTERRUPT_H_QIHZ66NP8K__ - - -/* Returns true if it handled an activbe interrupt */ -typedef int (*SystemInterruptFunc)(); - -typedef struct _SystemInterruptHandler SystemInterruptHandler; -struct _SystemInterruptHandler -{ - SystemInterruptHandler *next; - SystemInterruptFunc handler; -}; - - -void -sys_interrupt_enable(); - -void -sys_interrupt_disable(); - -void -sys_interrupt_append_handler(SystemInterruptHandler *handler); - -void -sys_interrupt_prepend_handler(SystemInterruptHandler *handler); - -void -sys_interrupt_remove_handler(SystemInterruptHandler *handler); - -#endif /* SYS_INTERRUPT_H_QIHZ66NP8K__ */ diff --git a/drivers/cpu/arm/at91sam7s/uip-log.c b/drivers/cpu/arm/at91sam7s/uip-log.c deleted file mode 100644 index 9a8044bf2..000000000 --- a/drivers/cpu/arm/at91sam7s/uip-log.c +++ /dev/null @@ -1,6 +0,0 @@ -#include - -void uip_log(char *msg) -{ - printf("uip: %s\n", msg); -} diff --git a/drivers/cpu/arm/at91sam7s/usb-arch.c b/drivers/cpu/arm/at91sam7s/usb-arch.c deleted file mode 100644 index da733a2f1..000000000 --- a/drivers/cpu/arm/at91sam7s/usb-arch.c +++ /dev/null @@ -1,878 +0,0 @@ -#include -#include -#include -#include -#include - - -/* #define DEBUG */ -#ifdef DEBUG -#define PRINTF(...) printf(__VA_ARGS__) -#else -#define PRINTF(...) -#endif - -#define USB_PULLUP_PIN AT91C_PIO_PA16 - -#ifndef AT91C_UDP_STALLSENT -#define AT91C_UDP_STALLSENT AT91C_UDP_ISOERROR -#endif - -/* Bits that won't effect the state if they're written at a specific level. - */ -/* Bits that should be written as 1 */ -#define NO_EFFECT_BITS (AT91C_UDP_TXCOMP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RXSETUP \ - | AT91C_UDP_ISOERROR | AT91C_UDP_RX_DATA_BK1) -/* Also includes bits that should be written as 0 */ -#define NO_EFFECT_MASK (NO_EFFECT_BITS | AT91C_UDP_TXPKTRDY) - -#define RXBYTECNT(s) (((s)>>16)&0x7ff) - - -static inline void -udp_set_ep_ctrl_flags(AT91_REG *reg, unsigned int flags, - unsigned int write_mask, unsigned int check_mask) -{ - while ( (*reg & check_mask) != (flags & check_mask)) { - *reg = (*reg & ~write_mask) | flags; - } -} - -#define UDP_SET_EP_CTRL_FLAGS(reg, flags, mask) \ -udp_set_ep_ctrl_flags((reg), \ - (NO_EFFECT_BITS & ~(mask)) | ((flags) & (mask)), (mask) | NO_EFFECT_MASK,\ - (mask)) - - -#define USB_DISABLE_INT *AT91C_AIC_IDCR = (1 << AT91C_ID_UDP) -#define USB_ENABLE_INT *AT91C_AIC_IECR = (1 << AT91C_ID_UDP) - -#define USB_DISABLE_EP_INT(hw_ep) *AT91C_UDP_IDR = (1 << (hw_ep)) -#define USB_ENABLE_EP_INT(hw_ep) *AT91C_UDP_IER = (1 << (hw_ep)) - -#if CTRL_EP_SIZE > 8 -#error Control endpoint size too big -#endif - -#if USB_EP1_SIZE > 64 -#error Endpoint 1 size too big -#endif - -#if USB_EP2_SIZE > 64 -#error Endpoint 2 size too big -#endif - -#if USB_EP3_SIZE > 64 -#error Endpoint 3 size too big -#endif - -static const uint16_t ep_xfer_size[8] = - { - CTRL_EP_SIZE, - USB_EP1_SIZE, - USB_EP2_SIZE, - USB_EP3_SIZE - }; - -#define USB_EP_XFER_SIZE(ep) ep_xfer_size[ep] - -typedef struct _USBEndpoint USBEndpoint; -struct _USBEndpoint -{ - uint16_t status; - uint8_t addr; - uint8_t flags; - USBBuffer *buffer; /* NULL if no current buffer */ - struct process *event_process; - unsigned int events; - uint16_t xfer_size; -}; - -#define USB_EP_FLAGS_TYPE_MASK 0x03 -#define USB_EP_FLAGS_TYPE_BULK 0x00 -#define USB_EP_FLAGS_TYPE_CONTROL 0x01 -#define USB_EP_FLAGS_TYPE_ISO 0x02 -#define USB_EP_FLAGS_TYPE_INTERRUPT 0x03 - -#define EP_TYPE(ep) ((ep)->flags & USB_EP_FLAGS_TYPE_MASK) -#define IS_EP_TYPE(ep, type) (EP_TYPE(ep) == (type)) -#define IS_CONTROL_EP(ep) IS_EP_TYPE(ep, USB_EP_FLAGS_TYPE_CONTROL) -#define IS_BULK_EP(ep) IS_EP_TYPE(ep, USB_EP_FLAGS_TYPE_BULK) - -#define USB_EP_FLAGS_ENABLED 0x04 - -/* A packet has been received but the data is still in hardware buffer */ -#define USB_EP_FLAGS_RECV_PENDING 0x08 -/* The pending packet is a SETUP packet */ -#define USB_EP_FLAGS_SETUP_PENDING 0x10 - -/* The data in the hardware buffer is being transmitted */ -#define USB_EP_FLAGS_TRANSMITTING 0x20 - -/* The receiver is waiting for a packet */ -#define USB_EP_FLAGS_RECEIVING 0x40 - -/* For bulk endpoints. Both buffers are busy are in use, either by - hardware or software. */ -#define USB_EP_FLAGS_DOUBLE 0x80 - -/* The next packet received should be read from bank 1 if possible */ -#define USB_EP_FLAGS_BANK_1_RECV_NEXT 0x10 - -/* States for double buffered reception: - -Packets being received 0 1 2 1 0 0 -Packets pending 0 0 0 1 2 1 - -RECVING 0 1 1 1 0 0 -RECV_PENDING 0 0 0 1 1 1 -DOUBLE 0 0 1 0 1 0 -*/ - -/* States for double buffered transmission: - -Packets being transmitted 0 1 2 - -TRANSMITTING 0 1 1 -DOUBLE 0 0 1 -*/ - -/* Index in endpoint array */ -#define EP_INDEX(addr) ((addr) & 0x7f) - -/* Get address of endpoint struct */ -#define EP_STRUCT(addr) &usb_endpoints[EP_INDEX(addr)]; - -/* Number of hardware endpoint */ -#define EP_HW_NUM(addr) ((addr) & 0x7f) - - -static USBEndpoint usb_endpoints[USB_MAX_ENDPOINTS]; -struct process *event_process = 0; -volatile unsigned int events = 0; - -static void -notify_process(unsigned int e) -{ - events |= e; - if (event_process) { - process_poll(event_process); - } -} - -static void -notify_ep_process(USBEndpoint *ep, unsigned int e) -{ - ep->events |= e; - if (ep->event_process) { - process_poll(ep->event_process); - } -} - - -static void -usb_arch_reset(void) -{ - unsigned int e; - for (e = 0; e < USB_MAX_ENDPOINTS; e++) { - if (usb_endpoints[e].flags &USB_EP_FLAGS_ENABLED) { - USBBuffer *buffer = usb_endpoints[e].buffer; - usb_endpoints[e].flags = 0; - usb_disable_endpoint(e); - while(buffer) { - buffer->flags &= ~USB_BUFFER_SUBMITTED; - buffer = buffer->next; - } - } - } - usb_arch_setup_control_endpoint(0); - -} - -void -usb_arch_setup(void) -{ - unsigned int i; - /* Assume 96MHz PLL frequency */ - *AT91C_CKGR_PLLR = ((*AT91C_CKGR_PLLR & ~AT91C_CKGR_USBDIV) - | AT91C_CKGR_USBDIV_1); - /* Enable 48MHz USB clock */ - *AT91C_PMC_SCER = AT91C_PMC_UDP; - /* Enable USB main clock */ - *AT91C_PMC_PCER = (1 << AT91C_ID_UDP); - - /* Enable pullup */ - *AT91C_PIOA_PER = USB_PULLUP_PIN; - *AT91C_PIOA_OER = USB_PULLUP_PIN; - *AT91C_PIOA_CODR = USB_PULLUP_PIN; - - for(i = 0; i < USB_MAX_ENDPOINTS; i++) { - usb_endpoints[i].flags = 0; - usb_endpoints[i].event_process = 0; - } - - usb_arch_reset(); - /* Enable usb_interrupt */ - AT91C_AIC_SMR[AT91C_ID_UDP] = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | 4; - AT91C_AIC_SVR[AT91C_ID_UDP] = (unsigned long) usb_int; - *AT91C_AIC_IECR = (1 << AT91C_ID_UDP); -} - - -static void -usb_arch_setup_endpoint(unsigned char addr, unsigned int hw_type) -{ - unsigned int ei = EP_HW_NUM(addr); - USBEndpoint *ep = EP_STRUCT(addr); - ep->status = 0; - ep->flags = USB_EP_FLAGS_ENABLED; - ep->buffer = 0; - ep->addr = addr; - ep->events = 0; - ep->xfer_size = 0; - - *AT91C_UDP_IDR = 1<flags |= USB_EP_FLAGS_TYPE_CONTROL; - ep->xfer_size = ep_xfer_size[ei]; - -} - -void -usb_arch_setup_bulk_endpoint(unsigned char addr) -{ - unsigned int ei = EP_HW_NUM(addr); - USBEndpoint *ep = EP_STRUCT(addr); - usb_arch_setup_endpoint(addr, ((addr & 0x80) - ? AT91C_UDP_EPTYPE_BULK_IN - : AT91C_UDP_EPTYPE_BULK_OUT)); - ep->flags |= USB_EP_FLAGS_TYPE_BULK; - ep->xfer_size = ep_xfer_size[ei]; -} - -void -usb_arch_setup_interrupt_endpoint(unsigned char addr) -{ - unsigned int ei = EP_HW_NUM(addr); - USBEndpoint *ep = EP_STRUCT(addr); - usb_arch_setup_endpoint(addr, ((addr & 0x80) - ? AT91C_UDP_EPTYPE_INT_IN - : AT91C_UDP_EPTYPE_INT_OUT)); - ep->flags |= USB_EP_FLAGS_TYPE_BULK; - ep->xfer_size = ep_xfer_size[ei]; -} - -void -usb_arch_disable_endpoint(uint8_t addr) -{ - USBEndpoint *ep = EP_STRUCT(addr); - ep->flags &= ~USB_EP_FLAGS_ENABLED; - - *AT91C_UDP_IDR = 1<flags & mask) == flags)) { - USBBuffer *next = buffer->next; - buffer->flags &= ~USB_BUFFER_SUBMITTED ; - buffer->flags |= USB_BUFFER_FAILED; - if (buffer->flags & USB_BUFFER_NOTIFY) *resp |= USB_READ_NOTIFY; - buffer = next; - } - return buffer; -} - -static void -read_hw_buffer(uint8_t *data, unsigned int hw_ep, unsigned int len) -{ - AT91_REG *fdr; - fdr = &AT91C_UDP_FDR[hw_ep]; - while(len-- > 0) { - *data++ = *fdr; - } -} - - -#define USB_WRITE_BLOCK 0x01 -#define USB_WRITE_NOTIFY 0x02 - -void -write_hw_buffer(const uint8_t *data, unsigned int hw_ep, unsigned int len) -{ - AT91_REG *fdr; - fdr = &AT91C_UDP_FDR[hw_ep]; - /* PRINTF("Write %d\n", len); */ - while(len-- > 0) { - *fdr = *data++; - } -} - -static unsigned int -get_receive_capacity(USBBuffer *buffer) -{ - unsigned int capacity = 0; - while(buffer && !(buffer->flags & (USB_BUFFER_IN| USB_BUFFER_SETUP|USB_BUFFER_HALT))) { - capacity += buffer->left; - buffer = buffer->next; - } - return capacity; -} - -static int -handle_pending_receive(USBEndpoint *ep) -{ - int short_packet; - unsigned int len; - unsigned int copy; - unsigned int res = 0; - unsigned int hw_ep = EP_HW_NUM(ep->addr); - USBBuffer *buffer = ep->buffer; - uint8_t *setup_data = NULL; - unsigned int flags = ep->flags; - if (!(flags & USB_EP_FLAGS_ENABLED) || !buffer) return USB_READ_BLOCK; - len = RXBYTECNT(AT91C_UDP_CSR[hw_ep]); - PRINTF("handle_pending_receive: %d\n", len); - switch(flags & USB_EP_FLAGS_TYPE_MASK) { - case USB_EP_FLAGS_TYPE_CONTROL: - if (flags & USB_EP_FLAGS_SETUP_PENDING) { - /* Discard buffers until we find a SETUP buffer */ - buffer = - skip_buffers_until(buffer, USB_BUFFER_SETUP, USB_BUFFER_SETUP, &res); - ep->buffer = buffer; - if (!buffer || buffer->left < len) { - res |= USB_READ_BLOCK; - return res; - } - /* SETUP packet must fit in a single buffer */ - if (buffer->left < len) { - buffer->flags |= USB_BUFFER_FAILED; - buffer->flags &= ~USB_BUFFER_SUBMITTED ; - if (buffer->flags & USB_BUFFER_NOTIFY) res |= USB_READ_NOTIFY; - ep->buffer = buffer->next; - res |= USB_READ_FAIL; - return res; - } - setup_data = buffer->data; - } else { - if (buffer->flags & (USB_BUFFER_SETUP|USB_BUFFER_IN)) { - buffer->flags |= USB_BUFFER_FAILED; - - buffer->flags &= ~USB_BUFFER_SUBMITTED ; - if (buffer->flags & USB_BUFFER_NOTIFY) res |= USB_READ_NOTIFY; - ep->buffer = buffer->next; - res |= USB_READ_FAIL; - return res; - } - - if (len == 0) { - /* Status OUT */ - if (buffer->left > 0) { - buffer->flags |= USB_BUFFER_FAILED; - res |= USB_READ_FAIL; - } - buffer->flags &= ~USB_BUFFER_SUBMITTED ; - if (buffer->flags & USB_BUFFER_NOTIFY) res |= USB_READ_NOTIFY; - ep->buffer = buffer->next; - return res; - } - if (get_receive_capacity(buffer) < len) return USB_READ_BLOCK; - } - break; - case USB_EP_FLAGS_TYPE_INTERRUPT: - case USB_EP_FLAGS_TYPE_BULK: - case USB_EP_FLAGS_TYPE_ISO: - if (get_receive_capacity(buffer) < len) { - return USB_READ_BLOCK; - } - break; - } - - short_packet = len < ep->xfer_size; - - do { - if (buffer->left < len) { - copy = buffer->left; - } else { - copy = len; - } - len -= copy; - buffer->left -= copy; - read_hw_buffer(buffer->data, hw_ep, copy); - buffer->data += copy; - - if (len == 0) break; - - /* Release buffer */ - buffer->flags &= ~(USB_BUFFER_SUBMITTED | USB_BUFFER_SHORT_PACKET); - if (buffer->flags & USB_BUFFER_NOTIFY) res |= USB_READ_NOTIFY; - /* Use next buffer. */ - buffer = buffer->next; - } while(1); - - if (short_packet) { - buffer->flags |= USB_BUFFER_SHORT_PACKET; - } - - if ((buffer->left == 0) - || (buffer->flags & USB_BUFFER_PACKET_END) - || (short_packet && (buffer->flags & USB_BUFFER_SHORT_END))) { - /* Release buffer */ - buffer->flags &= ~USB_BUFFER_SUBMITTED; - if (buffer->flags & USB_BUFFER_NOTIFY) res |= USB_READ_NOTIFY; - /* Use next buffer. */ - buffer = buffer->next; - } - - ep->buffer = buffer; - if (setup_data) { - /* Set direction according to request */ - UDP_SET_EP_CTRL_FLAGS(&AT91C_UDP_CSR[0], - ((setup_data[0] & 0x80) - ? AT91C_UDP_DIR : 0), AT91C_UDP_DIR); - } - return res; -} - - -static void -start_receive(USBEndpoint *ep) -{ - ep->flags |= USB_EP_FLAGS_RECEIVING; -} - -#if 0 -static unsigned int -get_transmit_length(USBBuffer *buffer) -{ - unsigned int length = 0; - while(buffer && (buffer->flags & USB_BUFFER_IN)) { - length += buffer->left; - buffer = buffer->next; - } - return length; -} -#endif - -static int -start_transmit(USBEndpoint *ep) -{ - unsigned int res = 0; - USBBuffer *buffer = ep->buffer; - unsigned int len; - unsigned int hw_ep = EP_HW_NUM(ep->addr); - unsigned int ep_flags = ep->flags; - len = ep->xfer_size; - if (!(ep_flags & USB_EP_FLAGS_ENABLED) || !buffer) return USB_WRITE_BLOCK; - switch(ep_flags & USB_EP_FLAGS_TYPE_MASK) { - case USB_EP_FLAGS_TYPE_BULK: - if (buffer->flags & USB_BUFFER_HALT) { - if (ep->status & 0x01) return USB_WRITE_BLOCK; - ep->status |= 0x01; - if (!(ep->flags & USB_EP_FLAGS_TRANSMITTING)) { - UDP_SET_EP_CTRL_FLAGS(&AT91C_UDP_CSR[hw_ep], - AT91C_UDP_FORCESTALL, AT91C_UDP_FORCESTALL); - PRINTF("HALT IN\n"); - } - return USB_WRITE_BLOCK; - } - case USB_EP_FLAGS_TYPE_ISO: - if (!(ep->flags & USB_EP_FLAGS_TRANSMITTING)) { - if (AT91C_UDP_CSR[hw_ep] & AT91C_UDP_TXPKTRDY) return USB_WRITE_BLOCK; - } - break; - default: - if (AT91C_UDP_CSR[hw_ep] & AT91C_UDP_TXPKTRDY) return USB_WRITE_BLOCK; - } - - - while (buffer) { - unsigned int copy; - if (buffer->left < len) { - copy = buffer->left; - } else { - copy = len; - } - len -= copy; - buffer->left -= copy; - write_hw_buffer(buffer->data, hw_ep, copy); - buffer->data += copy; - if (buffer->left == 0) { - if (buffer->flags & USB_BUFFER_SHORT_END) { - if (len == 0) { - /* Send zero length packet. */ - break; - } else { - len = 0; - } - } - /* Release buffer */ - buffer->flags &= ~USB_BUFFER_SUBMITTED; - if (buffer->flags & USB_BUFFER_NOTIFY) res = USB_WRITE_NOTIFY; - /* Use next buffer. */ - buffer = buffer->next; - } - if (len == 0) break; - } - ep->buffer = buffer; - if (ep->flags & USB_EP_FLAGS_TRANSMITTING) { - ep->flags |= USB_EP_FLAGS_DOUBLE; - } else { - ep->flags |= USB_EP_FLAGS_TRANSMITTING; - } - - PRINTF("start_transmit: sent %08x\n",AT91C_UDP_CSR[hw_ep]); - /* Start transmission */ - UDP_SET_EP_CTRL_FLAGS(&AT91C_UDP_CSR[hw_ep], - AT91C_UDP_TXPKTRDY, AT91C_UDP_TXPKTRDY); - - return res; -} - -static void -start_transfer(USBEndpoint *ep) -{ - unsigned int hw_ep = EP_HW_NUM(ep->addr); - int res; - while (1) { - if (!(ep->addr & 0x80)) { - if (ep->buffer && (ep->buffer->flags & USB_BUFFER_HALT)) { - if (ep->status & 0x01) return ; - ep->status |= 0x01; - UDP_SET_EP_CTRL_FLAGS(&AT91C_UDP_CSR[EP_HW_NUM(ep->addr)], - AT91C_UDP_FORCESTALL, AT91C_UDP_FORCESTALL); - PRINTF("HALT OUT\n"); - *AT91C_UDP_IDR = 1<flags & USB_EP_FLAGS_RECV_PENDING)) break; - res = handle_pending_receive(ep); - if (res & USB_READ_NOTIFY) { - notify_ep_process(ep, USB_EP_EVENT_NOTIFICATION); - } - PRINTF("received res = %d\n", res); - if (res & USB_READ_BLOCK) { - *AT91C_UDP_IDR = 1<flags & USB_EP_FLAGS_BANK_1_RECV_NEXT) - ? AT91C_UDP_RX_DATA_BK1 - : AT91C_UDP_RX_DATA_BK0); - ep->flags ^= USB_EP_FLAGS_BANK_1_RECV_NEXT; - } else { - /* Ping-pong or single buffer */ - UDP_SET_EP_CTRL_FLAGS(&AT91C_UDP_CSR[hw_ep],0, - AT91C_UDP_RX_DATA_BK0); - ep->flags |= USB_EP_FLAGS_BANK_1_RECV_NEXT; - } - - if (ep->flags & USB_EP_FLAGS_DOUBLE) { - ep->flags &= ~USB_EP_FLAGS_DOUBLE; - } else if IS_CONTROL_EP(ep) { - ep->flags &= ~(USB_EP_FLAGS_RECV_PENDING|USB_EP_FLAGS_SETUP_PENDING); - } else { - ep->flags &= ~USB_EP_FLAGS_RECV_PENDING; - } - if (res & USB_READ_FAIL) { - /* Only fails for control endpoints */ - usb_arch_control_stall(ep->addr); - return; - } - *AT91C_UDP_IER = 1<flags & (USB_EP_FLAGS_TRANSMITTING | USB_EP_FLAGS_RECEIVING)) { -#if 0 - if (!IS_BULK_EP(ep) || (ep->flags & USB_EP_FLAGS_DOUBLE)) { -#else - if(1) { -#endif - PRINTF("Busy\n"); - return; - } - } - if (ep->status & 0x01) return; /* Don't start transfer if halted */ - if (ep->buffer) { - if (ep->buffer->flags & USB_BUFFER_IN) { - res = start_transmit(ep); - if (res & USB_WRITE_NOTIFY) { - notify_ep_process(ep, USB_EP_EVENT_NOTIFICATION); - } - } else { - start_receive(ep); - } - } -} - - -void -usb_arch_transfer_complete(unsigned int hw_ep) -{ - unsigned int status = AT91C_UDP_CSR[hw_ep]; - USBEndpoint *ep = &usb_endpoints[hw_ep]; - PRINTF("transfer_complete: %d\n", hw_ep); - if (status & AT91C_UDP_STALLSENT) { - /* Acknowledge */ - UDP_SET_EP_CTRL_FLAGS(&AT91C_UDP_CSR[hw_ep],0, AT91C_UDP_STALLSENT); - } - if (status & (AT91C_UDP_RXSETUP - | AT91C_UDP_RX_DATA_BK1 | AT91C_UDP_RX_DATA_BK0)) { - if (status & AT91C_UDP_RXSETUP) { - PRINTF("SETUP\n"); - ep->flags |= USB_EP_FLAGS_SETUP_PENDING; - } - if (ep->flags & USB_EP_FLAGS_DOUBLE) { - ep->flags &= ~USB_EP_FLAGS_DOUBLE; - } else { - ep->flags &= ~USB_EP_FLAGS_RECEIVING; - } - if ( ep->flags & USB_EP_FLAGS_RECV_PENDING) { - ep->flags |= USB_EP_FLAGS_DOUBLE; - } else { - ep->flags |= USB_EP_FLAGS_RECV_PENDING; - } - start_transfer(ep); - } - if (status & AT91C_UDP_TXCOMP) { - PRINTF("Sent packet\n"); - if (ep->flags & USB_EP_FLAGS_DOUBLE) { - ep->flags &= ~USB_EP_FLAGS_DOUBLE; - } else { - ep->flags &= ~USB_EP_FLAGS_TRANSMITTING; - } - UDP_SET_EP_CTRL_FLAGS(&AT91C_UDP_CSR[hw_ep],0, AT91C_UDP_TXCOMP); - if (ep->status & 0x01) { - UDP_SET_EP_CTRL_FLAGS(&AT91C_UDP_CSR[hw_ep], - AT91C_UDP_FORCESTALL, AT91C_UDP_FORCESTALL); - PRINTF("HALT IN\n"); - } else { - start_transfer(ep); - } - } - -} - - -void -usb_set_ep_event_process(unsigned char addr, struct process *p) -{ - USBEndpoint *ep = &usb_endpoints[EP_INDEX(addr)]; - ep->event_process = p; -} - -/* Select what process should be polled when a global event occurs */ -void -usb_arch_set_global_event_process(struct process *p) -{ - event_process = p; -} - -unsigned int -usb_arch_get_global_events(void) -{ - unsigned int e; - USB_DISABLE_INT; - e = events; - events = 0; - USB_ENABLE_INT; - return e; -} - -unsigned int -usb_get_ep_events(unsigned char addr) -{ - unsigned int e; - unsigned int ei = EP_HW_NUM(addr); - USB_DISABLE_INT; - e = usb_endpoints[ei].events; - usb_endpoints[ei].events = 0; - USB_ENABLE_INT; - return e; -} - - -void -usb_submit_recv_buffer(unsigned char ep_addr, USBBuffer *buffer) -{ - USBBuffer **tailp; - USBEndpoint *ep = &usb_endpoints[EP_INDEX(ep_addr)]; - if (!(ep->flags & USB_EP_FLAGS_ENABLED)) return; - /* PRINTF("buffer: %p\n", ep->buffer); */ - /* dbg_drain(); */ - USB_DISABLE_INT; - tailp = (USBBuffer**)&ep->buffer; - while(*tailp) { - tailp = &(*tailp)->next; - } - *tailp = buffer; - while(buffer) { - buffer->flags |= USB_BUFFER_SUBMITTED; - buffer = buffer->next; - } - start_transfer(ep); - - USB_ENABLE_INT; -} - -void -usb_submit_xmit_buffer(unsigned char ep_addr, USBBuffer *buffer) -{ - USBBuffer **tailp; - USBEndpoint *ep = &usb_endpoints[EP_INDEX(ep_addr)]; - if (!(ep->flags & USB_EP_FLAGS_ENABLED)) return; - /* PRINTF("usb_submit_xmit_buffer %d\n", buffer->left); */ - USB_DISABLE_INT; - tailp = (USBBuffer**)&ep->buffer; - while(*tailp) { - tailp = &(*tailp)->next; - } - *tailp = buffer; - while(buffer) { - buffer->flags |= USB_BUFFER_SUBMITTED | USB_BUFFER_IN; - buffer = buffer->next; - } - start_transfer(ep); - USB_ENABLE_INT; -} - -void -usb_arch_discard_all_buffers(unsigned char ep_addr) -{ - USBBuffer *buffer; - volatile USBEndpoint *ep = &usb_endpoints[EP_INDEX(ep_addr)]; - USB_DISABLE_EP_INT(EP_HW_NUM(ep_addr)); - buffer = ep->buffer; - ep->buffer = NULL; - - USB_ENABLE_EP_INT(EP_HW_NUM(ep_addr)); - while(buffer) { - buffer->flags &= ~USB_BUFFER_SUBMITTED; - buffer = buffer->next; - } -} - -uint16_t -usb_arch_get_ep_status(uint8_t addr) -{ - if (EP_INDEX(addr) > USB_MAX_ENDPOINTS) return 0; - return usb_endpoints[EP_INDEX(addr)].status; -} - -void -usb_arch_set_configuration(uint8_t usb_configuration_value) -{ - /* Nothing needs to be done */ -} - -void -usb_arch_control_stall(unsigned char addr) -{ - if (EP_INDEX(addr) > USB_MAX_ENDPOINTS) return; - UDP_SET_EP_CTRL_FLAGS(&AT91C_UDP_CSR[EP_HW_NUM(addr)], - AT91C_UDP_FORCESTALL, AT91C_UDP_FORCESTALL); -} - -/* Not for control endpoints */ -void -usb_arch_halt_endpoint(unsigned char ep_addr, int halt) -{ - if (EP_INDEX(ep_addr) > USB_MAX_ENDPOINTS) return; - if (!usb_endpoints[EP_INDEX(ep_addr)].flags & USB_EP_FLAGS_ENABLED) return; - *AT91C_UDP_IDR = 1<status &= ~0x01; - *AT91C_UDP_IDR = 1<buffer && (ep->buffer->flags & USB_BUFFER_HALT)) { - ep->buffer->flags &= ~USB_BUFFER_SUBMITTED; - if (ep->buffer->flags & USB_BUFFER_NOTIFY) { - notify_ep_process(ep,USB_EP_EVENT_NOTIFICATION); - } - ep->buffer = ep->buffer->next; - } - - /* Restart transmission */ - start_transfer(&usb_endpoints[EP_INDEX(ep_addr)]); - } - *AT91C_UDP_IER = 1< -#include -#include -#include -#include - -static void -usb_int_safe (void) __attribute__((noinline)); - -static void -usb_int_safe (void) -{ - unsigned int int_status; - /* putchar('*'); */ - int_status = *AT91C_UDP_ISR & *AT91C_UDP_IMR; - - if (int_status & (AT91C_UDP_EP0 | AT91C_UDP_EP1 | AT91C_UDP_EP2 - | AT91C_UDP_EP3)) { - unsigned int ep_index; - /* Handle enabled interrupts */ - for (ep_index = 0; ep_index < 4; ep_index++) { - if (int_status & (1<