319 lines
14 KiB
C
319 lines
14 KiB
C
//*********************************************************************************
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// Parameter summary
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// Address: 0
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// Address0: 0xAA
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// Address1: 0xBB
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// Frequency: 915.00000 MHz
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// Data Format: Serial mode disable
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// Deviation: 25.000 kHz
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// pktLen: 30
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// 802.15.4g Mode: 0
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// Select bit order to transmit PSDU octets:: 1
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// Packet Length Config: Variable
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// Max Packet Length: 255
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// Packet Length: 20
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// Packet Data: 255
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// RX Filter BW: 98.0 kHz
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// Symbol Rate: 50.00000 kBaud
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// Sync Word Length: 24 Bits
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// For Default PA:
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// TX Power: 13.5 dBm (requires define CCFG_FORCE_VDDR_HH = 1 in ccfg.c, see CC13xx/CC26xx Technical Reference Manual)
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// Enable high output power PA: false
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// For High PA:
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// TX Power: 20 dBm (requires define CCFG_FORCE_VDDR_HH = 0 in ccfg.c, see CC13xx/CC26xx Technical Reference Manual)
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// Enable high output power PA: true
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// Whitening: Dynamically IEEE 802.15.4g compatible whitener and 16/32-bit CRC
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#include <ti/devices/DeviceFamily.h>
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#include DeviceFamily_constructPath(driverlib/rf_mailbox.h)
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#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h)
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#include DeviceFamily_constructPath(driverlib/rf_prop_cmd.h)
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#include DeviceFamily_constructPath(rf_patches/rf_patch_cpe_prop.h)
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#include DeviceFamily_constructPath(rf_patches/rf_patch_rfe_genfsk.h)
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#include DeviceFamily_constructPath(rf_patches/rf_patch_mce_genfsk.h)
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#include <ti/drivers/rf/RF.h>
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#include "prop-settings.h"
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// TI-RTOS RF Mode Object
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RF_Mode RF_propMode =
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{
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.rfMode = RF_MODE_AUTO,
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.cpePatchFxn = &rf_patch_cpe_prop,
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.mcePatchFxn = &rf_patch_mce_genfsk,
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.rfePatchFxn = &rf_patch_rfe_genfsk,
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};
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// TX Power table
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// The RF_TxPowerTable_DEFAULT_PA_ENTRY macro is defined in RF.h and requires the following arguments:
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// RF_TxPowerTable_DEFAULT_PA_ENTRY(bias, gain, boost coefficient)
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// See the Technical Reference Manual for further details about the "txPower" Command field.
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// The PA settings require the CCFG_FORCE_VDDR_HH = 0 unless stated otherwise.
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RF_TxPowerTable_Entry defaultPaTxPowerTable[19] =
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{
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{ -20, RF_TxPowerTable_DEFAULT_PA_ENTRY( 0, 3, 0, 2) },
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{ -15, RF_TxPowerTable_DEFAULT_PA_ENTRY( 1, 3, 0, 3) },
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{ -10, RF_TxPowerTable_DEFAULT_PA_ENTRY( 2, 3, 0, 3) },
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{ -5, RF_TxPowerTable_DEFAULT_PA_ENTRY( 4, 3, 0, 6) },
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{ 0, RF_TxPowerTable_DEFAULT_PA_ENTRY( 7, 3, 0, 8) },
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{ 1, RF_TxPowerTable_DEFAULT_PA_ENTRY( 8, 3, 0, 9) },
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{ 2, RF_TxPowerTable_DEFAULT_PA_ENTRY( 9, 3, 0, 9) },
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{ 3, RF_TxPowerTable_DEFAULT_PA_ENTRY(11, 3, 0, 11) },
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{ 4, RF_TxPowerTable_DEFAULT_PA_ENTRY(12, 3, 0, 12) },
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{ 5, RF_TxPowerTable_DEFAULT_PA_ENTRY(14, 3, 0, 14) },
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{ 6, RF_TxPowerTable_DEFAULT_PA_ENTRY( 6, 2, 0, 14) },
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{ 7, RF_TxPowerTable_DEFAULT_PA_ENTRY( 4, 1, 0, 16) },
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{ 8, RF_TxPowerTable_DEFAULT_PA_ENTRY( 6, 1, 0, 19) },
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{ 9, RF_TxPowerTable_DEFAULT_PA_ENTRY( 8, 1, 0, 25) },
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{ 10, RF_TxPowerTable_DEFAULT_PA_ENTRY(13, 1, 0, 40) },
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{ 11, RF_TxPowerTable_DEFAULT_PA_ENTRY(10, 0, 0, 71) },
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{ 12, RF_TxPowerTable_DEFAULT_PA_ENTRY(63, 0, 0, 64) },
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// This setting requires CCFG_FORCE_VDDR_HH = 1.
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// The original PA value (13.5 dBm) have been rounded to an integer value.
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{ 14, RF_TxPowerTable_DEFAULT_PA_ENTRY(63, 0, 1, 0) },
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RF_TxPowerTable_TERMINATION_ENTRY
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};
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// TX Power table
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// The RF_TxPowerTable_HIGH_PA_ENTRY macro is defined in RF.h and requires the following arguments:
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// RF_TxPowerTable_HIGH_PA_ENTRY(bias, ibboost, boost, coefficient, ldoTrim)
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// See the Technical Reference Manual for further details about the "txPower" Command field.
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// The PA settings require the CCFG_FORCE_VDDR_HH = 0 unless stated otherwise.
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RF_TxPowerTable_Entry highPaTxPowerTable[8] =
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{
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{ 14, RF_TxPowerTable_HIGH_PA_ENTRY( 7, 0, 0, 23, 4) },
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{ 15, RF_TxPowerTable_HIGH_PA_ENTRY(10, 0, 0, 26, 4) },
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{ 16, RF_TxPowerTable_HIGH_PA_ENTRY(14, 0, 0, 33, 4) },
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{ 17, RF_TxPowerTable_HIGH_PA_ENTRY(18, 0, 0, 40, 6) },
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{ 18, RF_TxPowerTable_HIGH_PA_ENTRY(24, 0, 0, 51, 8) },
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{ 19, RF_TxPowerTable_HIGH_PA_ENTRY(32, 0, 0, 73, 12) },
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{ 20, RF_TxPowerTable_HIGH_PA_ENTRY(27, 0, 0, 85, 32) },
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RF_TxPowerTable_TERMINATION_ENTRY
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};
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// Overrides for CMD_PROP_RADIO_DIV_SETUP
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uint32_t pDefaultPaOverrides[] =
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{
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// override_use_patch_prop_genfsk.xml
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MCE_RFE_OVERRIDE(1,0,0,1,0,0), // PHY: Use MCE RAM patch, RFE RAM patch
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// override_synth_prop_863_930_div5.xml
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(uint32_t)0x02400403, // Synth: Use 48 MHz crystal as synth clock, enable extra PLL filtering
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(uint32_t)0x00068793, // Synth: Set minimum RTRIM to 6
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(uint32_t)0x001C8473, // Synth: Configure extra PLL filtering
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(uint32_t)0x00088433, // Synth: Configure extra PLL filtering
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(uint32_t)0x000684A3, // Synth: Set Fref to 4 MHz
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HW32_ARRAY_OVERRIDE(0x4004,1), // Synth: Configure faster calibration
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(uint32_t)0x180C0618, // Synth: Configure faster calibration
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(uint32_t)0xC00401A1, // Synth: Configure faster calibration
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(uint32_t)0x00010101, // Synth: Configure faster calibration
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(uint32_t)0xC0040141, // Synth: Configure faster calibration
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(uint32_t)0x00214AD3, // Synth: Configure faster calibration
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(uint32_t)0x02980243, // Synth: Decrease synth programming time-out by 90 us from default (0x0298 RAT ticks = 166 us)
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(uint32_t)0x0A480583, // Synth: Set loop bandwidth after lock to 20 kHz
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(uint32_t)0x7AB80603, // Synth: Set loop bandwidth after lock to 20 kHz
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(uint32_t)0x00000623, // Synth: Set loop bandwidth after lock to 20 kHz
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// override_phy_tx_pa_ramp_genfsk_hpa.xml
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HW_REG_OVERRIDE(0x6028,0x002F), // Tx: Configure PA ramping, set wait time before turning off (0x2F ticks of 16/24 us = 31.3 us).
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ADI_HALFREG_OVERRIDE(0,16,0x8,0x8), // Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[3]=1)
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ADI_HALFREG_OVERRIDE(0,17,0x1,0x1), // Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[4]=1)
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// override_phy_rx_frontend_genfsk.xml
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HW_REG_OVERRIDE(0x609C,0x001A), // Rx: Set AGC reference level to 0x1A (default: 0x2E)
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(uint32_t)0x00018883, // Rx: Set LNA bias current offset to adjust +1 (default: 0)
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(uint32_t)0x000288A3, // Rx: Set RSSI offset to adjust reported RSSI by -2 dB (default: 0)
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// override_phy_rx_aaf_bw_0xd.xml
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ADI_HALFREG_OVERRIDE(0,61,0xF,0xD), // Rx: Set anti-aliasing filter bandwidth to 0xD (in ADI0, set IFAMPCTL3[7:4]=0xD)
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// TX power override
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(uint32_t)0xFFFC08C3, // DC/DC regulator: In Tx with 14 dBm PA setting, use DCDCCTL5[3:0]=0xF (DITHER_EN=1 and IPEAK=7). In Rx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4).
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ADI_REG_OVERRIDE(0,12,0xF8), // Tx: Set PA trim to max to maximize its output power (in ADI0, set PACTL0=0xF8)
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(uint32_t)0xFFFFFFFF,
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};
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// Overrides for CMD_PROP_RADIO_DIV_SETUP
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uint32_t pHighPaOverrides[] =
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{
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// override_use_patch_prop_genfsk.xml
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MCE_RFE_OVERRIDE(1,0,0,1,0,0), // PHY: Use MCE RAM patch, RFE RAM patch
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// override_synth_prop_863_930_div5.xml
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(uint32_t)0x02400403, // Synth: Use 48 MHz crystal as synth clock, enable extra PLL filtering
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(uint32_t)0x00068793, // Synth: Set minimum RTRIM to 6
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(uint32_t)0x001C8473, // Synth: Configure extra PLL filtering
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(uint32_t)0x00088433, // Synth: Configure extra PLL filtering
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(uint32_t)0x000684A3, // Synth: Set Fref to 4 MHz
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HW32_ARRAY_OVERRIDE(0x4004,1), // Synth: Configure faster calibration
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(uint32_t)0x180C0618, // Synth: Configure faster calibration
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(uint32_t)0xC00401A1, // Synth: Configure faster calibration
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(uint32_t)0x00010101, // Synth: Configure faster calibration
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(uint32_t)0xC0040141, // Synth: Configure faster calibration
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(uint32_t)0x00214AD3, // Synth: Configure faster calibration
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(uint32_t)0x02980243, // Synth: Decrease synth programming time-out by 90 us from default (0x0298 RAT ticks = 166 us)
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(uint32_t)0x0A480583, // Synth: Set loop bandwidth after lock to 20 kHz
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(uint32_t)0x7AB80603, // Synth: Set loop bandwidth after lock to 20 kHz
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(uint32_t)0x00000623, // Synth: Set loop bandwidth after lock to 20 kHz
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// override_phy_tx_pa_ramp_genfsk_hpa.xml
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HW_REG_OVERRIDE(0x6028,0x002F), // Tx: Configure PA ramping, set wait time before turning off (0x2F ticks of 16/24 us = 31.3 us).
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ADI_HALFREG_OVERRIDE(0,16,0x8,0x8), // Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[3]=1)
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ADI_HALFREG_OVERRIDE(0,17,0x1,0x1), // Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[4]=1)
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// override_phy_rx_frontend_genfsk.xml
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HW_REG_OVERRIDE(0x609C,0x001A), // Rx: Set AGC reference level to 0x1A (default: 0x2E)
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(uint32_t)0x00018883, // Rx: Set LNA bias current offset to adjust +1 (default: 0)
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(uint32_t)0x000288A3, // Rx: Set RSSI offset to adjust reported RSSI by -2 dB (default: 0)
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// override_phy_rx_aaf_bw_0xd.xml
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ADI_HALFREG_OVERRIDE(0,61,0xF,0xD), // Rx: Set anti-aliasing filter bandwidth to 0xD (in ADI0, set IFAMPCTL3[7:4]=0xD)
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// TX power override
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(uint32_t)0xFCFC08C3, // DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4). In Rx, use DCDCCTL5[3:0]=0xC (DITHER_EN=1 and IPEAK=4).
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(uint32_t)0x82A86C2B, // txHighPA=0x20AA1B
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(uint32_t)0xFFFFFFFF,
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};
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// CMD_PROP_RADIO_DIV_SETUP
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// Proprietary Mode Radio Setup Command for All Frequency Bands
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rfc_CMD_PROP_RADIO_DIV_SETUP_t RF_cmdPropRadioDivSetup =
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{
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.commandNo = 0x3807,
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.status = 0x0000,
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.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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.startTime = 0x00000000,
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.startTrigger.triggerType = 0x0,
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.startTrigger.bEnaCmd = 0x0,
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.startTrigger.triggerNo = 0x0,
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.startTrigger.pastTrig = 0x0,
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.condition.rule = 0x1,
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.condition.nSkip = 0x0,
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.modulation.modType = 0x1,
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.modulation.deviation = 0x64,
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.modulation.deviationStepSz = 0x0,
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.symbolRate.preScale = 0xF,
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.symbolRate.rateWord = 0x8000,
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.symbolRate.decimMode = 0x0,
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.rxBw = 0x52,
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.preamConf.nPreamBytes = 0x3,
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.preamConf.preamMode = 0x0,
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.formatConf.nSwBits = 0x18,
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.formatConf.bBitReversal = 0x0,
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.formatConf.bMsbFirst = 0x1,
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.formatConf.fecMode = 0x0,
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.formatConf.whitenMode = 0x7,
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.config.frontEndMode = 0x0,
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.config.biasMode = 0x1,
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.config.analogCfgMode = 0x0,
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.config.bNoFsPowerUp = 0x0,
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.txPower = 0x013F,
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.pRegOverride = pOverrides,
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.centerFreq = 0x0393,
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.intFreq = 0x8000,
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.loDivider = 0x05,
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};
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// CMD_FS
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// Frequency Synthesizer Programming Command
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rfc_CMD_FS_t RF_cmdFs =
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{
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.commandNo = 0x0803,
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.status = 0x0000,
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.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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.startTime = 0x00000000,
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.startTrigger.triggerType = 0x0,
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.startTrigger.bEnaCmd = 0x0,
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.startTrigger.triggerNo = 0x0,
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.startTrigger.pastTrig = 0x0,
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.condition.rule = 0x1,
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.condition.nSkip = 0x0,
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.frequency = 0x0393,
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.fractFreq = 0x0000,
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.synthConf.bTxMode = 0x0,
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.synthConf.refFreq = 0x0,
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.__dummy0 = 0x00,
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.__dummy1 = 0x00,
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.__dummy2 = 0x00,
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.__dummy3 = 0x0000,
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};
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// CMD_PROP_TX_ADV
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// Proprietary Mode Advanced Transmit Command
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rfc_CMD_PROP_TX_ADV_t RF_cmdPropTxAdv =
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{
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.commandNo = 0x3803,
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.status = 0x0000,
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.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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.startTime = 0x00000000,
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.startTrigger.triggerType = 0x2,
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.startTrigger.bEnaCmd = 0x0,
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.startTrigger.triggerNo = 0x0,
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.startTrigger.pastTrig = 0x1,
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.condition.rule = 0x1,
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.condition.nSkip = 0x0,
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.pktConf.bFsOff = 0x0,
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.pktConf.bUseCrc = 0x1,
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.pktConf.bCrcIncSw = 0x0,
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.pktConf.bCrcIncHdr = 0x0,
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.numHdrBits = 0x10,
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.pktLen = 0x0014,
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.startConf.bExtTxTrig = 0x0,
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.startConf.inputMode = 0x0,
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.startConf.source = 0x0,
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.preTrigger.triggerType = 0x4,
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.preTrigger.bEnaCmd = 0x0,
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.preTrigger.triggerNo = 0x0,
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.preTrigger.pastTrig = 0x1,
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.preTime = 0x00000000,
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.syncWord = 0x0055904E,
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.pPkt = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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};
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// CMD_PROP_RX_ADV
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// Proprietary Mode Advanced Receive Command
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rfc_CMD_PROP_RX_ADV_t RF_cmdPropRxAdv =
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{
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.commandNo = 0x3804,
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.status = 0x0000,
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.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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.startTime = 0x00000000,
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.startTrigger.triggerType = 0x0,
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.startTrigger.bEnaCmd = 0x0,
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.startTrigger.triggerNo = 0x0,
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.startTrigger.pastTrig = 0x0,
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.condition.rule = 0x1,
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.condition.nSkip = 0x0,
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.pktConf.bFsOff = 0x0,
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.pktConf.bRepeatOk = 0x0,
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.pktConf.bRepeatNok = 0x0,
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.pktConf.bUseCrc = 0x0,
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.pktConf.bCrcIncSw = 0x0,
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.pktConf.bCrcIncHdr = 0x0,
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.pktConf.endType = 0x0,
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.pktConf.filterOp = 0x0,
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.rxConf.bAutoFlushIgnored = 0x0,
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.rxConf.bAutoFlushCrcErr = 0x0,
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.rxConf.bIncludeHdr = 0x0,
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.rxConf.bIncludeCrc = 0x0,
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.rxConf.bAppendRssi = 0x0,
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.rxConf.bAppendTimestamp = 0x0,
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.rxConf.bAppendStatus = 0x0,
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.syncWord0 = 0x930B51DE,
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.syncWord1 = 0x00000000,
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.maxPktLen = 0x00FF,
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.hdrConf.numHdrBits = 0x0,
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.hdrConf.lenPos = 0x0,
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.hdrConf.numLenBits = 0x0,
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.addrConf.addrType = 0x0,
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.addrConf.addrSize = 0x0,
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.addrConf.addrPos = 0x0,
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.addrConf.numAddr = 0x0,
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.lenOffset = 0x00,
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.endTrigger.triggerType = 0x0,
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.endTrigger.bEnaCmd = 0x0,
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.endTrigger.triggerNo = 0x0,
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.endTrigger.pastTrig = 0x0,
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.endTime = 0x00000000,
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.pAddr = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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.pQueue = 0, // INSERT APPLICABLE POINTER: (dataQueue_t*)&xxx
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.pOutput = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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};
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