117 lines
2.0 KiB
ArmAsm
117 lines
2.0 KiB
ArmAsm
/*
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ARM System Developer's Guide, Chapter 9 Section 1 (y. 2004-2008) (page 323)
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*/
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.data
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und_msg:
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.string "Undefined Instruction"
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swi_msg:
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.string "Hello. I am the sample SWI handler! =)"
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prefetch_abt_msg:
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.string "Prefetch Abort"
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data_abt_msg:
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.string "Data Abort @ "
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irq_msg:
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.string "IRQ"
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fiq_msg:
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.string "FIQ"
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.text
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.balign 32
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.global vectab
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vectab:
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ldr pc, =panic
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ldr pc, =und_handler
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ldr pc, =swi_handler
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ldr pc, =prefetch_abt_handler
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ldr pc, =data_abt_handler
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nop
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ldr pc, =irq_handler
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ldr pc, =fiq_handler
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und_handler:
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stmfd sp!, {lr}
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ldr r0, =und_msg
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bl printkl
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ldmfd sp!, {pc}^
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swi_handler:
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stmfd sp!, {r0-r12, lr}
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/* Get SWI number to pass to c_swi_handler */
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ldr r10, [lr, #-4]
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and r10, #0x00ffffff
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mov r0, r10
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mov r1, sp
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mrs r2, spsr
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stmfd sp!, {r2}
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bl c_swi_handler
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ldmfd sp!, {r2}
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msr spsr_cxsf, r2
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ldmfd sp!, {r0-r12, pc}^
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// TODO: untested
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prefetch_abt_handler:
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sub lr, #4
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stmfd sp!, {lr}
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ldr r0, =prefetch_abt_msg
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bl printkl
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ldmfd sp!, {pc}^
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data_abt_handler:
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sub lr, #8
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stmfd sp!, {lr}
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ldr r0, =data_abt_msg
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bl printk
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ldmfd sp!, {r0}
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bl itoa
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bl printkl
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b panic
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ldmfd sp!, {pc}^
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irq_handler:
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// mask FIQ (IRQ already masked by hardware when entering IRQ mode)
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cpsid f
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// Prepare return address and store context on stack
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sub lr, #0x4
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stmfd sp!, {r0-r12, lr}
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// Acknoweledge interrupt
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ldr r10, =0x01c8200c // IAR
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ldr r0, [r10]
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push {r0}
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// Complex handlers in C++
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bl c_irq_handler
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// Send End of Interrupt
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pop {r0}
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ldr r10, =0x01c82010 // EOIR address
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mov r1, #1023 // check for spurious interrupt
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cmp r0, r1
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strne r0, [r10] // ack interrupt only if not spurious (see GICC_EOIR)
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// Reload context from stack
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// and also restore CPSR from SPSR (that caret)
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ldmfd sp!, {r0-r12, pc}^
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// TODO: untested
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fiq_handler:
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stmfd sp!, {lr}
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ldr r0, =fiq_msg
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bl printkl
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ldmfd sp!, {pc}^
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