From a3fc600996b49638584a93156fa231e4aeca769f Mon Sep 17 00:00:00 2001
From: giomba <giomba@glgprograms.it>
Date: Sat, 8 Oct 2022 15:11:59 +0200
Subject: [PATCH] Rewrite some non-real-time initialization code in C.

---
 macro.h |  2 +-
 main.S  | 51 ++++++++++++---------------------------------------
 main.c  | 51 ++++++++++++++++++++++++++++++++++++++++++---------
 3 files changed, 55 insertions(+), 49 deletions(-)

diff --git a/macro.h b/macro.h
index 2dc8ee9..4bc7b62 100644
--- a/macro.h
+++ b/macro.h
@@ -1 +1 @@
-#define IO(x) x - 0x20
+#define IO(x) ((x) - 0x20)
diff --git a/main.S b/main.S
index a015f2d..38896c5 100644
--- a/main.S
+++ b/main.S
@@ -1,12 +1,14 @@
+; main.S
+;
+; This file is part of OSDY VideoCharGen
+; a do-it-yourself on-screen-display image generator
+; for superimposition of analog PAL signals
+;
 #include <avr/io.h>
 #include "macro.h"
 #include "const.h"
 
-
 .data
-image:
-.byte 0xff
-
 show_image:
 .byte 0x00
 
@@ -18,48 +20,19 @@ current_jump_table:
 
 .text
 
-.global main
-main:
-    ldi r16, 0x30       ; port B, pin 4 and 5 as output, others as input
-    sts DDRB, r16
-
-    ; set interrupt vectors at address 0x0, not bootloader
-    ; timing is important, see atmel datasheet
-    ldi r16, (1 << IVCE)
-    ldi r17, 0
-    out IO(MCUCR), r16
-    out IO(MCUCR), r17
-
-    ldi r16, 0xa        ; external interrupt 0 and 1, falling edge
-    sts EICRA, r16
-
-    ldi r16, 0x3        ; external interrupt 0 and 1, mask enable
-    sts EIMSK, r16
-
-    ldi r16, 0x02       ; don't connect output pins to timer, CTC[1:0] mode
-    sts TCCR0A, r16
-    ldi r16, 0x01       ; CTC[2] mode, no prescaler
-    sts TCCR0B, r16
-
+.global main_asm
+main_asm:
     ; init variables
     ldi r16, 0
-    sts frame, r16
-    sts frame + 1, r16
-    sts line, r16
-    ldi r16, 0xfe
-    sts line + 1, r16
-    ldi r16, 0xff
-    sts image, r16
-    ldi r16, 0
     sts show_image, r16
 
     ; r0 always holds 0
     clr r0
 
-    call setup_c
-
-    sei                 ; global interrupt enable
+    ; global interrupt enable
+    sei
 
+    ; endless loop
 1:
     rjmp 1b
 
@@ -182,7 +155,7 @@ check_if_released:
     in r31, IO(PINB)
     andi r31, 0x04
     ; if transition mode == 1, then always show image
-    ; TODO an huge shitty spaghetti code
+    ; Nice to have: maybe this can be written better.
     breq 1f
     ldi r31, 0
     sts show_image, r31
diff --git a/main.c b/main.c
index 6c74c6c..c3ac480 100644
--- a/main.c
+++ b/main.c
@@ -1,21 +1,54 @@
-#include <avr/io.h>
-#include <avr/interrupt.h>
+/**
+ * @file main.c
+ * @author giomba@glgprograms.it
+ * @brief OSDY main.
+ *
+ * @copyright Copyright RetrOfficina GLG Programs (c) 2022
+ *
+ * Video image generator superimposition for analog PAL signals,
+ * with Atmega328, for your retro OSD titles.
+ *
+ */
 #include "const.h"
+#include <avr/interrupt.h>
+#include <avr/io.h>
 #include <string.h>
 
-volatile uint16_t frame;
-volatile uint16_t line;
+volatile uint16_t frame = 0;
+volatile uint16_t line = 0xfe;
+volatile uint8_t image = 0xff;
 
 ISR(INT0_vect, ISR_NAKED) {
-    asm("jmp int_vertical_sync");
+  // vertical sync interrupt
+  asm("jmp int_vertical_sync");
 }
 ISR(INT1_vect, ISR_NAKED) {
-    asm("jmp int_horizontal_sync");
+  // horizontal sync interrupt
+  asm("jmp int_horizontal_sync");
 }
 ISR(TIMER0_COMPA_vect, ISR_NAKED) {
-    asm("jmp int_timer_0");
+  // back porch timer interrupt
+  asm("jmp int_timer_0");
 }
 
-void setup_c() {
-}
+// external assembly main loop
+void main_asm(void);
 
+int main() {
+  // port B, pin 4 and 5 as output, others as input
+  DDRB |= 0x30;
+
+  // set interrupt vectors at address 0x0, not bootloader
+  // timing is important, see atmel datasheet
+  _SFR_IO8(MCUCR) = (1 << IVCE);
+  _SFR_IO8(MCUCR) = 0;
+
+  EICRA = 0x0a; // external interrupt 0 and 1, falling edge
+  EIMSK = 0x03; // external interrupt 0 and 1, mask enable
+
+  TCCR0A = 0x02; // don't connect output pins to timer, CTC[1:0] mode
+
+  TCCR0B = 0x01; // CTC[2] mode, no prescaler
+
+  main_asm();
+}