2015-02-25 12:09:56 +00:00
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/*
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* Copyright (c) 2014, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "contiki-conf.h"
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#include "cc26xx-uart.h"
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#include "hw_types.h"
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#include "hw_memmap.h"
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#include "sys_ctrl.h"
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#include "prcm.h"
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#include "ioc.h"
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#include "uart.h"
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#include "lpm.h"
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#include "ti-lib.h"
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#include "sys/energest.h"
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#include <stdint.h>
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2015-05-01 16:03:26 +00:00
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#include <stdbool.h>
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2015-02-25 12:09:56 +00:00
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/*---------------------------------------------------------------------------*/
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/* Which events to trigger a UART interrupt */
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#define CC26XX_UART_RX_INTERRUPT_TRIGGERS (UART_INT_RX | UART_INT_RT)
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/* All interrupt masks */
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#define CC26XX_UART_INTERRUPT_ALL (UART_INT_OE | UART_INT_BE | UART_INT_PE | \
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UART_INT_FE | UART_INT_RT | UART_INT_TX | \
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UART_INT_RX | UART_INT_CTS)
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/*---------------------------------------------------------------------------*/
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#define cc26xx_uart_isr UART0IntHandler
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/*---------------------------------------------------------------------------*/
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static int (*input_handler)(unsigned char c);
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/*---------------------------------------------------------------------------*/
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2015-05-01 16:03:26 +00:00
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static bool
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usable(void)
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{
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if(BOARD_IOID_UART_RX == IOID_UNUSED ||
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BOARD_IOID_UART_TX == IOID_UNUSED ||
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CC26XX_UART_CONF_ENABLE == 0) {
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return false;
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}
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return true;
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}
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/*---------------------------------------------------------------------------*/
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2015-02-25 12:09:56 +00:00
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static void
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2015-05-01 16:03:26 +00:00
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power_and_clock(void)
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2015-02-25 12:09:56 +00:00
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{
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2015-05-01 16:03:26 +00:00
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/* Power on the SERIAL PD */
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2015-02-25 12:09:56 +00:00
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ti_lib_prcm_power_domain_on(PRCM_DOMAIN_SERIAL);
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while(ti_lib_prcm_power_domain_status(PRCM_DOMAIN_SERIAL)
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!= PRCM_DOMAIN_POWER_ON);
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2015-05-01 16:03:26 +00:00
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/* Enable UART clock in active mode */
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ti_lib_prcm_peripheral_run_enable(PRCM_PERIPH_UART0);
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ti_lib_prcm_load_set();
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while(!ti_lib_prcm_load_get());
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}
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/*---------------------------------------------------------------------------*/
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/*
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* Returns 0 if either the SERIAL PD is off, or the PD is on but the run mode
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* clock is gated. If this function would return 0, accessing UART registers
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* will return a precise bus fault. If this function returns 1, it is safe to
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* access UART registers.
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*
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* This function only checks the 'run mode' clock gate, since it can only ever
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* be called with the MCU in run mode.
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*/
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static bool
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accessible(void)
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{
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/* First, check the PD */
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if(ti_lib_prcm_power_domain_status(PRCM_DOMAIN_SERIAL)
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!= PRCM_DOMAIN_POWER_ON) {
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return false;
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}
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/* Then check the 'run mode' clock gate */
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if(!(HWREG(PRCM_BASE + PRCM_O_UARTCLKGR) & PRCM_UARTCLKGR_CLK_EN)) {
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return false;
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}
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return true;
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2015-02-25 12:09:56 +00:00
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}
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/*---------------------------------------------------------------------------*/
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static void
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2015-05-01 16:03:26 +00:00
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disable_interrupts(void)
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2015-02-25 12:09:56 +00:00
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{
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2015-05-01 16:03:26 +00:00
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/* Acknowledge UART interrupts */
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ti_lib_int_disable(INT_UART0);
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/* Disable all UART module interrupts */
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ti_lib_uart_int_disable(UART0_BASE, CC26XX_UART_INTERRUPT_ALL);
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/* Clear all UART interrupts */
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ti_lib_uart_int_clear(UART0_BASE, CC26XX_UART_INTERRUPT_ALL);
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}
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/*---------------------------------------------------------------------------*/
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static void
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enable_interrupts(void)
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{
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/* Clear all UART interrupts */
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ti_lib_uart_int_clear(UART0_BASE, CC26XX_UART_INTERRUPT_ALL);
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/* Enable RX-related interrupts only if we have an input handler */
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if(input_handler) {
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/* Configure which interrupts to generate: FIFO level or after RX timeout */
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ti_lib_uart_int_enable(UART0_BASE, CC26XX_UART_RX_INTERRUPT_TRIGGERS);
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/* Acknowledge UART interrupts */
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ti_lib_int_enable(INT_UART0);
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}
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2015-02-25 12:09:56 +00:00
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}
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/*---------------------------------------------------------------------------*/
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static void
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2015-05-01 16:03:26 +00:00
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configure(void)
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2015-02-25 12:09:56 +00:00
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{
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2015-05-01 16:03:26 +00:00
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uint32_t ctl_val = UART_CTL_UARTEN | UART_CTL_TXE;
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/*
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* Make sure the TX pin is output / high before assigning it to UART control
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* to avoid falling edge glitches
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*/
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ti_lib_ioc_pin_type_gpio_output(BOARD_IOID_UART_TX);
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ti_lib_gpio_pin_write(BOARD_UART_TX, 1);
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2015-02-25 12:09:56 +00:00
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/*
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* Map UART signals to the correct GPIO pins and configure them as
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* hardware controlled.
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*/
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ti_lib_ioc_pin_type_uart(UART0_BASE, BOARD_IOID_UART_RX, BOARD_IOID_UART_TX,
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BOARD_IOID_UART_CTS, BOARD_IOID_UART_RTS);
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2015-05-01 16:03:26 +00:00
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/* Configure the UART for 115,200, 8-N-1 operation. */
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ti_lib_uart_config_set_exp_clk(UART0_BASE,
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ti_lib_sys_ctrl_peripheral_clock_get(
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PRCM_PERIPH_UART0,
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SYSCTRL_SYSBUS_ON),
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CC26XX_UART_CONF_BAUD_RATE,
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(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
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UART_CONFIG_PAR_NONE));
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2015-02-25 12:09:56 +00:00
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/*
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* Generate an RX interrupt at FIFO 1/2 full.
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* We don't really care about the TX interrupt
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*/
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ti_lib_uart_fifo_level_set(UART0_BASE, UART_FIFO_TX7_8, UART_FIFO_RX4_8);
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2015-05-01 16:03:26 +00:00
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/* Enable FIFOs */
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HWREG(UART0_BASE + UART_O_LCRH) |= UART_LCRH_FEN;
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2015-02-25 12:09:56 +00:00
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2015-05-01 16:03:26 +00:00
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if(input_handler) {
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ctl_val += UART_CTL_RXE;
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2015-02-25 12:09:56 +00:00
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}
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2015-05-01 16:03:26 +00:00
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/* Enable TX, RX (conditionally), and the UART. */
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HWREG(UART0_BASE + UART_O_CTL) = ctl_val;
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2015-02-25 12:09:56 +00:00
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}
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/*---------------------------------------------------------------------------*/
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static void
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lpm_drop_handler(uint8_t mode)
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{
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2015-05-01 16:03:26 +00:00
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/*
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* First, wait for any outstanding TX to complete. If we have an input
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* handler, the SERIAL PD will be kept on and the UART module clock will
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* be enabled under sleep as well as deep sleep. In theory, this means that
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* we shouldn't lose any outgoing bytes, but we actually do on occasion.
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* This byte loss may (or may not) be related to the freezing of IO latches
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* between MCU and AON when we drop to deep sleep. This here is essentially a
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* workaround
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*/
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if(accessible() == true) {
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while(ti_lib_uart_busy(UART0_BASE));
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2015-02-25 12:09:56 +00:00
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}
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/*
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2015-05-01 16:03:26 +00:00
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* If we have a registered input_handler then we need to retain RX
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* capability. Thus, if this is not a shutdown notification and we have an
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* input handler, we do nothing
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2015-02-25 12:09:56 +00:00
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*/
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2015-05-01 16:03:26 +00:00
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if((mode != LPM_MODE_SHUTDOWN) && (input_handler != NULL)) {
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2015-02-25 12:09:56 +00:00
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return;
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}
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2015-05-01 16:03:26 +00:00
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/*
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* If we reach here, we either don't care about staying awake or we have
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* received a shutdown notification
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*
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* Only touch UART registers if the module is powered and clocked
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*/
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if(accessible() == true) {
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/* Disable the module */
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ti_lib_uart_disable(UART0_BASE);
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2015-02-25 12:09:56 +00:00
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2015-05-01 16:03:26 +00:00
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/* Disable all UART interrupts and clear all flags */
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disable_interrupts();
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}
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2015-02-25 12:09:56 +00:00
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2015-05-01 16:03:26 +00:00
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/*
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* Always stop the clock in run mode. Also stop in Sleep and Deep Sleep if
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* this is a request for full shutdown
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*/
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ti_lib_prcm_peripheral_run_disable(PRCM_PERIPH_UART0);
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if(mode == LPM_MODE_SHUTDOWN) {
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ti_lib_prcm_peripheral_sleep_disable(PRCM_PERIPH_UART0);
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ti_lib_prcm_peripheral_deep_sleep_disable(PRCM_PERIPH_UART0);
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}
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2015-02-25 12:09:56 +00:00
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ti_lib_prcm_load_set();
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while(!ti_lib_prcm_load_get());
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2015-05-01 16:03:26 +00:00
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/* Set pins to low leakage configuration in preparation for deep sleep */
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lpm_pin_set_default_state(BOARD_IOID_UART_TX);
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lpm_pin_set_default_state(BOARD_IOID_UART_RX);
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lpm_pin_set_default_state(BOARD_IOID_UART_CTS);
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lpm_pin_set_default_state(BOARD_IOID_UART_RTS);
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}
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/*---------------------------------------------------------------------------*/
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/* Declare a data structure to register with LPM. */
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LPM_MODULE(uart_module, NULL, lpm_drop_handler, NULL, LPM_DOMAIN_NONE);
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/*---------------------------------------------------------------------------*/
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static void
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enable(void)
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{
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power_and_clock();
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2015-02-25 12:09:56 +00:00
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/* Make sure the peripheral is disabled */
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ti_lib_uart_disable(UART0_BASE);
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2015-05-01 16:03:26 +00:00
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/* Disable all UART interrupts and clear all flags */
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disable_interrupts();
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2015-02-25 12:09:56 +00:00
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2015-05-01 16:03:26 +00:00
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/* Setup pins, Baud rate and FIFO levels */
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configure();
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2015-02-25 12:09:56 +00:00
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2015-05-01 16:03:26 +00:00
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/* Enable UART interrupts */
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enable_interrupts();
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}
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/*---------------------------------------------------------------------------*/
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void
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cc26xx_uart_init()
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{
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bool interrupts_disabled;
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2015-02-25 12:09:56 +00:00
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2015-05-01 16:03:26 +00:00
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/* Return early if disabled by user conf or if ports are misconfigured */
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if(usable() == false) {
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return;
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}
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2015-02-25 12:09:56 +00:00
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2015-05-01 16:03:26 +00:00
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/* Disable Interrupts */
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interrupts_disabled = ti_lib_int_master_disable();
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2015-02-25 12:09:56 +00:00
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/* Register ourselves with the LPM module */
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lpm_register_module(&uart_module);
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2015-05-01 16:03:26 +00:00
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/* Only TX and EN to start with. RX will be enabled only if needed */
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input_handler = NULL;
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/*
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* init() won't actually fire up the UART. We turn it on only when (and if)
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* it gets requested, either to enable input or to send out a character
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*
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* Thus, we simply re-enable processor interrupts here
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*/
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if(!interrupts_disabled) {
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ti_lib_int_master_enable();
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}
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2015-02-25 12:09:56 +00:00
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}
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/*---------------------------------------------------------------------------*/
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void
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cc26xx_uart_write_byte(uint8_t c)
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{
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2015-05-01 16:03:26 +00:00
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/* Return early if disabled by user conf or if ports are misconfigured */
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if(usable() == false) {
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2015-02-25 12:09:56 +00:00
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return;
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}
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2015-05-01 16:03:26 +00:00
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if(accessible() == false) {
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enable();
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}
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2015-02-25 12:09:56 +00:00
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ti_lib_uart_char_put(UART0_BASE, c);
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}
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/*---------------------------------------------------------------------------*/
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void
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cc26xx_uart_set_input(int (*input)(unsigned char c))
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{
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input_handler = input;
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2015-05-01 16:03:26 +00:00
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/* Return early if disabled by user conf or if ports are misconfigured */
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if(usable() == false) {
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return;
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}
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if(input == NULL) {
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/* Let the SERIAL PD power down */
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uart_module.domain_lock = LPM_DOMAIN_NONE;
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/* Disable module clocks under sleep and deep sleep */
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ti_lib_prcm_peripheral_sleep_disable(PRCM_PERIPH_UART0);
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ti_lib_prcm_peripheral_deep_sleep_disable(PRCM_PERIPH_UART0);
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} else {
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/* Request the SERIAL PD to stay on during deep sleep */
|
|
|
|
uart_module.domain_lock = LPM_DOMAIN_SERIAL;
|
|
|
|
|
|
|
|
/* Enable module clocks under sleep and deep sleep */
|
|
|
|
ti_lib_prcm_peripheral_sleep_enable(PRCM_PERIPH_UART0);
|
|
|
|
ti_lib_prcm_peripheral_deep_sleep_enable(PRCM_PERIPH_UART0);
|
|
|
|
}
|
|
|
|
|
|
|
|
ti_lib_prcm_load_set();
|
|
|
|
while(!ti_lib_prcm_load_get());
|
|
|
|
|
|
|
|
enable();
|
|
|
|
|
2015-02-25 12:09:56 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
2015-05-01 16:03:26 +00:00
|
|
|
uint8_t
|
|
|
|
cc26xx_uart_busy(void)
|
|
|
|
{
|
|
|
|
/* Return early if disabled by user conf or if ports are misconfigured */
|
|
|
|
if(usable() == false) {
|
|
|
|
return UART_IDLE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If the UART is not accessible, it is not busy */
|
|
|
|
if(accessible() == false) {
|
|
|
|
return UART_IDLE;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ti_lib_uart_busy(UART0_BASE);
|
|
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
2015-02-25 12:09:56 +00:00
|
|
|
void
|
|
|
|
cc26xx_uart_isr(void)
|
|
|
|
{
|
|
|
|
char the_char;
|
|
|
|
uint32_t flags;
|
|
|
|
|
|
|
|
ENERGEST_ON(ENERGEST_TYPE_IRQ);
|
|
|
|
|
2015-05-01 16:03:26 +00:00
|
|
|
power_and_clock();
|
|
|
|
|
2015-02-25 12:09:56 +00:00
|
|
|
/* Read out the masked interrupt status */
|
|
|
|
flags = ti_lib_uart_int_status(UART0_BASE, true);
|
|
|
|
|
|
|
|
/* Clear all UART interrupt flags */
|
|
|
|
ti_lib_uart_int_clear(UART0_BASE, CC26XX_UART_INTERRUPT_ALL);
|
|
|
|
|
|
|
|
if((flags & CC26XX_UART_RX_INTERRUPT_TRIGGERS) != 0) {
|
|
|
|
/*
|
|
|
|
* If this was a FIFO RX or an RX timeout, read all bytes available in the
|
|
|
|
* RX FIFO.
|
|
|
|
*/
|
|
|
|
while(ti_lib_uart_chars_avail(UART0_BASE)) {
|
|
|
|
the_char = ti_lib_uart_char_get_non_blocking(UART0_BASE);
|
|
|
|
|
|
|
|
if(input_handler != NULL) {
|
|
|
|
input_handler((unsigned char)the_char);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
|
|
|
|
}
|