97 lines
3.6 KiB
C
97 lines
3.6 KiB
C
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/*
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* Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
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* to the MC1322x project (http://mc1322x.devl.org)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of libmc1322x: see http://mc1322x.devl.org
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* for details.
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*
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* $Id: isr.h,v 1.1 2010/06/10 14:55:39 maralvira Exp $
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*/
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#ifndef ISR_H
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#define ISR_H
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#define INTBASE (0x80020000)
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#define INTCNTL_OFF (0x0)
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#define INTENNUM_OFF (0x8)
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#define INTDISNUM_OFF (0xC)
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#define INTENABLE_OFF (0x10)
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#define INTSRC_OFF (0x30)
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#define INTFRC_OFF (0x34)
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#define NIPEND_OFF (0x38)
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#define INTCNTL ((volatile uint32_t *) (INTBASE + INTCNTL_OFF))
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#define INTENNUM ((volatile uint32_t *) (INTBASE + INTENNUM_OFF))
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#define INTDISNUM ((volatile uint32_t *) (INTBASE + INTDISNUM_OFF))
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#define INTENABLE ((volatile uint32_t *) (INTBASE + INTENABLE_OFF))
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#define INTSRC ((volatile uint32_t *) (INTBASE + INTSRC_OFF))
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#define INTFRC ((volatile uint32_t *) (INTBASE + INTFRC_OFF))
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#define NIPEND ((volatile uint32_t *) (INTBASE + NIPEND_OFF))
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enum interrupt_nums {
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INT_NUM_ASM = 0,
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INT_NUM_UART1,
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INT_NUM_UART2,
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INT_NUM_CRM,
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INT_NUM_I2C,
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INT_NUM_TMR,
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INT_NUM_SPIF,
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INT_NUM_MACA,
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INT_NUM_SSI,
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INT_NUM_ADC,
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INT_NUM_SPI,
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};
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#define global_irq_disable() (set_bit(*INTCNTL,20))
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#define global_irq_enable() (clear_bit(*INTCNTL,20))
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#define enable_irq(irq) (*INTENNUM = INT_NUM_##irq)
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#define disable_irq(irq) (*INTDISNUM = INT_NUM_##irq)
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#define safe_irq_disable(x) volatile uint32_t saved_irq; saved_irq = *INTENABLE; disable_irq(x)
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#define irq_restore() *INTENABLE = saved_irq
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extern void tmr0_isr(void) __attribute__((weak));
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extern void tmr1_isr(void) __attribute__((weak));
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extern void tmr2_isr(void) __attribute__((weak));
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extern void tmr3_isr(void) __attribute__((weak));
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extern void rtc_isr(void) __attribute__((weak));
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extern void kbi4_isr(void) __attribute__((weak));
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extern void kbi5_isr(void) __attribute__((weak));
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extern void kbi6_isr(void) __attribute__((weak));
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extern void kbi7_isr(void) __attribute__((weak));
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extern void uart1_isr(void) __attribute__((weak));
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extern void maca_isr(void) __attribute__((weak));
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#endif
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