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nes-proj/cpu/x86/drivers/legacy_pc/pci.h

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x86: Add PCI support This patch adds the pci.c and pci.h files, which support access to PCI configuration registers through a function interface. It defines the PCI configuration register access I/O port addresses and the pci_config_addr union and structure to assist in specifying addresses of PCI configuration registers. It also defines the PCI configuration register identifier for PCI BAR0. This patch also adds wrappers for 32-bit 'in' and 'out' port I/O instructions. They were placed in helpers.S, since they may be useful to other modules besides just the PCI support module.
2015-07-03 07:27:11 +00:00
/*
* Copyright (C) 2015, Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef CPU_X86_DRIVERS_LEGACY_PC_PCI_H_
#define CPU_X86_DRIVERS_LEGACY_PC_PCI_H_
#include <stdint.h>
x86: Extend PCI driver module with support for metadata and configuration writes This patch adds the 'meta' field to the generic driver structure to point to optional driver-defined metadata. It also modifies the associated initialization routine to populate it and updates the 16X50 UART driver to use the new initialization routine signature. This patch also adds a function to perform PCI configuration register writes, definitions for the PCI Command configuration register address and some of the bits in that register, and a function to set additional bits in that register. Finally, it adds macros to help with performing MMIO to and from PCI devices.
2015-07-08 20:36:29 +00:00
#include "helpers.h"
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 15:34:02 +00:00
#include <stdlib.h>
#include "prot-domains.h"
x86: Add PCI support This patch adds the pci.c and pci.h files, which support access to PCI configuration registers through a function interface. It defines the PCI configuration register access I/O port addresses and the pci_config_addr union and structure to assist in specifying addresses of PCI configuration registers. It also defines the PCI configuration register identifier for PCI BAR0. This patch also adds wrappers for 32-bit 'in' and 'out' port I/O instructions. They were placed in helpers.S, since they may be useful to other modules besides just the PCI support module.
2015-07-03 07:27:11 +00:00
x86: Add support for PCI BAR1 This patch adds support for PCI BAR1 and also changes the pci_init(), instead of having one function for each `bar` we now set the `bar` to pci_config_addr_t parameter before calling the pci_init() function..
2015-09-10 14:26:00 +00:00
/** PCI configuration register identifier for Base Address Registers */
x86: Add PCI support This patch adds the pci.c and pci.h files, which support access to PCI configuration registers through a function interface. It defines the PCI configuration register access I/O port addresses and the pci_config_addr union and structure to assist in specifying addresses of PCI configuration registers. It also defines the PCI configuration register identifier for PCI BAR0. This patch also adds wrappers for 32-bit 'in' and 'out' port I/O instructions. They were placed in helpers.S, since they may be useful to other modules besides just the PCI support module.
2015-07-03 07:27:11 +00:00
#define PCI_CONFIG_REG_BAR0 0x10
x86: Add support for PCI BAR1 This patch adds support for PCI BAR1 and also changes the pci_init(), instead of having one function for each `bar` we now set the `bar` to pci_config_addr_t parameter before calling the pci_init() function..
2015-09-10 14:26:00 +00:00
#define PCI_CONFIG_REG_BAR1 0x14
x86: Add PCI support This patch adds the pci.c and pci.h files, which support access to PCI configuration registers through a function interface. It defines the PCI configuration register access I/O port addresses and the pci_config_addr union and structure to assist in specifying addresses of PCI configuration registers. It also defines the PCI configuration register identifier for PCI BAR0. This patch also adds wrappers for 32-bit 'in' and 'out' port I/O instructions. They were placed in helpers.S, since they may be useful to other modules besides just the PCI support module.
2015-07-03 07:27:11 +00:00
x86: Add Intel Quark X1000 PCI Interrupt Routing support PCI Interrupt Routing is mapped using Interrupt Queue Agents IRQAGENT[0:3] and aggregating the INT[A:D] interrupts for each PCI-mapped device in the SoC. PCI based interrupts PIRQ[A:H] are then available for consumption by either the 8259 PICs or the IO-APIC, depending on the configuration of the 8 PIRQx Routing Control Registers PIRQ[A:H]. More information about can be find in Intel Quark X1000 datasheet[1] section 21.11. [1] - http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-datasheet.html
2015-10-05 18:38:50 +00:00
/** PCI Interrupt Routing is mapped using Interrupt Queue Agents */
typedef enum {
IRQAGENT0,
IRQAGENT1,
IRQAGENT2,
IRQAGENT3
} IRQAGENT;
/** PCI Interupt Pins */
typedef enum {
INTA,
INTB,
INTC,
INTD
} INTR_PIN;
/**
* PCI based interrupts PIRQ[A:H] are then available for consumption by either
* the 8259 PICs or the IO-APIC.
*/
typedef enum {
PIRQA,
PIRQB,
PIRQC,
PIRQD,
PIRQE,
PIRQF,
PIRQG,
PIRQH,
} PIRQ;
x86: Extend PCI driver module with support for metadata and configuration writes This patch adds the 'meta' field to the generic driver structure to point to optional driver-defined metadata. It also modifies the associated initialization routine to populate it and updates the 16X50 UART driver to use the new initialization routine signature. This patch also adds a function to perform PCI configuration register writes, definitions for the PCI Command configuration register address and some of the bits in that register, and a function to set additional bits in that register. Finally, it adds macros to help with performing MMIO to and from PCI devices.
2015-07-08 20:36:29 +00:00
/** PCI command register bit to enable bus mastering */
#define PCI_CMD_2_BUS_MST_EN BIT(2)
/** PCI command register bit to enable memory space */
#define PCI_CMD_1_MEM_SPACE_EN BIT(1)
x86: Add PCI support This patch adds the pci.c and pci.h files, which support access to PCI configuration registers through a function interface. It defines the PCI configuration register access I/O port addresses and the pci_config_addr union and structure to assist in specifying addresses of PCI configuration registers. It also defines the PCI configuration register identifier for PCI BAR0. This patch also adds wrappers for 32-bit 'in' and 'out' port I/O instructions. They were placed in helpers.S, since they may be useful to other modules besides just the PCI support module.
2015-07-03 07:27:11 +00:00
/**
* PCI configuration address
*
* Refer to Intel Quark SoC X1000 Datasheet, Section 5.5 for more details on
* PCI configuration register access.
*/
typedef union pci_config_addr {
struct {
/** Register/offset number. Least-significant two bits should be zero. */
uint32_t reg_off : 8;
uint32_t func : 3; /**< Function number */
uint32_t dev : 5; /**< Device number */
uint32_t bus : 8; /**< Bus number */
uint32_t : 7;
/** Must be set to perform PCI configuration access. */
uint32_t en_mapping : 1;
};
uint32_t raw;
} pci_config_addr_t;
uint32_t pci_config_read(pci_config_addr_t addr);
x86: Extend PCI driver module with support for metadata and configuration writes This patch adds the 'meta' field to the generic driver structure to point to optional driver-defined metadata. It also modifies the associated initialization routine to populate it and updates the 16X50 UART driver to use the new initialization routine signature. This patch also adds a function to perform PCI configuration register writes, definitions for the PCI Command configuration register address and some of the bits in that register, and a function to set additional bits in that register. Finally, it adds macros to help with performing MMIO to and from PCI devices.
2015-07-08 20:36:29 +00:00
void pci_config_write(pci_config_addr_t addr, uint32_t data);
void pci_command_enable(pci_config_addr_t addr, uint32_t flags);
x86: Add PCI support This patch adds the pci.c and pci.h files, which support access to PCI configuration registers through a function interface. It defines the PCI configuration register access I/O port addresses and the pci_config_addr union and structure to assist in specifying addresses of PCI configuration registers. It also defines the PCI configuration register identifier for PCI BAR0. This patch also adds wrappers for 32-bit 'in' and 'out' port I/O instructions. They were placed in helpers.S, since they may be useful to other modules besides just the PCI support module.
2015-07-03 07:27:11 +00:00
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 15:34:02 +00:00
typedef dom_client_data_t pci_driver_t;
x86: Add generic driver structure and associated initialization code This patch adds a generic device driver structure with a field for referencing an MMIO range. It also provides a structure initialization procedure that initializes the MMIO range field with the value read from the PCI BAR0 register for a device.
2015-07-03 12:03:12 +00:00
x86: Add TSS-based protection domain support This patch extends the protection domain framework with an additional plugin to use Task-State Segment (TSS) structures to offload much of the work of switching protection domains to the CPU. This can save space compared to paging, since paging requires two 4KiB page tables and one 32-byte page table plus one whole-system TSS and an additional 32-byte data structure for each protection domain, whereas the approach implemented by this patch just requires a 128-byte data structure for each protection domain. Only a small number of protection domains will typically be used, so n * 128 < 8328 + (n * 32). For additional information, please refer to cpu/x86/mm/README.md. GCC 6 is introducing named address spaces for the FS and GS segments [1]. LLVM Clang also provides address spaces for the FS and GS segments [2]. This patch also adds support to the multi-segment X86 memory management subsystem for using these features instead of inline assembly blocks, which enables type checking to detect some address space mismatches. [1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html [2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
2015-08-07 22:43:10 +00:00
void pci_init(pci_driver_t ATTR_KERN_ADDR_SPACE *c_this,
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 15:34:02 +00:00
pci_config_addr_t pci_addr,
size_t mmio_sz,
uintptr_t meta,
size_t meta_sz);
void pci_irq_agent_set_pirq(IRQAGENT agent, INTR_PIN pin, PIRQ pirq);
x86: Add Intel Quark X1000 PCI Interrupt Routing support PCI Interrupt Routing is mapped using Interrupt Queue Agents IRQAGENT[0:3] and aggregating the INT[A:D] interrupts for each PCI-mapped device in the SoC. PCI based interrupts PIRQ[A:H] are then available for consumption by either the 8259 PICs or the IO-APIC, depending on the configuration of the 8 PIRQx Routing Control Registers PIRQ[A:H]. More information about can be find in Intel Quark X1000 datasheet[1] section 21.11. [1] - http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-datasheet.html
2015-10-05 18:38:50 +00:00
void pci_pirq_set_irq(PIRQ pirq, uint8_t irq, uint8_t route_to_legacy);
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 15:34:02 +00:00
void pci_root_complex_init(void);
void pci_root_complex_lock(void);
x86: Add generic driver structure and associated initialization code This patch adds a generic device driver structure with a field for referencing an MMIO range. It also provides a structure initialization procedure that initializes the MMIO range field with the value read from the PCI BAR0 register for a device.
2015-07-03 12:03:12 +00:00
x86: Extend PCI driver module with support for metadata and configuration writes This patch adds the 'meta' field to the generic driver structure to point to optional driver-defined metadata. It also modifies the associated initialization routine to populate it and updates the 16X50 UART driver to use the new initialization routine signature. This patch also adds a function to perform PCI configuration register writes, definitions for the PCI Command configuration register address and some of the bits in that register, and a function to set additional bits in that register. Finally, it adds macros to help with performing MMIO to and from PCI devices.
2015-07-08 20:36:29 +00:00
#define PCI_MMIO_READL(c_this, dest, reg_addr) \
x86: Add TSS-based protection domain support This patch extends the protection domain framework with an additional plugin to use Task-State Segment (TSS) structures to offload much of the work of switching protection domains to the CPU. This can save space compared to paging, since paging requires two 4KiB page tables and one 32-byte page table plus one whole-system TSS and an additional 32-byte data structure for each protection domain, whereas the approach implemented by this patch just requires a 128-byte data structure for each protection domain. Only a small number of protection domains will typically be used, so n * 128 < 8328 + (n * 32). For additional information, please refer to cpu/x86/mm/README.md. GCC 6 is introducing named address spaces for the FS and GS segments [1]. LLVM Clang also provides address spaces for the FS and GS segments [2]. This patch also adds support to the multi-segment X86 memory management subsystem for using these features instead of inline assembly blocks, which enables type checking to detect some address space mismatches. [1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html [2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
2015-08-07 22:43:10 +00:00
MMIO_READL(dest, \
*((volatile uint32_t ATTR_MMIO_ADDR_SPACE *) \
(((uintptr_t)PROT_DOMAINS_MMIO(c_this)) + (reg_addr))))
x86: Extend PCI driver module with support for metadata and configuration writes This patch adds the 'meta' field to the generic driver structure to point to optional driver-defined metadata. It also modifies the associated initialization routine to populate it and updates the 16X50 UART driver to use the new initialization routine signature. This patch also adds a function to perform PCI configuration register writes, definitions for the PCI Command configuration register address and some of the bits in that register, and a function to set additional bits in that register. Finally, it adds macros to help with performing MMIO to and from PCI devices.
2015-07-08 20:36:29 +00:00
#define PCI_MMIO_WRITEL(c_this, reg_addr, src) \
x86: Add TSS-based protection domain support This patch extends the protection domain framework with an additional plugin to use Task-State Segment (TSS) structures to offload much of the work of switching protection domains to the CPU. This can save space compared to paging, since paging requires two 4KiB page tables and one 32-byte page table plus one whole-system TSS and an additional 32-byte data structure for each protection domain, whereas the approach implemented by this patch just requires a 128-byte data structure for each protection domain. Only a small number of protection domains will typically be used, so n * 128 < 8328 + (n * 32). For additional information, please refer to cpu/x86/mm/README.md. GCC 6 is introducing named address spaces for the FS and GS segments [1]. LLVM Clang also provides address spaces for the FS and GS segments [2]. This patch also adds support to the multi-segment X86 memory management subsystem for using these features instead of inline assembly blocks, which enables type checking to detect some address space mismatches. [1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html [2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
2015-08-07 22:43:10 +00:00
MMIO_WRITEL(*((volatile uint32_t ATTR_MMIO_ADDR_SPACE *) \
(((uintptr_t)PROT_DOMAINS_MMIO(c_this)) + (reg_addr))), \
src)
x86: Extend PCI driver module with support for metadata and configuration writes This patch adds the 'meta' field to the generic driver structure to point to optional driver-defined metadata. It also modifies the associated initialization routine to populate it and updates the 16X50 UART driver to use the new initialization routine signature. This patch also adds a function to perform PCI configuration register writes, definitions for the PCI Command configuration register address and some of the bits in that register, and a function to set additional bits in that register. Finally, it adds macros to help with performing MMIO to and from PCI devices.
2015-07-08 20:36:29 +00:00
x86: Add PCI support This patch adds the pci.c and pci.h files, which support access to PCI configuration registers through a function interface. It defines the PCI configuration register access I/O port addresses and the pci_config_addr union and structure to assist in specifying addresses of PCI configuration registers. It also defines the PCI configuration register identifier for PCI BAR0. This patch also adds wrappers for 32-bit 'in' and 'out' port I/O instructions. They were placed in helpers.S, since they may be useful to other modules besides just the PCI support module.
2015-07-03 07:27:11 +00:00
#endif /* CPU_X86_DRIVERS_LEGACY_PC_PCI_H_ */
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