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nes-proj/cpu/x86/drivers/legacy_pc/pic.h

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x86: Initialize the 8259 PIC The Programmable Interrupt Controller is a chip responsible for translating hardware interrupts to system interrupts. When it receives an Interrupt Request (IRQ), it triggers the appropriate interrupt line reaching the appropriate IDT gate, following a previously setup offset. There are 2 daisy-chained PICs. PIC1 handles IRQs 0-7 and PIC2 handles IRQs 8-15. If no vector offset is set, an IRQ0, for instance, would trigger the interrupt 0, clashing with the "Division by zero exception" handler. Thus the IRQs must be remapped. This patch implements the PICs initialization through their 4 Initialization Command Words (ICWs) in a very "canonical" way: - ICW1: the initializing command; - ICW2: the vector offset for the PIC1 and PIC2 (we add an offset of 32 positions); - ICW3: the inter-PICs wiring setup (we connect PIC2 to PIC1's IRQ2); - ICW4: extra systems information (we set PIC1 as Master and PIC2 as slave). It then masks the Interrupt Mask Register, blocking all IRQs but #2 initially. These must be unmasked on demand. The IMR is 8-bits long, so setting the n^th bit to 1 would DISABLE the IRQ n while setting it to 0 would ENABLE IRQ n. As stated, this is an implementation of the legacy 8259 PIC. More investigation is needed so we decide if it is enough or if we need the (newer) APIC implementation instead. This patch also adds the outb() helper function to helpers.h. The helpers is a wrapper for assembly 'out' instruction. Finally, since we now properly support hardware interrupts, this patch also enables IRQs in platform main(). More information: - Quark X1000 Datasheet, section 21.12, page 898. - http://wiki.osdev.org/8259_PIC - http://stanislavs.org/helppc/8259.html
2015-04-08 20:18:27 +00:00
/*
* Copyright (C) 2015, Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef PIC_H
#define PIC_H
#include "helpers.h"
#define PIC1_CMD_PORT 0x20
#define PIC1_DATA_PORT 0x21
#define PIC2_CMD_PORT 0xA0
#define PIC2_DATA_PORT 0xA1
x86: Add APIs to 8259 PIC driver This commit implements pic_eoi(int irq) and a helper macro PIC_INT(irq). This first checks which PICs should be 'acked' given an IRQ number, while the macro returns the actual system interrupt number for the IRQ according to the offset used on the PIC initialization.
2015-07-02 21:24:20 +00:00
#define PIC1_OFFSET 0x20
#define PIC2_OFFSET PIC1_OFFSET + 8
/*
* Returns the actual interrupt number of a given IRQ,
* no matter which PIC it is part of.
*/
#define PIC_INT(a) (a + PIC1_OFFSET)
x86: Initialize the 8259 PIC The Programmable Interrupt Controller is a chip responsible for translating hardware interrupts to system interrupts. When it receives an Interrupt Request (IRQ), it triggers the appropriate interrupt line reaching the appropriate IDT gate, following a previously setup offset. There are 2 daisy-chained PICs. PIC1 handles IRQs 0-7 and PIC2 handles IRQs 8-15. If no vector offset is set, an IRQ0, for instance, would trigger the interrupt 0, clashing with the "Division by zero exception" handler. Thus the IRQs must be remapped. This patch implements the PICs initialization through their 4 Initialization Command Words (ICWs) in a very "canonical" way: - ICW1: the initializing command; - ICW2: the vector offset for the PIC1 and PIC2 (we add an offset of 32 positions); - ICW3: the inter-PICs wiring setup (we connect PIC2 to PIC1's IRQ2); - ICW4: extra systems information (we set PIC1 as Master and PIC2 as slave). It then masks the Interrupt Mask Register, blocking all IRQs but #2 initially. These must be unmasked on demand. The IMR is 8-bits long, so setting the n^th bit to 1 would DISABLE the IRQ n while setting it to 0 would ENABLE IRQ n. As stated, this is an implementation of the legacy 8259 PIC. More investigation is needed so we decide if it is enough or if we need the (newer) APIC implementation instead. This patch also adds the outb() helper function to helpers.h. The helpers is a wrapper for assembly 'out' instruction. Finally, since we now properly support hardware interrupts, this patch also enables IRQs in platform main(). More information: - Quark X1000 Datasheet, section 21.12, page 898. - http://wiki.osdev.org/8259_PIC - http://stanislavs.org/helppc/8259.html
2015-04-08 20:18:27 +00:00
x86: Add pic_unmask_irq() helper This patch implements the pic_unmask_irq() helper and uses it where applicable. This function zeros the corresponding bit from the IRQ number in IMR register. This patch doesn't implement the pic_mask_irq() helper since it is not useful at this moment.
2015-07-02 20:46:47 +00:00
void pic_unmask_irq(unsigned int num);
x86: Initialize the 8259 PIC The Programmable Interrupt Controller is a chip responsible for translating hardware interrupts to system interrupts. When it receives an Interrupt Request (IRQ), it triggers the appropriate interrupt line reaching the appropriate IDT gate, following a previously setup offset. There are 2 daisy-chained PICs. PIC1 handles IRQs 0-7 and PIC2 handles IRQs 8-15. If no vector offset is set, an IRQ0, for instance, would trigger the interrupt 0, clashing with the "Division by zero exception" handler. Thus the IRQs must be remapped. This patch implements the PICs initialization through their 4 Initialization Command Words (ICWs) in a very "canonical" way: - ICW1: the initializing command; - ICW2: the vector offset for the PIC1 and PIC2 (we add an offset of 32 positions); - ICW3: the inter-PICs wiring setup (we connect PIC2 to PIC1's IRQ2); - ICW4: extra systems information (we set PIC1 as Master and PIC2 as slave). It then masks the Interrupt Mask Register, blocking all IRQs but #2 initially. These must be unmasked on demand. The IMR is 8-bits long, so setting the n^th bit to 1 would DISABLE the IRQ n while setting it to 0 would ENABLE IRQ n. As stated, this is an implementation of the legacy 8259 PIC. More investigation is needed so we decide if it is enough or if we need the (newer) APIC implementation instead. This patch also adds the outb() helper function to helpers.h. The helpers is a wrapper for assembly 'out' instruction. Finally, since we now properly support hardware interrupts, this patch also enables IRQs in platform main(). More information: - Quark X1000 Datasheet, section 21.12, page 898. - http://wiki.osdev.org/8259_PIC - http://stanislavs.org/helppc/8259.html
2015-04-08 20:18:27 +00:00
/* This function initializes the daisy-chained Master and Slave 8259 PICs.
* It is only called once, so let's give the compiler the option to inline it.
* For more information about the ICWs, please refer to http://stanislavs.org/helppc/8259.html.
*/
static inline void
pic_init(void)
{
/* ICW1: Initialization. */
outb(PIC1_CMD_PORT, 0x11);
outb(PIC2_CMD_PORT, 0x11);
/* ICW2: Remap IRQs by setting an IDT Offset for each PIC. */
x86: Add APIs to 8259 PIC driver This commit implements pic_eoi(int irq) and a helper macro PIC_INT(irq). This first checks which PICs should be 'acked' given an IRQ number, while the macro returns the actual system interrupt number for the IRQ according to the offset used on the PIC initialization.
2015-07-02 21:24:20 +00:00
outb(PIC1_DATA_PORT, PIC1_OFFSET);
outb(PIC2_DATA_PORT, PIC2_OFFSET);
x86: Initialize the 8259 PIC The Programmable Interrupt Controller is a chip responsible for translating hardware interrupts to system interrupts. When it receives an Interrupt Request (IRQ), it triggers the appropriate interrupt line reaching the appropriate IDT gate, following a previously setup offset. There are 2 daisy-chained PICs. PIC1 handles IRQs 0-7 and PIC2 handles IRQs 8-15. If no vector offset is set, an IRQ0, for instance, would trigger the interrupt 0, clashing with the "Division by zero exception" handler. Thus the IRQs must be remapped. This patch implements the PICs initialization through their 4 Initialization Command Words (ICWs) in a very "canonical" way: - ICW1: the initializing command; - ICW2: the vector offset for the PIC1 and PIC2 (we add an offset of 32 positions); - ICW3: the inter-PICs wiring setup (we connect PIC2 to PIC1's IRQ2); - ICW4: extra systems information (we set PIC1 as Master and PIC2 as slave). It then masks the Interrupt Mask Register, blocking all IRQs but #2 initially. These must be unmasked on demand. The IMR is 8-bits long, so setting the n^th bit to 1 would DISABLE the IRQ n while setting it to 0 would ENABLE IRQ n. As stated, this is an implementation of the legacy 8259 PIC. More investigation is needed so we decide if it is enough or if we need the (newer) APIC implementation instead. This patch also adds the outb() helper function to helpers.h. The helpers is a wrapper for assembly 'out' instruction. Finally, since we now properly support hardware interrupts, this patch also enables IRQs in platform main(). More information: - Quark X1000 Datasheet, section 21.12, page 898. - http://wiki.osdev.org/8259_PIC - http://stanislavs.org/helppc/8259.html
2015-04-08 20:18:27 +00:00
/* ICW3: Setup Slave to Master's IRQ2. */
outb(PIC1_DATA_PORT, 0x04);
outb(PIC2_DATA_PORT, 0x02);
/* ICW4: Environment setup. Set PIC1 as master and PIC2 as slave. */
outb(PIC1_DATA_PORT, 0x01);
outb(PIC2_DATA_PORT, 0x01);
/* Set the IMR register, masking all hardware interrupts but IRQ 2.
* We will have to unmask each IRQ when registering them. */
outb(PIC1_DATA_PORT, 0xfb);
outb(PIC2_DATA_PORT, 0xff);
}
x86: Add APIs to 8259 PIC driver This commit implements pic_eoi(int irq) and a helper macro PIC_INT(irq). This first checks which PICs should be 'acked' given an IRQ number, while the macro returns the actual system interrupt number for the IRQ according to the offset used on the PIC initialization.
2015-07-02 21:24:20 +00:00
/*
* This function sends an end-of-interrupt (EOI) to the correct PIC according
* to the IRQ line number.
*/
void pic_eoi(unsigned int irq);
x86: Initialize the 8259 PIC The Programmable Interrupt Controller is a chip responsible for translating hardware interrupts to system interrupts. When it receives an Interrupt Request (IRQ), it triggers the appropriate interrupt line reaching the appropriate IDT gate, following a previously setup offset. There are 2 daisy-chained PICs. PIC1 handles IRQs 0-7 and PIC2 handles IRQs 8-15. If no vector offset is set, an IRQ0, for instance, would trigger the interrupt 0, clashing with the "Division by zero exception" handler. Thus the IRQs must be remapped. This patch implements the PICs initialization through their 4 Initialization Command Words (ICWs) in a very "canonical" way: - ICW1: the initializing command; - ICW2: the vector offset for the PIC1 and PIC2 (we add an offset of 32 positions); - ICW3: the inter-PICs wiring setup (we connect PIC2 to PIC1's IRQ2); - ICW4: extra systems information (we set PIC1 as Master and PIC2 as slave). It then masks the Interrupt Mask Register, blocking all IRQs but #2 initially. These must be unmasked on demand. The IMR is 8-bits long, so setting the n^th bit to 1 would DISABLE the IRQ n while setting it to 0 would ENABLE IRQ n. As stated, this is an implementation of the legacy 8259 PIC. More investigation is needed so we decide if it is enough or if we need the (newer) APIC implementation instead. This patch also adds the outb() helper function to helpers.h. The helpers is a wrapper for assembly 'out' instruction. Finally, since we now properly support hardware interrupts, this patch also enables IRQs in platform main(). More information: - Quark X1000 Datasheet, section 21.12, page 898. - http://wiki.osdev.org/8259_PIC - http://stanislavs.org/helppc/8259.html
2015-04-08 20:18:27 +00:00
#endif /* PIC_H */
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