177 lines
8.8 KiB
C
177 lines
8.8 KiB
C
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/*
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* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538-rfcore
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* @{
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*
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* \file
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* Header with declarations of the RF Core SFR registers. Includes
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* declarations of MAC timer registers.
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*/
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#ifndef RFCORE_SFR_H_
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#define RFCORE_SFR_H_
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR register offsets (MAC Timer)
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* @{
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*/
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#define RFCORE_SFR_MTCSPCFG 0x40088800 /**< MAC Timer event configuration */
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#define RFCORE_SFR_MTCTRL 0x40088804 /**< MAC Timer control register */
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#define RFCORE_SFR_MTIRQM 0x40088808 /**< MAC Timer interrupt mask */
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#define RFCORE_SFR_MTIRQF 0x4008880C /**< MAC Timer interrupt flags */
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#define RFCORE_SFR_MTMSEL 0x40088810 /**< MAC Timer multiplex select */
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#define RFCORE_SFR_MTM0 0x40088814 /**< MAC Timer MUX register 0 */
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#define RFCORE_SFR_MTM1 0x40088818 /**< MAC Timer MUX register 1 */
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#define RFCORE_SFR_MTMOVF2 0x4008881C /**< MAC Timer MUX overflow 2 */
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#define RFCORE_SFR_MTMOVF1 0x40088820 /**< MAC Timer MUX overflow 1 */
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#define RFCORE_SFR_MTMOVF0 0x40088824 /**< MAC Timer MUX overflow 0 */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR register offsets (RF)
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* @{
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*/
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#define RFCORE_SFR_RFDATA 0x40088828 /**< TX/RX FIFO data */
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#define RFCORE_SFR_RFERRF 0x4008882C /**< RF error interrupt flags */
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#define RFCORE_SFR_RFIRQF1 0x40088830 /**< RF interrupt flags */
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#define RFCORE_SFR_RFIRQF0 0x40088834 /**< RF interrupt flags */
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#define RFCORE_SFR_RFST 0x40088838 /**< RF CSMA-CA/strobe processor */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR_MTCSPCFG register bit masks
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* @{
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*/
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#define RFCORE_SFR_MTCSPCFG_MACTIMER_EVENMT_CFG 0x00000070 /**< MT_EVENT2 pulse event trigger */
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#define RFCORE_SFR_MTCSPCFG_MACTIMER_EVENT1_CFG 0x00000007 /**< MT_EVENT1 pulse event trigger */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR_MTCTRL register bit masks
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* @{
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*/
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#define RFCORE_SFR_MTCTRL_LATCH_MODE 0x00000008 /**< OVF counter latch mode */
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#define RFCORE_SFR_MTCTRL_STATE 0x00000004 /**< State of MAC Timer */
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#define RFCORE_SFR_MTCTRL_SYNC 0x00000002 /**< Timer start/stop timing */
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#define RFCORE_SFR_MTCTRL_RUN 0x00000001 /**< Timer start/stop */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR_MTIRQM register bit masks
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* @{
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*/
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#define RFCORE_SFR_MTIRQM_MACTIMER_OVF_COMPARE2M 0x00000020 /**< MACTIMER_OVF_COMPARE2 mask */
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#define RFCORE_SFR_MTIRQM_MACTIMER_OVF_COMPARE1M 0x00000010 /**< MACTIMER_OVF_COMPARE1 mask */
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#define RFCORE_SFR_MTIRQM_MACTIMER_OVF_PERM 0x00000008 /**< MACTIMER_OVF_PER mask */
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#define RFCORE_SFR_MTIRQM_MACTIMER_COMPARE2M 0x00000004 /**< MACTIMER_COMPARE2 mask */
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#define RFCORE_SFR_MTIRQM_MACTIMER_COMPARE1M 0x00000002 /**< MACTIMER_COMPARE1 mask */
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#define RFCORE_SFR_MTIRQM_MACTIMER_PERM 0x00000001 /**< MACTIMER_PER mask */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR_MTIRQF register bit masks
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* @{
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*/
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#define RFCORE_SFR_MTIRQF_MACTIMER_OVF_COMPARE2F 0x00000020 /**< MACTIMER_OVF_COMPARE2 flag */
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#define RFCORE_SFR_MTIRQF_MACTIMER_OVF_COMPARE1F 0x00000010 /**< MACTIMER_OVF_COMPARE1 flag */
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#define RFCORE_SFR_MTIRQF_MACTIMER_OVF_PERF 0x00000008 /**< MACTIMER_OVF_PER flag */
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#define RFCORE_SFR_MTIRQF_MACTIMER_COMPARE2F 0x00000004 /**< MACTIMER_COMPARE2 flag */
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#define RFCORE_SFR_MTIRQF_MACTIMER_COMPARE1F 0x00000002 /**< MACTIMER_COMPARE1 flag */
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#define RFCORE_SFR_MTIRQF_MACTIMER_PERF 0x00000001 /**< MACTIMER_PER flag */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR_MTMSEL register bit masks
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* @{
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*/
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#define RFCORE_SFR_MTMSEL_MTMOVFSEL 0x00000070 /**< MTMOVF register select */
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#define RFCORE_SFR_MTMSEL_MTMSEL 0x00000007 /**< MTM register select */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR_MTM[0:2] register bit masks
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* @{
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*/
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#define RFCORE_SFR_MTM0_MTM0 0x000000FF /**< Register[7:0] */
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#define RFCORE_SFR_MTM1_MTM1 0x000000FF /**< Register[15:8] */
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#define RFCORE_SFR_MTMOVF2_MTMOVF2 0x000000FF /**< Register[23:16] */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR_MTMOVF[1:0] register bit masks
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* @{
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*/
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#define RFCORE_SFR_MTMOVF1_MTMOVF1 0x000000FF /**< Register[15:8] */
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#define RFCORE_SFR_MTMOVF0_MTMOVF0 0x000000FF /**< Register[7:0] */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR_RFDATA register bit masks
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* @{
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*/
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#define RFCORE_SFR_RFDATA_RFD 0x000000FF /**< Read/Write Data from RF FIFO */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR_RFERRF register bit masks
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* @{
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*/
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#define RFCORE_SFR_RFERRF_STROBEERR 0x00000040 /**< Strobe error */
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#define RFCORE_SFR_RFERRF_TXUNDERF 0x00000020 /**< TX FIFO underflowed */
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#define RFCORE_SFR_RFERRF_TXOVERF 0x00000010 /**< TX FIFO overflowed */
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#define RFCORE_SFR_RFERRF_RXUNDERF 0x00000008 /**< RX FIFO underflowed */
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#define RFCORE_SFR_RFERRF_RXOVERF 0x00000004 /**< RX FIFO overflowed */
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#define RFCORE_SFR_RFERRF_RXABO 0x00000002 /**< Frame RX was aborted */
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#define RFCORE_SFR_RFERRF_NLOCK 0x00000001 /**< Frequency synthesizer lock error */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR_RFIRQF1 register bit masks
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* @{
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*/
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#define RFCORE_SFR_RFIRQF1_CSP_WAIT 0x00000020 /**< CSP Execution continued */
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#define RFCORE_SFR_RFIRQF1_CSP_STOP 0x00000010 /**< CSP has stopped program */
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#define RFCORE_SFR_RFIRQF1_CSP_MANINT 0x00000008 /**< CSP Manual interrupt */
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#define RFCORE_SFR_RFIRQF1_RFIDLE 0x00000004 /**< IDLE state entered */
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#define RFCORE_SFR_RFIRQF1_TXDONE 0x00000002 /**< Complete frame TX finished */
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#define RFCORE_SFR_RFIRQF1_TXACKDONE 0x00000001 /**< ACK frame TX finished */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR_RFIRQF0 register bit masks
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* @{
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*/
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#define RFCORE_SFR_RFIRQF0_RXMASKZERO 0x00000080 /**< RXENABLE gone all-zero */
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#define RFCORE_SFR_RFIRQF0_RXPKTDONE 0x00000040 /**< Complete frame RX */
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#define RFCORE_SFR_RFIRQF0_FRAME_ACCEPTED 0x00000020 /**< Frame has passed frame filter */
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#define RFCORE_SFR_RFIRQF0_SRC_MATCH_FOUND 0x00000010 /**< Source match is found */
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#define RFCORE_SFR_RFIRQF0_SRC_MATCH_DONE 0x00000008 /**< Source matching is complete */
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#define RFCORE_SFR_RFIRQF0_FIFOP 0x00000004 /**< RX FIFO exceeded threshold */
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#define RFCORE_SFR_RFIRQF0_SFD 0x00000002 /**< SFD TX or RX */
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#define RFCORE_SFR_RFIRQF0_ACT_UNUSED 0x00000001 /**< Reserved */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name RFCORE_SFR_RFST register bit masks
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* @{
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*/
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#define RFCORE_SFR_RFST_INSTR 0x000000FF /**< Data written to this register */
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/** @} */
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#endif /* RFCORE_SFR_H_ */
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/** @} */
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