499 lines
16 KiB
ArmAsm
499 lines
16 KiB
ArmAsm
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/***********************************************************************/
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/* */
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/* startup_SAM7S.S: Startup file for Atmel AT91SAM7S device series */
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/* */
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/***********************************************************************/
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/* ported to arm-elf-gcc / WinARM by Martin Thomas, KL, .de */
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/* <eversmith@heizung-thomas.de> */
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/* modifications Copyright Martin Thomas 2005 */
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/* */
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/* Based on a file that has been a part of the uVision/ARM */
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/* development tools, Copyright KEIL ELEKTRONIK GmbH 2002-2004 */
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/***********************************************************************/
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/*
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Modifications by Martin Thomas:
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- added handling of execption vectors in RAM ("ramfunc")
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- added options to remap the interrupt vectors to RAM
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(see makefile for switch-option)
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- replaced all ";" and "#" for comments with // or / * * /
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- added C++ ctor handling
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- .text in RAM for debugging (RAM_RUN)
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*/
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/*
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Modifications by Simon Berg
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- added stack segment
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- running program as system by defining RUN_AS_SYSTEM
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*/
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// mt: this file should not be used with the Configuration Wizard
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// since a lot of changes have been done for the WinARM/gcc example
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/*
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// *** <<< Use Configuration Wizard in Context Menu >>> ***
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*/
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// *** Startup Code (executed after Reset) ***
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// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
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.equ Mode_USR, 0x10
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.equ Mode_FIQ, 0x11
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.equ Mode_IRQ, 0x12
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.equ Mode_SVC, 0x13
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.equ Mode_ABT, 0x17
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.equ Mode_UND, 0x1B
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.equ Mode_SYS, 0x1F
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.equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
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.equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
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// Internal Memory Base Addresses
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.equ FLASH_BASE, 0x00100000
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.equ RAM_BASE, 0x00200000
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/*
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// <h> Stack Configuration
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// <o> Top of Stack Address <0x0-0xFFFFFFFF:4>
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// <h> Stack Sizes (in Bytes)
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// <o1> Undefined Mode <0x0-0xFFFFFFFF:4>
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// <o2> Supervisor Mode <0x0-0xFFFFFFFF:4>
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// <o3> Abort Mode <0x0-0xFFFFFFFF:4>
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// <o4> Fast Interrupt Mode <0x0-0xFFFFFFFF:4>
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// <o5> Interrupt Mode <0x0-0xFFFFFFFF:4>
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// <o6> User/System Mode <0x0-0xFFFFFFFF:4>
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// </h>
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// </h>
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*/
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.equ Top_Stack, 0x00204000
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.equ UND_Stack_Size, 0x00000004
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.equ SVC_Stack_Size, 0x00000400
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.equ ABT_Stack_Size, 0x00000004
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.equ FIQ_Stack_Size, 0x00000004
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.equ IRQ_Stack_Size, 0x00000400
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.equ USR_Stack_Size, 0x00000400
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.bss
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.section .stack , "aw", %nobits
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USR_Stack_Start:
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.skip USR_Stack_Size
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USR_Stack_End:
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IRQ_Stack_Start:
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.skip IRQ_Stack_Size
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IRQ_Stack_End:
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FIQ_Stack_Start:
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.skip FIQ_Stack_Size
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FIQ_Stack_End:
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ABT_Stack_Start:
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.skip ABT_Stack_Size
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ABT_Stack_End:
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SVC_Stack_Start:
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.skip SVC_Stack_Size
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SVC_Stack_End:
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UND_Stack_Start:
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.skip UND_Stack_Size
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UND_Stack_End:
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// Embedded Flash Controller (EFC) definitions
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.equ EFC_BASE, 0xFFFFFF00 /* EFC Base Address */
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.equ EFC_FMR, 0x60 /* EFC_FMR Offset */
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/*
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// <e> Embedded Flash Controller (EFC)
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// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255>
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// <i> Number of Master Clock Cycles in 1us
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// <o1.8..9> FWS: Flash Wait State
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// <0=> Read: 1 cycle / Write: 2 cycles
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// <1=> Read: 2 cycle / Write: 3 cycles
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// <2=> Read: 3 cycle / Write: 4 cycles
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// <3=> Read: 4 cycle / Write: 4 cycles
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// </e>
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*/
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.equ EFC_SETUP, 1
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.equ EFC_FMR_Val, 0x00320100
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// Watchdog Timer (WDT) definitions
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.equ WDT_BASE, 0xFFFFFD40 /* WDT Base Address */
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.equ WDT_MR, 0x04 /* WDT_MR Offset */
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/*
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// <e> Watchdog Timer (WDT)
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// <o1.0..11> WDV: Watchdog Counter Value <0-4095>
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// <o1.16..27> WDD: Watchdog Delta Value <0-4095>
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// <o1.12> WDFIEN: Watchdog Fault Interrupt Enable
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// <o1.13> WDRSTEN: Watchdog Reset Enable
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// <o1.14> WDRPROC: Watchdog Reset Processor
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// <o1.28> WDDBGHLT: Watchdog Debug Halt
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// <o1.29> WDIDLEHLT: Watchdog Idle Halt
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// <o1.15> WDDIS: Watchdog Disable
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// </e>
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*/
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.equ WDT_SETUP, 1
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.equ WDT_MR_Val, 0x00008000 // Disable watchdog
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// Power Mangement Controller (PMC) definitions
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.equ PMC_BASE, 0xFFFFFC00 /* PMC Base Address */
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.equ PMC_MOR, 0x20 /* PMC_MOR Offset */
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.equ PMC_MCFR, 0x24 /* PMC_MCFR Offset */
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.equ PMC_PLLR, 0x2C /* PMC_PLLR Offset */
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.equ PMC_MCKR, 0x30 /* PMC_MCKR Offset */
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.equ PMC_SR, 0x68 /* PMC_SR Offset */
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.equ PMC_MOSCEN, (1<<0) /* Main Oscillator Enable */
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.equ PMC_OSCBYPASS, (1<<1) /* Main Oscillator Bypass */
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.equ PMC_OSCOUNT, (0xFF<<8) /* Main OScillator Start-up Time */
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.equ PMC_DIV, (0xFF<<0) /* PLL Divider */
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.equ PMC_PLLCOUNT, (0x3F<<8) /* PLL Lock Counter */
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.equ PMC_OUT, (0x03<<14) /* PLL Clock Frequency Range */
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.equ PMC_MUL, (0x7FF<<16) /* PLL Multiplier */
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.equ PMC_USBDIV, (0x03<<28) /* USB Clock Divider */
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.equ PMC_CSS, (3<<0) /* Clock Source Selection */
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.equ PMC_PRES, (7<<2) /* Prescaler Selection */
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.equ PMC_MOSCS, (1<<0) /* Main Oscillator Stable */
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.equ PMC_LOCK, (1<<2) /* PLL Lock Status */
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/*
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// <e> Power Mangement Controller (PMC)
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// <h> Main Oscillator
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// <o1.0> MOSCEN: Main Oscillator Enable
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// <o1.1> OSCBYPASS: Oscillator Bypass
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// <o1.8..15> OSCCOUNT: Main Oscillator Startup Time <0-255>
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// </h>
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// <h> Phase Locked Loop (PLL)
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// <o2.0..7> DIV: PLL Divider <0-255>
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// <o2.16..26> MUL: PLL Multiplier <0-2047>
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// <i> PLL Output is multiplied by MUL+1
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// <o2.14..15> OUT: PLL Clock Frequency Range
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// <0=> 80..160MHz <1=> Reserved
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// <2=> 150..220MHz <3=> Reserved
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// <o2.8..13> PLLCOUNT: PLL Lock Counter <0-63>
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// <o2.28..29> USBDIV: USB Clock Divider
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// <0=> None <1=> 2 <2=> 4 <3=> Reserved
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// </h>
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// <o3.0..1> CSS: Clock Source Selection
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// <0=> Slow Clock
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// <1=> Main Clock
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// <2=> Reserved
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// <3=> PLL Clock
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// <o3.2..4> PRES: Prescaler
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// <0=> None
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// <1=> Clock / 2 <2=> Clock / 4
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// <3=> Clock / 8 <4=> Clock / 16
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// <5=> Clock / 32 <6=> Clock / 64
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// <7=> Reserved
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// </e>
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*/
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.equ PMC_SETUP, 1
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.equ PMC_MOR_Val, 0x00000601 /* Enable main oscilator,
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48 cycles startup */
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.equ PMC_PLLR_Val, 0x00191C05 /* 28 cycles startup,
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PLL = 5.2* * main clock */
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.equ PMC_MCKR_Val, 0x0000000B /* MCK = PLL/4 */
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/* Reset controller */
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.equ RSTC_BASE, 0xfffffd00
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.equ RSTC_CR, 0x00
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.equ RSTC_SR, 0x04
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.equ RSTC_MR, 0x08
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.equ RSTC_SETUP, 1
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.equ RSTC_MR_Val, 0xa5000001 /* Enable user reset */
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#if (defined(VECTORS_IN_RAM) && defined(ROM_RUN)) || defined(USE_SAMBA)
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/*
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Exception Vectors to be placed in RAM - added by mt
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-> will be used after remapping in ROM_RUN
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-> not needed for RAM_RUN
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-> moved to address 0 after remapping
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Mapped to Address 0 after remapping in ROM_RUN
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Absolute addressing mode must be used.
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Dummy Handlers are implemented as infinite loops which can be modified.
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VECTORS_IN_RAM defined in makefile/by commandline
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*/
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.text
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.arm
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.section .vectram, "ax"
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VectorsRAM: LDR PC,Reset_AddrR
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LDR PC,Undef_AddrR
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LDR PC,SWI_AddrR
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LDR PC,PAbt_AddrR
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LDR PC,DAbt_AddrR
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NOP /* Reserved Vector */
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LDR PC,[PC,#-0xF20] /* Vector From AIC_IVR */
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LDR PC,[PC,#-0xF20] /* Vector From AIC_FVR */
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Reset_AddrR: .word Reset_Handler
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Undef_AddrR: .word Undef_HandlerR
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SWI_AddrR: .word SWI_HandlerR
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PAbt_AddrR: .word PAbt_HandlerR
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DAbt_AddrR: .word DAbt_HandlerR
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// .word 0xdeadbeef /* Test Reserved Address */
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.word 0 /* Reserved Address */
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IRQ_AddrR: .word IRQ_HandlerR
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FIQ_AddrR: .word FIQ_HandlerR
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Undef_HandlerR: B Undef_HandlerR
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SWI_HandlerR: B SWI_HandlerR
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PAbt_HandlerR: B PAbt_HandlerR
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DAbt_HandlerR: B DAbt_HandlerR
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IRQ_HandlerR: B IRQ_HandlerR
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FIQ_HandlerR: B FIQ_HandlerR
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VectorsRAM_end:
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#endif /* VECTORS_IN_RAM && ROM_RUN */
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#ifndef USE_SAMBA
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/*
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Exception Vectors
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- for ROM_RUN: placed in 0x00000000
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- for RAM_RUN: placed at 0x00200000 (on AT91SAM7S64)
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- for USE_SAMBA: not used
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-> will be used during startup before remapping with target ROM_RUN
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-> will be used "always" in code without remapping or with target RAM_RUN
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Mapped to Address relative address 0 of .text
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Absolute addressing mode must be used.
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Dummy Handlers are implemented as infinite loops which can be modified.
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*/
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.text
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.arm
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.section .vectrom, "ax"
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Vectors: LDR PC,Reset_Addr
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LDR PC,Undef_Addr
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LDR PC,SWI_Addr
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LDR PC,PAbt_Addr
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LDR PC,DAbt_Addr
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NOP /* Reserved Vector */
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// LDR PC,IRQ_Addr
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LDR PC,[PC,#-0xF20] /* Vector From AIC_IVR */
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// LDR PC,FIQ_Addr
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LDR PC,[PC,#-0xF20] /* Vector From AIC_FVR */
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Reset_Addr: .word Reset_Handler
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Undef_Addr: .word Undef_Handler
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SWI_Addr: .word SWI_Handler
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PAbt_Addr: .word PAbt_Handler
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DAbt_Addr: .word DAbt_Handler
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.word 0 /* Reserved Address */
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IRQ_Addr: .word IRQ_Handler
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FIQ_Addr: .word FIQ_Handler
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Undef_Handler: B Undef_Handler
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SWI_Handler: B SWI_Handler
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PAbt_Handler: B PAbt_Handler
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DAbt_Handler: B DAbt_Handler
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IRQ_Handler: B IRQ_Handler
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FIQ_Handler: B FIQ_Handler
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#endif
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// Starupt Code must be linked first at Address at which it expects to run.
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.text
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.arm
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.section .init, "ax"
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.global _startup
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.func _startup
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_startup:
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// Reset Handler
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LDR pc, =Reset_Handler
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Reset_Handler:
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// Setup EFC
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.if EFC_SETUP
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LDR R0, =EFC_BASE
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LDR R1, =EFC_FMR_Val
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STR R1, [R0, #EFC_FMR]
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.endif
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// Setup WDT
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.if WDT_SETUP
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LDR R0, =WDT_BASE
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LDR R1, =WDT_MR_Val
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STR R1, [R0, #WDT_MR]
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.endif
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// Setup reset controller
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.if RSTC_SETUP
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LDR R0, =RSTC_BASE
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LDR R1, =RSTC_MR_Val
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STR R1, [R0, #RSTC_MR]
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.endif
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// Setup PMC
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.if PMC_SETUP
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LDR R0, =PMC_BASE
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// Setup Main Oscillator
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LDR R1, =PMC_MOR_Val
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STR R1, [R0, #PMC_MOR]
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// Wait until Main Oscillator is stablilized
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.if (PMC_MOR_Val & PMC_MOSCEN)
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MOSCS_Loop: LDR R2, [R0, #PMC_SR]
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ANDS R2, R2, #PMC_MOSCS
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BEQ MOSCS_Loop
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.endif
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// Setup the PLL
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||
|
|
.if (PMC_PLLR_Val & PMC_MUL)
|
||
|
|
LDR R1, =PMC_PLLR_Val
|
||
|
|
STR R1, [R0, #PMC_PLLR]
|
||
|
|
|
||
|
|
// Wait until PLL is stabilized
|
||
|
|
PLL_Loop: LDR R2, [R0, #PMC_SR]
|
||
|
|
ANDS R2, R2, #PMC_LOCK
|
||
|
|
BEQ PLL_Loop
|
||
|
|
.endif
|
||
|
|
|
||
|
|
// Select Clock
|
||
|
|
LDR R1, =PMC_MCKR_Val
|
||
|
|
STR R1, [R0, #PMC_MCKR]
|
||
|
|
.endif
|
||
|
|
|
||
|
|
|
||
|
|
// Setup Stack for each mode
|
||
|
|
|
||
|
|
LDR R0, =Top_Stack
|
||
|
|
|
||
|
|
// Enter Undefined Instruction Mode and set its Stack Pointer
|
||
|
|
MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
|
||
|
|
LDR SP, =UND_Stack_End
|
||
|
|
|
||
|
|
// Enter Abort Mode and set its Stack Pointer
|
||
|
|
MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
|
||
|
|
LDR SP, =ABT_Stack_End
|
||
|
|
|
||
|
|
// Enter FIQ Mode and set its Stack Pointer
|
||
|
|
MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
|
||
|
|
LDR SP, =FIQ_Stack_End
|
||
|
|
|
||
|
|
// Enter IRQ Mode and set its Stack Pointer
|
||
|
|
MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
|
||
|
|
LDR SP, =IRQ_Stack_End
|
||
|
|
|
||
|
|
// Enter Supervisor Mode and set its Stack Pointer
|
||
|
|
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
|
||
|
|
LDR SP, =SVC_Stack_End
|
||
|
|
|
||
|
|
// Enter User Mode and set its Stack Pointer
|
||
|
|
#ifndef RUN_AS_SYSTEM
|
||
|
|
MSR CPSR_c, #Mode_SYS
|
||
|
|
#else
|
||
|
|
MSR CPSR_c, #Mode_USR
|
||
|
|
#endif
|
||
|
|
LDR SP, =USR_Stack_End
|
||
|
|
|
||
|
|
// Setup a default Stack Limit (when compiled with "-mapcs-stack-check")
|
||
|
|
LDR SL, =USR_Stack_End
|
||
|
|
|
||
|
|
#ifdef ROM_RUN
|
||
|
|
// Relocate .data section (Copy from ROM to RAM)
|
||
|
|
LDR R1, =_etext
|
||
|
|
LDR R2, =_data
|
||
|
|
LDR R3, =_edata
|
||
|
|
LoopRel: CMP R2, R3
|
||
|
|
LDRLO R0, [R1], #4
|
||
|
|
STRLO R0, [R2], #4
|
||
|
|
BLO LoopRel
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
// Clear .bss section (Zero init)
|
||
|
|
MOV R0, #0
|
||
|
|
LDR R1, =__bss_start__
|
||
|
|
LDR R2, =__bss_end__
|
||
|
|
LoopZI: CMP R1, R2
|
||
|
|
STRLO R0, [R1], #4
|
||
|
|
BLO LoopZI
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(VECTORS_IN_RAM) || defined(RAM_RUN)
|
||
|
|
/*
|
||
|
|
*** Remap ***
|
||
|
|
ROM_RUN: exception vectors for RAM have been already copied
|
||
|
|
to 0x00200000 by the .data copy-loop
|
||
|
|
RAM_RUN: exception vectors are already placed at 0x0020000 by
|
||
|
|
linker settings
|
||
|
|
*/
|
||
|
|
.equ MC_BASE,0xFFFFFF00 /* MC Base Address */
|
||
|
|
.equ MC_RCR, 0x00 /* MC_RCR Offset */
|
||
|
|
|
||
|
|
LDR R0, =MC_BASE
|
||
|
|
MOV R1, #1
|
||
|
|
STR R1, [R0, #MC_RCR] // Remap
|
||
|
|
#endif /* VECTORS_IN_RAM || RAM_RUN */
|
||
|
|
|
||
|
|
#ifdef USE_SAMBA
|
||
|
|
// Copy interrupt vectors to RAM, that has previously been mapped to 0
|
||
|
|
MOV R1, #0
|
||
|
|
LDR R2, = VectorsRAM
|
||
|
|
LDR R3, = VectorsRAM_end
|
||
|
|
LoopVectCopy: CMP R2, R3
|
||
|
|
LDRLO R0, [R2], #4
|
||
|
|
STRLO R0, [R1], #4
|
||
|
|
BLO LoopVectCopy
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
Call C++ constructors (for objects in "global scope")
|
||
|
|
added by Martin Thomas based on a Anglia Design
|
||
|
|
example-application for STR7 ARM
|
||
|
|
*/
|
||
|
|
|
||
|
|
LDR r0, =__ctors_start__
|
||
|
|
LDR r1, =__ctors_end__
|
||
|
|
ctor_loop:
|
||
|
|
CMP r0, r1
|
||
|
|
BEQ ctor_end
|
||
|
|
LDR r2, [r0], #4 /* this ctor's address */
|
||
|
|
STMFD sp!, {r0-r1} /* save loop counters */
|
||
|
|
MOV lr, pc /* set return address */
|
||
|
|
// MOV pc, r2
|
||
|
|
BX r2 /* call ctor */
|
||
|
|
LDMFD sp!, {r0-r1} /* restore loop counters */
|
||
|
|
B ctor_loop
|
||
|
|
ctor_end:
|
||
|
|
|
||
|
|
|
||
|
|
// Enter the C code
|
||
|
|
mov r0,#0 // no arguments (argc = 0)
|
||
|
|
mov r1,r0
|
||
|
|
mov r2,r0
|
||
|
|
mov fp,r0 // null frame pointer
|
||
|
|
mov r7,r0 // null frame pointer for thumb
|
||
|
|
ldr r10,=main
|
||
|
|
adr lr, __main_exit
|
||
|
|
bx r10 // enter main()
|
||
|
|
|
||
|
|
__main_exit: B __main_exit
|
||
|
|
|
||
|
|
|
||
|
|
.size _startup, . - _startup
|
||
|
|
.endfunc
|
||
|
|
|
||
|
|
.end
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|