#define TCON_ENABLE_DIS (0x0 << 4 ) /* DIS. Disable the timer. Clearing this bit resets the timer, including the T0VAL register. */
#define TCON_ENABLE_EN (0x1 << 4 ) /* EN. Enable the timer. The timer starts counting from its initial value, 0 if count-up mode or 0xFFFF if count-down mode. */
#define TCLRI_CAP_CLR (0x1 << 1 ) /* CLR. Clear a captured event interrupt. This bit always reads 0. */
/* TCLRI[TMOUT] - Clear timeout interrupt. */
#define TCLRI_TMOUT_MSK (0x1 << 0 )
#define TCLRI_TMOUT (0x1 << 0 )
#define TCLRI_TMOUT_CLR (0x1 << 0 ) /* CLR. Clear a timeout interrupt. This bit always reads 0. */
/* TSTA[CLRI] - T0CLRI write sync in progress.. */
#define TSTA_CLRI_MSK (0x1 << 7 )
#define TSTA_CLRI (0x1 << 7 )
#define TSTA_CLRI_CLR (0x0 << 7 ) /* CLR. Cleared when the interrupt is cleared in the timer clock domain. */
#define TSTA_CLRI_SET (0x1 << 7 ) /* SET. Set automatically when the T0CLRI value is being updated in the timer clock domain, indicating that the timers configuration is not yet valid. */
/* TSTA[CON] - T0CON write sync in progress. */
#define TSTA_CON_MSK (0x1 << 6 )
#define TSTA_CON (0x1 << 6 )
#define TSTA_CON_CLR (0x0 << 6 ) /* CLR. Timer ready to receive commands to T0CON. The previous change of T0CON has been synchronized in the timer clock domain. */
#define TSTA_CON_SET (0x1 << 6 ) /* SET. Timer not ready to receive commands to T0CON. Previous change of the T0CON value has not been synchronized in the timer clock domain. */
/* TSTA[CAP] - Capture event pending. */
#define TSTA_CAP_MSK (0x1 << 1 )
#define TSTA_CAP (0x1 << 1 )
#define TSTA_CAP_CLR (0x0 << 1 ) /* CLR. No capture event is pending. */
#define TSTA_TMOUT_CLR (0x0 << 0 ) /* CLR. No timeout event has occurred. */
#define TSTA_TMOUT_SET (0x1 << 0 ) /* SET. Timeout event has occurred. For count-up mode, this is when the counter reaches full scale. For count-down mode, this is when the counter reaches 0. */
/* GPCON[CON7] - Configuration bits for Px.7 (not available for port 1). */
#define GPCON_CON7_MSK (0x3 << 14 )
/* GPCON[CON6] - Configuration bits for Px.6 (not available for port 1). */
#define GPCON_CON6_MSK (0x3 << 12 )
/* GPCON[CON5] - Configuration bits for Px.5. */
#define GPCON_CON5_MSK (0x3 << 10 )
/* GPCON[CON4] - Configuration bits for Px.4. */
#define GPCON_CON4_MSK (0x3 << 8 )
/* GPCON[CON3] - Configuration bits for Px.3. */
#define GPCON_CON3_MSK (0x3 << 6 )
/* GPCON[CON2] - Configuration bits for Px.2. */
#define GPCON_CON2_MSK (0x3 << 4 )
/* GPCON[CON1] - Configuration bits for Px.1. */
#define GPCON_CON1_MSK (0x3 << 2 )
/* GPCON[CON0] - Configuration bits for Px.0. */
#define GPCON_CON0_MSK (0x3 << 0 )
/* GPOEN[OEN7] - Port pin direction. */
#define GPOEN_OEN7_MSK (0x1 << 7 )
#define GPOEN_OEN7 (0x1 << 7 )
#define GPOEN_OEN7_IN (0x0 << 7 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */
#define GPOEN_OEN7_OUT (0x1 << 7 ) /* OUT. Enables the output on corresponding port pin. */
/* GPOEN[OEN6] - Port pin direction. */
#define GPOEN_OEN6_MSK (0x1 << 6 )
#define GPOEN_OEN6 (0x1 << 6 )
#define GPOEN_OEN6_IN (0x0 << 6 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */
#define GPOEN_OEN6_OUT (0x1 << 6 ) /* OUT. Enables the output on corresponding port pin. */
/* GPOEN[OEN5] - Port pin direction. */
#define GPOEN_OEN5_MSK (0x1 << 5 )
#define GPOEN_OEN5 (0x1 << 5 )
#define GPOEN_OEN5_IN (0x0 << 5 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */
#define GPOEN_OEN5_OUT (0x1 << 5 ) /* OUT. Enables the output on corresponding port pin. */
/* GPOEN[OEN4] - Port pin direction. */
#define GPOEN_OEN4_MSK (0x1 << 4 )
#define GPOEN_OEN4 (0x1 << 4 )
#define GPOEN_OEN4_IN (0x0 << 4 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */
#define GPOEN_OEN4_OUT (0x1 << 4 ) /* OUT. Enables the output on corresponding port pin. */
/* GPOEN[OEN3] - Port pin direction. */
#define GPOEN_OEN3_MSK (0x1 << 3 )
#define GPOEN_OEN3 (0x1 << 3 )
#define GPOEN_OEN3_IN (0x0 << 3 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */
#define GPOEN_OEN3_OUT (0x1 << 3 ) /* OUT. Enables the output on corresponding port pin. */
/* GPOEN[OEN2] - Port pin direction. */
#define GPOEN_OEN2_MSK (0x1 << 2 )
#define GPOEN_OEN2 (0x1 << 2 )
#define GPOEN_OEN2_IN (0x0 << 2 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */
#define GPOEN_OEN2_OUT (0x1 << 2 ) /* OUT. Enables the output on corresponding port pin. */
/* GPOEN[OEN1] - Port pin direction. */
#define GPOEN_OEN1_MSK (0x1 << 1 )
#define GPOEN_OEN1 (0x1 << 1 )
#define GPOEN_OEN1_IN (0x0 << 1 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */
#define GPOEN_OEN1_OUT (0x1 << 1 ) /* OUT. Enables the output on corresponding port pin. */
/* GPOEN[OEN0] - Port pin direction. */
#define GPOEN_OEN0_MSK (0x1 << 0 )
#define GPOEN_OEN0 (0x1 << 0 )
#define GPOEN_OEN0_IN (0x0 << 0 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */
#define GPOEN_OEN0_OUT (0x1 << 0 ) /* OUT. Enables the output on corresponding port pin.. */
/* GPIN[IN7] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */
#define GPIN_IN7_MSK (0x1 << 7 )
#define GPIN_IN7 (0x1 << 7 )
#define GPIN_IN7_LOW (0x0 << 7 ) /* LOW */
#define GPIN_IN7_HIGH (0x1 << 7 ) /* HIGH */
/* GPIN[IN6] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */
#define GPIN_IN6_MSK (0x1 << 6 )
#define GPIN_IN6 (0x1 << 6 )
#define GPIN_IN6_LOW (0x0 << 6 ) /* LOW */
#define GPIN_IN6_HIGH (0x1 << 6 ) /* HIGH */
/* GPIN[IN5] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */
#define GPIN_IN5_MSK (0x1 << 5 )
#define GPIN_IN5 (0x1 << 5 )
#define GPIN_IN5_LOW (0x0 << 5 ) /* LOW */
#define GPIN_IN5_HIGH (0x1 << 5 ) /* HIGH */
/* GPIN[IN4] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */
#define GPIN_IN4_MSK (0x1 << 4 )
#define GPIN_IN4 (0x1 << 4 )
#define GPIN_IN4_LOW (0x0 << 4 ) /* LOW */
#define GPIN_IN4_HIGH (0x1 << 4 ) /* HIGH */
/* GPIN[IN3] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */
#define GPIN_IN3_MSK (0x1 << 3 )
#define GPIN_IN3 (0x1 << 3 )
#define GPIN_IN3_LOW (0x0 << 3 ) /* LOW */
#define GPIN_IN3_HIGH (0x1 << 3 ) /* HIGH */
/* GPIN[IN2] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */
#define GPIN_IN2_MSK (0x1 << 2 )
#define GPIN_IN2 (0x1 << 2 )
#define GPIN_IN2_LOW (0x0 << 2 ) /* LOW */
#define GPIN_IN2_HIGH (0x1 << 2 ) /* HIGH */
/* GPIN[IN1] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */
#define GPIN_IN1_MSK (0x1 << 1 )
#define GPIN_IN1 (0x1 << 1 )
#define GPIN_IN1_LOW (0x0 << 1 ) /* LOW */
#define GPIN_IN1_HIGH (0x1 << 1 ) /* HIGH */
/* GPIN[IN0] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */
#define GPIN_IN0_MSK (0x1 << 0 )
#define GPIN_IN0 (0x1 << 0 )
#define GPIN_IN0_LOW (0x0 << 0 ) /* LOW */
#define GPIN_IN0_HIGH (0x1 << 0 ) /* HIGH */
/* GPOUT[OUT7] - Data out register. */
#define GPOUT_OUT7_MSK (0x1 << 7 )
#define GPOUT_OUT7 (0x1 << 7 )
#define GPOUT_OUT7_LOW (0x0 << 7 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */
#define GPOUT_OUT7_HIGH (0x1 << 7 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */
/* GPOUT[OUT6] - Data out register. */
#define GPOUT_OUT6_MSK (0x1 << 6 )
#define GPOUT_OUT6 (0x1 << 6 )
#define GPOUT_OUT6_LOW (0x0 << 6 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */
#define GPOUT_OUT6_HIGH (0x1 << 6 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */
/* GPOUT[OUT5] - Data out register. */
#define GPOUT_OUT5_MSK (0x1 << 5 )
#define GPOUT_OUT5 (0x1 << 5 )
#define GPOUT_OUT5_LOW (0x0 << 5 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */
#define GPOUT_OUT5_HIGH (0x1 << 5 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */
/* GPOUT[OUT4] - Data out register. */
#define GPOUT_OUT4_MSK (0x1 << 4 )
#define GPOUT_OUT4 (0x1 << 4 )
#define GPOUT_OUT4_LOW (0x0 << 4 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */
#define GPOUT_OUT4_HIGH (0x1 << 4 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */
/* GPOUT[OUT3] - Data out register. */
#define GPOUT_OUT3_MSK (0x1 << 3 )
#define GPOUT_OUT3 (0x1 << 3 )
#define GPOUT_OUT3_LOW (0x0 << 3 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */
#define GPOUT_OUT3_HIGH (0x1 << 3 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */
/* GPOUT[OUT2] - Data out register. */
#define GPOUT_OUT2_MSK (0x1 << 2 )
#define GPOUT_OUT2 (0x1 << 2 )
#define GPOUT_OUT2_LOW (0x0 << 2 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */
#define GPOUT_OUT2_HIGH (0x1 << 2 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */
/* GPOUT[OUT1] - Data out register. */
#define GPOUT_OUT1_MSK (0x1 << 1 )
#define GPOUT_OUT1 (0x1 << 1 )
#define GPOUT_OUT1_LOW (0x0 << 1 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */
#define GPOUT_OUT1_HIGH (0x1 << 1 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */
/* GPOUT[OUT0] - Data out register. */
#define GPOUT_OUT0_MSK (0x1 << 0 )
#define GPOUT_OUT0 (0x1 << 0 )
#define GPOUT_OUT0_LOW (0x0 << 0 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */
#define GPOUT_OUT0_HIGH (0x1 << 0 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */
/* GPSET[SET7] - Set output high for corresponding port pin. */
#define GPSET_SET7_MSK (0x1 << 7 )
#define GPSET_SET7 (0x1 << 7 )
#define GPSET_SET7_SET (0x1 << 7 ) /* SET. Set by user code to drive the corresponding GPIO high. */
/* GPSET[SET6] - Set output high for corresponding port pin. */
#define GPSET_SET6_MSK (0x1 << 6 )
#define GPSET_SET6 (0x1 << 6 )
#define GPSET_SET6_SET (0x1 << 6 ) /* SET. Set by user code to drive the corresponding GPIO high. */
/* GPSET[SET5] - Set output high for corresponding port pin. */
#define GPSET_SET5_MSK (0x1 << 5 )
#define GPSET_SET5 (0x1 << 5 )
#define GPSET_SET5_SET (0x1 << 5 ) /* SET. Set by user code to drive the corresponding GPIO high. */
/* GPSET[SET4] - Set output high for corresponding port pin. */
#define GPSET_SET4_MSK (0x1 << 4 )
#define GPSET_SET4 (0x1 << 4 )
#define GPSET_SET4_SET (0x1 << 4 ) /* SET. Set by user code to drive the corresponding GPIO high. */
/* GPSET[SET3] - Set output high for corresponding port pin. */
#define GPSET_SET3_MSK (0x1 << 3 )
#define GPSET_SET3 (0x1 << 3 )
#define GPSET_SET3_SET (0x1 << 3 ) /* SET. Set by user code to drive the corresponding GPIO high. */
/* GPSET[SET2] - Set output high for corresponding port pin. */
#define GPSET_SET2_MSK (0x1 << 2 )
#define GPSET_SET2 (0x1 << 2 )
#define GPSET_SET2_SET (0x1 << 2 ) /* SET. Set by user code to drive the corresponding GPIO high. */
/* GPSET[SET1] - Set output high for corresponding port pin. */
#define GPSET_SET1_MSK (0x1 << 1 )
#define GPSET_SET1 (0x1 << 1 )
#define GPSET_SET1_SET (0x1 << 1 ) /* SET. Set by user code to drive the corresponding GPIO high. */
/* GPSET[SET0] - Set output high for corresponding port pin. */
#define GPSET_SET0_MSK (0x1 << 0 )
#define GPSET_SET0 (0x1 << 0 )
#define GPSET_SET0_SET (0x1 << 0 ) /* SET. Set by user code to drive the corresponding GPIO high. */
/* GPCLR[CLR7] - Set by user code to drive the corresponding GPIO low. */
#define GPCLR_CLR7_MSK (0x1 << 7 )
#define GPCLR_CLR7 (0x1 << 7 )
#define GPCLR_CLR7_CLR (0x1 << 7 ) /* CLR */
/* GPCLR[CLR6] - Set by user code to drive the corresponding GPIO low. */
#define GPCLR_CLR6_MSK (0x1 << 6 )
#define GPCLR_CLR6 (0x1 << 6 )
#define GPCLR_CLR6_CLR (0x1 << 6 ) /* CLR */
/* GPCLR[CLR5] - Set by user code to drive the corresponding GPIO low. */
#define GPCLR_CLR5_MSK (0x1 << 5 )
#define GPCLR_CLR5 (0x1 << 5 )
#define GPCLR_CLR5_CLR (0x1 << 5 ) /* CLR */
/* GPCLR[CLR4] - Set by user code to drive the corresponding GPIO low. */
#define GPCLR_CLR4_MSK (0x1 << 4 )
#define GPCLR_CLR4 (0x1 << 4 )
#define GPCLR_CLR4_CLR (0x1 << 4 ) /* CLR */
/* GPCLR[CLR3] - Set by user code to drive the corresponding GPIO low. */
#define GPCLR_CLR3_MSK (0x1 << 3 )
#define GPCLR_CLR3 (0x1 << 3 )
#define GPCLR_CLR3_CLR (0x1 << 3 ) /* CLR */
/* GPCLR[CLR2] - Set by user code to drive the corresponding GPIO low. */
#define GPCLR_CLR2_MSK (0x1 << 2 )
#define GPCLR_CLR2 (0x1 << 2 )
#define GPCLR_CLR2_CLR (0x1 << 2 ) /* CLR */
/* GPCLR[CLR1] - Set by user code to drive the corresponding GPIO low. */
#define GPCLR_CLR1_MSK (0x1 << 1 )
#define GPCLR_CLR1 (0x1 << 1 )
#define GPCLR_CLR1_CLR (0x1 << 1 ) /* CLR */
/* GPCLR[CLR0] - Set by user code to drive the corresponding GPIO low. */
#define GPCLR_CLR0_MSK (0x1 << 0 )
#define GPCLR_CLR0 (0x1 << 0 )
#define GPCLR_CLR0_CLR (0x1 << 0 ) /* CLR */
/* GPTGL[TGL7] - Toggle for corresponding port pin. */
#define GPTGL_TGL7_MSK (0x1 << 7 )
#define GPTGL_TGL7 (0x1 << 7 )
#define GPTGL_TGL7_TGL (0x1 << 7 ) /* TGL. Set by user code to invert the corresponding GPIO. */
/* GPTGL[TGL6] - Toggle for corresponding port pin. */
#define GPTGL_TGL6_MSK (0x1 << 6 )
#define GPTGL_TGL6 (0x1 << 6 )
#define GPTGL_TGL6_TGL (0x1 << 6 ) /* TGL. Set by user code to invert the corresponding GPIO. */
/* GPTGL[TGL5] - Toggle for corresponding port pin. */
#define GPTGL_TGL5_MSK (0x1 << 5 )
#define GPTGL_TGL5 (0x1 << 5 )
#define GPTGL_TGL5_TGL (0x1 << 5 ) /* TGL. Set by user code to invert the corresponding GPIO. */
/* GPTGL[TGL4] - Toggle for corresponding port pin. */
#define GPTGL_TGL4_MSK (0x1 << 4 )
#define GPTGL_TGL4 (0x1 << 4 )
#define GPTGL_TGL4_TGL (0x1 << 4 ) /* TGL. Set by user code to invert the corresponding GPIO. */
/* GPTGL[TGL3] - Toggle for corresponding port pin. */
#define GPTGL_TGL3_MSK (0x1 << 3 )
#define GPTGL_TGL3 (0x1 << 3 )
#define GPTGL_TGL3_TGL (0x1 << 3 ) /* TGL. Set by user code to invert the corresponding GPIO. */
/* GPTGL[TGL2] - Toggle for corresponding port pin. */
#define GPTGL_TGL2_MSK (0x1 << 2 )
#define GPTGL_TGL2 (0x1 << 2 )
#define GPTGL_TGL2_TGL (0x1 << 2 ) /* TGL. Set by user code to invert the corresponding GPIO. */
/* GPTGL[TGL1] - Toggle for corresponding port pin. */
#define GPTGL_TGL1_MSK (0x1 << 1 )
#define GPTGL_TGL1 (0x1 << 1 )
#define GPTGL_TGL1_TGL (0x1 << 1 ) /* TGL. Set by user code to invert the corresponding GPIO. */
/* GPTGL[TGL0] - Toggle for corresponding port pin. */
#define GPTGL_TGL0_MSK (0x1 << 0 )
#define GPTGL_TGL0 (0x1 << 0 )
#define GPTGL_TGL0_TGL (0x1 << 0 ) /* TGL. Set by user code to invert the corresponding GPIO. */
/* SPIDIV[BCRST] - Configures the behavior of SPI communication after an abrupt deassertion of CS. This bit should be set in slave and master mode. */
#define SPIDIV_BCRST_MSK (0x1 << 7 )
#define SPIDIV_BCRST (0x1 << 7 )
#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS. Resumes communication from where it stopped when the CS is deasserted. The rest of the bits are then received/ transmitted when CS returns low. User code should ignore the CSERR interrupt. */
#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN. Enabled for a clean restart of SPI transfer after a CSERR condition. User code must also clear the SPI enable bit in SPI0CON during the CSERR interrupt. */
/* SPIDIV[DIV] - Factor used to divide UCLK in the generation of the master mode serial clock. */
#define SPIDIV_DIV_MSK (0x3F << 0 )
/* SPICON[MOD] - IRQ mode bits. When TIM is set these bits configure when the Tx/Rx interrupts occur in a transfer. For a DMA Rx transfer, these bits should be 00. */
#define SPICON_MOD_MSK (0x3 << 14 )
#define SPICON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1. Tx/Rx interrupt occurs when 1 byte has been transmitted/received from/into the FIFO. */
#define SPICON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2. Tx/Rx interrupt occurs when 2 bytes have been transmitted/received from/into the FIFO. */
#define SPICON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3. Tx/Rx interrupt occurs when 3 bytes have been transmitted/received from/into the FIFO. */
#define SPICON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4. Tx/Rx interrupt occurs when 4 bytes have been transmitted/received from/into the FIFO. */
#define SPICON_TFLUSH_EN (0x1 << 13 ) /* EN. Flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the ZEN bit (SPI0CON[7]). Any writes to the Tx FIFO are ignored while this bit is set. */
#define SPICON_RFLUSH_EN (0x1 << 12 ) /* EN. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and TIM = 0 (SPI0CON[6]), a read of the Rx FIFO initiates a transfer. */
/* SPICON[CON] - Continuous transfer enable bit. */
#define SPICON_CON_MSK (0x1 << 11 )
#define SPICON_CON (0x1 << 11 )
#define SPICON_CON_DIS (0x0 << 11 ) /* DIS. Disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPIxTX register, then a new transfer is initiated after a stall period of one serial clock cycle. The CS line is deactivated for this one serial clock cycle. */
#define SPICON_CON_EN (0x1 << 11 ) /* EN. Enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. */
#define SPICON_LOOPBACK_EN (0x1 << 10 ) /* EN. Connect MISO to MOSI, thus, data transmitted from Tx register is looped back to the Rx register. SPI must be configured in master mode. */
/* SPICON[SOEN] - Slave output enable bit. */
#define SPICON_SOEN_MSK (0x1 << 9 )
#define SPICON_SOEN (0x1 << 9 )
#define SPICON_SOEN_DIS (0x0 << 9 ) /* DIS. Disable the output driver on the MISO pin. The MISO pin is open-circuit when this bit is clear. */
#define SPICON_RXOF_DIS (0x0 << 8 ) /* DIS. The new serial byte received is discarded when there is no space left in the FIFO */
#define SPICON_RXOF_EN (0x1 << 8 ) /* EN. The valid data in the Rx register is overwritten by the new serial byte received when there is no space left in the FIFO. */
/* SPICON[ZEN] - Transmit underrun: Transmit 0s when the Tx FIFO is empty */
#define SPICON_ZEN_MSK (0x1 << 7 )
#define SPICON_ZEN (0x1 << 7 )
#define SPICON_ZEN_DIS (0x0 << 7 ) /* DIS. The last byte from the previous transmission is shifted out when a transfer is initiated with no valid data in the FIFO. */
#define SPICON_ZEN_EN (0x1 << 7 ) /* EN. Transmit 0x00 when a transfer is initiated with no valid data in the FIFO. */
/* SPICON[TIM] - Transfer and interrupt mode bit. */
#define SPICON_TIM_MSK (0x1 << 6 )
#define SPICON_TIM (0x1 << 6 )
#define SPICON_TIM_TXWR (0x1 << 6 ) /* TXWR. Initiate transfer with a write to the SPIxTX register. Interrupt only occurs when Tx is empty. */
#define SPICON_TIM_RXRD (0x0 << 6 ) /* RXRD. Initiate transfer with a read of the SPIxRX register. The read must be done while the SPI interface is idle. Interrupt only occurs when Rx is full. */
/* SPICON[LSB] - LSB first transfer enable bit. */
#define SPICON_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable the SPI. Clearing this bit will also reset all the FIFO related logic to enable a clean start. */
/* SPIDMA[ENABLE] - DMA data transfer enable bit. */
#define SPIDMA_ENABLE_MSK (0x1 << 0 )
#define SPIDMA_ENABLE (0x1 << 0 )
#define SPIDMA_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable DMA transfer. This bit needs to be cleared to prevent extra DMA request to the µDMA controller. */
#define SPIDMA_ENABLE_EN (0x1 << 0 ) /* EN. Enable a DMA transfer. Starts the transfer of a master configured to initiate transfer on transmit. */
/* SPISTA[CSERR] - CS error status bit. This bit generates an interrupt when detecting an abrupt CS desassertion before the full byte of data is transmitted completely. */
#define SPISTA_CSERR_MSK (0x1 << 12 )
#define SPISTA_CSERR (0x1 << 12 )
#define SPISTA_CSERR_CLR (0x0 << 12 ) /* CLR: Cleared when no CS error is detected. Cleared to 0 on a read of SPI0STA register. */
#define SPISTA_CSERR_SET (0x1 << 12 ) /* SET: Set when the CS line is deasserted abruptly. */
/* SPISTA[RXS] - Rx FIFO excess bytes present. */
#define SPISTA_RXS_MSK (0x1 << 11 )
#define SPISTA_RXS (0x1 << 11 )
#define SPISTA_RXS_CLR (0x0 << 11 ) /* CLR. When the number of bytes in the FIFO is equal or less than the number in SPI0CON[15:14]. This bit is not cleared on a read of SPI0STA register. */
#define SPISTA_RXS_SET (0x1 << 11 ) /* SET. When there are more bytes in the Rx FIFO than configured in MOD (SPI0CON[15:14]). For example if MOD = TX1RX1, RXS is set when there are 2 or more bytes in the Rx FIFO. This bit does not dependent on SPI0CON[6] and does not cause an interrupt. */
/* SPISTA[RXFSTA] - Rx FIFO status bits, indicates how many valid bytes are in the Rx FIFO. */
#define SPISTA_RXFSTA_MSK (0x7 << 8 )
#define SPISTA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY. When Rx FIFO is empty. */
#define SPISTA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE. When 1 valid byte is in the FIFO. */
#define SPISTA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES. When 2 valid bytes are in the FIFO. */
#define SPISTA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES. When 3 valid bytes are in the FIFO. */
#define SPISTA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES. When 4 valid bytes are in the FIFO. */
/* SPISTA[RXOF] - Rx FIFO overflow status bit. This bit generates an interrupt. */
#define SPISTA_RXOF_MSK (0x1 << 7 )
#define SPISTA_RXOF (0x1 << 7 )
#define SPISTA_RXOF_CLR (0x0 << 7 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */
#define SPISTA_RXOF_SET (0x1 << 7 ) /* SET. Set when the Rx FIFO is already full when new data is loaded to the FIFO. This bit generates an interrupt except when RFLUSH is set. (SPI0CON[12]). */
/* SPISTA[RX] - Rx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */
#define SPISTA_RX_MSK (0x1 << 6 )
#define SPISTA_RX (0x1 << 6 )
#define SPISTA_RX_CLR (0x0 << 6 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */
#define SPISTA_RX_SET (0x1 << 6 ) /* SET. Set when a receive interrupt occurs. This bit is set when TIM (SPI0CON[6]) is cleared and the required number of bytes have been received. */
/* SPISTA[TX] - Tx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */
#define SPISTA_TX_MSK (0x1 << 5 )
#define SPISTA_TX (0x1 << 5 )
#define SPISTA_TX_CLR (0x0 << 5 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */
#define SPISTA_TX_SET (0x1 << 5 ) /* SET. Set when a transmit interrupt occurs. This bit is set when TIM (SPI0CON[6]) set and the required number of bytes have been transmitted. */
/* SPISTA[TXUR] - Tx FIFO Underrun. This bit generates an interrupt. */
#define SPISTA_TXUR_MSK (0x1 << 4 )
#define SPISTA_TXUR (0x1 << 4 )
#define SPISTA_TXUR_CLR (0x0 << 4 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */
#define SPISTA_TXUR_SET (0x1 << 4 ) /* SET. Set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when TFLUSH is set in SPI0CON. */
/* SPISTA[TXFSTA] - Tx FIFO status bits, indicates how many valid bytes are in the Tx FIFO. */
#define SPISTA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE. 1 valid byte is in the FIFO. */
#define SPISTA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES. 2 valid bytes are in the FIFO. */
#define SPISTA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES. 3 valid bytes are in the FIFO. */
#define SPISTA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES . 4 valid bytes are in the FIFO. */
/* SPISTA[IRQ] - Interrupt status bit. */
#define SPISTA_IRQ_MSK (0x1 << 0 )
#define SPISTA_IRQ (0x1 << 0 )
#define SPISTA_IRQ_CLR (0x0 << 0 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */
#define SPISTA_IRQ_SET (0x1 << 0 ) /* SET. Set to 1 when an SPI0 based interrupt occurs. */
/* SPIDIV[BCRST] - Configures the behavior of SPI communication after an abrupt deassertion of CS. This bit should be set in slave and master mode. */
#define SPIDIV_BCRST_MSK (0x1 << 7 )
#define SPIDIV_BCRST (0x1 << 7 )
#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS. Resumes communication from where it stopped when the CS is deasserted. The rest of the bits are then received/ transmitted when CS returns low. User code should ignore the CSERR interrupt. */
#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN. Enabled for a clean restart of SPI transfer after a CSERR condition. User code must also clear the SPI enable bit in SPI0CON during the CSERR interrupt. */
/* SPIDIV[DIV] - Factor used to divide UCLK in the generation of the master mode serial clock. */
#define ADCCON_REFBUF_BBA (*(volatile unsigned long *) 0x42A0009C)
#define ADCCON_REFBUF_MSK (0x1 << 7 )
#define ADCCON_REFBUF (0x1 << 7 )
#define ADCCON_REFBUF_EN (0x0 << 7 ) /* EN. Turn on the reference buffer. The reference buffer takes 5 ms to settle and consumes approximately 210 μA. */
#define ADCCON_REFBUF_DIS (0x1 << 7 ) /* DIS. Turn off the reference buffer. The internal reference buffer must be turned off if using an external reference. */
/* ADCCON[DMA] - DMA transfer enable bit. */
#define ADCCON_DMA_BBA (*(volatile unsigned long *) 0x42A00098)
#define ADCCON_START_BBA (*(volatile unsigned long *) 0x42A00080)
#define ADCCON_START_MSK (0x1 << 0 )
#define ADCCON_START (0x1 << 0 )
#define ADCCON_START_DIS (0x0 << 0 ) /* DIS. Has no effect. */
#define ADCCON_START_EN (0x1 << 0 ) /* EN. Start conversion when SOFT conversion mode is selected. This bit does not clear after a single software conversion. */
/* Reset Value for ADCSTA*/
#define ADCSTA_RVAL 0x0
/* ADCSTA[READY] - ADC Ready bit */
#define ADCSTA_READY_BBA (*(volatile unsigned long *) 0x42A00100)
#define ADCSTA_READY_MSK (0x1 << 0 )
#define ADCSTA_READY (0x1 << 0 )
#define ADCSTA_READY_CLR (0x0 << 0 ) /* CLR. Cleared automatically when ADCDAT is read. */
#define ADCSTA_READY_EN (0x1 << 0 ) /* EN. Set by the ADC when a conversion is complete. This bit generates an interrupt if enabled (IEN set in ADCCON). */
/* Reset Value for ADCDAT*/
#define ADCDAT_RVAL 0x0
/* ADCDAT[VALUE] - ADC result */
#define ADCDAT_VALUE_MSK (0xFFF << 2 )
/* ADCDAT[Value_Reserved] - ADC result / Reserved */
__IOuint32_tDMAERRCLR;/*!< Bus Error Clear Register */
}ADI_DMA_TypeDef;
#else // (__NO_MMR_STRUCTS__==0)
#define DMASTA (*(volatile unsigned long *) 0x40010000)
#define DMACFG (*(volatile unsigned long *) 0x40010004)
#define DMAPDBPTR (*(volatile unsigned long *) 0x40010008)
#define DMAADBPTR (*(volatile unsigned long *) 0x4001000C)
#define DMASWREQ (*(volatile unsigned long *) 0x40010014)
#define DMARMSKSET (*(volatile unsigned long *) 0x40010020)
#define DMARMSKCLR (*(volatile unsigned long *) 0x40010024)
#define DMAENSET (*(volatile unsigned long *) 0x40010028)
#define DMAENCLR (*(volatile unsigned long *) 0x4001002C)
#define DMAALTSET (*(volatile unsigned long *) 0x40010030)
#define DMAALTCLR (*(volatile unsigned long *) 0x40010034)
#define DMAPRISET (*(volatile unsigned long *) 0x40010038)
#define DMAPRICLR (*(volatile unsigned long *) 0x4001003C)
#define DMAERRCLR (*(volatile unsigned long *) 0x4001004C)
#endif // (__NO_MMR_STRUCTS__==0)
/* Reset Value for DMASTA*/
#define DMASTA_RVAL 0xD0000
/* DMASTA[CHNLSMINUS1] - Number of available DMA channels minus 1. For example, if there are 14 channels available, the register reads back 0xD for these bits. */
#define DMASTA_CHNLSMINUS1_MSK (0x1F << 16 )
#define DMASTA_CHNLSMINUS1_FOURTEENCHNLS (0xD << 16 ) /* FOURTEENCHNLS - Controller configured to use 14 DMA channels. */
/* DMASTA[STATE] - Current state of DMA controller state machine. Provides insight into the operation performed by the DMA at the time this register is read. */
/* DMAPDBPTR[CTRLBASEPTR] - Pointer to the base address of the primary data structure. 5 + log (2)M LSBs are reserved and must be written 0. M is the number of channels. */
/* DMAADBPTR[ALTCBPTR] - Base address of the alternate data structure. */
#define DMAADBPTR_ALTCBPTR_MSK (0xFFFFFFFF << 0 )
/* Reset Value for DMASWREQ*/
#define DMASWREQ_RVAL 0x0
/* DMASWREQ[SPI0RX] - DMA SPI0 RX. */
#define DMASWREQ_SPI0RX_BBA (*(volatile unsigned long *) 0x422002B4)
#define DMASWREQ_SPI0RX_MSK (0x1 << 13 )
#define DMASWREQ_SPI0RX (0x1 << 13 )
#define DMASWREQ_SPI0RX_DIS (0x0 << 13 ) /* DIS. Does not create a DMA request for SPI0RX. */
#define DMASWREQ_SPI0RX_EN (0x1 << 13 ) /* EN. Generates a DMA request for SPI0RX. */
/* DMASWREQ[SPI0TX] - DMA SPI0 TX. */
#define DMASWREQ_SPI0TX_BBA (*(volatile unsigned long *) 0x422002B0)
#define DMASWREQ_SPI0TX_MSK (0x1 << 12 )
#define DMASWREQ_SPI0TX (0x1 << 12 )
#define DMASWREQ_SPI0TX_DIS (0x0 << 12 ) /* DIS. Does not create a DMA request for SPI0TX. */
#define DMASWREQ_SPI0TX_EN (0x1 << 12 ) /* EN. Generates a DMA request for SPI0TX. */
/* DMASWREQ[ADC] - DMA ADC. */
#define DMASWREQ_ADC_BBA (*(volatile unsigned long *) 0x422002AC)
#define DMASWREQ_ADC_MSK (0x1 << 11 )
#define DMASWREQ_ADC (0x1 << 11 )
#define DMASWREQ_ADC_DIS (0x0 << 11 ) /* DIS. Does not create a DMA request for ADC. */
#define DMASWREQ_ADC_EN (0x1 << 11 ) /* EN. Generates a DMA request for ADC. */
/* DMASWREQ[I2CMRX] - DMA I2C Master RX. */
#define DMASWREQ_I2CMRX_BBA (*(volatile unsigned long *) 0x4220029C)
#define DMASWREQ_I2CMRX_MSK (0x1 << 7 )
#define DMASWREQ_I2CMRX (0x1 << 7 )
#define DMASWREQ_I2CMRX_DIS (0x0 << 7 ) /* DIS. Does not create a DMA request for I2CMRX. */
#define DMASWREQ_I2CMRX_EN (0x1 << 7 ) /* EN. Generates a DMA request for I2CMRX. */
/* DMASWREQ[I2CMTX] - DMA I2C Master TX. */
#define DMASWREQ_I2CMTX_BBA (*(volatile unsigned long *) 0x42200298)
#define DMASWREQ_I2CMTX_MSK (0x1 << 6 )
#define DMASWREQ_I2CMTX (0x1 << 6 )
#define DMASWREQ_I2CMTX_DIS (0x0 << 6 ) /* DIS. Does not create a DMA request for I2CMTX. */
#define DMASWREQ_I2CMTX_EN (0x1 << 6 ) /* EN. Generates a DMA request for I2CMTX. */
/* DMASWREQ[I2CSRX] - DMA I2C Slave RX. */
#define DMASWREQ_I2CSRX_BBA (*(volatile unsigned long *) 0x42200294)
#define DMASWREQ_I2CSRX_MSK (0x1 << 5 )
#define DMASWREQ_I2CSRX (0x1 << 5 )
#define DMASWREQ_I2CSRX_DIS (0x0 << 5 ) /* DIS. Does not create a DMA request for I2CSRX. */
#define DMASWREQ_I2CSRX_EN (0x1 << 5 ) /* EN. Generates a DMA request for I2CSRX. */
/* DMASWREQ[I2CSTX] - DMA I2C Slave TX. */
#define DMASWREQ_I2CSTX_BBA (*(volatile unsigned long *) 0x42200290)
#define DMASWREQ_I2CSTX_MSK (0x1 << 4 )
#define DMASWREQ_I2CSTX (0x1 << 4 )
#define DMASWREQ_I2CSTX_DIS (0x0 << 4 ) /* DIS. Does not create a DMA request for I2CSTX. */
#define DMASWREQ_I2CSTX_EN (0x1 << 4 ) /* EN. Generates a DMA request for I2CSTX. */
/* DMASWREQ[UARTRX] - DMA UART RX. */
#define DMASWREQ_UARTRX_BBA (*(volatile unsigned long *) 0x4220028C)
#define DMASWREQ_UARTRX_MSK (0x1 << 3 )
#define DMASWREQ_UARTRX (0x1 << 3 )
#define DMASWREQ_UARTRX_DIS (0x0 << 3 ) /* DIS. Does not create a DMA request for UARTRX. */
#define DMASWREQ_UARTRX_EN (0x1 << 3 ) /* EN. Generates a DMA request for UARTRX. */
/* DMASWREQ[UARTTX] - DMA UART TX. */
#define DMASWREQ_UARTTX_BBA (*(volatile unsigned long *) 0x42200288)
#define DMASWREQ_UARTTX_MSK (0x1 << 2 )
#define DMASWREQ_UARTTX (0x1 << 2 )
#define DMASWREQ_UARTTX_DIS (0x0 << 2 ) /* DIS. Does not create a DMA request for UARTTX. */
#define DMASWREQ_UARTTX_EN (0x1 << 2 ) /* EN. Generates a DMA request for UARTTX. */
/* DMASWREQ[SPI1RX] - DMA SPI 1 RX. */
#define DMASWREQ_SPI1RX_BBA (*(volatile unsigned long *) 0x42200284)
#define DMASWREQ_SPI1RX_MSK (0x1 << 1 )
#define DMASWREQ_SPI1RX (0x1 << 1 )
#define DMASWREQ_SPI1RX_DIS (0x0 << 1 ) /* DIS. Does not create a DMA request for SPI1RX. */
#define DMASWREQ_SPI1RX_EN (0x1 << 1 ) /* EN. Generates a DMA request for SPI1RX. */
/* DMASWREQ[SPI1TX] - DMA SPI 1 TX. */
#define DMASWREQ_SPI1TX_BBA (*(volatile unsigned long *) 0x42200280)
#define DMASWREQ_SPI1TX_MSK (0x1 << 0 )
#define DMASWREQ_SPI1TX (0x1 << 0 )
#define DMASWREQ_SPI1TX_DIS (0x0 << 0 ) /* DIS. Does not create a DMA request for SPI1TX. */
#define DMASWREQ_SPI1TX_EN (0x1 << 0 ) /* EN. Generates a DMA request for SPI1TX. */
/* Reset Value for DMARMSKSET*/
#define DMARMSKSET_RVAL 0x0
/* DMARMSKSET[SPI0RX] - DMA SPI0 RX. */
#define DMARMSKSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200434)
#define DMARMSKSET_SPI0RX_MSK (0x1 << 13 )
#define DMARMSKSET_SPI0RX (0x1 << 13 )
#define DMARMSKSET_SPI0RX_DIS (0x0 << 13 ) /* DIS. When read: Requests are enabled for SPI0RX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */
#define DMARMSKSET_SPI0RX_EN (0x1 << 13 ) /* EN. When read: Requests are disabled for SPI0RX. When written: Disables peripheral associated with SPI0RX from generating DMA requests. */
/* DMARMSKSET[SPI0TX] - DMA SPI0 TX. */
#define DMARMSKSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200430)
#define DMARMSKSET_SPI0TX_MSK (0x1 << 12 )
#define DMARMSKSET_SPI0TX (0x1 << 12 )
#define DMARMSKSET_SPI0TX_DIS (0x0 << 12 ) /* DIS. When read: Requests are enabled for SPI0TX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */
#define DMARMSKSET_SPI0TX_EN (0x1 << 12 ) /* EN. When read: Requests are disabled for SPI0TX. When written: Disables peripheral associated with SPI0TX from generating DMA requests. */
/* DMARMSKSET[ADC] - DMA ADC. */
#define DMARMSKSET_ADC_BBA (*(volatile unsigned long *) 0x4220042C)
#define DMARMSKSET_ADC_MSK (0x1 << 11 )
#define DMARMSKSET_ADC (0x1 << 11 )
#define DMARMSKSET_ADC_DIS (0x0 << 11 ) /* DIS. When read: Requests are enabled for ADC. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */
#define DMARMSKSET_ADC_EN (0x1 << 11 ) /* EN. When read: Requests are disabled for ADC. When written: Disables peripheral associated with ADC from generating DMA requests. */
/* DMARMSKSET[I2CMRX] - DMA I2C Master RX. */
#define DMARMSKSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220041C)
#define DMARMSKSET_I2CMRX_MSK (0x1 << 7 )
#define DMARMSKSET_I2CMRX (0x1 << 7 )
#define DMARMSKSET_I2CMRX_DIS (0x0 << 7 ) /* DIS. When read: Requests are enabled for I2CMRX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */
#define DMARMSKSET_I2CMRX_EN (0x1 << 7 ) /* EN. When read: Requests are disabled for I2CMRX. When written: Disables peripheral associated with I2CMRX from generating DMA requests. */
/* DMARMSKSET[I2CMTX] - DMA I2C Master TX. */
#define DMARMSKSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200418)
#define DMARMSKSET_I2CMTX_MSK (0x1 << 6 )
#define DMARMSKSET_I2CMTX (0x1 << 6 )
#define DMARMSKSET_I2CMTX_DIS (0x0 << 6 ) /* DIS. When read: Requests are enabled for I2CMTX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */
#define DMARMSKSET_I2CMTX_EN (0x1 << 6 ) /* EN. When read: Requests are disabled for I2CMTX. When written: Disables peripheral associated with I2CMTX from generating DMA requests. */
/* DMARMSKSET[I2CSRX] - DMA I2C Slave RX. */
#define DMARMSKSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200414)
#define DMARMSKSET_I2CSRX_MSK (0x1 << 5 )
#define DMARMSKSET_I2CSRX (0x1 << 5 )
#define DMARMSKSET_I2CSRX_DIS (0x0 << 5 ) /* DIS. When read: Requests are enabled for I2CSRX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */
#define DMARMSKSET_I2CSRX_EN (0x1 << 5 ) /* EN. When read: Requests are disabled for I2CSRX. When written: Disables peripheral associated with I2CSRX from generating DMA requests. */
/* DMARMSKSET[I2CSTX] - DMA I2C Slave TX. */
#define DMARMSKSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200410)
#define DMARMSKSET_I2CSTX_MSK (0x1 << 4 )
#define DMARMSKSET_I2CSTX (0x1 << 4 )
#define DMARMSKSET_I2CSTX_DIS (0x0 << 4 ) /* DIS. When read: Requests are enabled forI2CSTX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */
#define DMARMSKSET_I2CSTX_EN (0x1 << 4 ) /* EN. When read: Requests are disabled for I2CSTX. When written: Disables peripheral associated with I2CSTX from generating DMA requests. */
/* DMARMSKSET[UARTRX] - DMA UART RX. */
#define DMARMSKSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220040C)
#define DMARMSKSET_UARTRX_MSK (0x1 << 3 )
#define DMARMSKSET_UARTRX (0x1 << 3 )
#define DMARMSKSET_UARTRX_DIS (0x0 << 3 ) /* DIS. When read: Requests are enabled for UARTRX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */
#define DMARMSKSET_UARTRX_EN (0x1 << 3 ) /* EN. When read: Requests are disabled for UARTRX. When written: Disables peripheral associated with UARTRX from generating DMA requests. */
/* DMARMSKSET[UARTTX] - DMA UART TX. */
#define DMARMSKSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200408)
#define DMARMSKSET_UARTTX_MSK (0x1 << 2 )
#define DMARMSKSET_UARTTX (0x1 << 2 )
#define DMARMSKSET_UARTTX_DIS (0x0 << 2 ) /* DIS. When read: Requests are enabled for UARTTX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */
#define DMARMSKSET_UARTTX_EN (0x1 << 2 ) /* EN. When read: Requests are disabled for UARTTX. When written: Disables peripheral associated with UARTTX from generating DMA requests. */
/* DMARMSKSET[SPI1RX] - DMA SPI 1 RX. */
#define DMARMSKSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200404)
#define DMARMSKSET_SPI1RX_MSK (0x1 << 1 )
#define DMARMSKSET_SPI1RX (0x1 << 1 )
#define DMARMSKSET_SPI1RX_DIS (0x0 << 1 ) /* DIS. When read: Requests are enabled for SPI1RX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */
#define DMARMSKSET_SPI1RX_EN (0x1 << 1 ) /* EN. When read: Requests are disabled for SPI1RX. When written: Disables peripheral associated with SPI1RX from generating DMA requests. */
/* DMARMSKSET[SPI1TX] - DMA SPI 1 TX. */
#define DMARMSKSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200400)
#define DMARMSKSET_SPI1TX_MSK (0x1 << 0 )
#define DMARMSKSET_SPI1TX (0x1 << 0 )
#define DMARMSKSET_SPI1TX_DIS (0x0 << 0 ) /* DIS. When read: Requests are enabled for SPI1TX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */
#define DMARMSKSET_SPI1TX_EN (0x1 << 0 ) /* EN. When read: Requests are disabled for SPI1TX When written: Disables peripheral associated with SPI1TX from generating DMA requests. */
/* Reset Value for DMARMSKCLR*/
#define DMARMSKCLR_RVAL 0x0
/* DMARMSKCLR[SPI0RX] - DMA SPI0 RX. */
#define DMARMSKCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422004B4)
#define DMARMSKCLR_SPI0RX_MSK (0x1 << 13 )
#define DMARMSKCLR_SPI0RX (0x1 << 13 )
#define DMARMSKCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */
#define DMARMSKCLR_SPI0RX_EN (0x1 << 13 ) /* EN. Enables peripheral associated with SPI0RX to generate DMA requests. */
/* DMARMSKCLR[SPI0TX] - DMA SPI0 TX. */
#define DMARMSKCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422004B0)
#define DMARMSKCLR_SPI0TX_MSK (0x1 << 12 )
#define DMARMSKCLR_SPI0TX (0x1 << 12 )
#define DMARMSKCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */
#define DMARMSKCLR_SPI0TX_EN (0x1 << 12 ) /* EN. Enables peripheral associated with SPI0TX to generate DMA requests. */
/* DMARMSKCLR[ADC] - DMA ADC. */
#define DMARMSKCLR_ADC_BBA (*(volatile unsigned long *) 0x422004AC)
#define DMARMSKCLR_ADC_MSK (0x1 << 11 )
#define DMARMSKCLR_ADC (0x1 << 11 )
#define DMARMSKCLR_ADC_DIS (0x0 << 11 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */
#define DMARMSKCLR_ADC_EN (0x1 << 11 ) /* EN. Enables peripheral associated with ADC to generate DMA requests. */
/* DMARMSKCLR[I2CMRX] - DMA I2C Master RX. */
#define DMARMSKCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220049C)
#define DMARMSKCLR_I2CMRX_MSK (0x1 << 7 )
#define DMARMSKCLR_I2CMRX (0x1 << 7 )
#define DMARMSKCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */
#define DMARMSKCLR_I2CMRX_EN (0x1 << 7 ) /* EN. Enables peripheral associated with I2CMRX to generate DMA requests. */
/* DMARMSKCLR[I2CMTX] - DMA I2C Master TX. */
#define DMARMSKCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200498)
#define DMARMSKCLR_I2CMTX_MSK (0x1 << 6 )
#define DMARMSKCLR_I2CMTX (0x1 << 6 )
#define DMARMSKCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */
#define DMARMSKCLR_I2CMTX_EN (0x1 << 6 ) /* EN. Enables peripheral associated with I2CMTX to generate DMA requests. */
/* DMARMSKCLR[I2CSRX] - DMA I2C Slave RX. */
#define DMARMSKCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200494)
#define DMARMSKCLR_I2CSRX_MSK (0x1 << 5 )
#define DMARMSKCLR_I2CSRX (0x1 << 5 )
#define DMARMSKCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */
#define DMARMSKCLR_I2CSRX_EN (0x1 << 5 ) /* EN. Enables peripheral associated with I2CSRX to generate DMA requests. */
/* DMARMSKCLR[I2CSTX] - DMA I2C Slave TX. */
#define DMARMSKCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200490)
#define DMARMSKCLR_I2CSTX_MSK (0x1 << 4 )
#define DMARMSKCLR_I2CSTX (0x1 << 4 )
#define DMARMSKCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */
#define DMARMSKCLR_I2CSTX_EN (0x1 << 4 ) /* EN. Enables peripheral associated with I2CSTX to generate DMA requests. */
/* DMARMSKCLR[UARTRX] - DMA UART RX. */
#define DMARMSKCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220048C)
#define DMARMSKCLR_UARTRX_MSK (0x1 << 3 )
#define DMARMSKCLR_UARTRX (0x1 << 3 )
#define DMARMSKCLR_UARTRX_DIS (0x0 << 3 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */
#define DMARMSKCLR_UARTRX_EN (0x1 << 3 ) /* EN. Enables peripheral associated with UARTRX to generate DMA requests. */
/* DMARMSKCLR[UARTTX] - DMA UART TX. */
#define DMARMSKCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200488)
#define DMARMSKCLR_UARTTX_MSK (0x1 << 2 )
#define DMARMSKCLR_UARTTX (0x1 << 2 )
#define DMARMSKCLR_UARTTX_DIS (0x0 << 2 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */
#define DMARMSKCLR_UARTTX_EN (0x1 << 2 ) /* EN. Enables peripheral associated with UARTTX to generate DMA requests. */
/* DMARMSKCLR[SPI1RX] - DMA SPI 1 RX. */
#define DMARMSKCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200484)
#define DMARMSKCLR_SPI1RX_MSK (0x1 << 1 )
#define DMARMSKCLR_SPI1RX (0x1 << 1 )
#define DMARMSKCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */
#define DMARMSKCLR_SPI1RX_EN (0x1 << 1 ) /* EN. Enables peripheral associated with SPI1RX to generate DMA requests. */
/* DMARMSKCLR[SPI1TX] - DMA SPI 1 TX. */
#define DMARMSKCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200480)
#define DMARMSKCLR_SPI1TX_MSK (0x1 << 0 )
#define DMARMSKCLR_SPI1TX (0x1 << 0 )
#define DMARMSKCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */
#define DMARMSKCLR_SPI1TX_EN (0x1 << 0 ) /* EN. Enables peripheral associated with SPI1TX to generate DMA requests. */
/* Reset Value for DMAENSET*/
#define DMAENSET_RVAL 0x0
/* DMAENSET[SPI0RX] - DMA SPI0 RX */
#define DMAENSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200534)
#define DMAENSET_SPI0RX_MSK (0x1 << 13 )
#define DMAENSET_SPI0RX (0x1 << 13 )
#define DMAENSET_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */
#define DMAALTSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200634)
#define DMAALTSET_SPI0RX_MSK (0x1 << 13 )
#define DMAALTSET_SPI0RX (0x1 << 13 )
#define DMAALTSET_SPI0RX_DIS (0x0 << 13 ) /* DIS. When read: DMA SPI0RX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set SPI0RX to 0. */
#define DMAALTSET_SPI0RX_EN (0x1 << 13 ) /* EN. When read: DMA SPI0RX is using the alternate data structure. When written: Selects the alternate data structure for SPI0RX. */
/* DMAALTSET[SPI0TX] - DMA SPI0 TX. */
#define DMAALTSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200630)
#define DMAALTSET_SPI0TX_MSK (0x1 << 12 )
#define DMAALTSET_SPI0TX (0x1 << 12 )
#define DMAALTSET_SPI0TX_DIS (0x0 << 12 ) /* DIS. When read: DMA SPI0TX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set SPI0TX to 0. */
#define DMAALTSET_SPI0TX_EN (0x1 << 12 ) /* EN. When read: DMA SPI0TX is using the alternate data structure. When written: Selects the alternate data structure for SPI0TX. */
/* DMAALTSET[ADC] - DMA ADC. */
#define DMAALTSET_ADC_BBA (*(volatile unsigned long *) 0x4220062C)
#define DMAALTSET_ADC_MSK (0x1 << 11 )
#define DMAALTSET_ADC (0x1 << 11 )
#define DMAALTSET_ADC_DIS (0x0 << 11 ) /* DIS. When read: DMA ADC is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set ADC to 0. */
#define DMAALTSET_ADC_EN (0x1 << 11 ) /* EN. When read: DMA ADC is using the alternate data structure. When written: Selects the alternate data structure for ADC. */
/* DMAALTSET[I2CMRX] - DMA I2C Master RX. */
#define DMAALTSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220061C)
#define DMAALTSET_I2CMRX_MSK (0x1 << 7 )
#define DMAALTSET_I2CMRX (0x1 << 7 )
#define DMAALTSET_I2CMRX_DIS (0x0 << 7 ) /* DIS. When read: DMA I2CMRX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set I2CMRX to 0. */
#define DMAALTSET_I2CMRX_EN (0x1 << 7 ) /* EN. When read: DMA I2CMRX is using the alternate data structure. When written: Selects the alternate data structure for I2CMRX. */
/* DMAALTSET[I2CMTX] - DMA I2C Master TX. */
#define DMAALTSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200618)
#define DMAALTSET_I2CMTX_MSK (0x1 << 6 )
#define DMAALTSET_I2CMTX (0x1 << 6 )
#define DMAALTSET_I2CMTX_DIS (0x0 << 6 ) /* DIS. When read: DMA I2CMTX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set I2CMTX to 0. */
#define DMAALTSET_I2CMTX_EN (0x1 << 6 ) /* EN. When read: DMA I2CMTX is using the alternate data structure. When written: Selects the alternate data structure forI2CMTX. */
/* DMAALTSET[I2CSRX] - DMA I2C Slave RX. */
#define DMAALTSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200614)
#define DMAALTSET_I2CSRX_MSK (0x1 << 5 )
#define DMAALTSET_I2CSRX (0x1 << 5 )
#define DMAALTSET_I2CSRX_DIS (0x0 << 5 ) /* DIS. When read: DMA I2CSRX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set I2CSRX to 0. */
#define DMAALTSET_I2CSRX_EN (0x1 << 5 ) /* EN. When read: DMA I2CSRX is using the alternate data structure. When written: Selects the alternate data structure for I2CSRX. */
/* DMAALTSET[I2CSTX] - DMA I2C Slave TX. */
#define DMAALTSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200610)
#define DMAALTSET_I2CSTX_MSK (0x1 << 4 )
#define DMAALTSET_I2CSTX (0x1 << 4 )
#define DMAALTSET_I2CSTX_DIS (0x0 << 4 ) /* DIS. When read: DMA I2CSTX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set I2CSTX to 0. */
#define DMAALTSET_I2CSTX_EN (0x1 << 4 ) /* EN. When read: DMA I2CSTX is using the alternate data structure. When written: Selects the alternate data structure for I2CSTX. */
/* DMAALTSET[UARTRX] - DMA UART RX. */
#define DMAALTSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220060C)
#define DMAALTSET_UARTRX_MSK (0x1 << 3 )
#define DMAALTSET_UARTRX (0x1 << 3 )
#define DMAALTSET_UARTRX_DIS (0x0 << 3 ) /* DIS. When read: DMA UARTRX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set UARTRX to 0. */
#define DMAALTSET_UARTRX_EN (0x1 << 3 ) /* EN. When read: DMA UARTRX is using the alternate data structure. When written: Selects the alternate data structure for UARTRX. */
/* DMAALTSET[UARTTX] - DMA UART TX. */
#define DMAALTSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200608)
#define DMAALTSET_UARTTX_MSK (0x1 << 2 )
#define DMAALTSET_UARTTX (0x1 << 2 )
#define DMAALTSET_UARTTX_DIS (0x0 << 2 ) /* DIS. When read: DMA UARTTX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set UARTTX to 0. */
#define DMAALTSET_UARTTX_EN (0x1 << 2 ) /* EN. When read: DMA UARTTX is using the alternate data structure. When written: Selects the alternate data structure for UARTTX. */
/* DMAALTSET[SPI1RX] - DMA SPI 1 RX. */
#define DMAALTSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200604)
#define DMAALTSET_SPI1RX_MSK (0x1 << 1 )
#define DMAALTSET_SPI1RX (0x1 << 1 )
#define DMAALTSET_SPI1RX_DIS (0x0 << 1 ) /* DIS. When read: DMA SPI1RX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set SPI1RX to 0. */
#define DMAALTSET_SPI1RX_EN (0x1 << 1 ) /* EN. When read: DMA SPI1RX is using the alternate data structure. When written: Selects the alternate data structure for SPI1RX. */
/* DMAALTSET[SPI1TX] - DMA SPI 1 TX. */
#define DMAALTSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200600)
#define DMAALTSET_SPI1TX_MSK (0x1 << 0 )
#define DMAALTSET_SPI1TX (0x1 << 0 )
#define DMAALTSET_SPI1TX_DIS (0x0 << 0 ) /* DIS. When read: DMA SPI1TX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set SPI1TX to 0. */
#define DMAALTSET_SPI1TX_EN (0x1 << 0 ) /* EN. When read: DMA SPI1TX is using the alternate data structure. When written: Selects the alternate data structure for SPI1TX. */
/* Reset Value for DMAALTCLR*/
#define DMAALTCLR_RVAL 0x0
/* DMAALTCLR[SPI0RX] - DMA SPI0 RX. */
#define DMAALTCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422006B4)
#define DMAALTCLR_SPI0RX_MSK (0x1 << 13 )
#define DMAALTCLR_SPI0RX (0x1 << 13 )
#define DMAALTCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */
#define DMAALTCLR_SPI0RX_EN (0x1 << 13 ) /* EN. Selects the primary data structure for SPI0RX. */
/* DMAALTCLR[SPI0TX] - DMA SPI0 TX. */
#define DMAALTCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422006B0)
#define DMAALTCLR_SPI0TX_MSK (0x1 << 12 )
#define DMAALTCLR_SPI0TX (0x1 << 12 )
#define DMAALTCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */
#define DMAALTCLR_SPI0TX_EN (0x1 << 12 ) /* EN. Selects the primary data structure for SPI0TX. */
/* DMAALTCLR[ADC] - DMA ADC. */
#define DMAALTCLR_ADC_BBA (*(volatile unsigned long *) 0x422006AC)
#define DMAALTCLR_ADC_MSK (0x1 << 11 )
#define DMAALTCLR_ADC (0x1 << 11 )
#define DMAALTCLR_ADC_DIS (0x0 << 11 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */
#define DMAALTCLR_ADC_EN (0x1 << 11 ) /* EN. Selects the primary data structure for ADC. */
/* DMAALTCLR[I2CMRX] - DMA I2C Master RX. */
#define DMAALTCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220069C)
#define DMAALTCLR_I2CMRX_MSK (0x1 << 7 )
#define DMAALTCLR_I2CMRX (0x1 << 7 )
#define DMAALTCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */
#define DMAALTCLR_I2CMRX_EN (0x1 << 7 ) /* EN. Selects the primary data structure for I2CMRX. */
/* DMAALTCLR[I2CMTX] - DMA I2C Master TX. */
#define DMAALTCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200698)
#define DMAALTCLR_I2CMTX_MSK (0x1 << 6 )
#define DMAALTCLR_I2CMTX (0x1 << 6 )
#define DMAALTCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */
#define DMAALTCLR_I2CMTX_EN (0x1 << 6 ) /* EN. Selects the primary data structure for I2CMTX. */
/* DMAALTCLR[I2CSRX] - DMA I2C Slave RX. */
#define DMAALTCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200694)
#define DMAALTCLR_I2CSRX_MSK (0x1 << 5 )
#define DMAALTCLR_I2CSRX (0x1 << 5 )
#define DMAALTCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */
#define DMAALTCLR_I2CSRX_EN (0x1 << 5 ) /* EN. Selects the primary data structure for I2CSRX. */
/* DMAALTCLR[I2CSTX] - DMA I2C Slave TX. */
#define DMAALTCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200690)
#define DMAALTCLR_I2CSTX_MSK (0x1 << 4 )
#define DMAALTCLR_I2CSTX (0x1 << 4 )
#define DMAALTCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */
#define DMAALTCLR_I2CSTX_EN (0x1 << 4 ) /* EN. Selects the primary data structure for I2CSTX. */
/* DMAALTCLR[UARTRX] - DMA UART RX. */
#define DMAALTCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220068C)
#define DMAALTCLR_UARTRX_MSK (0x1 << 3 )
#define DMAALTCLR_UARTRX (0x1 << 3 )
#define DMAALTCLR_UARTRX_DIS (0x0 << 3 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */
#define DMAALTCLR_UARTRX_EN (0x1 << 3 ) /* EN. Selects the primary data structure for UARTRX. */
/* DMAALTCLR[UARTTX] - DMA UART TX. */
#define DMAALTCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200688)
#define DMAALTCLR_UARTTX_MSK (0x1 << 2 )
#define DMAALTCLR_UARTTX (0x1 << 2 )
#define DMAALTCLR_UARTTX_DIS (0x0 << 2 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */
#define DMAALTCLR_UARTTX_EN (0x1 << 2 ) /* EN. Selects the primary data structure for UARTTX. */
/* DMAALTCLR[SPI1RX] - DMA SPI 1 RX. */
#define DMAALTCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200684)
#define DMAALTCLR_SPI1RX_MSK (0x1 << 1 )
#define DMAALTCLR_SPI1RX (0x1 << 1 )
#define DMAALTCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */
#define DMAALTCLR_SPI1RX_EN (0x1 << 1 ) /* EN. Selects the primary data structure for SPI1RX. */
/* DMAALTCLR[SPI1TX] - DMA SPI 1 TX. */
#define DMAALTCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200680)
#define DMAALTCLR_SPI1TX_MSK (0x1 << 0 )
#define DMAALTCLR_SPI1TX (0x1 << 0 )
#define DMAALTCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */
#define DMAALTCLR_SPI1TX_EN (0x1 << 0 ) /* EN. Selects the primary data structure for SPI1TX. */
/* Reset Value for DMAPRISET*/
#define DMAPRISET_RVAL 0x0
/* DMAPRISET[SPI0RX] - DMA SPI0 RX. */
#define DMAPRISET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200734)
#define DMAPRISET_SPI0RX_MSK (0x1 << 13 )
#define DMAPRISET_SPI0RX (0x1 << 13 )
#define DMAPRISET_SPI0RX_DIS (0x0 << 13 ) /* DIS. When read: DMA SPI0RX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set SPI0RX to the default priority level. */
#define DMAPRISET_SPI0RX_EN (0x1 << 13 ) /* EN. When read: DMA SPI0RX is using a high priority level. When written: SPI0RX uses the high priority level. */
/* DMAPRISET[SPI0TX] - DMA SPI0 TX. */
#define DMAPRISET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200730)
#define DMAPRISET_SPI0TX_MSK (0x1 << 12 )
#define DMAPRISET_SPI0TX (0x1 << 12 )
#define DMAPRISET_SPI0TX_DIS (0x0 << 12 ) /* DIS. When read: DMA SPI0TX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set SPI0TX to the default priority level. */
#define DMAPRISET_SPI0TX_EN (0x1 << 12 ) /* EN. When read: DMA SPI0TX is using a high priority level. When written: SPI0TX uses the high priority level. */
/* DMAPRISET[ADC] - DMA ADC. */
#define DMAPRISET_ADC_BBA (*(volatile unsigned long *) 0x4220072C)
#define DMAPRISET_ADC_MSK (0x1 << 11 )
#define DMAPRISET_ADC (0x1 << 11 )
#define DMAPRISET_ADC_DIS (0x0 << 11 ) /* DIS. When read: DMA ADC is using the default priority level. When written: No effect. Use the DMAPRICLR register to set ADC to the default priority level. */
#define DMAPRISET_ADC_EN (0x1 << 11 ) /* EN. When read: DMA ADCs using a high priority level. When written: ADC uses the high priority level. */
/* DMAPRISET[I2CMRX] - DMA I2C Master RX. */
#define DMAPRISET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220071C)
#define DMAPRISET_I2CMRX_MSK (0x1 << 7 )
#define DMAPRISET_I2CMRX (0x1 << 7 )
#define DMAPRISET_I2CMRX_DIS (0x0 << 7 ) /* DIS. When read: DMA I2CMRX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set I2CMRX to the default priority level. */
#define DMAPRISET_I2CMRX_EN (0x1 << 7 ) /* EN. When read: DMA I2CMRX is using a high priority level. When written: I2CMRX uses the high priority level. */
/* DMAPRISET[I2CMTX] - DMA I2C Master TX. */
#define DMAPRISET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200718)
#define DMAPRISET_I2CMTX_MSK (0x1 << 6 )
#define DMAPRISET_I2CMTX (0x1 << 6 )
#define DMAPRISET_I2CMTX_DIS (0x0 << 6 ) /* DIS. When read: DMA I2CMTX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set I2CMTX to the default priority level. */
#define DMAPRISET_I2CMTX_EN (0x1 << 6 ) /* EN. When read: DMA I2CMTX is using a high priority level. When written: I2CMTX uses the high priority level. */
/* DMAPRISET[I2CSRX] - DMA I2C Slave RX. */
#define DMAPRISET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200714)
#define DMAPRISET_I2CSRX_MSK (0x1 << 5 )
#define DMAPRISET_I2CSRX (0x1 << 5 )
#define DMAPRISET_I2CSRX_DIS (0x0 << 5 ) /* DIS. When read: DMA I2CSRX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set I2CSRX to the default priority level. */
#define DMAPRISET_I2CSRX_EN (0x1 << 5 ) /* EN. When read: DMA I2CSRX is using a high priority level. When written: I2CSRX uses the high priority level. */
/* DMAPRISET[I2CSTX] - DMA I2C Slave TX. */
#define DMAPRISET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200710)
#define DMAPRISET_I2CSTX_MSK (0x1 << 4 )
#define DMAPRISET_I2CSTX (0x1 << 4 )
#define DMAPRISET_I2CSTX_DIS (0x0 << 4 ) /* DIS. When read: DMA I2CSTX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set I2CSTX to the default priority level. */
#define DMAPRISET_I2CSTX_EN (0x1 << 4 ) /* EN. When read: DMA I2CSTX is using a high priority level. When written: I2CSTX uses the high priority level. */
/* DMAPRISET[UARTRX] - DMA UART RX. */
#define DMAPRISET_UARTRX_BBA (*(volatile unsigned long *) 0x4220070C)
#define DMAPRISET_UARTRX_MSK (0x1 << 3 )
#define DMAPRISET_UARTRX (0x1 << 3 )
#define DMAPRISET_UARTRX_DIS (0x0 << 3 ) /* DIS. When read: DMA UARTRX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set UARTRX to the default priority level. */
#define DMAPRISET_UARTRX_EN (0x1 << 3 ) /* EN. When read: DMA UARTRX is using a high priority level. When written: UARTRX uses the high priority level. */
/* DMAPRISET[UARTTX] - DMA UART TX. */
#define DMAPRISET_UARTTX_BBA (*(volatile unsigned long *) 0x42200708)
#define DMAPRISET_UARTTX_MSK (0x1 << 2 )
#define DMAPRISET_UARTTX (0x1 << 2 )
#define DMAPRISET_UARTTX_DIS (0x0 << 2 ) /* DIS. When read: DMA UARTTX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set UARTTX to the default priority level. */
#define DMAPRISET_UARTTX_EN (0x1 << 2 ) /* EN. When read: DMA UARTTX is using a high priority level. When written: UARTTX uses the high priority level. */
/* DMAPRISET[SPI1RX] - DMA SPI 1 RX. */
#define DMAPRISET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200704)
#define DMAPRISET_SPI1RX_MSK (0x1 << 1 )
#define DMAPRISET_SPI1RX (0x1 << 1 )
#define DMAPRISET_SPI1RX_DIS (0x0 << 1 ) /* DIS. When read: DMA SPI1RX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set SPI1RX to the default priority level. */
#define DMAPRISET_SPI1RX_EN (0x1 << 1 ) /* EN. When read: DMA SPI1RX is using a high priority level. When written: SPI1RX uses the high priority level. */
/* DMAPRISET[SPI1TX] - DMA SPI 1 TX. */
#define DMAPRISET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200700)
#define DMAPRISET_SPI1TX_MSK (0x1 << 0 )
#define DMAPRISET_SPI1TX (0x1 << 0 )
#define DMAPRISET_SPI1TX_DIS (0x0 << 0 ) /* DIS. When read: DMA SPI1TX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set SPI1TX to the default priority level. */
#define DMAPRISET_SPI1TX_EN (0x1 << 0 ) /* EN. When read: DMA SPI1TX is using a high priority level. When written: SPI1TX uses the high priority level. */
/* Reset Value for DMAPRICLR*/
#define DMAPRICLR_RVAL 0x0
/* DMAPRICLR[SPI0RX] - DMA SPI0 RX. */
#define DMAPRICLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422007B4)
#define DMAPRICLR_SPI0RX_MSK (0x1 << 13 )
#define DMAPRICLR_SPI0RX (0x1 << 13 )
#define DMAPRICLR_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMAPRISET register to set SPI0RX to the high priority level. */
__IOuint16_tFEEAEN0;/*!< Interrupt Abort Register (Interrupt 15 to Interrupt 0) */
__Iuint16_tRESERVED15;
__IOuint16_tFEEAEN1;/*!< Interrupt Abort Register (Interrupt 31 to Interrupt 16) */
__Iuint16_tRESERVED16;
__IOuint16_tFEEAEN2;/*!< Interrupt Abort Register (Interrupt 42 to Interrupt 32) */
}ADI_FEE_TypeDef;
#else // (__NO_MMR_STRUCTS__==0)
#define FEESTA (*(volatile unsigned short int *) 0x40002800)
#define FEECON0 (*(volatile unsigned short int *) 0x40002804)
#define FEECMD (*(volatile unsigned short int *) 0x40002808)
#define FEEADR0L (*(volatile unsigned short int *) 0x40002810)
#define FEEADR0H (*(volatile unsigned short int *) 0x40002814)
#define FEEADR1L (*(volatile unsigned short int *) 0x40002818)
#define FEEADR1H (*(volatile unsigned short int *) 0x4000281C)
#define FEEKEY (*(volatile unsigned short int *) 0x40002820)
#define FEEPROL (*(volatile unsigned short int *) 0x40002828)
#define FEEPROH (*(volatile unsigned short int *) 0x4000282C)
#define FEESIGL (*(volatile unsigned short int *) 0x40002830)
#define FEESIGH (*(volatile unsigned short int *) 0x40002834)
#define FEECON1 (*(volatile unsigned short int *) 0x40002838)
#define FEEADRAL (*(volatile unsigned short int *) 0x40002848)
#define FEEADRAH (*(volatile unsigned short int *) 0x4000284C)
#define FEEAEN0 (*(volatile unsigned short int *) 0x40002878)
#define FEEAEN1 (*(volatile unsigned short int *) 0x4000287C)
#define FEEAEN2 (*(volatile unsigned short int *) 0x40002880)
#endif // (__NO_MMR_STRUCTS__==0)
/* Reset Value for FEESTA*/
#define FEESTA_RVAL 0x0
/* FEESTA[SIGNERR] - Kernel space signature check on reset error */
#define FEESTA_SIGNERR_BBA (*(volatile unsigned long *) 0x42050018)
#define FEESTA_SIGNERR_MSK (0x1 << 6 )
#define FEESTA_SIGNERR (0x1 << 6 )
#define FEESTA_SIGNERR_CLR (0x0 << 6 ) /* CLR. Cleared, if the signature check of the kernel passes. */
#define FEESTA_SIGNERR_SET (0x1 << 6 ) /* SET. Set, if the signature check of the kernel fails. User code does not execute. */
/* FEESTA[CMDRES] - These two bits indicate the status of a command on completion or the status of a write. If multiple commands are executed or there are multiple writes via the AHB bus without a read of the status register, then the first error encountered is stored. */
#define FEESTA_CMDRES_MSK (0x3 << 4 )
#define FEESTA_CMDRES_SUCCESS (0x0 << 4 ) /* SUCCESS. Indicates a successful completion of a command or a write. Also cleared after a read of FEESTA. */
#define FEESTA_CMDRES_PROTECTED (0x1 << 4 ) /* PROTECTED. Indicates an attempted erase of a protected location. */
#define FEESTA_CMDRES_VERIFYERR (0x2 << 4 ) /* VERIFYERR. Indicates a read verify error. After an erase the controller reads the corresponding word(s) to verify that the transaction completed successfully. If data read is not all 'F's this is the resulting status. If the Sign command is executed and the resulting signature does not match the data in the upper 4 bytes of the upper page in a block then this is the resulting status. */
#define FEESTA_CMDRES_ABORT (0x3 << 4 ) /* ABORT. Indicates that a command or a write was aborted by an abort command or a system interrupt has caused an abort. */
/* FEESTA[WRDONE] - Write complete. */
#define FEESTA_WRDONE_BBA (*(volatile unsigned long *) 0x4205000C)
#define FEESTA_WRDONE_MSK (0x1 << 3 )
#define FEESTA_WRDONE (0x1 << 3 )
#define FEESTA_WRDONE_CLR (0x0 << 3 ) /* CLR. Cleared after a read of FEESTA. */
#define FEESTA_WRDONE_SET (0x1 << 3 ) /* SET. Set when a write completes. If there are multiple writes or a burst write, this status bit asserts after the first long word written and stays asserted until read. If there is a burst write to flash, then this bit asserts after every long word written, assuming that user code read FEESTA after every long word written. */
/* FEESTA[CMDDONE] - Command complete. */
#define FEESTA_CMDDONE_BBA (*(volatile unsigned long *) 0x42050008)
#define FEESTA_CMDDONE_MSK (0x1 << 2 )
#define FEESTA_CMDDONE (0x1 << 2 )
#define FEESTA_CMDDONE_CLR (0x0 << 2 ) /* CLR. Cleared after a read of FEESTA. */
#define FEESTA_CMDDONE_SET (0x1 << 2 ) /* SET. Set when a command completes. If there are multiple commands, this status bit asserts after the first command completes and stays asserted until read. */
/* FEESTA[WRBUSY] - Write busy. */
#define FEESTA_WRBUSY_BBA (*(volatile unsigned long *) 0x42050004)
#define FEESTA_WRBUSY_MSK (0x1 << 1 )
#define FEESTA_WRBUSY (0x1 << 1 )
#define FEESTA_WRBUSY_CLR (0x0 << 1 ) /* CLR. Cleared after a read of FEESTA. */
#define FEESTA_WRBUSY_SET (0x1 << 1 ) /* SET. Set when the flash block is executing a write. */
/* FEESTA[CMDBUSY] - Command busy. */
#define FEESTA_CMDBUSY_BBA (*(volatile unsigned long *) 0x42050000)
#define FEESTA_CMDBUSY_MSK (0x1 << 0 )
#define FEESTA_CMDBUSY (0x1 << 0 )
#define FEESTA_CMDBUSY_CLR (0x0 << 0 ) /* CLR. Cleared after a read of FEESTA. */
#define FEESTA_CMDBUSY_SET (0x1 << 0 ) /* SET. Set when the flash block is executing any command entered via the command register. */
/* Reset Value for FEECON0*/
#define FEECON0_RVAL 0x0
/* FEECON0[WREN] - Write enable bit. */
#define FEECON0_WREN_BBA (*(volatile unsigned long *) 0x42050088)
#define FEECON0_WREN_MSK (0x1 << 2 )
#define FEECON0_WREN (0x1 << 2 )
#define FEECON0_WREN_DIS (0x0 << 2 ) /* DIS. Disables Flash writes. A flash write when this bit is 0 results in a hard fault system exception error and the write does not take place. */
#define FEECMD_CMD_ERASEPAGE (0x1 << 0 ) /* ERASEPAGE. Write the address of the page to be erased to FEEADR0L/H, then write this code to the FEECMD register and the flash will erase the page. When the erase has completed, the flash reads every location in the page to verify that all words in the page are erased. If there is a read verify error, this is indicated in FEESTA. To erase multiple pages, wait until a previous page erase has completed. Check the status, and then issue a command to start the next page erase. Before entering this command, 0xF456 followed by 0xF123 must be written to the key register. */
#define FEECMD_CMD_SIGN (0x2 << 0 ) /* SIGN. Use this command to generate a signature for a block of data. The signature is generated on a page-by-page basis. To generate a signature, the address of the first page of the block is entered in FEEADR0L/FEEADR0H. The address of the last page is written to FEEADR1L/FEEADR1H. Then write this code to the FEECMD register. When the command has completed, the signature is available for reading in FEESIGL/FEESIGH. The last four bytes of the last page in a block is reserved for storing the signature. Before entering this command, 0xF456 followed 0xF123 must be written to the key register. */
#define FEECMD_CMD_MASSERASE (0x3 << 0 ) /* MASSERASE. Erase all of user space. To enable this operation, 0xF456 followed by 0xF123 must first be written to FEEKEY (this is to prevent accidental erases). When the mass erase has completed, the controller reads every location to verify that all locations are 0xFFFFFFFF. If there is a read verify error this is indicated in FEESTA. */
#define FEECMD_CMD_ABORT (0x4 << 0 ) /* ABORT. If this command is issued, then any command currently in progress is stopped. The status indicates command completed with an error status in FEESTA[5:4]. Note that this is the only command that can be issued while another command is already in progress. This command can also be used to stop a write that may be in progress. If a write is aborted, the address of the location being written can be read via the FEEADRAL/FEEADRAH register. While the flash controller is writing one longword, another longword write may be in the pipeline from the Cortex-M3 or DMA engine (depending on how the software implements writes). Therefore, both writes may need to be aborted. If a write or erase is aborted, then the flash timing is violated and it is not possible to determine if the write or erase completed successfully. To enable this operation, 0xF456 followed by 0xF123 must first be written to FEEKEY (this is to prevent accidental aborts). */
/* Reset Value for FEEADR0L*/
#define FEEADR0L_RVAL 0x0
/* FEEADR0L[VALUE] - Used in conjunction with FEEADR0H, to indicate the page to be erased, or the start of a section to be signed. The address of a memory location inside the page should be stored in FEEADR0L/H, bits[15:0] in FEEADR0L, and bits[17:16] in FEEADR0H. The 9 LSBs of the address are ignored. */
#define FEEADR0L_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for FEEADR0H*/
#define FEEADR0H_RVAL 0x0
/* FEEADR0H[VALUE] - Used in conjunction with FEEADR0L, to indicate the page to be erased, or the start of a section to be signed. The address of a memory location inside the page should be stored in FEEADR0L/H, bits[15:0] in FEEADR0L, and bits[17:16] in FEEADR0H. */
#define FEEADR0H_VALUE_MSK (0x3 << 0 )
/* Reset Value for FEEADR1L*/
#define FEEADR1L_RVAL 0x0
/* FEEADR1L[VALUE] - Used in conjunction with FEEADR1H, to identify the last page used by the Sign command. The address of a memory location inside the page should be stored in FEEADR1L/H, bits[15:0] in FEEADR1L, and bits[17:16] in FEEADR1H. The 9 LSBs of the address are ignored. */
#define FEEADR1L_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for FEEADR1H*/
#define FEEADR1H_RVAL 0x0
/* FEEADR1H[VALUE] - Used in conjunction with FEEADR1L, to identify the last page used by the Sign command. The address of a memory location inside the page should be stored in FEEADR1L/H, bits[15:0] in FEEADR1L, and bits[17:16] in FEEADR1H. */
#define FEEADR1H_VALUE_MSK (0x3 << 0 )
/* Reset Value for FEEKEY*/
#define FEEKEY_RVAL 0x0
/* FEEKEY[VALUE] - Enter 0xF456 followed by 0xF123. Returns 0x0 if read. */
/* FEEPROL[VALUE] - Lower 16 bits of the write protection. This register is read only if the write protection in flash has been programmed, i.e. FEEPROH/L have previously been configured to protect pages. */
#define FEEPROL_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for FEEPROH*/
#define FEEPROH_RVAL 0xFFFF
/* FEEPROH[VALUE] - Upper 16 bits of the write protection. This register is read only if the write protection in flash has been programmed, i.e. FEEPROH/L have previously been configured to protect pages. */
#define FEEPROH_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for FEESIGL*/
#define FEESIGL_RVAL 0xFFFF
/* FEESIGL[VALUE] - Lower 16 bits of the signature. Signature[15:0]. */
#define FEESIGL_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for FEESIGH*/
#define FEESIGH_RVAL 0xFFFF
/* FEESIGH[VALUE] - Upper eight bits of the signature. Signature[23:16]. */
#define FEESIGH_VALUE_MSK (0xFF << 0 )
/* Reset Value for FEECON1*/
#define FEECON1_RVAL 0x1
/* FEECON1[DBG] - Serial Wire debug enable. */
#define FEECON1_DBG_BBA (*(volatile unsigned long *) 0x42050700)
#define FEECON1_DBG_MSK (0x1 << 0 )
#define FEECON1_DBG (0x1 << 0 )
#define FEECON1_DBG_DIS (0x0 << 0 ) /* DIS. Disable access via the serial wire debug interface. */
#define FEECON1_DBG_EN (0x1 << 0 ) /* EN. Enable access via the serial wire debug interface. */
/* Reset Value for FEEADRAL*/
#define FEEADRAL_RVAL 0x800
/* FEEADRAL[VALUE] - Lower 16 bits of the FEEADRA register. If a write is aborted then this will contain the address of the location been written when the write was aborted. */
#define FEEADRAL_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for FEEADRAH*/
#define FEEADRAH_RVAL 0x2
/* FEEADRAH[VALUE] - Upper 16 bits of the FEEADRA register. */
#define FEEADRAH_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for FEEAEN0*/
#define FEEAEN0_RVAL 0x0
/* FEEAEN0[FEE] - Flash controller interrupt abort enable bit */
#define FEEAEN0_FEE_BBA (*(volatile unsigned long *) 0x42050F3C)
/* GPDWN[DWN1] - Pull down resistor control bit */
#define GPDWN_DWN1_BBA (*(volatile unsigned long *) 0x420C1E04)
#define GPDWN_DWN1_MSK (0x1 << 1 )
#define GPDWN_DWN1 (0x1 << 1 )
#define GPDWN_DWN1_EN (0x0 << 1 ) /* EN to enable the pull down resistor on P3.4 by software. The hardware only enables this pull down automatically at power up. */
#define GPDWN_DWN1_DIS (0x1 << 1 ) /* DIS to disable the pull down resistor on P3.4. Disabled automatically by hardware if GP3PUL[4] =1 or if GP3OEN[4]=1. */
#define I2CMCON_IENCMP_EN (0x1 << 8 ) /* EN. Interrupt enabled. A master I2C interrupt is generated when a STOP is detected. Enables TCOMP to geneerate an interrupt. */
/* I2CMCON[IENNACK] - NACK received interrupt enable. */
#define I2CMCON_IENNACK_BBA (*(volatile unsigned long *) 0x4206001C)
#define I2CMCON_IENALOST_EN (0x1 << 6 ) /* EN. Interrupt enabled. A master I2C interrupt is generated if the master looses arbitration.Enables ALOST to generate an interrupt. */
#define I2CMCON_IENTX_EN (0x1 << 5 ) /* EN. Interrupt enabled. A master I2C interrupt is generated when the Tx FIFO is not full and the direction bit is 0. */
#define I2CMCON_STRETCH_EN (0x1 << 3 ) /* EN. Setting this bit instructs the device that if I2CSCL is 0, hold it at 0. Or if I2CSCL is 1, then when it next goes to 0, hold it at 0. */
/* I2CMCON[LOOPBACK] - Internal loop back enable. */
#define I2CMCON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42060008)
#define I2CMCON_LOOPBACK_EN (0x1 << 2 ) /* EN. I2CSCL and I2CSDA out of the device are muxed onto their corresponding inputs. Note that is also possible for the master to loop back a transfer to the slave as long as the device address corresponds, that is, external loopback. */
/* I2CMCON[COMPETE] - Start back-off disable. */
#define I2CMCON_COMPETE_BBA (*(volatile unsigned long *) 0x42060004)
#define I2CMCON_COMPETE_EN (0x1 << 1 ) /* EN. Enables the device to compete for ownership even if another device is currently driving a start condition. */
/* I2CMCON[MAS] - Master enable bit. */
#define I2CMCON_MAS_BBA (*(volatile unsigned long *) 0x42060000)
#define I2CMCON_MAS_MSK (0x1 << 0 )
#define I2CMCON_MAS (0x1 << 0 )
#define I2CMCON_MAS_DIS (0x0 << 0 ) /* DIS. The master is disabled. The master state machine is reset.The master should be disabled when not in use. This bit should not be cleared until a transaction has completed. TCOMP in I2CMSTA indicates when a transaction is complete. */
#define I2CMSTA_TXUR_SET (0x1 << 12 ) /* SET. Set when the I2C master ends the transaction due to a Tx FIFO empty condition. This bit is only set when IENTX (I2CSCON[5]) is set. */
/* I2CMSTA[MSTOP] - STOP driven by the I2C master. */
#define I2CMSTA_MSTOP_BBA (*(volatile unsigned long *) 0x420600AC)
#define I2CMSTA_MSTOP_SET (0x1 << 11 ) /* SET. Set when the I2C master drives a stop condition on the I2C bus, therefore indicating a transaction completion, Tx underrun, Rx overflow, or a NACK by the slave. It is different from TCOMP because it is not set when the stop condition occurs due to any other master on the I2C bus. This bit does not generate an interrupt. See the TCOMP description for available interrupts related to the stop condition. */
/* I2CMSTA[LINEBUSY] - Line is busy. */
#define I2CMSTA_LINEBUSY_BBA (*(volatile unsigned long *) 0x420600A8)
#define I2CMSTA_LINEBUSY_MSK (0x1 << 10 )
#define I2CMSTA_LINEBUSY (0x1 << 10 )
#define I2CMSTA_LINEBUSY_CLR (0x0 << 10 ) /* CLR. Cleared when a stop is detected on the I2C bus. */
#define I2CMSTA_LINEBUSY_SET (0x1 << 10 ) /* SET. Set when a start is detected on the I2C bus. */
/* I2CMSTA[RXOF] - Receive FIFO overflow. */
#define I2CMSTA_RXOF_BBA (*(volatile unsigned long *) 0x420600A4)
#define I2CMSTA_TCOMP_SET (0x1 << 8 ) /* SET. Set when a STOP condition is detected on the I2C bus. If IENCMP is 1, an interrupt is generated when this bit asserts. This bit only asserts if the master is enabled (MASEN = 1). This bit should be used to determine when it is safe to disable the master. It can also be used to wait for another master's transaction to complete on the I2C bus when this master loses arbitration. */
/* I2CMSTA[NACKDATA] - NACK received in response to data write. (Can drive an interrupt). */
#define I2CMSTA_NACKDATA_BBA (*(volatile unsigned long *) 0x4206009C)
#define I2CMSTA_NACKDATA_MSK (0x1 << 7 )
#define I2CMSTA_NACKDATA (0x1 << 7 )
#define I2CMSTA_NACKDATA_CLR (0x0 << 7 ) /* CLR. Cleared on a read of the I2CMSTA register. */
#define I2CMSTA_NACKDATA_SET (0x1 << 7 ) /* SET. Set when a NACK is received in response to a data write transfer. If IENNACK is 1, an interrupt is generated when this bit asserts. */
/* I2CMSTA[BUSY] - Master busy. */
#define I2CMSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060098)
#define I2CMSTA_BUSY_MSK (0x1 << 6 )
#define I2CMSTA_BUSY (0x1 << 6 )
#define I2CMSTA_BUSY_CLR (0x0 << 6 ) /* CLR. Cleared if the state machine is idle or another device has control of the I2C bus. */
#define I2CMSTA_BUSY_SET (0x1 << 6 ) /* SET. Set when the master state machine is servicing a transaction. */
/* I2CMSTA[ALOST] - Arbitration lost. (Can drive an interrupt). */
#define I2CMSTA_ALOST_BBA (*(volatile unsigned long *) 0x42060094)
#define I2CMSTA_ALOST_MSK (0x1 << 5 )
#define I2CMSTA_ALOST (0x1 << 5 )
#define I2CMSTA_ALOST_CLR (0x0 << 5 ) /* CLR. Cleared on a read of the I2CMSTA register. */
#define I2CMSTA_ALOST_SET (0x1 << 5 ) /* SET. Set if the master looses arbitration. If IENALOST is 1, an interrupt is generated when this bit asserts. */
/* I2CMSTA[NACKADDR] - NACK received in response to an address. (Can drive an interrupt). */
#define I2CMSTA_NACKADDR_BBA (*(volatile unsigned long *) 0x42060090)
#define I2CMSTA_NACKADDR_MSK (0x1 << 4 )
#define I2CMSTA_NACKADDR (0x1 << 4 )
#define I2CMSTA_NACKADDR_CLR (0x0 << 4 ) /* CLR. Cleared on a read of the I2CMSTA register. */
#define I2CMSTA_NACKADDR_SET (0x1 << 4 ) /* SET. Set if a NACK received in response to an address. If IENNACK is 1, an interrupt is generated when this bit asserts. */
/* I2CMSTA[RXREQ] - Receive Request. (Can drive an interrupt). */
#define I2CMSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206008C)
#define I2CMSTA_RXREQ_SET (0x1 << 3 ) /* SET. Set when there is data in the receive FIFO. If IENRX is 1, an interrupt is generated when this bit asserts. */
/* I2CMSTA[TXREQ] - Transmit Request. (Can drive an interrupt). */
#define I2CMSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060088)
#define I2CMSTA_TXREQ_MSK (0x1 << 2 )
#define I2CMSTA_TXREQ (0x1 << 2 )
#define I2CMSTA_TXREQ_CLR (0x0 << 2 ) /* CLR. Cleared when the transmit FIFO underrun condition is not met. */
#define I2CMSTA_TXREQ_SET (0x1 << 2 ) /* SET. Set when the direction bit is 0 and the transmit FIFO is either empty or not full. If IENTX is 1, an interrupt is generated when this bit asserts. */
/* I2CMRX[VALUE] - Receive register. This register allows access to the receive data FIFO. The FIFO can hold two bytes. */
#define I2CMRX_VALUE_MSK (0xFF << 0 )
/* Reset Value for I2CMTX*/
#define I2CMTX_RVAL 0x0
/* I2CMTX[VALUE] - Transmit register. This register allows access to the transmit data FIFO. The FIFO can hold two bytes. */
#define I2CMTX_VALUE_MSK (0xFF << 0 )
/* Reset Value for I2CMRXCNT*/
#define I2CMRXCNT_RVAL 0x0
/* I2CMRXCNT[EXTEND] - Extended read: Use this bit if greater than 256 bytes are required on a read. For example: To receive 412 bytes, write 0x100 (EXTEND = 1) to this register (I2CMRXCNT). Wait for the first byte to be received, then check the I2CMCRXCNT register for every byte received thereafter. When I2CMCRXCNT returns to 0, 256 bytes have been received. Then, write 0x09C (412 - 256 = 156 decimal (equal to 0x9C) with the EXTEND bit set to 0) to this register (I2CMRXCNT). */
#define I2CMRXCNT_EXTEND_BBA (*(volatile unsigned long *) 0x42060220)
/* I2CMRXCNT[COUNT] - Receive count. Program the number of bytes required minus one to this register. If just one byte is required write 0 to this register. If greater than 256 bytes are required, then use EXTEND. */
#define I2CMRXCNT_COUNT_MSK (0xFF << 0 )
/* Reset Value for I2CMCRXCNT*/
#define I2CMCRXCNT_RVAL 0x0
/* I2CMCRXCNT[VALUE] - Current receive count. This register gives the total number of bytes received so far. If 256 bytes are requested, then this register reads 0 when the transaction has completed. */
#define I2CMCRXCNT_VALUE_MSK (0xFF << 0 )
/* Reset Value for I2CADR0*/
#define I2CADR0_RVAL 0x0
/* I2CADR0[VALUE] - Address byte. If a 7-bit address is required, then I2CADR0[7:1] is programmed with the address and I2CADR0[0] is programmed with the direction (read or write). If a 10-bit address is required then I2CADR0[7:3] is programmed with '11110', I2CADR0[2:1] is programmed with the two MSBs of the address, and, again, I2CADR0[0] is programmed with the direction bit (read or write). */
#define I2CADR0_VALUE_MSK (0xFF << 0 )
/* Reset Value for I2CADR1*/
#define I2CADR1_RVAL 0x0
/* I2CADR1[VALUE] - Address byte. This register is only required when addressing a slave with 10-bit addressing. I2CADR1[7:0] is programmed with the lower eight bits of the address. */
#define I2CADR1_VALUE_MSK (0xFF << 0 )
/* Reset Value for I2CDIV*/
#define I2CDIV_RVAL 0x1F1F
/* I2CDIV[HIGH] - Serial clock high time. This register controls the clock high time. See the serial clock generation section for more details. */
#define I2CDIV_HIGH_MSK (0xFF << 8 )
/* I2CDIV[LOW] - Serial clock low time. This register controls the clock low time. See the serial clock generation section for more details. */
#define I2CSCON_NACK_EN (0x1 << 7 ) /* EN. Allow the next communication to be NACK'ed. This can be used for example if during a 24xx I2C serial eeprom style access, an attempt was made to write to a read only or nonexisting location in system memory. That is the indirect address in a 24xx I2C serial eeprom style write pointed to an unwritable memory location. */
/* I2CSCON[STRETCH] - Stretch I2CSCL enable. */
#define I2CSCON_STRETCH_BBA (*(volatile unsigned long *) 0x42060518)
#define I2CSCON_STRETCH_EN (0x1 << 6 ) /* EN. Tell the device that, if I2CSCL is 0, hold it at 0. Or if I2CSCL is 1, then when it next goes to 0 hold it at 0. */
/* I2CSCON[EARLYTXR] - Early transmit request mode. */
#define I2CSCON_EARLYTXR_BBA (*(volatile unsigned long *) 0x42060514)
#define I2CSCON_EARLYTXR_EN (0x1 << 5 ) /* EN. Enable a transmit request just after the positive edge of the direction bit (READ/WRITE) I2CSCL clock pulse. */
/* I2CSCON[GCSB] - General call status bit clear. */
#define I2CSCON_GCSB_BBA (*(volatile unsigned long *) 0x42060510)
#define I2CSCON_GCSB_MSK (0x1 << 4 )
#define I2CSCON_GCSB (0x1 << 4 )
#define I2CSCON_GCSB_CLR (0x1 << 4 ) /* CLR. Clear the General Call status and General Call ID bits. The General Call status and General Call ID bits are not reset by anything other than a write to this bit or a full reset. */
/* I2CSCON[HGC] - Hardware general call enable. */
#define I2CSCON_HGC_BBA (*(volatile unsigned long *) 0x4206050C)
#define I2CSCON_HGC_EN (0x1 << 3 ) /* EN. When this bit and the General Call enable bit are set the device after receiving a general call, Address 0x00 and a data byte checks the contents of the I2CALT against the receive shift register. If they match, the device has received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a broadcast message to all master devices in the bus. The device that requires attention embeds its own address into the message. The LSB of the I2CALT register should always be written to a 1. */
/* I2CSCON[GC] - General call enable. */
#define I2CSCON_GC_BBA (*(volatile unsigned long *) 0x42060508)
#define I2CSCON_GC_EN (0x1 << 2 ) /* EN. Enable the I2C slave to ACK an I2C general call, Address 0x00 (write). */
/* I2CSCON[ADR10] - Enable 10 bit addressing. */
#define I2CSCON_ADR10_BBA (*(volatile unsigned long *) 0x42060504)
#define I2CSCON_ADR10_MSK (0x1 << 1 )
#define I2CSCON_ADR10 (0x1 << 1 )
#define I2CSCON_ADR10_DIS (0x0 << 1 ) /* DIS. If this bit is clear, the slave can support four slave addresses, programmed in Registers I2CID0 to I2CID3. */
#define I2CSCON_ADR10_EN (0x1 << 1 ) /* EN. Enable 10-bit addressing. One 10-bit address is supported by the slave and is stored in I2CID0 and I2CID1, where I2CID0 contains the first byte of the address and the upper five bits must be programmed to 11110' I2CID2 and I2CID3 can be programmed with 7-bit addresses at the same time. */
/* I2CSCON[SLV] - Slave enable. */
#define I2CSCON_SLV_BBA (*(volatile unsigned long *) 0x42060500)
#define I2CSCON_SLV_MSK (0x1 << 0 )
#define I2CSCON_SLV (0x1 << 0 )
#define I2CSCON_SLV_DIS (0x0 << 0 ) /* DIS. Disable the slave and all slave state machine flops are held in reset. */
/* I2CSSTA[START] - Start and matching address. */
#define I2CSSTA_START_BBA (*(volatile unsigned long *) 0x420605B8)
#define I2CSSTA_START_MSK (0x1 << 14 )
#define I2CSSTA_START (0x1 << 14 )
#define I2CSSTA_START_CLR (0x0 << 14 ) /* CLR. Cleared on receipt of either a stop or start condition. */
#define I2CSSTA_START_SET (0x1 << 14 ) /* SET. Set if a start is detected on I2CSCL/I2CSDA and one of the following is true: The device address is matched. A general call (GC = 0000_0000) code is received and GC is enabled. A high speed (HS = 0000_1XXX) code is received. A start byte (0000_0001) is received. */
/* I2CSSTA[REPSTART] - Repeated start and matching address. (Can drive an interrupt). */
#define I2CSSTA_REPSTART_BBA (*(volatile unsigned long *) 0x420605B4)
#define I2CSSTA_REPSTART_MSK (0x1 << 13 )
#define I2CSSTA_REPSTART (0x1 << 13 )
#define I2CSSTA_REPSTART_CLR (0x0 << 13 ) /* CLR. Cleared when read or on receipt of a stop condition. */
#define I2CSSTA_REPSTART_SET (0x1 << 13 ) /* SET. Set if START (I2CSSTA[14]) is already asserted and then a repeated start is detected. */
/* I2CSSTA[IDMAT] - Device ID matched. */
#define I2CSSTA_IDMAT_MSK (0x3 << 11 )
/* I2CSSTA[STOP] - Stop after start and matching address. (Can drive an interrupt). */
#define I2CSSTA_STOP_BBA (*(volatile unsigned long *) 0x420605A8)
#define I2CSSTA_STOP_MSK (0x1 << 10 )
#define I2CSSTA_STOP (0x1 << 10 )
#define I2CSSTA_STOP_CLR (0x0 << 10 ) /* CLR. Cleared by a read of the status register. */
#define I2CSSTA_STOP_SET (0x1 << 10 ) /* SET. Set if the slave device received a stop condition after a previous start condition and a matching address. */
/* I2CSSTA[GCID] - General call ID. Cleared when the GCSBCLR (I2CSCON[4]) is written to 1. These status bits are not cleared by a general call reset. */
#define I2CSSTA_GCID_MSK (0x3 << 8 )
/* I2CSSTA[GCINT] - General call interrupt. (Always drives an interrupt). */
#define I2CSSTA_GCINT_BBA (*(volatile unsigned long *) 0x4206059C)
#define I2CSSTA_GCINT_MSK (0x1 << 7 )
#define I2CSSTA_GCINT (0x1 << 7 )
#define I2CSSTA_GCINT_CLR (0x0 << 7 ) /* CLR. To clear this bit, write 1 to the I2CSCON[4]. If it was a general call reset, all registers are at their default values. If it was a hardware general call, the Rx FIFO holds the second byte of the general call and this can be compared with the ALT register. */
#define I2CSSTA_GCINT_SET (0x1 << 7 ) /* SET. Set if the slave device receives a general call of any type. */
/* I2CSSTA[BUSY] - Slave busy. */
#define I2CSSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060598)
#define I2CSSTA_BUSY_MSK (0x1 << 6 )
#define I2CSSTA_BUSY (0x1 << 6 )
#define I2CSSTA_BUSY_CLR (0x0 << 6 ) /* CLR. Cleared by hardware on any of the following conditions: The address does not match an ID register, the slave device receives a I2C stop condition or if a repeated start address doesnt match. */
#define I2CSSTA_BUSY_SET (0x1 << 6 ) /* SET. Set if the slave device receives an I2C start condition. */
/* I2CSSTA[NOACK] - NACK generated by the slave. */
#define I2CSSTA_NOACK_BBA (*(volatile unsigned long *) 0x42060594)
#define I2CSSTA_NOACK_MSK (0x1 << 5 )
#define I2CSSTA_NOACK (0x1 << 5 )
#define I2CSSTA_NOACK_CLR (0x0 << 5 ) /* CLR. Cleared on a read of the I2CSSTA register. */
#define I2CSSTA_NOACK_SET (0x1 << 5 ) /* SET. Set to indicate that the slave responded to its device address with a NACK. Set under any of the following conditions: If there was no data to transmit and sequence was a slave read, the device address is NACK'ed or if the NACK bit was set in the slave control register and the device was addressed. */
/* I2CSSTA[RXOF] - Receive FIFO overflow. */
#define I2CSSTA_RXOF_BBA (*(volatile unsigned long *) 0x42060590)
#define I2CSSTA_RXOF_SET (0x1 << 4 ) /* SET. Set when a byte is written to the receive FIFO when the FIFO is already full. */
/* I2CSSTA[RXREQ] - Receive request. (Can drive an interrupt). */
#define I2CSSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206058C)
#define I2CSSTA_RXREQ_MSK (0x1 << 3 )
#define I2CSSTA_RXREQ (0x1 << 3 )
#define I2CSSTA_RXREQ_CLR (0x0 << 3 ) /* CLR. Cleared when the receive FIFO is read or flushed. */
#define I2CSSTA_RXREQ_SET (0x1 << 3 ) /* SET. Set when the receive FIFO is not empty. Set on the falling edge of the I2CSCL clock pulse that clocks in the last data bit of a byte. */
/* I2CSSTA[TXREQ] - Transmit request. (Can drive an interrupt). */
#define I2CSSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060588)
#define I2CSSTA_TXREQ_MSK (0x1 << 2 )
#define I2CSSTA_TXREQ (0x1 << 2 )
#define I2CSSTA_TXREQ_CLR (0x0 << 2 ) /* CLR. This bit is cleared on a read of the I2CSSTA register. */
#define I2CSSTA_TXREQ_SET (0x1 << 2 ) /* SET. If EARLYTXR = 0, TXREQ is set when the direction bit for a transfer is received high. Thereafter, as long as the transmit FIFO is not full, this bit remains asserted. Initially, it is asserted on the negative edge of the SCL pulse that clocks in the direction bit (if the device address matched also). If EARLYTXR = 1, TXREQ is set when the direction bit for a transfer is received high. Thereafter, as long as the transmit FIFO is not full, this bit will remain asserted. Initially, it is asserted after the positive edge of the SCL pulse that clocks in the direction bit (if the device address matched also). */
/* I2CSSTA[TXUR] - Transmit FIFO underflow. */
#define I2CSSTA_TXUR_BBA (*(volatile unsigned long *) 0x42060584)
#define I2CSSTA_TXUR_SET (0x1 << 1 ) /* SET. Set to 1 if a master requests data from the device and the Tx FIFO is empty for the rising edge of SCL. */
/* I2CSSTA[TXFSEREQ] - Tx FIFO status. */
#define I2CSSTA_TXFSEREQ_BBA (*(volatile unsigned long *) 0x42060580)
#define I2CSSTA_TXFSEREQ_SET (0x1 << 0 ) /* SET. Set whenever the slave Tx FIFO is empty. */
/* Reset Value for I2CSRX*/
#define I2CSRX_RVAL 0x0
/* I2CSRX[VALUE] - Receive register. */
#define I2CSRX_VALUE_MSK (0xFF << 0 )
/* Reset Value for I2CSTX*/
#define I2CSTX_RVAL 0x0
/* I2CSTX[VALUE] - Transmit register. */
#define I2CSTX_VALUE_MSK (0xFF << 0 )
/* Reset Value for I2CALT*/
#define I2CALT_RVAL 0x0
/* I2CALT[VALUE] - ALT register.This register is used in conjunction with HGC (I2CSCON[3]) to match a master generating a hardware general call. It is used in the case where a master device cannot be programmed with a slaves address and, instead, the slave must recognize the masters address. */
/* PWRMOD[WICENACK] - WIC Acknowledge, for cortex M3 deep sleep mode */
#define PWRMOD_WICENACK_BBA (*(volatile unsigned long *) 0x4204800C)
#define PWRMOD_WICENACK_MSK (0x1 << 3 )
#define PWRMOD_WICENACK (0x1 << 3 )
#define PWRMOD_WICENACK_CLR (0x0 << 3 ) /* CLR. Cleared automatically by hardware when the cortex M3 processor is not ready to enter deep sleep mode including if serial wire activity is detected. */
#define PWRMOD_WICENACK_SET (0x1 << 3 ) /* SET. Set automatically by the cortex M3 processor when ready to enter sleep deep mode. */
#define PWMCLRI (*(volatile unsigned short int *) 0x40001008)
#define PWM0COM0 (*(volatile unsigned short int *) 0x40001010)
#define PWM0COM1 (*(volatile unsigned short int *) 0x40001014)
#define PWM0COM2 (*(volatile unsigned short int *) 0x40001018)
#define PWM0LEN (*(volatile unsigned short int *) 0x4000101C)
#define PWM1COM0 (*(volatile unsigned short int *) 0x40001020)
#define PWM1COM1 (*(volatile unsigned short int *) 0x40001024)
#define PWM1COM2 (*(volatile unsigned short int *) 0x40001028)
#define PWM1LEN (*(volatile unsigned short int *) 0x4000102C)
#define PWM2COM0 (*(volatile unsigned short int *) 0x40001030)
#define PWM2COM1 (*(volatile unsigned short int *) 0x40001034)
#define PWM2COM2 (*(volatile unsigned short int *) 0x40001038)
#define PWM2LEN (*(volatile unsigned short int *) 0x4000103C)
#define PWM3COM0 (*(volatile unsigned short int *) 0x40001040)
#define PWM3COM1 (*(volatile unsigned short int *) 0x40001044)
#define PWM3COM2 (*(volatile unsigned short int *) 0x40001048)
#define PWM3LEN (*(volatile unsigned short int *) 0x4000104C)
#endif // (__NO_MMR_STRUCTS__==0)
/* Reset Value for PWMCON0*/
#define PWMCON0_RVAL 0x12
/* PWMCON0[SYNC] - PWM Synchronization. */
#define PWMCON0_SYNC_BBA (*(volatile unsigned long *) 0x4202003C)
#define PWMCON0_SYNC_MSK (0x1 << 15 )
#define PWMCON0_SYNC (0x1 << 15 )
#define PWMCON0_SYNC_DIS (0x0 << 15 ) /* DIS. Ignore transitions on the PWMSYNC pin. */
#define PWMCON0_SYNC_EN (0x1 << 15 ) /* EN. All PWM counters are reset on the next clock edge after the detection of a falling edge on the PWMSYNC pin. */
/* PWMCON0[PWM7INV] - Inversion of PWM output. Available in standard mode only. */
#define PWMCON0_PWM7INV_BBA (*(volatile unsigned long *) 0x42020038)
#define PWMCON0_HOFF_EN (0x1 << 4 ) /* EN. Force PWM0 and PWM2 outputs high and PWM1 and PWM3 low. */
/* PWMCON0[LCOMP] - Load Compare Registers. */
#define PWMCON0_LCOMP_BBA (*(volatile unsigned long *) 0x4202000C)
#define PWMCON0_LCOMP_MSK (0x1 << 3 )
#define PWMCON0_LCOMP (0x1 << 3 )
#define PWMCON0_LCOMP_DIS (0x0 << 3 ) /* DIS. Use the values previously stored in the internal compare registers. */
#define PWMCON0_LCOMP_EN (0x1 << 3 ) /* EN. Load the internal compare registers with the values in PWMxCOMx on the next transition of the PWM timer from 0x00 to 0x01. */
/* PWMCON0[DIR] - Direction Control. Available in H-Bridge mode only. */
#define PWMCON0_DIR_BBA (*(volatile unsigned long *) 0x42020008)
#define PWMCON0_DIR_MSK (0x1 << 2 )
#define PWMCON0_DIR (0x1 << 2 )
#define PWMCON0_DIR_DIS (0x0 << 2 ) /* DIS. Enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low. */
#define PWMCON0_DIR_EN (0x1 << 2 ) /* EN. Enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low. */
/* PWMCON0[HMODE] - Enable H-Bridge Mode. */
#define PWMCON0_HMODE_BBA (*(volatile unsigned long *) 0x42020004)
#define PWMCON0_HMODE_MSK (0x1 << 1 )
#define PWMCON0_HMODE (0x1 << 1 )
#define PWMCON0_HMODE_DIS (0x0 << 1 ) /* DIS. The PWM operates in standard mode. */
#define PWMCON0_HMODE_EN (0x1 << 1 ) /* EN. The PWM is configured in H-Bridge mode. */
/* PWMCON0[PWMEN] - Enable all PWM outputs. */
#define PWMCON0_PWMEN_BBA (*(volatile unsigned long *) 0x42020000)
#define RSTSTA_SWRST_BBA (*(volatile unsigned long *) 0x42048810)
#define RSTSTA_SWRST_MSK (0x1 << 4 )
#define RSTSTA_SWRST (0x1 << 4 )
#define RSTSTA_SWRST_CLR (0x0 << 4 ) /* CLR. Indicates that no software reset has occurred. */
#define RSTSTA_SWRST_SET (0x1 << 4 ) /* SET. Indicates that a software reset has occurred. */
/* RSTSTA[WDRST] - Watchdog reset status bit */
#define RSTSTA_WDRST_BBA (*(volatile unsigned long *) 0x4204880C)
#define RSTSTA_WDRST_MSK (0x1 << 3 )
#define RSTSTA_WDRST (0x1 << 3 )
#define RSTSTA_WDRST_CLR (0x0 << 3 ) /* CLR. Indicates that no watchdog reset has occurred. */
#define RSTSTA_WDRST_SET (0x1 << 3 ) /* SET. Indicates that a Watchdog Reset has occurred. */
/* RSTSTA[EXTRST] - External reset status bit */
#define RSTSTA_EXTRST_BBA (*(volatile unsigned long *) 0x42048808)
#define RSTSTA_EXTRST_MSK (0x1 << 2 )
#define RSTSTA_EXTRST (0x1 << 2 )
#define RSTSTA_EXTRST_CLR (0x0 << 2 ) /* CLR. Indicates that no external reset has occurred. */
#define RSTSTA_EXTRST_SET (0x1 << 2 ) /* SET. Indicates an external reset has occurred. */
/* RSTSTA[PORHV] - Power-on reset status bit HV */
#define RSTSTA_PORHV_BBA (*(volatile unsigned long *) 0x42048804)
#define RSTSTA_PORHV_MSK (0x1 << 1 )
#define RSTSTA_PORHV (0x1 << 1 )
#define RSTSTA_PORHV_CLR (0x0 << 1 ) /* CLR. Indicates a POR or wake up from SHUTDOWN has not occurred. */
#define RSTSTA_PORHV_SET (0x1 << 1 ) /* SET. This bit indicates that the AVDD supply has dropped below the POR trip point, causing a Power On Reset. It is also set when waking up from SHUTDOWN mode. */
/* RSTSTA[PORLV] - Power-on reset status bit LV */
#define RSTSTA_PORLV_BBA (*(volatile unsigned long *) 0x42048800)
#define RSTSTA_PORLV_MSK (0x1 << 0 )
#define RSTSTA_PORLV (0x1 << 0 )
#define RSTSTA_PORLV_CLR (0x0 << 0 ) /* CLR. Indicates a POR or wake up from SHUTDOWN has not occurred. */
#define RSTSTA_PORLV_SET (0x1 << 0 ) /* SET. This bit indicates that the AVDD supply has dropped below the POR trip point, causing a Power On Reset. It is also set when waking up from SHUTDOWN mode. */
/* Reset Value for RSTCLR*/
#define RSTCLR_RVAL 0x3
/* RSTCLR[SWRST] - Software reset clear status bit */
#define RSTCLR_SWRST_BBA (*(volatile unsigned long *) 0x42048810)
#define RSTCLR_SWRST_MSK (0x1 << 4 )
#define RSTCLR_SWRST (0x1 << 4 )
#define RSTCLR_SWRST_DIS (0x0 << 4 ) /* DIS. Has no effect. */
#define RSTCLR_SWRST_EN (0x1 << 4 ) /* EN. Clears the SWRST status bit in RSTSTA. */
/* RSTCLR[WDRST] - Watchdog reset clear status bit */
#define RSTCLR_WDRST_BBA (*(volatile unsigned long *) 0x4204880C)
#define RSTCLR_WDRST_MSK (0x1 << 3 )
#define RSTCLR_WDRST (0x1 << 3 )
#define RSTCLR_WDRST_DIS (0x0 << 3 ) /* DIS. Has no effect. */
#define RSTCLR_WDRST_EN (0x1 << 3 ) /* EN. Clears the WDRST status bit in RSTSTA. */
/* RSTCLR[EXTRST] - External reset clear status bit */
#define RSTCLR_EXTRST_BBA (*(volatile unsigned long *) 0x42048808)
#define RSTCLR_EXTRST_MSK (0x1 << 2 )
#define RSTCLR_EXTRST (0x1 << 2 )
#define RSTCLR_EXTRST_DIS (0x0 << 2 ) /* DIS. Has no effect. */
#define RSTCLR_EXTRST_EN (0x1 << 2 ) /* EN. Clears the EXTRST status bit in RSTSTA. */
/* RSTCLR[PORHV] - Power on reset clear status bit */
#define RSTCLR_PORHV_BBA (*(volatile unsigned long *) 0x42048804)
#define RSTCLR_PORHV_MSK (0x1 << 1 )
#define RSTCLR_PORHV (0x1 << 1 )
#define RSTCLR_PORHV_DIS (0x0 << 1 ) /* DIS. Has no effect. */
#define RSTCLR_PORHV_EN (0x1 << 1 ) /* EN. Clears PORLV status bit in RSTSTA. */
/* RSTCLR[PORLV] - Power-on reset clear status bit LV */
#define RSTCLR_PORLV_BBA (*(volatile unsigned long *) 0x42048800)
#define RSTCLR_PORLV_MSK (0x1 << 0 )
#define RSTCLR_PORLV (0x1 << 0 )
#define RSTCLR_PORLV_DIS (0x0 << 0 ) /* DIS. Has no effect. */
#define RSTCLR_PORLV_EN (0x1 << 0 ) /* EN. Clears the PORLV status bit in RSTSTA. */
#define SPI0DIV (*(volatile unsigned short int *) 0x4000400C)
#define SPI0CON (*(volatile unsigned short int *) 0x40004010)
#define SPI0DMA (*(volatile unsigned short int *) 0x40004014)
#define SPI0CNT (*(volatile unsigned short int *) 0x40004018)
#endif // (__NO_MMR_STRUCTS__==0)
/* Reset Value for SPI0STA*/
#define SPI0STA_RVAL 0x0
/* SPI0STA[CSERR] - CS error status bit. This bit generates an interrupt when detecting an abrupt CS desassertion before the full byte of data is transmitted completely. */
#define SPI0STA_CSERR_BBA (*(volatile unsigned long *) 0x42080030)
#define SPI0STA_CSERR_MSK (0x1 << 12 )
#define SPI0STA_CSERR (0x1 << 12 )
#define SPI0STA_CSERR_CLR (0x0 << 12 ) /* CLR: Cleared when no CS error is detected. Cleared to 0 on a read of SPI0STA register. */
#define SPI0STA_CSERR_SET (0x1 << 12 ) /* SET: Set when the CS line is deasserted abruptly. */
#define SPI0STA_RXS_BBA (*(volatile unsigned long *) 0x4208002C)
#define SPI0STA_RXS_MSK (0x1 << 11 )
#define SPI0STA_RXS (0x1 << 11 )
#define SPI0STA_RXS_CLR (0x0 << 11 ) /* CLR. When the number of bytes in the FIFO is equal or less than the number in SPI0CON[15:14]. This bit is not cleared on a read of SPI0STA register. */
#define SPI0STA_RXS_SET (0x1 << 11 ) /* SET. When there are more bytes in the Rx FIFO than configured in MOD (SPI0CON[15:14]). For example if MOD = TX1RX1, RXS is set when there are 2 or more bytes in the Rx FIFO. This bit does not dependent on SPI0CON[6] and does not cause an interrupt. */
/* SPI0STA[RXFSTA] - Rx FIFO status bits, indicates how many valid bytes are in the Rx FIFO. */
#define SPI0STA_RXFSTA_MSK (0x7 << 8 )
#define SPI0STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY. When Rx FIFO is empty. */
#define SPI0STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE. When 1 valid byte is in the FIFO. */
#define SPI0STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES. When 2 valid bytes are in the FIFO. */
#define SPI0STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES. When 3 valid bytes are in the FIFO. */
#define SPI0STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES. When 4 valid bytes are in the FIFO. */
/* SPI0STA[RXOF] - Rx FIFO overflow status bit. This bit generates an interrupt. */
#define SPI0STA_RXOF_BBA (*(volatile unsigned long *) 0x4208001C)
#define SPI0STA_RXOF_MSK (0x1 << 7 )
#define SPI0STA_RXOF (0x1 << 7 )
#define SPI0STA_RXOF_CLR (0x0 << 7 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */
#define SPI0STA_RXOF_SET (0x1 << 7 ) /* SET. Set when the Rx FIFO is already full when new data is loaded to the FIFO. This bit generates an interrupt except when RFLUSH is set. (SPI0CON[12]). */
/* SPI0STA[RX] - Rx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */
#define SPI0STA_RX_BBA (*(volatile unsigned long *) 0x42080018)
#define SPI0STA_RX_MSK (0x1 << 6 )
#define SPI0STA_RX (0x1 << 6 )
#define SPI0STA_RX_CLR (0x0 << 6 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */
#define SPI0STA_RX_SET (0x1 << 6 ) /* SET. Set when a receive interrupt occurs. This bit is set when TIM (SPI0CON[6]) is cleared and the required number of bytes have been received. */
/* SPI0STA[TX] - Tx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */
#define SPI0STA_TX_BBA (*(volatile unsigned long *) 0x42080014)
#define SPI0STA_TX_MSK (0x1 << 5 )
#define SPI0STA_TX (0x1 << 5 )
#define SPI0STA_TX_CLR (0x0 << 5 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */
#define SPI0STA_TX_SET (0x1 << 5 ) /* SET. Set when a transmit interrupt occurs. This bit is set when TIM (SPI0CON[6]) set and the required number of bytes have been transmitted. */
/* SPI0STA[TXUR] - Tx FIFO Underrun. This bit generates an interrupt. */
#define SPI0STA_TXUR_BBA (*(volatile unsigned long *) 0x42080010)
#define SPI0STA_TXUR_MSK (0x1 << 4 )
#define SPI0STA_TXUR (0x1 << 4 )
#define SPI0STA_TXUR_CLR (0x0 << 4 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */
#define SPI0STA_TXUR_SET (0x1 << 4 ) /* SET. Set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when TFLUSH is set in SPI0CON. */
/* SPI0STA[TXFSTA] - Tx FIFO status bits, indicates how many valid bytes are in the Tx FIFO. */
#define SPI0STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE. 1 valid byte is in the FIFO. */
#define SPI0STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES. 2 valid bytes are in the FIFO. */
#define SPI0STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES. 3 valid bytes are in the FIFO. */
#define SPI0STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES . 4 valid bytes are in the FIFO. */
/* SPI0STA[IRQ] - Interrupt status bit. */
#define SPI0STA_IRQ_BBA (*(volatile unsigned long *) 0x42080000)
#define SPI0STA_IRQ_MSK (0x1 << 0 )
#define SPI0STA_IRQ (0x1 << 0 )
#define SPI0STA_IRQ_CLR (0x0 << 0 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */
#define SPI0STA_IRQ_SET (0x1 << 0 ) /* SET. Set to 1 when an SPI0 based interrupt occurs. */
/* Reset Value for SPI0RX*/
#define SPI0RX_RVAL 0x0
/* SPI0RX[VALUE] - 8-bit receive register. A read of the RX FIFO returns the next byte to be read from the FIFO. A read of the FIFO when it is empty returns zero. */
#define SPI0RX_VALUE_MSK (0xFF << 0 )
/* Reset Value for SPI0TX*/
#define SPI0TX_RVAL 0x0
/* SPI0TX[VALUE] - 8-bit transmit register. A write to the Tx FIFO address space writes data to the next available location in the Tx FIFO. If the FIFO is full, the oldest byte of data in the FIFO is overwritten. A read from this address location return zero. */
#define SPI0TX_VALUE_MSK (0xFF << 0 )
/* Reset Value for SPI0DIV*/
#define SPI0DIV_RVAL 0x0
/* SPI0DIV[BCRST] - Configures the behavior of SPI communication after an abrupt deassertion of CS. This bit should be set in slave and master mode. */
#define SPI0DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208019C)
#define SPI0DIV_BCRST_MSK (0x1 << 7 )
#define SPI0DIV_BCRST (0x1 << 7 )
#define SPI0DIV_BCRST_DIS (0x0 << 7 ) /* DIS. Resumes communication from where it stopped when the CS is deasserted. The rest of the bits are then received/ transmitted when CS returns low. User code should ignore the CSERR interrupt. */
#define SPI0DIV_BCRST_EN (0x1 << 7 ) /* EN. Enabled for a clean restart of SPI transfer after a CSERR condition. User code must also clear the SPI enable bit in SPI0CON during the CSERR interrupt. */
/* SPI0DIV[DIV] - Factor used to divide UCLK in the generation of the master mode serial clock. */
#define SPI0DIV_DIV_MSK (0x3F << 0 )
/* Reset Value for SPI0CON*/
#define SPI0CON_RVAL 0x0
/* SPI0CON[MOD] - IRQ mode bits. When TIM is set these bits configure when the Tx/Rx interrupts occur in a transfer. For a DMA Rx transfer, these bits should be 00. */
#define SPI0CON_MOD_MSK (0x3 << 14 )
#define SPI0CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1. Tx/Rx interrupt occurs when 1 byte has been transmitted/received from/into the FIFO. */
#define SPI0CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2. Tx/Rx interrupt occurs when 2 bytes have been transmitted/received from/into the FIFO. */
#define SPI0CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3. Tx/Rx interrupt occurs when 3 bytes have been transmitted/received from/into the FIFO. */
#define SPI0CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4. Tx/Rx interrupt occurs when 4 bytes have been transmitted/received from/into the FIFO. */
/* SPI0CON[TFLUSH] - Tx FIFO flush enable bit. */
#define SPI0CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42080234)
#define SPI0CON_TFLUSH_EN (0x1 << 13 ) /* EN. Flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the ZEN bit (SPI0CON[7]). Any writes to the Tx FIFO are ignored while this bit is set. */
/* SPI0CON[RFLUSH] - Rx FIFO flush enable bit. */
#define SPI0CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42080230)
#define SPI0CON_RFLUSH_EN (0x1 << 12 ) /* EN. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and TIM = 0 (SPI0CON[6]), a read of the Rx FIFO initiates a transfer. */
/* SPI0CON[CON] - Continuous transfer enable bit. */
#define SPI0CON_CON_BBA (*(volatile unsigned long *) 0x4208022C)
#define SPI0CON_CON_MSK (0x1 << 11 )
#define SPI0CON_CON (0x1 << 11 )
#define SPI0CON_CON_DIS (0x0 << 11 ) /* DIS. Disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPIxTX register, then a new transfer is initiated after a stall period of one serial clock cycle. The CS line is deactivated for this one serial clock cycle. */
#define SPI0CON_CON_EN (0x1 << 11 ) /* EN. Enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. */
/* SPI0CON[LOOPBACK] - Loopback enable bit. */
#define SPI0CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42080228)
#define SPI0CON_LOOPBACK_EN (0x1 << 10 ) /* EN. Connect MISO to MOSI, thus, data transmitted from Tx register is looped back to the Rx register. SPI must be configured in master mode. */
/* SPI0CON[SOEN] - Slave output enable bit. */
#define SPI0CON_SOEN_BBA (*(volatile unsigned long *) 0x42080224)
#define SPI0CON_SOEN_MSK (0x1 << 9 )
#define SPI0CON_SOEN (0x1 << 9 )
#define SPI0CON_SOEN_DIS (0x0 << 9 ) /* DIS. Disable the output driver on the MISO pin. The MISO pin is open-circuit when this bit is clear. */
#define SPI0CON_RXOF_BBA (*(volatile unsigned long *) 0x42080220)
#define SPI0CON_RXOF_MSK (0x1 << 8 )
#define SPI0CON_RXOF (0x1 << 8 )
#define SPI0CON_RXOF_DIS (0x0 << 8 ) /* DIS. The new serial byte received is discarded when there is no space left in the FIFO */
#define SPI0CON_RXOF_EN (0x1 << 8 ) /* EN. The valid data in the Rx register is overwritten by the new serial byte received when there is no space left in the FIFO. */
/* SPI0CON[ZEN] - Transmit underrun: Transmit 0s when the Tx FIFO is empty */
#define SPI0CON_ZEN_BBA (*(volatile unsigned long *) 0x4208021C)
#define SPI0CON_ZEN_MSK (0x1 << 7 )
#define SPI0CON_ZEN (0x1 << 7 )
#define SPI0CON_ZEN_DIS (0x0 << 7 ) /* DIS. The last byte from the previous transmission is shifted out when a transfer is initiated with no valid data in the FIFO. */
#define SPI0CON_ZEN_EN (0x1 << 7 ) /* EN. Transmit 0x00 when a transfer is initiated with no valid data in the FIFO. */
/* SPI0CON[TIM] - Transfer and interrupt mode bit. */
#define SPI0CON_TIM_BBA (*(volatile unsigned long *) 0x42080218)
#define SPI0CON_TIM_MSK (0x1 << 6 )
#define SPI0CON_TIM (0x1 << 6 )
#define SPI0CON_TIM_TXWR (0x1 << 6 ) /* TXWR. Initiate transfer with a write to the SPIxTX register. Interrupt only occurs when Tx is empty. */
#define SPI0CON_TIM_RXRD (0x0 << 6 ) /* RXRD. Initiate transfer with a read of the SPIxRX register. The read must be done while the SPI interface is idle. Interrupt only occurs when Rx is full. */
/* SPI0CON[LSB] - LSB first transfer enable bit. */
#define SPI0CON_LSB_BBA (*(volatile unsigned long *) 0x42080214)
#define SPI0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42080200)
#define SPI0CON_ENABLE_MSK (0x1 << 0 )
#define SPI0CON_ENABLE (0x1 << 0 )
#define SPI0CON_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable the SPI. Clearing this bit will also reset all the FIFO related logic to enable a clean start. */
/* SPI0DMA[ENABLE] - DMA data transfer enable bit. */
#define SPI0DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42080280)
#define SPI0DMA_ENABLE_MSK (0x1 << 0 )
#define SPI0DMA_ENABLE (0x1 << 0 )
#define SPI0DMA_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable DMA transfer. This bit needs to be cleared to prevent extra DMA request to the µDMA controller. */
#define SPI0DMA_ENABLE_EN (0x1 << 0 ) /* EN. Enable a DMA transfer. Starts the transfer of a master configured to initiate transfer on transmit. */
/* Reset Value for SPI0CNT*/
#define SPI0CNT_RVAL 0x0
/* SPI0CNT[VALUE] - Number of bytes requested by the SPI master during DMA transfer, when configured to initiate a transfer on a read of SPI0RX. This register is only used in DMA, master, Rx mode. */
#define SPI0CNT_VALUE_MSK (0xFF << 0 )
#if (__NO_MMR_STRUCTS__==1)
#define SPI1STA (*(volatile unsigned short int *) 0x40004400)
#define SPI1DIV (*(volatile unsigned short int *) 0x4000440C)
#define SPI1CON (*(volatile unsigned short int *) 0x40004410)
#define SPI1DMA (*(volatile unsigned short int *) 0x40004414)
#define SPI1CNT (*(volatile unsigned short int *) 0x40004418)
#endif // (__NO_MMR_STRUCTS__==1)
/* Reset Value for SPI1STA*/
#define SPI1STA_RVAL 0x0
/* SPI1STA[CSERR] - CS error status bit. This bit generates an interrupt when detecting an abrupt CS desassertion before the full byte of data is transmitted completely. */
#define SPI1STA_CSERR_BBA (*(volatile unsigned long *) 0x42088030)
#define SPI1STA_CSERR_MSK (0x1 << 12 )
#define SPI1STA_CSERR (0x1 << 12 )
#define SPI1STA_CSERR_CLR (0x0 << 12 ) /* CLR: Cleared when no CS error is detected. Cleared to 0 on a read of SPI1STA register. */
#define SPI1STA_CSERR_SET (0x1 << 12 ) /* SET. Set when the CS line is deasserted abruptly. */
#define SPI1STA_RXS_BBA (*(volatile unsigned long *) 0x4208802C)
#define SPI1STA_RXS_MSK (0x1 << 11 )
#define SPI1STA_RXS (0x1 << 11 )
#define SPI1STA_RXS_CLR (0x0 << 11 ) /* CLR. When the number of bytes in the FIFO is equal or less than the number in SPI0CON[15:14]. This bit is not cleared on a read of SPI0STA register. */
#define SPI1STA_RXS_SET (0x1 << 11 ) /* SET. When there are more bytes in the Rx FIFO than configured in MOD (SPI1CON[15:14]). For example if MOD = TX1RX1, RXS is set when there are 2 or more bytes in the Rx FIFO. This bit does not dependent on SPI1CON[6] and does not cause an interrupt. */
/* SPI1STA[RXFSTA] - Rx FIFO status bits, indicates how many valid bytes are in the Rx FIFO. */
#define SPI1STA_RXFSTA_MSK (0x7 << 8 )
#define SPI1STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY. When Rx FIFO is empty. */
#define SPI1STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE. When 1 valid byte is in the FIFO. */
#define SPI1STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES. When 2 valid bytes are in the FIFO. */
#define SPI1STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES. When 3 valid bytes are in the FIFO. */
#define SPI1STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES. When 4 valid bytes are in the FIFO. */
/* SPI1STA[RXOF] - Rx FIFO overflow status bit. This bit generates an interrupt. */
#define SPI1STA_RXOF_BBA (*(volatile unsigned long *) 0x4208801C)
#define SPI1STA_RXOF_MSK (0x1 << 7 )
#define SPI1STA_RXOF (0x1 << 7 )
#define SPI1STA_RXOF_CLR (0x0 << 7 ) /* CLR.Cleared to 0 on a read of SPI1STA register. */
#define SPI1STA_RXOF_SET (0x1 << 7 ) /* SET. Set when the Rx FIFO is already full when new data is loaded to the FIFO. This bit generates an interrupt except when RFLUSH is set. (SPI1CON[12]). */
/* SPI1STA[RX] - Rx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */
#define SPI1STA_RX_BBA (*(volatile unsigned long *) 0x42088018)
#define SPI1STA_RX_MSK (0x1 << 6 )
#define SPI1STA_RX (0x1 << 6 )
#define SPI1STA_RX_CLR (0x0 << 6 ) /* CLR. Cleared to 0 on a read of SPI1STA register. */
#define SPI1STA_RX_SET (0x1 << 6 ) /* SET. Set when a receive interrupt occurs. This bit is set when TIM (SPI1CON[6]) is cleared and the required number of bytes have been received. */
/* SPI1STA[TX] - Tx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */
#define SPI1STA_TX_BBA (*(volatile unsigned long *) 0x42088014)
#define SPI1STA_TX_MSK (0x1 << 5 )
#define SPI1STA_TX (0x1 << 5 )
#define SPI1STA_TX_CLR (0x0 << 5 ) /* CLR. Cleared to 0 on a read of SPI1STA register. */
#define SPI1STA_TX_SET (0x1 << 5 ) /* SET. Set when a transmit interrupt occurs. This bit is set when TIM (SPI1CON[6]) is set and the required number of bytes have been transmitted. */
/* SPI1STA[TXUR] - Tx FIFO Underrun. This bit generates an interrupt. */
#define SPI1STA_TXUR_BBA (*(volatile unsigned long *) 0x42088010)
#define SPI1STA_TXUR_MSK (0x1 << 4 )
#define SPI1STA_TXUR (0x1 << 4 )
#define SPI1STA_TXUR_CLR (0x0 << 4 ) /* CLR. Cleared to 0 on a read of SPI1STA register. */
#define SPI1STA_TXUR_SET (0x1 << 4 ) /* SET. Set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when TFLUSH is set in SPI1CON. */
/* SPI1STA[TXFSTA] - Tx FIFO status bits, indicates how many valid bytes are in the Tx FIFO. */
#define SPI1STA_TXFSTA_MSK (0x7 << 1 )
#define SPI1STA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY. When Tx FIFO is empty. */
#define SPI1STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE. 1 valid byte is in the FIFO. */
#define SPI1STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES. 2 valid bytes are in the FIFO. */
#define SPI1STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES. 3 valid bytes are in the FIFO. */
#define SPI1STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES. 4 valid bytes are in the FIFO. */
/* SPI1STA[IRQ] - Interrupt status bit. */
#define SPI1STA_IRQ_BBA (*(volatile unsigned long *) 0x42088000)
#define SPI1STA_IRQ_MSK (0x1 << 0 )
#define SPI1STA_IRQ (0x1 << 0 )
#define SPI1STA_IRQ_CLR (0x0 << 0 ) /* CLR. Cleared to 0 on a read of SPI1STA register. */
#define SPI1STA_IRQ_SET (0x1 << 0 ) /* SET. Set to 1 when an SPI1 based interrupt occurs. */
/* Reset Value for SPI1RX*/
#define SPI1RX_RVAL 0x0
/* SPI1RX[VALUE] - 8-bit receive register. A read of the RX FIFO returns the next byte to be read from the FIFO. A read of the FIFO when it is empty returns zero. */
#define SPI1RX_VALUE_MSK (0xFF << 0 )
/* Reset Value for SPI1TX*/
#define SPI1TX_RVAL 0x0
/* SPI1TX[VALUE] - 8-bit transmit register. A write to the Tx FIFO address space writes data to the next available location in the Tx FIFO. If the FIFO is full, the oldest byte of data in the FIFO is overwritten. A read from this address location return zero. */
#define SPI1TX_VALUE_MSK (0xFF << 0 )
/* Reset Value for SPI1DIV*/
#define SPI1DIV_RVAL 0x0
/* SPI1DIV[BCRST] - Configures the behavior of SPI communication after an abrupt deassertion of CS. This bit should be set in slave and master mode. */
#define SPI1DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208819C)
#define SPI1DIV_BCRST_MSK (0x1 << 7 )
#define SPI1DIV_BCRST (0x1 << 7 )
#define SPI1DIV_BCRST_DIS (0x0 << 7 ) /* DIS. Resumes communication from where it stopped when the CS is deasserted. The rest of the bits are then received/ transmitted when CS returns low. User code should ignore the CSERR interrupt. */
#define SPI1DIV_BCRST_EN (0x1 << 7 ) /* EN. Enabled for a clean restart of SPI transfer after a CSERR condition. User code must also clear the SPI enable bit in SPI1CON during the CSERR interrupt. */
/* SPI1DIV[DIV] - Factor used to divide UCLK in the generation of the master mode serial clock. */
#define SPI1DIV_DIV_MSK (0x3F << 0 )
/* Reset Value for SPI1CON*/
#define SPI1CON_RVAL 0x0
/* SPI1CON[MOD] - IRQ mode bits. When TIM is set these bits configure when the Tx/Rx interrupts occur in a transfer. For a DMA Rx transfer, these bits should be 00. */
#define SPI1CON_MOD_MSK (0x3 << 14 )
#define SPI1CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1. Tx/Rx interrupt occurs when 1 byte has been transmitted/received from/into the FIFO. */
#define SPI1CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2. Tx/Rx interrupt occurs when 2 bytes have been transmitted/received from/into the FIFO. */
#define SPI1CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3. Tx/Rx interrupt occurs when 3 bytes have been transmitted/received from/into the FIFO. */
#define SPI1CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4. Tx/Rx interrupt occurs when 4 bytes have been transmitted/received from/into the FIFO. */
/* SPI1CON[TFLUSH] - Tx FIFO flush enable bit. */
#define SPI1CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42088234)
#define SPI1CON_TFLUSH_EN (0x1 << 13 ) /* EN. Flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the ZEN bit (SPI1CON[7]). Any writes to the Tx FIFO are ignored while this bit is set. */
/* SPI1CON[RFLUSH] - Rx FIFO flush enable bit. */
#define SPI1CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42088230)
#define SPI1CON_RFLUSH_EN (0x1 << 12 ) /* EN. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and TIM = 0 (SPI1CON[6]), a read of the Rx FIFO initiates a transfer. */
/* SPI1CON[CON] - Continuous transfer enable bit. */
#define SPI1CON_CON_BBA (*(volatile unsigned long *) 0x4208822C)
#define SPI1CON_CON_MSK (0x1 << 11 )
#define SPI1CON_CON (0x1 << 11 )
#define SPI1CON_CON_DIS (0x0 << 11 ) /* DIS. Disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPIxTX register, then a new transfer is initiated after a stall period of one serial clock cycle. The CS line is deactivated for this one serial clock cycle. */
#define SPI1CON_CON_EN (0x1 << 11 ) /* EN. Enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. */
/* SPI1CON[LOOPBACK] - Loopback enable bit. */
#define SPI1CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42088228)
#define SPI1CON_LOOPBACK_EN (0x1 << 10 ) /* EN. Connect MISO to MOSI, thus, data transmitted from Tx register is looped back to the Rx register. SPI must be configured in master mode. */
/* SPI1CON[SOEN] - Slave output enable bit. */
#define SPI1CON_SOEN_BBA (*(volatile unsigned long *) 0x42088224)
#define SPI1CON_SOEN_MSK (0x1 << 9 )
#define SPI1CON_SOEN (0x1 << 9 )
#define SPI1CON_SOEN_DIS (0x0 << 9 ) /* DIS. Disable the output driver on the MISO pin. The MISO pin is open-circuit when this bit is clear. */
#define SPI1CON_RXOF_BBA (*(volatile unsigned long *) 0x42088220)
#define SPI1CON_RXOF_MSK (0x1 << 8 )
#define SPI1CON_RXOF (0x1 << 8 )
#define SPI1CON_RXOF_DIS (0x0 << 8 ) /* DIS. The new serial byte received is discarded when there is no space left in the FIFO */
#define SPI1CON_RXOF_EN (0x1 << 8 ) /* EN. The valid data in the Rx register is overwritten by the new serial byte received when there is no space left in the FIFO. */
/* SPI1CON[ZEN] - TX underrun: Transmit 0s when Tx FIFO is empty. */
#define SPI1CON_ZEN_BBA (*(volatile unsigned long *) 0x4208821C)
#define SPI1CON_ZEN_MSK (0x1 << 7 )
#define SPI1CON_ZEN (0x1 << 7 )
#define SPI1CON_ZEN_DIS (0x0 << 7 ) /* DIS. The last byte from the previous transmission is shifted out when a transfer is initiated with no valid data in the FIFO. */
#define SPI1CON_ZEN_EN (0x1 << 7 ) /* EN. Transmit 0x00 when a transfer is initiated with no valid data in the FIFO. */
/* SPI1CON[TIM] - Transfer and interrupt mode bit. */
#define SPI1CON_TIM_BBA (*(volatile unsigned long *) 0x42088218)
#define SPI1CON_TIM_MSK (0x1 << 6 )
#define SPI1CON_TIM (0x1 << 6 )
#define SPI1CON_TIM_TXWR (0x1 << 6 ) /* TXWR. Initiate transfer with a write to the SPIxTX register. Interrupt only occurs when Tx is empty. */
#define SPI1CON_TIM_RXRD (0x0 << 6 ) /* RXRD. Initiate transfer with a read of the SPIxRX register. The read must be done while the SPI interface is idle. Interrupt only occurs when Rx is full. */
/* SPI1CON[LSB] - LSB first transfer enable bit. */
#define SPI1CON_LSB_BBA (*(volatile unsigned long *) 0x42088214)
#define SPI1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42088200)
#define SPI1CON_ENABLE_MSK (0x1 << 0 )
#define SPI1CON_ENABLE (0x1 << 0 )
#define SPI1CON_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable the SPI. Clearing this bit will also reset all the FIFO related logic to enable a clean start. */
/* SPI1DMA[ENABLE] - DMA data transfer enable bit. */
#define SPI1DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42088280)
#define SPI1DMA_ENABLE_MSK (0x1 << 0 )
#define SPI1DMA_ENABLE (0x1 << 0 )
#define SPI1DMA_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable DMA transfer. This bit needs to be cleared to prevent extra DMA request to the µDMA controller. */
#define SPI1DMA_ENABLE_EN (0x1 << 0 ) /* EN. Enable a DMA transfer. Starts the transfer of a master configured to initiate transfer on transmit. */
/* Reset Value for SPI1CNT*/
#define SPI1CNT_RVAL 0x0
/* SPI1CNT[VALUE] - Number of bytes requested by the SPI master during DMA transfer, when configured to initiate a transfer on a read of SPI0RX. This register is only used in DMA, master, Rx mode.. */
#define T0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42000110)
#define T0CON_ENABLE_MSK (0x1 << 4 )
#define T0CON_ENABLE (0x1 << 4 )
#define T0CON_ENABLE_DIS (0x0 << 4 ) /* DIS. Disable the timer. Clearing this bit resets the timer, including the T0VAL register. */
#define T0CON_ENABLE_EN (0x1 << 4 ) /* EN. Enable the timer. The timer starts counting from its initial value, 0 if count-up mode or 0xFFFF if count-down mode. */
/* T0CON[MOD] - Timer mode. */
#define T0CON_MOD_BBA (*(volatile unsigned long *) 0x4200010C)
#define T0CLRI_CAP_BBA (*(volatile unsigned long *) 0x42000184)
#define T0CLRI_CAP_MSK (0x1 << 1 )
#define T0CLRI_CAP (0x1 << 1 )
#define T0CLRI_CAP_CLR (0x1 << 1 ) /* CLR. Clear a captured event interrupt. This bit always reads 0. */
/* T0CLRI[TMOUT] - Clear timeout interrupt. */
#define T0CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42000180)
#define T0CLRI_TMOUT_MSK (0x1 << 0 )
#define T0CLRI_TMOUT (0x1 << 0 )
#define T0CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR. Clear a timeout interrupt. This bit always reads 0. */
/* Reset Value for T0CAP*/
#define T0CAP_RVAL 0x0
/* T0CAP[VALUE] - Capture value. */
#define T0CAP_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for T0STA*/
#define T0STA_RVAL 0x0
/* T0STA[CLRI] - T0CLRI write sync in progress.. */
#define T0STA_CLRI_BBA (*(volatile unsigned long *) 0x4200039C)
#define T0STA_CLRI_MSK (0x1 << 7 )
#define T0STA_CLRI (0x1 << 7 )
#define T0STA_CLRI_CLR (0x0 << 7 ) /* CLR. Cleared when the interrupt is cleared in the timer clock domain. */
#define T0STA_CLRI_SET (0x1 << 7 ) /* SET. Set automatically when the T0CLRI value is being updated in the timer clock domain, indicating that the timers configuration is not yet valid. */
/* T0STA[CON] - T0CON write sync in progress. */
#define T0STA_CON_BBA (*(volatile unsigned long *) 0x42000398)
#define T0STA_CON_MSK (0x1 << 6 )
#define T0STA_CON (0x1 << 6 )
#define T0STA_CON_CLR (0x0 << 6 ) /* CLR. Timer ready to receive commands to T0CON. The previous change of T0CON has been synchronized in the timer clock domain. */
#define T0STA_CON_SET (0x1 << 6 ) /* SET. Timer not ready to receive commands to T0CON. Previous change of the T0CON value has not been synchronized in the timer clock domain. */
/* T0STA[CAP] - Capture event pending. */
#define T0STA_CAP_BBA (*(volatile unsigned long *) 0x42000384)
#define T0STA_CAP_MSK (0x1 << 1 )
#define T0STA_CAP (0x1 << 1 )
#define T0STA_CAP_CLR (0x0 << 1 ) /* CLR. No capture event is pending. */
#define T0STA_TMOUT_BBA (*(volatile unsigned long *) 0x42000380)
#define T0STA_TMOUT_MSK (0x1 << 0 )
#define T0STA_TMOUT (0x1 << 0 )
#define T0STA_TMOUT_CLR (0x0 << 0 ) /* CLR. No timeout event has occurred. */
#define T0STA_TMOUT_SET (0x1 << 0 ) /* SET. Timeout event has occurred. For count-up mode, this is when the counter reaches full scale. For count-down mode, this is when the counter reaches 0. */
#if (__NO_MMR_STRUCTS__==1)
#define T1LD (*(volatile unsigned short int *) 0x40000400)
#define T1VAL (*(volatile unsigned short int *) 0x40000404)
#define T1CON (*(volatile unsigned short int *) 0x40000408)
#define T1CLRI (*(volatile unsigned short int *) 0x4000040C)
#define T1CAP (*(volatile unsigned short int *) 0x40000410)
#define T1STA (*(volatile unsigned short int *) 0x4000041C)
#endif // (__NO_MMR_STRUCTS__==1)
/* Reset Value for T1LD*/
#define T1LD_RVAL 0x0
/* T1LD[VALUE] - Load value. */
#define T1LD_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for T1VAL*/
#define T1VAL_RVAL 0x0
/* T1VAL[VALUE] - Current counter value. */
#define T1VAL_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for T1CON*/
#define T1CON_RVAL 0xA
/* T1CON[EVENTEN] - Enable event bit. */
#define T1CON_EVENTEN_BBA (*(volatile unsigned long *) 0x42008130)
#define T1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42008110)
#define T1CON_ENABLE_MSK (0x1 << 4 )
#define T1CON_ENABLE (0x1 << 4 )
#define T1CON_ENABLE_DIS (0x0 << 4 ) /* DIS. Disable the timer. Clearing this bit resets the timer, including the T1VAL register. */
#define T1CON_ENABLE_EN (0x1 << 4 ) /* EN. Enable the timer. The timer starts counting from its initial value, 0 if count-up mode or 0xFFFF if count-down mode. */
/* T1CON[MOD] - Timer mode. */
#define T1CON_MOD_BBA (*(volatile unsigned long *) 0x4200810C)
#define T1CLRI_CAP_BBA (*(volatile unsigned long *) 0x42008184)
#define T1CLRI_CAP_MSK (0x1 << 1 )
#define T1CLRI_CAP (0x1 << 1 )
#define T1CLRI_CAP_CLR (0x1 << 1 ) /* CLR. Clear a captured event interrupt. This bit always reads 0. */
/* T1CLRI[TMOUT] - Clear timeout interrupt. */
#define T1CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42008180)
#define T1CLRI_TMOUT_MSK (0x1 << 0 )
#define T1CLRI_TMOUT (0x1 << 0 )
#define T1CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR. Clear a timeout interrupt. This bit always reads 0. */
/* Reset Value for T1CAP*/
#define T1CAP_RVAL 0x0
/* T1CAP[VALUE] - Capture value. */
#define T1CAP_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for T1STA*/
#define T1STA_RVAL 0x0
/* T1STA[CLRI] - T1CLRI write sync in progress. */
#define T1STA_CLRI_BBA (*(volatile unsigned long *) 0x4200839C)
#define T1STA_CLRI_MSK (0x1 << 7 )
#define T1STA_CLRI (0x1 << 7 )
#define T1STA_CLRI_CLR (0x0 << 7 ) /* CLR. Cleared when the interrupt is cleared in the timer clock domain. */
#define T1STA_CLRI_SET (0x1 << 7 ) /* SET. Set automatically when the T1CLRI value is being updated in the timer clock domain, indicating that the timers configuration is not yet valid. */
/* T1STA[CON] - T1CON write sync in progress. */
#define T1STA_CON_BBA (*(volatile unsigned long *) 0x42008398)
#define T1STA_CON_MSK (0x1 << 6 )
#define T1STA_CON (0x1 << 6 )
#define T1STA_CON_CLR (0x0 << 6 ) /* CLR. Timer ready to receive commands to T1CON. The previous change of T1CON has been synchronized in the timer clock domain. */
#define T1STA_CON_SET (0x1 << 6 ) /* SET. Timer not ready to receive commands to T1CON. Previous change of the T1CON value has not been synchronized in the timer clock domain. */
/* T1STA[CAP] - Capture event pending. */
#define T1STA_CAP_BBA (*(volatile unsigned long *) 0x42008384)
#define T1STA_CAP_MSK (0x1 << 1 )
#define T1STA_CAP (0x1 << 1 )
#define T1STA_CAP_CLR (0x0 << 1 ) /* CLR. No capture event is pending. */
#define T1STA_TMOUT_BBA (*(volatile unsigned long *) 0x42008380)
#define T1STA_TMOUT_MSK (0x1 << 0 )
#define T1STA_TMOUT (0x1 << 0 )
#define T1STA_TMOUT_CLR (0x0 << 0 ) /* CLR. No timeout event has occurred. */
#define T1STA_TMOUT_SET (0x1 << 0 ) /* SET. Timeout event has occurred. For count-up mode, this is when the counter reaches full scale. For count-down mode, this is when the counter reaches 0. */
#define COMIEN_ETBEI_EN (0x1 << 1 ) /* EN. Enable the transmit interrupt. An interrupt is generated when the COMTX register is empty. Note that if the COMTX is already empty when enabling this bit, an interrupt is generated immediately. */
/* COMIEN[ERBFI] - Receive buffer full interrupt */
#define COMIEN_ERBFI_BBA (*(volatile unsigned long *) 0x420A0080)
#define COMIEN_ERBFI_EN (0x1 << 0 ) /* EN. Enable the receive interrupt. An interrupt is generated when the COMRX register is loaded with the received data. Note that if the COMRX is already full when enabling this bit, an interrupt is generated immediately. */
#define COMIIR_STA_RXBUFFULL (0x2 << 1 ) /* RXBUFFULL. Receive buffer full interrupt. Read COMRX register to clear. */
#define COMIIR_STA_RXLINESTATUS (0x3 << 1 ) /* RXLINESTATUS. Receive line status interrupt. Read COMLSR register to clear. */
/* COMIIR[NINT] - Interrupt flag. */
#define COMIIR_NINT_BBA (*(volatile unsigned long *) 0x420A0100)
#define COMIIR_NINT_MSK (0x1 << 0 )
#define COMIIR_NINT (0x1 << 0 )
#define COMIIR_NINT_CLR (0x0 << 0 ) /* CLR. Indicates any of the following: receive buffer full, transmit buffer empty, line status, or modem status interrupt occurred. */
#define COMIIR_NINT_SET (0x1 << 0 ) /* SET. There is no interrupt (default). */
/* Reset Value for COMLCR*/
#define COMLCR_RVAL 0x0
/* COMLCR[BRK] - Set Break. */
#define COMLCR_BRK_BBA (*(volatile unsigned long *) 0x420A0198)
#define COMLCR_BRK_MSK (0x1 << 6 )
#define COMLCR_BRK (0x1 << 6 )
#define COMLCR_BRK_DIS (0x0 << 6 ) /* DIS to operate in normal mode. */
#define COMLCR_BRK_EN (0x1 << 6 ) /* EN to force TxD to 0. */
/* COMLCR[SP] - Stick Parity. */
#define COMLCR_SP_BBA (*(volatile unsigned long *) 0x420A0194)
#define COMLCR_SP_MSK (0x1 << 5 )
#define COMLCR_SP (0x1 << 5 )
#define COMLCR_SP_DIS (0x0 << 5 ) /* DIS. Parity is not forced based on EPS and PEN values. */
#define COMLCR_SP_EN (0x1 << 5 ) /* EN. Force parity to defined values based on EPS and PEN values. EPS = 1 and PEN = 1, parity forced to 1 EPS = 0 and PEN = 1, parity forced to 0 EPS = X and PEN = 0, no parity transmitted. */
/* COMLCR[EPS] - Even Parity Select Bit. */
#define COMLCR_EPS_BBA (*(volatile unsigned long *) 0x420A0190)
#define COMLCR_PEN_BBA (*(volatile unsigned long *) 0x420A018C)
#define COMLCR_PEN_MSK (0x1 << 3 )
#define COMLCR_PEN (0x1 << 3 )
#define COMLCR_PEN_DIS (0x0 << 3 ) /* DIS. No parity transmission or checking. */
#define COMLCR_PEN_EN (0x1 << 3 ) /* EN. Transmit and check the parity bit. */
/* COMLCR[STOP] - Stop Bit. */
#define COMLCR_STOP_BBA (*(volatile unsigned long *) 0x420A0188)
#define COMLCR_STOP_MSK (0x1 << 2 )
#define COMLCR_STOP (0x1 << 2 )
#define COMLCR_STOP_DIS (0x0 << 2 ) /* DIS. Generate one stop bit in the transmitted data. */
#define COMLCR_STOP_EN (0x1 << 2 ) /* EN. Transmit 1.5 stop bits if the word length is 5 bits, or 2 stop bits if the word length is 6, 7, or 8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. */
/* COMMCR[RTS] - Request To Send output control bit. */
#define COMMCR_RTS_BBA (*(volatile unsigned long *) 0x420A0204)
#define COMMCR_RTS_MSK (0x1 << 1 )
#define COMMCR_RTS (0x1 << 1 )
#define COMMCR_RTS_DIS (0x0 << 1 ) /* DIS. Force the RTS output to 1. */
#define COMMCR_RTS_EN (0x1 << 1 ) /* EN. Force the RTS output to 0. */
/* Reset Value for COMLSR*/
#define COMLSR_RVAL 0x60
/* COMLSR[TEMT] - COMTX and Shift Register Empty Status Bit. */
#define COMLSR_TEMT_BBA (*(volatile unsigned long *) 0x420A0298)
#define COMLSR_TEMT_MSK (0x1 << 6 )
#define COMLSR_TEMT (0x1 << 6 )
#define COMLSR_TEMT_CLR (0x0 << 6 ) /* CLR. Cleared when writing to COMTX. */
#define COMLSR_TEMT_SET (0x1 << 6 ) /* SET. If COMTX and the shift register are empty, this bit indicates that the data has been transmitted, that is, it is no longer present in the shift register (default). */
/* COMLSR[THRE] - COMTX Empty Status Bit. */
#define COMLSR_THRE_BBA (*(volatile unsigned long *) 0x420A0294)
#define COMLSR_THRE_MSK (0x1 << 5 )
#define COMLSR_THRE (0x1 << 5 )
#define COMLSR_THRE_CLR (0x0 << 5 ) /* CLR. Cleared when writing to COMTX. */
#define COMLSR_THRE_SET (0x1 << 5 ) /* SET. If COMTX is empty, COMTX can be written as soon as this bit is set. The previous data may not have been transmitted yet and can still be present in the shift register (default). */
/* COMLSR[BI] - Break Indicator. */
#define COMLSR_BI_BBA (*(volatile unsigned long *) 0x420A0290)
__IOuint16_tT2VAL0;/*!< Current Wake-Up Timer Value LSB */
__Iuint16_tRESERVED0;
__IOuint16_tT2VAL1;/*!< Current Wake-Up Timer Value MSB */
__Iuint16_tRESERVED1;
__IOuint16_tT2CON;/*!< Control Register */
__Iuint16_tRESERVED2;
__IOuint16_tT2INC;/*!< 12-bit Interval Register for Wake-Up Field A */
__Iuint16_tRESERVED3;
__IOuint16_tT2WUFB0;/*!< Wake-Up Field B LSB */
__Iuint16_tRESERVED4;
__IOuint16_tT2WUFB1;/*!< Wake-Up Field B MSB */
__Iuint16_tRESERVED5;
__IOuint16_tT2WUFC0;/*!< Wake-Up Field C LSB */
__Iuint16_tRESERVED6;
__IOuint16_tT2WUFC1;/*!< Wake-Up Field C MSB */
__Iuint16_tRESERVED7;
__IOuint16_tT2WUFD0;/*!< Wake-UpField D LSB */
__Iuint16_tRESERVED8;
__IOuint16_tT2WUFD1;/*!< Wake-Up Field D MSB */
__Iuint16_tRESERVED9;
__IOuint16_tT2IEN;/*!< Interrupt Enable */
__Iuint16_tRESERVED10;
__IOuint16_tT2STA;/*!< Status */
__Iuint16_tRESERVED11;
__IOuint16_tT2CLRI;/*!< Clear Interrupts */
__Iuint16_tRESERVED12[5];
__IOuint16_tT2WUFA0;/*!< Wake-Up Field A LSB */
__Iuint16_tRESERVED13;
__IOuint16_tT2WUFA1;/*!< Wake-Up Field A MSB */
}ADI_WUT_TypeDef;
#else // (__NO_MMR_STRUCTS__==0)
#define T2VAL0 (*(volatile unsigned short int *) 0x40002500)
#define T2VAL1 (*(volatile unsigned short int *) 0x40002504)
#define T2CON (*(volatile unsigned short int *) 0x40002508)
#define T2INC (*(volatile unsigned short int *) 0x4000250C)
#define T2WUFB0 (*(volatile unsigned short int *) 0x40002510)
#define T2WUFB1 (*(volatile unsigned short int *) 0x40002514)
#define T2WUFC0 (*(volatile unsigned short int *) 0x40002518)
#define T2WUFC1 (*(volatile unsigned short int *) 0x4000251C)
#define T2WUFD0 (*(volatile unsigned short int *) 0x40002520)
#define T2WUFD1 (*(volatile unsigned short int *) 0x40002524)
#define T2IEN (*(volatile unsigned short int *) 0x40002528)
#define T2STA (*(volatile unsigned short int *) 0x4000252C)
#define T2CLRI (*(volatile unsigned short int *) 0x40002530)
#define T2WUFA0 (*(volatile unsigned short int *) 0x4000253C)
#define T2WUFA1 (*(volatile unsigned short int *) 0x40002540)
#endif // (__NO_MMR_STRUCTS__==0)
/* Reset Value for T2VAL0*/
#define T2VAL0_RVAL 0x0
/* T2VAL0[VALUE] - Current Wake-Up timer value (bits 15 to 0). */
#define T2VAL0_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for T2VAL1*/
#define T2VAL1_RVAL 0x0
/* T2VAL1[VALUE] - Current Wake-Up timer value (bits 31 to 16). */
#define T2VAL1_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for T2CON*/
#define T2CON_RVAL 0x40
/* T2CON[STOPINC] - Allows the user to update the interval register safely. */
#define T2CON_STOPINC_BBA (*(volatile unsigned long *) 0x4204A12C)
#define T2CON_STOPINC_MSK (0x1 << 11 )
#define T2CON_STOPINC (0x1 << 11 )
#define T2CON_STOPINC_DIS (0x0 << 11 ) /* DIS. Allows the wake-up field A to be updated by hardware. */
#define T2CON_STOPINC_EN (0x1 << 11 ) /* EN. Prevents wake-up field A being automatically updated by hardware.This allows user software to update the T2INC register value. */
/* T2CON[WUEN] - Wake-up enable bits for time field values. */
#define T2CON_WUEN_BBA (*(volatile unsigned long *) 0x4204A120)
#define T2CON_WUEN_MSK (0x1 << 8 )
#define T2CON_WUEN (0x1 << 8 )
#define T2CON_WUEN_DIS (0x0 << 8 ) /* DIS. Disable asynchronous Wake-Up timer. Interrupt conditions will not wake-up the part from sleep mode. */
#define T2CON_WUEN_EN (0x1 << 8 ) /* EN. Enable asynchronous Wake-Up timer even when the core clock is off. Once the timer value equals any of the interrupt enabled compare field, a wake-up signal is generated. */
/* T2CON[ENABLE] - Timer enable bit. */
#define T2CON_ENABLE_BBA (*(volatile unsigned long *) 0x4204A11C)
#define T2CON_FREEZE_EN (0x1 << 3 ) /* EN. Enable the freeze of the high 16 bits after the lower bits have been read from T2VAL0. This ensures that the software reads an atomic shot of the timer. The entire T2VAL register unfreezes after the high bits (T2VAL1) have been read. */
/* T2CON[PRE] - Prescaler. */
#define T2CON_PRE_MSK (0x3 << 0 )
#define T2CON_PRE_DIV1 (0x0 << 0 ) /* DIV1. Source clock/1. If the selected clock source is PCLK this setting results in a prescaler of 4. */
#define T2IEN_WUFA_EN (0x1 << 0 ) /* EN. Generate an interrupt when T2VAL reaches T2WUFA. */
/* Reset Value for T2STA*/
#define T2STA_RVAL 0x0
/* T2STA[CON] - Indicates when a change in the enable bit is synchronized to the 32 kHz clock domain (Done automatically) */
#define T2STA_CON_BBA (*(volatile unsigned long *) 0x4204A5A0)
#define T2STA_CON_MSK (0x1 << 8 )
#define T2STA_CON (0x1 << 8 )
#define T2STA_CON_CLR (0x0 << 8 ) /* CLR. It returns low when the change in the Enable bit has been synchronised to the 32 kHz clock domain. */
#define T2STA_CON_SET (0x1 << 8 ) /* SET. This bit is set high when the Enable bit (bit 5) in the Control register is set or cleared and it is not synchronised to tthe 32 kHz clock. */
/* T2STA[FREEZE] - Status of T2VAL freeze */
#define T2STA_FREEZE_BBA (*(volatile unsigned long *) 0x4204A59C)
#define T2STA_FREEZE_MSK (0x1 << 7 )
#define T2STA_FREEZE (0x1 << 7 )
#define T2STA_FREEZE_CLR (0x0 << 7 ) /* CLR. Reset low when T2VAL1 is read, indicating T2VAL is unfrozen. */
#define T2STA_FREEZE_SET (0x1 << 7 ) /* SET. Set high when the T2VAL0 is read, indicating T2VAL is frozen. */
/* T2STA[ROLL] - Interrupt status bit for instances when counter rolls over. Only occurs in free running mode. */
#define T2STA_ROLL_BBA (*(volatile unsigned long *) 0x4204A590)
#define T2STA_ROLL_MSK (0x1 << 4 )
#define T2STA_ROLL (0x1 << 4 )
#define T2STA_ROLL_CLR (0x0 << 4 ) /* CLR. Indicate that the timer has not rolled over. */
#define T2STA_ROLL_SET (0x1 << 4 ) /* SET. Set high when enabled in the interrupt enable register and the T2VALS counter register is equal to all 1s */
/* T2STA[WUFD] - T2WUFD interrupt flag */
#define T2STA_WUFD_BBA (*(volatile unsigned long *) 0x4204A58C)
#define T2STA_WUFD_MSK (0x1 << 3 )
#define T2STA_WUFD (0x1 << 3 )
#define T2STA_WUFD_CLR (0x0 << 3 ) /* CLR. Cleared after a write to the corresponding bit in T2CLRI. */
#define T2STA_WUFD_SET (0x1 << 3 ) /* SET. Indicates that a comparator interrupt has occurred. */
/* T2STA[WUFC] - T2WUFC interrupt flag */
#define T2STA_WUFC_BBA (*(volatile unsigned long *) 0x4204A588)
#define T2STA_WUFC_MSK (0x1 << 2 )
#define T2STA_WUFC (0x1 << 2 )
#define T2STA_WUFC_CLR (0x0 << 2 ) /* CLR. Cleared after a write to the corresponding bit in T2CLRI. */
#define T2STA_WUFC_SET (0x1 << 2 ) /* SET. Indicates that a comparator interrupt has occurred. */
/* T2STA[WUFB] - T2WUFB interrupt flag */
#define T2STA_WUFB_BBA (*(volatile unsigned long *) 0x4204A584)
#define T2STA_WUFB_MSK (0x1 << 1 )
#define T2STA_WUFB (0x1 << 1 )
#define T2STA_WUFB_CLR (0x0 << 1 ) /* CLR. Cleared after a write to the corresponding bit in T2CLRI. */
#define T2STA_WUFB_SET (0x1 << 1 ) /* SET. Indicates that a comparator interrupt has occurred. */
/* T2STA[WUFA] - T2WUFA interrupt flag */
#define T2STA_WUFA_BBA (*(volatile unsigned long *) 0x4204A580)
#define T2STA_WUFA_MSK (0x1 << 0 )
#define T2STA_WUFA (0x1 << 0 )
#define T2STA_WUFA_CLR (0x0 << 0 ) /* CLR. Cleared after a write to the corresponding bit in T2CLRI. */
#define T2STA_WUFA_SET (0x1 << 0 ) /* SET. Indicates that a comparator interrupt has occurred. */
/* Reset Value for T2CLRI*/
#define T2CLRI_RVAL 0x0
/* T2CLRI[ROLL] - Clear interrupt on Rollover. Only occurs in free running mode. */
#define T2CLRI_ROLL_BBA (*(volatile unsigned long *) 0x4204A610)
#define T2CLRI_ROLL_MSK (0x1 << 4 )
#define T2CLRI_ROLL (0x1 << 4 )
#define T2CLRI_ROLL_CLR (0x1 << 4 ) /* CLR. Interrupt clear bit for when counter rolls over. */
#define T3CON_IRQ_BBA (*(volatile unsigned long *) 0x4204B104)
#define T3CON_IRQ_MSK (0x1 << 1 )
#define T3CON_IRQ (0x1 << 1 )
#define T3CON_IRQ_DIS (0x0 << 1 ) /* DIS. Generate a reset on a timeout. */
#define T3CON_IRQ_EN (0x1 << 1 ) /* EN. Generate an interrupt when the timer times out. This feature is available in active mode only and can be used to debug the watchdog timeout events. */
/* T3CON[PD] - Stop count in hibernate mode. */
#define T3CON_PD_BBA (*(volatile unsigned long *) 0x4204B100)
#define T3CON_PD_MSK (0x1 << 0 )
#define T3CON_PD (0x1 << 0 )
#define T3CON_PD_DIS (0x0 << 0 ) /* DIS. The timer continues to count when in hibernate mode. */
#define T3CON_PD_EN (0x1 << 0 ) /* EN. The timer stops counting when in hibernate mode. */
/* Reset Value for T3CLRI*/
#define T3CLRI_RVAL 0x0
/* T3CLRI[VALUE] - Clear watchdog. */
#define T3CLRI_VALUE_MSK (0xFFFF << 0 )
/* Reset Value for T3STA*/
#define T3STA_RVAL 0x20
/* T3STA[LOCK] - Lock status bit. */
#define T3STA_LOCK_BBA (*(volatile unsigned long *) 0x4204B310)
#define T3STA_LOCK_MSK (0x1 << 4 )
#define T3STA_LOCK (0x1 << 4 )
#define T3STA_LOCK_CLR (0x0 << 4 ) /* CLR. Cleared after any reset and until user code sets T3CON[5]. */
#define T3STA_LOCK_SET (0x1 << 4 ) /* SET. Set automatically in hardware when user code sets T3CON[5]. */
/* T3STA[CON] - T3CON write sync in progress. */
#define T3STA_CON_BBA (*(volatile unsigned long *) 0x4204B30C)
#define T3STA_CON_MSK (0x1 << 3 )
#define T3STA_CON (0x1 << 3 )
#define T3STA_CON_CLR (0x0 << 3 ) /* CLR. Timer ready to receive commands to T3CON. The previous change of T3CON has been synchronized in the timer clock domain. */
#define T3STA_CON_SET (0x1 << 3 ) /* SET. Timer not ready to receive commands to T3CON. Previous change of the T3CON value has not been synchronized in the timer clock domain. */
/* T3STA[LD] - T3LD write sync in progress. */
#define T3STA_LD_BBA (*(volatile unsigned long *) 0x4204B308)
#define T3STA_LD_MSK (0x1 << 2 )
#define T3STA_LD (0x1 << 2 )
#define T3STA_LD_CLR (0x0 << 2 ) /* CLR. The previous change of T3LD has been synchronized in the timer clock domain. */
#define T3STA_LD_SET (0x1 << 2 ) /* SET. Previous change of the T3LD value has not been synchronized in the timer clock domain. */
/* T3STA[CLRI] - T3CLRI write sync in progress. */
#define T3STA_CLRI_BBA (*(volatile unsigned long *) 0x4204B304)
#define T3STA_CLRI_MSK (0x1 << 1 )
#define T3STA_CLRI (0x1 << 1 )
#define T3STA_CLRI_CLR (0x0 << 1 ) /* CLR. Cleared when the interrupt is cleared in the timer clock domain. */
#define T3STA_CLRI_SET (0x1 << 1 ) /* SET. Set automatically when the T3CLRI value is being updated in the timer clock domain, indicating that the timers configuration is not yet valid. */
/* T3STA[IRQ] - Interrupt pending. */
#define T3STA_IRQ_BBA (*(volatile unsigned long *) 0x4204B300)
#define T3STA_IRQ_MSK (0x1 << 0 )
#define T3STA_IRQ (0x1 << 0 )
#define T3STA_IRQ_CLR (0x0 << 0 ) /* CLR. No timeout event has occurred. */
#define T3STA_IRQ_SET (0x1 << 0 ) /* SET. A timeout event has occurred. */
/* -------------------- End of section using anonymous unions ------------------- */