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nes-proj/cpu/x86/init/common/idt.c

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x86: Initialize Interrupt Descriptor Table This patch adds code to handle Interrupt Descriptor Table (IDT) initialization. The IDT is initialized with null descriptors therefore any interrupt at this point will cause a triple fault. The IDT initialization is part of x86 CPU initialization. Strictly speaking, there is no need to use attribute packed in struct intr_gate_desc however we use it for readability reasons.
2015-04-15 18:03:51 +00:00
/*
* Copyright (C) 2015, Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 15:34:02 +00:00
#include "gdt-layout.h"
#include "prot-domains.h"
x86: Initialize Interrupt Descriptor Table This patch adds code to handle Interrupt Descriptor Table (IDT) initialization. The IDT is initialized with null descriptors therefore any interrupt at this point will cause a triple fault. The IDT initialization is part of x86 CPU initialization. Strictly speaking, there is no need to use attribute packed in struct intr_gate_desc however we use it for readability reasons.
2015-04-15 18:03:51 +00:00
#include <stdint.h>
#include "helpers.h"
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 15:34:02 +00:00
#include "segmentation.h"
#include "idt.h"
x86: Initialize Interrupt Descriptor Table This patch adds code to handle Interrupt Descriptor Table (IDT) initialization. The IDT is initialized with null descriptors therefore any interrupt at this point will cause a triple fault. The IDT initialization is part of x86 CPU initialization. Strictly speaking, there is no need to use attribute packed in struct intr_gate_desc however we use it for readability reasons.
2015-04-15 18:03:51 +00:00
#define NUM_DESC 256
typedef struct idtr {
uint16_t limit;
uint32_t base;
} __attribute__((packed)) idtr_t;
x86: Add TSS-based protection domain support This patch extends the protection domain framework with an additional plugin to use Task-State Segment (TSS) structures to offload much of the work of switching protection domains to the CPU. This can save space compared to paging, since paging requires two 4KiB page tables and one 32-byte page table plus one whole-system TSS and an additional 32-byte data structure for each protection domain, whereas the approach implemented by this patch just requires a 128-byte data structure for each protection domain. Only a small number of protection domains will typically be used, so n * 128 < 8328 + (n * 32). For additional information, please refer to cpu/x86/mm/README.md. GCC 6 is introducing named address spaces for the FS and GS segments [1]. LLVM Clang also provides address spaces for the FS and GS segments [2]. This patch also adds support to the multi-segment X86 memory management subsystem for using these features instead of inline assembly blocks, which enables type checking to detect some address space mismatches. [1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html [2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
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typedef union intr_gate_desc {
struct __attribute__((packed)) {
uint16_t offset_low;
uint16_t selector; /* Segment Selector for destination code segment */
uint16_t fixed:11;
uint16_t d:1; /* Size of gate: 1 = 32 bits; 0 = 16 bits */
uint16_t pad:1;
uint16_t dpl:2; /* Descriptor Privilege Level */
uint16_t p:1; /* Segment Present flag */
uint16_t offset_high;
};
uint64_t raw;
struct {
uint32_t raw_lo;
uint32_t raw_hi;
};
} intr_gate_desc_t;
x86: Initialize Interrupt Descriptor Table This patch adds code to handle Interrupt Descriptor Table (IDT) initialization. The IDT is initialized with null descriptors therefore any interrupt at this point will cause a triple fault. The IDT initialization is part of x86 CPU initialization. Strictly speaking, there is no need to use attribute packed in struct intr_gate_desc however we use it for readability reasons.
2015-04-15 18:03:51 +00:00
/* According to Intel Combined Manual, Vol. 3, Section 6.10, the base addresses
* of the IDT should be aligned on an 8-byte boundary to maximize performance
* of cache line fills.
*/
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 15:34:02 +00:00
static intr_gate_desc_t __attribute__((aligned(8))) ATTR_BSS_KERN
idt[NUM_DESC];
x86: Initialize Interrupt Descriptor Table This patch adds code to handle Interrupt Descriptor Table (IDT) initialization. The IDT is initialized with null descriptors therefore any interrupt at this point will cause a triple fault. The IDT initialization is part of x86 CPU initialization. Strictly speaking, there is no need to use attribute packed in struct intr_gate_desc however we use it for readability reasons.
2015-04-15 18:03:51 +00:00
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 15:34:02 +00:00
/*---------------------------------------------------------------------------*/
x86: Introduce interrupt.h This patch introduces the interrupt.h header file which provides some helper macros to set a interrupt handler and disable/enable maskable hardware interrupts. Since there is no easy way to write an Interrupt Service Routines (ISR) in C (for further information on this, see [1]), we introduce the SET_INTERRUPT_HANDLER helper macro. The macro does two things: 1) Defines an assembly trampolin to a C function that will, indeed, handle the interrupt. 2) Sets the corresponding interrupt gate descriptor in IDT. The macro usage is pretty straightforward. The macro is defined as SET_INTERRUPT_HANDLER(num, has_error_code, handler) where: @num: Interrupt number (0-255) @has_error_code: 0 if processor doesn't push error code onto the stack. Otherwise, set this argument to 1. @handler: Pointer to function that should be called once the interrupt is raised. In case has_error_code == 0 the function prototype should be the following: void handler(void) Otherwise, it should be: void handler(struct interrupt_context context) For instance, let's say we want to set a handler for a device interrupt (for example, interrupt number 101). Remember, hardware interrupts don't have error code. So we should have something like this: void interrupt_handler(void) { /* Handling code here */ } void my_device_init(void) { ... SET_INTERRUPT_HANDLER(101, 0, interrupt_handler); ... } Now, let's say we want to set an interrupt handler for Page Fault (interrupt number 14). Some exceptions, such as Page Fault, pushes an error code onto the stack and may require registers values in order to be properly be handled. Thus, the code should look like this: void pagefault_handler(struct interrupt_context context) { /* Handling code here */ } void init_memory(void) { ... SET_INTERRUPT_HANDLER(14, 1, pagefault_handler); ... } For further information about exceptions and error code, refer to Intel Combined Manual, Vol. 3, Sections 6.3 and 6.13. Finally, we don't define any API to unregister interrupt handlers since we believe that it wouldn't be useful at all, at least at this moment. Considering Contiki's context, interrupt handler registration is pretty "static" and defined at compile-time by platform code (or the device drivers used by the platform). [1] http://wiki.osdev.org/Interrupt_Service_Routines
2015-04-15 18:05:12 +00:00
/* XXX: If you change this function prototype, make sure you fix the assembly
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 15:34:02 +00:00
* code in SET_INT_EXC_HANDLER macro in interrupt.h. Otherwise, you might
x86: Introduce interrupt.h This patch introduces the interrupt.h header file which provides some helper macros to set a interrupt handler and disable/enable maskable hardware interrupts. Since there is no easy way to write an Interrupt Service Routines (ISR) in C (for further information on this, see [1]), we introduce the SET_INTERRUPT_HANDLER helper macro. The macro does two things: 1) Defines an assembly trampolin to a C function that will, indeed, handle the interrupt. 2) Sets the corresponding interrupt gate descriptor in IDT. The macro usage is pretty straightforward. The macro is defined as SET_INTERRUPT_HANDLER(num, has_error_code, handler) where: @num: Interrupt number (0-255) @has_error_code: 0 if processor doesn't push error code onto the stack. Otherwise, set this argument to 1. @handler: Pointer to function that should be called once the interrupt is raised. In case has_error_code == 0 the function prototype should be the following: void handler(void) Otherwise, it should be: void handler(struct interrupt_context context) For instance, let's say we want to set a handler for a device interrupt (for example, interrupt number 101). Remember, hardware interrupts don't have error code. So we should have something like this: void interrupt_handler(void) { /* Handling code here */ } void my_device_init(void) { ... SET_INTERRUPT_HANDLER(101, 0, interrupt_handler); ... } Now, let's say we want to set an interrupt handler for Page Fault (interrupt number 14). Some exceptions, such as Page Fault, pushes an error code onto the stack and may require registers values in order to be properly be handled. Thus, the code should look like this: void pagefault_handler(struct interrupt_context context) { /* Handling code here */ } void init_memory(void) { ... SET_INTERRUPT_HANDLER(14, 1, pagefault_handler); ... } For further information about exceptions and error code, refer to Intel Combined Manual, Vol. 3, Sections 6.3 and 6.13. Finally, we don't define any API to unregister interrupt handlers since we believe that it wouldn't be useful at all, at least at this moment. Considering Contiki's context, interrupt handler registration is pretty "static" and defined at compile-time by platform code (or the device drivers used by the platform). [1] http://wiki.osdev.org/Interrupt_Service_Routines
2015-04-15 18:05:12 +00:00
* face a very-hard-to-find bug in the interrupt handling system.
*/
x86: Initialize Interrupt Descriptor Table This patch adds code to handle Interrupt Descriptor Table (IDT) initialization. The IDT is initialized with null descriptors therefore any interrupt at this point will cause a triple fault. The IDT initialization is part of x86 CPU initialization. Strictly speaking, there is no need to use attribute packed in struct intr_gate_desc however we use it for readability reasons.
2015-04-15 18:03:51 +00:00
void
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 15:34:02 +00:00
idt_set_intr_gate_desc(int intr_num,
uint32_t offset,
uint16_t cs,
uint16_t dpl)
x86: Initialize Interrupt Descriptor Table This patch adds code to handle Interrupt Descriptor Table (IDT) initialization. The IDT is initialized with null descriptors therefore any interrupt at this point will cause a triple fault. The IDT initialization is part of x86 CPU initialization. Strictly speaking, there is no need to use attribute packed in struct intr_gate_desc however we use it for readability reasons.
2015-04-15 18:03:51 +00:00
{
x86: Add TSS-based protection domain support This patch extends the protection domain framework with an additional plugin to use Task-State Segment (TSS) structures to offload much of the work of switching protection domains to the CPU. This can save space compared to paging, since paging requires two 4KiB page tables and one 32-byte page table plus one whole-system TSS and an additional 32-byte data structure for each protection domain, whereas the approach implemented by this patch just requires a 128-byte data structure for each protection domain. Only a small number of protection domains will typically be used, so n * 128 < 8328 + (n * 32). For additional information, please refer to cpu/x86/mm/README.md. GCC 6 is introducing named address spaces for the FS and GS segments [1]. LLVM Clang also provides address spaces for the FS and GS segments [2]. This patch also adds support to the multi-segment X86 memory management subsystem for using these features instead of inline assembly blocks, which enables type checking to detect some address space mismatches. [1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html [2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
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intr_gate_desc_t desc;
desc.offset_low = offset & 0xFFFF;
desc.selector = cs;
desc.fixed = BIT(9) | BIT(10);
desc.pad = 0;
desc.d = 1;
desc.dpl = dpl;
desc.p = 1;
desc.offset_high = (offset >> 16) & 0xFFFF;
x86: Initialize Interrupt Descriptor Table This patch adds code to handle Interrupt Descriptor Table (IDT) initialization. The IDT is initialized with null descriptors therefore any interrupt at this point will cause a triple fault. The IDT initialization is part of x86 CPU initialization. Strictly speaking, there is no need to use attribute packed in struct intr_gate_desc however we use it for readability reasons.
2015-04-15 18:03:51 +00:00
x86: Add TSS-based protection domain support This patch extends the protection domain framework with an additional plugin to use Task-State Segment (TSS) structures to offload much of the work of switching protection domains to the CPU. This can save space compared to paging, since paging requires two 4KiB page tables and one 32-byte page table plus one whole-system TSS and an additional 32-byte data structure for each protection domain, whereas the approach implemented by this patch just requires a 128-byte data structure for each protection domain. Only a small number of protection domains will typically be used, so n * 128 < 8328 + (n * 32). For additional information, please refer to cpu/x86/mm/README.md. GCC 6 is introducing named address spaces for the FS and GS segments [1]. LLVM Clang also provides address spaces for the FS and GS segments [2]. This patch also adds support to the multi-segment X86 memory management subsystem for using these features instead of inline assembly blocks, which enables type checking to detect some address space mismatches. [1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html [2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
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KERN_WRITEL(idt[intr_num].raw_hi, desc.raw_hi);
KERN_WRITEL(idt[intr_num].raw_lo, desc.raw_lo);
x86: Initialize Interrupt Descriptor Table This patch adds code to handle Interrupt Descriptor Table (IDT) initialization. The IDT is initialized with null descriptors therefore any interrupt at this point will cause a triple fault. The IDT initialization is part of x86 CPU initialization. Strictly speaking, there is no need to use attribute packed in struct intr_gate_desc however we use it for readability reasons.
2015-04-15 18:03:51 +00:00
}
/*---------------------------------------------------------------------------*/
/* Initialize Interrupt Descriptor Table. The IDT is initialized with
* null descriptors. Therefore, any interrupt at this point will cause
* a triple fault.
*/
void
idt_init(void)
{
idtr_t idtr;
/* Initialize idtr structure */
idtr.limit = (sizeof(intr_gate_desc_t) * NUM_DESC) - 1;
x86: Add TSS-based protection domain support This patch extends the protection domain framework with an additional plugin to use Task-State Segment (TSS) structures to offload much of the work of switching protection domains to the CPU. This can save space compared to paging, since paging requires two 4KiB page tables and one 32-byte page table plus one whole-system TSS and an additional 32-byte data structure for each protection domain, whereas the approach implemented by this patch just requires a 128-byte data structure for each protection domain. Only a small number of protection domains will typically be used, so n * 128 < 8328 + (n * 32). For additional information, please refer to cpu/x86/mm/README.md. GCC 6 is introducing named address spaces for the FS and GS segments [1]. LLVM Clang also provides address spaces for the FS and GS segments [2]. This patch also adds support to the multi-segment X86 memory management subsystem for using these features instead of inline assembly blocks, which enables type checking to detect some address space mismatches. [1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html [2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
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idtr.base = KERN_DATA_OFF_TO_PHYS_ADDR((uint32_t)idt);
x86: Initialize Interrupt Descriptor Table This patch adds code to handle Interrupt Descriptor Table (IDT) initialization. The IDT is initialized with null descriptors therefore any interrupt at this point will cause a triple fault. The IDT initialization is part of x86 CPU initialization. Strictly speaking, there is no need to use attribute packed in struct intr_gate_desc however we use it for readability reasons.
2015-04-15 18:03:51 +00:00
/* Load IDTR register */
__asm__("lidt %0\n\t" :: "m" (idtr));
}
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