688 lines
20 KiB
C
688 lines
20 KiB
C
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/**************************************************************************//**
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* @file core_cmInstr.h
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* @brief CMSIS Cortex-M Core Instruction Access Header File
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* @version V3.30
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* @date 17. February 2014
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*
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* @note
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*
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******************************************************************************/
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/* Copyright (c) 2009 - 2014 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#ifndef __CORE_CMINSTR_H
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#define __CORE_CMINSTR_H
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/* ########################## Core Instruction Access ######################### */
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/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
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Access to dedicated instructions
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@{
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*/
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#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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/* ARM armcc specific functions */
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#if (__ARMCC_VERSION < 400677)
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#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
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#endif
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/** \brief No Operation
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No Operation does nothing. This instruction can be used for code alignment purposes.
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*/
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#define __NOP __nop
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/** \brief Wait For Interrupt
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Wait For Interrupt is a hint instruction that suspends execution
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until one of a number of events occurs.
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*/
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#define __WFI __wfi
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/** \brief Wait For Event
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Wait For Event is a hint instruction that permits the processor to enter
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a low-power state until one of a number of events occurs.
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*/
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#define __WFE __wfe
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/** \brief Send Event
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Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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*/
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#define __SEV __sev
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/** \brief Instruction Synchronization Barrier
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Instruction Synchronization Barrier flushes the pipeline in the processor,
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so that all instructions following the ISB are fetched from cache or
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memory, after the instruction has been completed.
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*/
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#define __ISB() __isb(0xF)
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/** \brief Data Synchronization Barrier
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This function acts as a special kind of Data Memory Barrier.
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It completes when all explicit memory accesses before this instruction complete.
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*/
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#define __DSB() __dsb(0xF)
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/** \brief Data Memory Barrier
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This function ensures the apparent order of the explicit memory operations before
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and after the instruction, without ensuring their completion.
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*/
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#define __DMB() __dmb(0xF)
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/** \brief Reverse byte order (32 bit)
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This function reverses the byte order in integer value.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REV __rev
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/** \brief Reverse byte order (16 bit)
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This function reverses the byte order in two unsigned short values.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
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{
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rev16 r0, r0
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bx lr
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}
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#endif
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/** \brief Reverse byte order in signed short value
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This function reverses the byte order in a signed short value with sign extension to integer.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
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{
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revsh r0, r0
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bx lr
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}
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#endif
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/** \brief Rotate Right in unsigned value (32 bit)
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This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
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\param [in] value Value to rotate
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\param [in] value Number of Bits to rotate
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\return Rotated value
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*/
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#define __ROR __ror
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/** \brief Breakpoint
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This function causes the processor to enter Debug state.
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Debug tools can use this to investigate system state when the instruction at a particular address is reached.
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\param [in] value is ignored by the processor.
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If required, a debugger can use it to store additional information about the breakpoint.
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*/
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#define __BKPT(value) __breakpoint(value)
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#if (__CORTEX_M >= 0x03)
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/** \brief Reverse bit order of value
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This function reverses the bit order of the given value.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __RBIT __rbit
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/** \brief LDR Exclusive (8 bit)
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This function performs a exclusive LDR command for 8 bit value.
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\param [in] ptr Pointer to data
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\return value of type uint8_t at (*ptr)
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*/
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#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
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/** \brief LDR Exclusive (16 bit)
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This function performs a exclusive LDR command for 16 bit values.
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\param [in] ptr Pointer to data
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\return value of type uint16_t at (*ptr)
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*/
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#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
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/** \brief LDR Exclusive (32 bit)
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This function performs a exclusive LDR command for 32 bit values.
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\param [in] ptr Pointer to data
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\return value of type uint32_t at (*ptr)
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*/
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#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
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/** \brief STR Exclusive (8 bit)
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This function performs a exclusive STR command for 8 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#define __STREXB(value, ptr) __strex(value, ptr)
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/** \brief STR Exclusive (16 bit)
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This function performs a exclusive STR command for 16 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#define __STREXH(value, ptr) __strex(value, ptr)
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/** \brief STR Exclusive (32 bit)
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This function performs a exclusive STR command for 32 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#define __STREXW(value, ptr) __strex(value, ptr)
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/** \brief Remove the exclusive lock
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This function removes the exclusive lock which is created by LDREX.
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*/
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#define __CLREX __clrex
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/** \brief Signed Saturate
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This function saturates a signed value.
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\param [in] value Value to be saturated
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\param [in] sat Bit position to saturate to (1..32)
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\return Saturated value
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*/
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#define __SSAT __ssat
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/** \brief Unsigned Saturate
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This function saturates an unsigned value.
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\param [in] value Value to be saturated
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\param [in] sat Bit position to saturate to (0..31)
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\return Saturated value
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*/
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#define __USAT __usat
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/** \brief Count leading zeros
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This function counts the number of leading zeros of a data value.
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\param [in] value Value to count the leading zeros
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\return number of leading zeros in value
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*/
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#define __CLZ __clz
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#endif /* (__CORTEX_M >= 0x03) */
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#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
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/* GNU gcc specific functions */
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/* Define macros for porting to both thumb1 and thumb2.
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* For thumb1, use low register (r0-r7), specified by constrant "l"
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* Otherwise, use general registers, specified by constrant "r" */
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#if defined (__thumb__) && !defined (__thumb2__)
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#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
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#define __CMSIS_GCC_USE_REG(r) "l" (r)
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#else
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#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
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#define __CMSIS_GCC_USE_REG(r) "r" (r)
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#endif
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/** \brief No Operation
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No Operation does nothing. This instruction can be used for code alignment purposes.
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
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{
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__ASM volatile ("nop");
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}
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/** \brief Wait For Interrupt
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Wait For Interrupt is a hint instruction that suspends execution
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until one of a number of events occurs.
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
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{
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__ASM volatile ("wfi");
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}
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/** \brief Wait For Event
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Wait For Event is a hint instruction that permits the processor to enter
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a low-power state until one of a number of events occurs.
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
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{
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__ASM volatile ("wfe");
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}
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/** \brief Send Event
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Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
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{
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__ASM volatile ("sev");
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}
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/** \brief Instruction Synchronization Barrier
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Instruction Synchronization Barrier flushes the pipeline in the processor,
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so that all instructions following the ISB are fetched from cache or
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memory, after the instruction has been completed.
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
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{
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__ASM volatile ("isb");
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}
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/** \brief Data Synchronization Barrier
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This function acts as a special kind of Data Memory Barrier.
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It completes when all explicit memory accesses before this instruction complete.
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
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{
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__ASM volatile ("dsb");
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}
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/** \brief Data Memory Barrier
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This function ensures the apparent order of the explicit memory operations before
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and after the instruction, without ensuring their completion.
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
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{
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__ASM volatile ("dmb");
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}
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/** \brief Reverse byte order (32 bit)
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This function reverses the byte order in integer value.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
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{
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#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
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return __builtin_bswap32(value);
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#else
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uint32_t result;
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__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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return(result);
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#endif
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}
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/** \brief Reverse byte order (16 bit)
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This function reverses the byte order in two unsigned short values.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
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{
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uint32_t result;
|
||
|
|
|
||
|
|
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/** \brief Reverse byte order in signed short value
|
||
|
|
|
||
|
|
This function reverses the byte order in a signed short value with sign extension to integer.
|
||
|
|
|
||
|
|
\param [in] value Value to reverse
|
||
|
|
\return Reversed value
|
||
|
|
*/
|
||
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||
|
|
{
|
||
|
|
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||
|
|
return (short)__builtin_bswap16(value);
|
||
|
|
#else
|
||
|
|
uint32_t result;
|
||
|
|
|
||
|
|
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
|
||
|
|
return(result);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/** \brief Rotate Right in unsigned value (32 bit)
|
||
|
|
|
||
|
|
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||
|
|
|
||
|
|
\param [in] value Value to rotate
|
||
|
|
\param [in] value Number of Bits to rotate
|
||
|
|
\return Rotated value
|
||
|
|
*/
|
||
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||
|
|
{
|
||
|
|
return (op1 >> op2) | (op1 << (32 - op2));
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/** \brief Breakpoint
|
||
|
|
|
||
|
|
This function causes the processor to enter Debug state.
|
||
|
|
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||
|
|
|
||
|
|
\param [in] value is ignored by the processor.
|
||
|
|
If required, a debugger can use it to store additional information about the breakpoint.
|
||
|
|
*/
|
||
|
|
#define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||
|
|
|
||
|
|
|
||
|
|
#if (__CORTEX_M >= 0x03)
|
||
|
|
|
||
|
|
/** \brief Reverse bit order of value
|
||
|
|
|
||
|
|
This function reverses the bit order of the given value.
|
||
|
|
|
||
|
|
\param [in] value Value to reverse
|
||
|
|
\return Reversed value
|
||
|
|
*/
|
||
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
|
||
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/** \brief LDR Exclusive (8 bit)
|
||
|
|
|
||
|
|
This function performs a exclusive LDR command for 8 bit value.
|
||
|
|
|
||
|
|
\param [in] ptr Pointer to data
|
||
|
|
\return value of type uint8_t at (*ptr)
|
||
|
|
*/
|
||
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
|
||
|
|
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||
|
|
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
||
|
|
#else
|
||
|
|
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||
|
|
accepted by assembler. So has to use following less efficient pattern.
|
||
|
|
*/
|
||
|
|
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||
|
|
#endif
|
||
|
|
return ((uint8_t) result); /* Add explicit type cast here */
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/** \brief LDR Exclusive (16 bit)
|
||
|
|
|
||
|
|
This function performs a exclusive LDR command for 16 bit values.
|
||
|
|
|
||
|
|
\param [in] ptr Pointer to data
|
||
|
|
\return value of type uint16_t at (*ptr)
|
||
|
|
*/
|
||
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
|
||
|
|
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||
|
|
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
||
|
|
#else
|
||
|
|
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||
|
|
accepted by assembler. So has to use following less efficient pattern.
|
||
|
|
*/
|
||
|
|
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||
|
|
#endif
|
||
|
|
return ((uint16_t) result); /* Add explicit type cast here */
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/** \brief LDR Exclusive (32 bit)
|
||
|
|
|
||
|
|
This function performs a exclusive LDR command for 32 bit values.
|
||
|
|
|
||
|
|
\param [in] ptr Pointer to data
|
||
|
|
\return value of type uint32_t at (*ptr)
|
||
|
|
*/
|
||
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
|
||
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/** \brief STR Exclusive (8 bit)
|
||
|
|
|
||
|
|
This function performs a exclusive STR command for 8 bit values.
|
||
|
|
|
||
|
|
\param [in] value Value to store
|
||
|
|
\param [in] ptr Pointer to location
|
||
|
|
\return 0 Function succeeded
|
||
|
|
\return 1 Function failed
|
||
|
|
*/
|
||
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
|
||
|
|
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/** \brief STR Exclusive (16 bit)
|
||
|
|
|
||
|
|
This function performs a exclusive STR command for 16 bit values.
|
||
|
|
|
||
|
|
\param [in] value Value to store
|
||
|
|
\param [in] ptr Pointer to location
|
||
|
|
\return 0 Function succeeded
|
||
|
|
\return 1 Function failed
|
||
|
|
*/
|
||
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
|
||
|
|
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/** \brief STR Exclusive (32 bit)
|
||
|
|
|
||
|
|
This function performs a exclusive STR command for 32 bit values.
|
||
|
|
|
||
|
|
\param [in] value Value to store
|
||
|
|
\param [in] ptr Pointer to location
|
||
|
|
\return 0 Function succeeded
|
||
|
|
\return 1 Function failed
|
||
|
|
*/
|
||
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
|
||
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||
|
|
return(result);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/** \brief Remove the exclusive lock
|
||
|
|
|
||
|
|
This function removes the exclusive lock which is created by LDREX.
|
||
|
|
|
||
|
|
*/
|
||
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
||
|
|
{
|
||
|
|
__ASM volatile ("clrex" ::: "memory");
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/** \brief Signed Saturate
|
||
|
|
|
||
|
|
This function saturates a signed value.
|
||
|
|
|
||
|
|
\param [in] value Value to be saturated
|
||
|
|
\param [in] sat Bit position to saturate to (1..32)
|
||
|
|
\return Saturated value
|
||
|
|
*/
|
||
|
|
#define __SSAT(ARG1,ARG2) \
|
||
|
|
({ \
|
||
|
|
uint32_t __RES, __ARG1 = (ARG1); \
|
||
|
|
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||
|
|
__RES; \
|
||
|
|
})
|
||
|
|
|
||
|
|
|
||
|
|
/** \brief Unsigned Saturate
|
||
|
|
|
||
|
|
This function saturates an unsigned value.
|
||
|
|
|
||
|
|
\param [in] value Value to be saturated
|
||
|
|
\param [in] sat Bit position to saturate to (0..31)
|
||
|
|
\return Saturated value
|
||
|
|
*/
|
||
|
|
#define __USAT(ARG1,ARG2) \
|
||
|
|
({ \
|
||
|
|
uint32_t __RES, __ARG1 = (ARG1); \
|
||
|
|
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||
|
|
__RES; \
|
||
|
|
})
|
||
|
|
|
||
|
|
|
||
|
|
/** \brief Count leading zeros
|
||
|
|
|
||
|
|
This function counts the number of leading zeros of a data value.
|
||
|
|
|
||
|
|
\param [in] value Value to count the leading zeros
|
||
|
|
\return number of leading zeros in value
|
||
|
|
*/
|
||
|
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
|
||
|
|
{
|
||
|
|
uint32_t result;
|
||
|
|
|
||
|
|
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||
|
|
return ((uint8_t) result); /* Add explicit type cast here */
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* (__CORTEX_M >= 0x03) */
|
||
|
|
|
||
|
|
|
||
|
|
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||
|
|
/* IAR iccarm specific functions */
|
||
|
|
#include <cmsis_iar.h>
|
||
|
|
|
||
|
|
|
||
|
|
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||
|
|
/* TI CCS specific functions */
|
||
|
|
#include <cmsis_ccs.h>
|
||
|
|
|
||
|
|
|
||
|
|
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||
|
|
/* TASKING carm specific functions */
|
||
|
|
/*
|
||
|
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||
|
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||
|
|
* Including the CMSIS ones.
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||
|
|
/* Cosmic specific functions */
|
||
|
|
#include <cmsis_csm.h>
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||
|
|
|
||
|
|
#endif /* __CORE_CMINSTR_H */
|