Merge branch 'master' of git://git.devl.org/git/malvira/libmc1322x
This commit is contained in:
commit
011c6e7276
66
lib/maca.c
66
lib/maca.c
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@ -423,45 +423,38 @@ static uint8_t ram_values[4];
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void init_phy(void)
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{
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volatile uint32_t cnt;
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*MACA_RESET = (1 << maca_reset_rst);
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for(cnt = 0; cnt < 100; cnt++) {};
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*MACA_RESET = (1 << maca_reset_clkon);
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*MACA_CONTROL = maca_ctrl_seq_nop;
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for(cnt = 0; cnt < 400000; cnt++) {};
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// *MACA_TMREN = (1 << maca_tmren_strt) | (1 << maca_tmren_cpl);
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*MACA_CLKDIV = MACA_CLOCK_DIV;
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*MACA_WARMUP = 0x00180012;
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*MACA_EOFDELAY = 0x00000004;
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*MACA_CCADELAY = 0x001a0022;
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*MACA_TXCCADELAY = 0x00000025;
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*MACA_FRAMESYNC0 = 0x000000A7;
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*MACA_CLK = 0x00000008;
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*MACA_MASKIRQ = ((1 << maca_irq_rst) |
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(1 << maca_irq_acpl) |
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(1 << maca_irq_cm) |
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(1 << maca_irq_flt) |
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(1 << maca_irq_crc) |
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(1 << maca_irq_di) |
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(1 << maca_irq_sftclk)
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);
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*MACA_SLOTOFFSET = 0x00350000;
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*MACA_CLKDIV = MACA_CLOCK_DIV;
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*MACA_WARMUP = 0x00180012;
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*MACA_EOFDELAY = 0x00000004;
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*MACA_CCADELAY = 0x001a0022;
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*MACA_TXCCADELAY = 0x00000025;
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*MACA_FRAMESYNC0 = 0x000000A7;
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*MACA_CLK = 0x00000008;
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*MACA_MASKIRQ = ((1 << maca_irq_rst) |
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(1 << maca_irq_acpl) |
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(1 << maca_irq_cm) |
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(1 << maca_irq_flt) |
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(1 << maca_irq_crc) |
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(1 << maca_irq_di) |
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(1 << maca_irq_sftclk)
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);
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*MACA_SLOTOFFSET = 0x00350000;
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}
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void reset_maca(void)
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{
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uint32_t tmp;
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volatile uint32_t cnt;
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*MACA_RESET = (1 << maca_reset_rst);
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for(cnt = 0; cnt < 100; cnt++) {};
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*MACA_RESET = (1 << maca_reset_clkon);
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*MACA_CONTROL = maca_ctrl_seq_nop;
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do {
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tmp = *MACA_STATUS;
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} while ((tmp & 0xf) == maca_cc_not_completed);
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for(cnt = 0; cnt < 400000; cnt++) {};
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/* Clear all interrupts. */
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*MACA_CLRIRQ = 0xffff;
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@ -580,6 +573,7 @@ void radio_on(void) {
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/* turn the radio regulators back on */
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reg(0x80003048) = 0x00000f78;
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/* reinitialize the phy */
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reset_maca();
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init_phy();
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enable_irq(MACA);
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@ -758,6 +752,8 @@ const uint32_t AIMVAL[19] = {
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#define ADDR_POW2 ADDR_POW1 + 12
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#define ADDR_POW3 ADDR_POW1 + 64
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void set_power(uint8_t power) {
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safe_irq_disable(MACA);
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reg(ADDR_POW1) = PSMVAL[power];
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/* see http://devl.org/pipermail/mc1322x/2009-October/000065.html */
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@ -769,6 +765,8 @@ void set_power(uint8_t power) {
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#endif
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reg(ADDR_POW3) = AIMVAL[power];
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irq_restore();
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}
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const uint8_t VCODivI[16] = {
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@ -816,6 +814,7 @@ const uint32_t VCODivF[16] = {
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#define ADDR_CHAN4 (ADDR_CHAN1+48)
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void set_channel(uint8_t chan) {
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volatile uint32_t tmp;
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safe_irq_disable(MACA);
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tmp = reg(ADDR_CHAN1);
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tmp = tmp & 0xbfffffff;
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@ -836,6 +835,7 @@ void set_channel(uint8_t chan) {
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tmp = tmp | (((ctov[chan])<<8)&0x1F00);
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reg(ADDR_CHAN4) = tmp;
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/* duh! */
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irq_restore();
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}
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#define ROM_END 0x0013ffff
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@ -1,8 +1,8 @@
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#ifndef LOWLEVEL_H
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#define LOWLEVEL_H
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#define trim_xtal() pack_XTAL_CNTL(CTUNE_4PF, CTUNE, FTUNE, IBIAS);
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void default_vreg_init(void);
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void uart1_init(uint16_t inc, uint16_t mod, uint8_t samp);
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#endif
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@ -23,7 +23,7 @@ void main(void) {
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*GPIO_DATA_SEL0 = ( 1 << LED );
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/* trim the reference osc. to 24MHz */
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pack_XTAL_CNTL(CTUNE_4PF, CTUNE, FTUNE, IBIAS);
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trim_xtal();
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uart_init(INC, MOD, SAMP);
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@ -33,7 +33,7 @@ void main(void) {
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volatile packet_t *p;
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/* trim the reference osc. to 24MHz */
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pack_XTAL_CNTL(CTUNE_4PF, CTUNE, FTUNE, IBIAS);
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trim_xtal();
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uart_init(INC, MOD, SAMP);
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