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Uncrustify.

This commit is contained in:
Dragos Bogdan 2014-01-04 17:27:29 -05:00 committed by Ian Martin
parent 68417a0728
commit 1667c4f0de
3 changed files with 409 additions and 419 deletions
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355
ADF7023.c
View File

@ -2,7 +2,7 @@
* @file ADF7023.c
* @brief Implementation of ADF7023 Driver.
* @author DBogdan (Dragos.Bogdan@analog.com)
********************************************************************************
********************************************************************************
* Copyright 2013(c) Analog Devices, Inc.
*
* All rights reserved.
@ -36,9 +36,9 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************
********************************************************************************
* SVN Revision: $WCREV$
*******************************************************************************/
*******************************************************************************/
/******************************************************************************/
/***************************** Include Files **********************************/
@ -66,122 +66,116 @@ struct ADF7023_BBRAM ADF7023_BBRAMCurrent;
* @param readByte - Read data.
*
* @return None.
*******************************************************************************/
void ADF7023_WriteReadByte(unsigned char writeByte,
unsigned char* readByte)
*******************************************************************************/
void
ADF7023_WriteReadByte(unsigned char writeByte,
unsigned char *readByte)
{
unsigned char data = 0;
data = writeByte;
SPI_Read(0, &data, 1);
if(readByte)
{
*readByte = data;
}
}
unsigned char data = 0;
data = writeByte;
SPI_Read(0, &data, 1);
if(readByte) {
*readByte = data;
}
}
/***************************************************************************//**
* @brief Initializes the ADF7023.
*
* @return retVal - Result of the initialization procedure.
* Example: 0 - if initialization was successful;
* -1 - if initialization was unsuccessful.
*******************************************************************************/
char ADF7023_Init(void)
*******************************************************************************/
char
ADF7023_Init(void)
{
char retVal = 0;
unsigned char miso = 0;
unsigned short timeout = 0;
unsigned char status = 0;
ADF7023_BBRAMCurrent = ADF7023_BBRAMDefault;
SPI_Init(0, // MSB first.
1000000, // Clock frequency.
0, // Idle state for clock is a high level; active state is a low level.
1); // Serial output data changes on transition from idle clock state to active clock state.
ADF7023_CS_ASSERT;
while ((miso == 0) && (timeout < 1000))
{
miso = ADF7023_MISO;
timeout++;
}
if(timeout == 1000)
{
retVal = -1;
}
while(!(status & STATUS_CMD_READY))
{
ADF7023_GetStatus(&status);
}
ADF7023_SetRAM(0x100, 64, (unsigned char*)&ADF7023_BBRAMCurrent);
ADF7023_SetCommand(CMD_CONFIG_DEV);
return retVal;
}
char retVal = 0;
unsigned char miso = 0;
unsigned short timeout = 0;
unsigned char status = 0;
ADF7023_BBRAMCurrent = ADF7023_BBRAMDefault;
SPI_Init(0, /* MSB first. */
1000000, /* Clock frequency. */
0, /* Idle state for clock is a high level; active state is a low level. */
1); /* Serial output data changes on transition from idle clock state to active clock state. */
ADF7023_CS_ASSERT;
while((miso == 0) && (timeout < 1000)) {
miso = ADF7023_MISO;
timeout++;
}
if(timeout == 1000) {
retVal = -1;
}
while(!(status & STATUS_CMD_READY)) {
ADF7023_GetStatus(&status);
}
ADF7023_SetRAM(0x100, 64, (unsigned char *)&ADF7023_BBRAMCurrent);
ADF7023_SetCommand(CMD_CONFIG_DEV);
return retVal;
}
/***************************************************************************//**
* @brief Reads the status word of the ADF7023.
*
* @param status - Status word.
*
* @return None.
*******************************************************************************/
void ADF7023_GetStatus(unsigned char* status)
*******************************************************************************/
void
ADF7023_GetStatus(unsigned char *status)
{
ADF7023_CS_ASSERT;
ADF7023_WriteReadByte(SPI_NOP, 0);
ADF7023_WriteReadByte(SPI_NOP, status);
ADF7023_CS_DEASSERT;
ADF7023_CS_ASSERT;
ADF7023_WriteReadByte(SPI_NOP, 0);
ADF7023_WriteReadByte(SPI_NOP, status);
ADF7023_CS_DEASSERT;
}
/***************************************************************************//**
* @brief Initiates a command.
*
* @param command - Command.
*
* @return None.
*******************************************************************************/
void ADF7023_SetCommand(unsigned char command)
*******************************************************************************/
void
ADF7023_SetCommand(unsigned char command)
{
ADF7023_CS_ASSERT;
ADF7023_WriteReadByte(command, 0);
ADF7023_CS_DEASSERT;
ADF7023_CS_ASSERT;
ADF7023_WriteReadByte(command, 0);
ADF7023_CS_DEASSERT;
}
/***************************************************************************//**
* @brief Sets a FW state and waits until the device enters in that state.
*
* @param fwState - FW state.
*
* @return None.
*******************************************************************************/
void ADF7023_SetFwState(unsigned char fwState)
*******************************************************************************/
void
ADF7023_SetFwState(unsigned char fwState)
{
unsigned char status = 0;
switch(fwState)
{
case FW_STATE_PHY_OFF:
ADF7023_SetCommand(CMD_PHY_OFF);
break;
case FW_STATE_PHY_ON:
ADF7023_SetCommand(CMD_PHY_ON);
break;
case FW_STATE_PHY_RX:
ADF7023_SetCommand(CMD_PHY_RX);
break;
case FW_STATE_PHY_TX:
ADF7023_SetCommand(CMD_PHY_TX);
break;
default:
ADF7023_SetCommand(CMD_PHY_SLEEP);
}
while((status & STATUS_FW_STATE) != fwState)
{
ADF7023_GetStatus(&status);
}
}
unsigned char status = 0;
switch(fwState) {
case FW_STATE_PHY_OFF:
ADF7023_SetCommand(CMD_PHY_OFF);
break;
case FW_STATE_PHY_ON:
ADF7023_SetCommand(CMD_PHY_ON);
break;
case FW_STATE_PHY_RX:
ADF7023_SetCommand(CMD_PHY_RX);
break;
case FW_STATE_PHY_TX:
ADF7023_SetCommand(CMD_PHY_TX);
break;
default:
ADF7023_SetCommand(CMD_PHY_SLEEP);
}
while((status & STATUS_FW_STATE) != fwState) {
ADF7023_GetStatus(&status);
}
}
/***************************************************************************//**
* @brief Reads data from the RAM.
*
@ -190,22 +184,21 @@ void ADF7023_SetFwState(unsigned char fwState)
* @param data - Read buffer.
*
* @return None.
*******************************************************************************/
void ADF7023_GetRAM(unsigned long address,
unsigned long length,
unsigned char* data)
*******************************************************************************/
void
ADF7023_GetRAM(unsigned long address,
unsigned long length,
unsigned char *data)
{
ADF7023_CS_ASSERT;
ADF7023_WriteReadByte(SPI_MEM_RD | ((address & 0x700) >> 8), 0);
ADF7023_WriteReadByte(address & 0xFF, 0);
ADF7023_WriteReadByte(SPI_NOP, 0);
while(length--)
{
ADF7023_WriteReadByte(SPI_NOP, data++);
}
ADF7023_CS_DEASSERT;
ADF7023_CS_ASSERT;
ADF7023_WriteReadByte(SPI_MEM_RD | ((address & 0x700) >> 8), 0);
ADF7023_WriteReadByte(address & 0xFF, 0);
ADF7023_WriteReadByte(SPI_NOP, 0);
while(length--) {
ADF7023_WriteReadByte(SPI_NOP, data++);
}
ADF7023_CS_DEASSERT;
}
/***************************************************************************//**
* @brief Writes data to RAM.
*
@ -214,21 +207,20 @@ void ADF7023_GetRAM(unsigned long address,
* @param data - Write buffer.
*
* @return None.
*******************************************************************************/
void ADF7023_SetRAM(unsigned long address,
unsigned long length,
unsigned char* data)
*******************************************************************************/
void
ADF7023_SetRAM(unsigned long address,
unsigned long length,
unsigned char *data)
{
ADF7023_CS_ASSERT;
ADF7023_WriteReadByte(SPI_MEM_WR | ((address & 0x700) >> 8), 0);
ADF7023_WriteReadByte(address & 0xFF, 0);
while(length--)
{
ADF7023_WriteReadByte(*(data++), 0);
}
ADF7023_CS_DEASSERT;
ADF7023_CS_ASSERT;
ADF7023_WriteReadByte(SPI_MEM_WR | ((address & 0x700) >> 8), 0);
ADF7023_WriteReadByte(address & 0xFF, 0);
while(length--) {
ADF7023_WriteReadByte(*(data++), 0);
}
ADF7023_CS_DEASSERT;
}
/***************************************************************************//**
* @brief Receives one packet.
*
@ -236,26 +228,25 @@ void ADF7023_SetRAM(unsigned long address,
* @param length - Number of received bytes.
*
* @return None.
*******************************************************************************/
void ADF7023_ReceivePacket(unsigned char* packet, unsigned char* length)
*******************************************************************************/
void
ADF7023_ReceivePacket(unsigned char *packet, unsigned char *length)
{
unsigned char interruptReg = 0;
ADF7023_SetFwState(FW_STATE_PHY_ON);
ADF7023_SetFwState(FW_STATE_PHY_RX);
while(!(interruptReg & BBRAM_INTERRUPT_MASK_0_INTERRUPT_CRC_CORRECT))
{
ADF7023_GetRAM(MCR_REG_INTERRUPT_SOURCE_0,
0x1,
&interruptReg);
}
ADF7023_SetRAM(MCR_REG_INTERRUPT_SOURCE_0,
unsigned char interruptReg = 0;
ADF7023_SetFwState(FW_STATE_PHY_ON);
ADF7023_SetFwState(FW_STATE_PHY_RX);
while(!(interruptReg & BBRAM_INTERRUPT_MASK_0_INTERRUPT_CRC_CORRECT)) {
ADF7023_GetRAM(MCR_REG_INTERRUPT_SOURCE_0,
0x1,
&interruptReg);
ADF7023_GetRAM(0x10, 1, length);
ADF7023_GetRAM(0x12, *length - 2, packet);
}
ADF7023_SetRAM(MCR_REG_INTERRUPT_SOURCE_0,
0x1,
&interruptReg);
ADF7023_GetRAM(0x10, 1, length);
ADF7023_GetRAM(0x12, *length - 2, packet);
}
/***************************************************************************//**
* @brief Transmits one packet.
*
@ -263,83 +254,83 @@ void ADF7023_ReceivePacket(unsigned char* packet, unsigned char* length)
* @param length - Number of bytes to transmit.
*
* @return None.
*******************************************************************************/
void ADF7023_TransmitPacket(unsigned char* packet, unsigned char length)
*******************************************************************************/
void
ADF7023_TransmitPacket(unsigned char *packet, unsigned char length)
{
unsigned char interruptReg = 0;
unsigned char header[2] = {0, 0};
header[0] = 2 + length;
header[1] = ADF7023_BBRAMCurrent.addressMatchOffset;
ADF7023_SetRAM(0x10, 2, header);
ADF7023_SetRAM(0x12, length, packet);
ADF7023_SetFwState(FW_STATE_PHY_ON);
ADF7023_SetFwState(FW_STATE_PHY_TX);
while(!(interruptReg & BBRAM_INTERRUPT_MASK_0_INTERRUPT_TX_EOF))
{
ADF7023_GetRAM(MCR_REG_INTERRUPT_SOURCE_0,
0x1,
&interruptReg);
}
}
unsigned char interruptReg = 0;
unsigned char header[2] = { 0, 0 };
header[0] = 2 + length;
header[1] = ADF7023_BBRAMCurrent.addressMatchOffset;
ADF7023_SetRAM(0x10, 2, header);
ADF7023_SetRAM(0x12, length, packet);
ADF7023_SetFwState(FW_STATE_PHY_ON);
ADF7023_SetFwState(FW_STATE_PHY_TX);
while(!(interruptReg & BBRAM_INTERRUPT_MASK_0_INTERRUPT_TX_EOF)) {
ADF7023_GetRAM(MCR_REG_INTERRUPT_SOURCE_0,
0x1,
&interruptReg);
}
}
/***************************************************************************//**
* @brief Sets the channel frequency.
*
* @param chFreq - Channel frequency.
*
* @return None.
*******************************************************************************/
void ADF7023_SetChannelFrequency(unsigned long chFreq)
*******************************************************************************/
void
ADF7023_SetChannelFrequency(unsigned long chFreq)
{
chFreq = (unsigned long)(((float)chFreq / 26000000) * 65535);
ADF7023_BBRAMCurrent.channelFreq0 = (chFreq & 0x0000FF) >> 0;
ADF7023_BBRAMCurrent.channelFreq1 = (chFreq & 0x00FF00) >> 8;
ADF7023_BBRAMCurrent.channelFreq2 = (chFreq & 0xFF0000) >> 16;
ADF7023_SetRAM(0x100, 64, (unsigned char*)&ADF7023_BBRAMCurrent);
chFreq = (unsigned long)(((float)chFreq / 26000000) * 65535);
ADF7023_BBRAMCurrent.channelFreq0 = (chFreq & 0x0000FF) >> 0;
ADF7023_BBRAMCurrent.channelFreq1 = (chFreq & 0x00FF00) >> 8;
ADF7023_BBRAMCurrent.channelFreq2 = (chFreq & 0xFF0000) >> 16;
ADF7023_SetRAM(0x100, 64, (unsigned char *)&ADF7023_BBRAMCurrent);
}
/***************************************************************************//**
* @brief Sets the data rate.
*
* @param dataRate - Data rate.
*
* @return None.
*******************************************************************************/
void ADF7023_SetDataRate(unsigned long dataRate)
*******************************************************************************/
void
ADF7023_SetDataRate(unsigned long dataRate)
{
unsigned char status = 0;
dataRate = (unsigned long)(dataRate / 100);
ADF7023_BBRAMCurrent.radioCfg0 =
BBRAM_RADIO_CFG_0_DATA_RATE_7_0((dataRate & 0x00FF) >> 0);
ADF7023_BBRAMCurrent.radioCfg1 &= ~BBRAM_RADIO_CFG_1_DATA_RATE_11_8(0xF);
ADF7023_BBRAMCurrent.radioCfg1 |=
BBRAM_RADIO_CFG_1_DATA_RATE_11_8((dataRate & 0x0F00) >> 8);
ADF7023_SetRAM(0x100, 64, (unsigned char*)&ADF7023_BBRAMCurrent);
ADF7023_SetFwState(FW_STATE_PHY_OFF);
ADF7023_SetCommand(CMD_CONFIG_DEV);
}
unsigned char status = 0;
dataRate = (unsigned long)(dataRate / 100);
ADF7023_BBRAMCurrent.radioCfg0 =
BBRAM_RADIO_CFG_0_DATA_RATE_7_0((dataRate & 0x00FF) >> 0);
ADF7023_BBRAMCurrent.radioCfg1 &= ~BBRAM_RADIO_CFG_1_DATA_RATE_11_8(0xF);
ADF7023_BBRAMCurrent.radioCfg1 |=
BBRAM_RADIO_CFG_1_DATA_RATE_11_8((dataRate & 0x0F00) >> 8);
ADF7023_SetRAM(0x100, 64, (unsigned char *)&ADF7023_BBRAMCurrent);
ADF7023_SetFwState(FW_STATE_PHY_OFF);
ADF7023_SetCommand(CMD_CONFIG_DEV);
}
/***************************************************************************//**
* @brief Sets the frequency deviation.
*
* @param freqDev - Frequency deviation.
*
* @return None.
*******************************************************************************/
void ADF7023_SetFrequencyDeviation(unsigned long freqDev)
*******************************************************************************/
void
ADF7023_SetFrequencyDeviation(unsigned long freqDev)
{
unsigned char status = 0;
freqDev = (unsigned long)(freqDev / 100);
ADF7023_BBRAMCurrent.radioCfg1 &=
~BBRAM_RADIO_CFG_1_FREQ_DEVIATION_11_8(0xF);
ADF7023_BBRAMCurrent.radioCfg1 |=
BBRAM_RADIO_CFG_1_FREQ_DEVIATION_11_8((freqDev & 0x0F00) >> 8);
ADF7023_BBRAMCurrent.radioCfg2 =
BBRAM_RADIO_CFG_2_FREQ_DEVIATION_7_0((freqDev & 0x00FF) >> 0);
ADF7023_SetRAM(0x100, 64, (unsigned char*)&ADF7023_BBRAMCurrent);
ADF7023_SetFwState(FW_STATE_PHY_OFF);
ADF7023_SetCommand(CMD_CONFIG_DEV);
unsigned char status = 0;
freqDev = (unsigned long)(freqDev / 100);
ADF7023_BBRAMCurrent.radioCfg1 &=
~BBRAM_RADIO_CFG_1_FREQ_DEVIATION_11_8(0xF);
ADF7023_BBRAMCurrent.radioCfg1 |=
BBRAM_RADIO_CFG_1_FREQ_DEVIATION_11_8((freqDev & 0x0F00) >> 8);
ADF7023_BBRAMCurrent.radioCfg2 =
BBRAM_RADIO_CFG_2_FREQ_DEVIATION_7_0((freqDev & 0x00FF) >> 0);
ADF7023_SetRAM(0x100, 64, (unsigned char *)&ADF7023_BBRAMCurrent);
ADF7023_SetFwState(FW_STATE_PHY_OFF);
ADF7023_SetCommand(CMD_CONFIG_DEV);
}

197
ADF7023.h
View File

@ -2,7 +2,7 @@
* @file ADF7023.h
* @brief Header file of ADF7023 Driver.
* @author DBogdan (Dragos.Bogdan@analog.com)
********************************************************************************
********************************************************************************
* Copyright 2013(c) Analog Devices, Inc.
*
* All rights reserved.
@ -36,9 +36,9 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************
********************************************************************************
* SVN Revision: $WCREV$
*******************************************************************************/
*******************************************************************************/
#ifndef __ADF7023_H__
#define __ADF7023_H__
@ -63,32 +63,32 @@
#define FW_STATE_AES_ENCRYPT 0x0A
/* SPI Memory Access Commands */
#define SPI_MEM_WR 0x18 // Write data to packet RAM sequentially.
#define SPI_MEM_RD 0x38 // Read data from packet RAM sequentially.
#define SPI_MEMR_WR 0x08 // Write data to packet RAM nonsequentially.
#define SPI_MEMR_RD 0x28 // Read data from packet RAM nonsequentially.
#define SPI_NOP 0xFF // No operation.
#define SPI_MEM_WR 0x18 /* Write data to packet RAM sequentially. */
#define SPI_MEM_RD 0x38 /* Read data from packet RAM sequentially. */
#define SPI_MEMR_WR 0x08 /* Write data to packet RAM nonsequentially. */
#define SPI_MEMR_RD 0x28 /* Read data from packet RAM nonsequentially. */
#define SPI_NOP 0xFF /* No operation. */
/* Radio Controller Commands */
#define CMD_SYNC 0xA2 // This is an optional command. It is not necessary to use it during device initialization
#define CMD_PHY_OFF 0xB0 // Performs a transition of the device into the PHY_OFF state.
#define CMD_PHY_ON 0xB1 // Performs a transition of the device into the PHY_ON state.
#define CMD_PHY_RX 0xB2 // Performs a transition of the device into the PHY_RX state.
#define CMD_PHY_TX 0xB5 // Performs a transition of the device into the PHY_TX state.
#define CMD_PHY_SLEEP 0xBA // Performs a transition of the device into the PHY_SLEEP state.
#define CMD_CONFIG_DEV 0xBB // Configures the radio parameters based on the BBRAM values.
#define CMD_GET_RSSI 0xBC // Performs an RSSI measurement.
#define CMD_BB_CAL 0xBE // Performs a calibration of the IF filter.
#define CMD_HW_RESET 0xC8 // Performs a full hardware reset. The device enters the PHY_SLEEP state.
#define CMD_RAM_LOAD_INIT 0xBF // Prepares the program RAM for a firmware module download.
#define CMD_RAM_LOAD_DONE 0xC7 // Performs a reset of the communications processor after download of a firmware module to program RAM.
#define CMD_IR_CAL 0xBD // Initiates an image rejection calibration routine.
#define CMD_AES_ENCRYPT 0xD0 // Performs an AES encryption on the transmit payload data stored in packet RAM.
#define CMD_AES_DECRYPT 0xD2 // Performs an AES decryption on the received payload data stored in packet RAM.
#define CMD_AES_DECRYPT_INIT 0xD1 // Initializes the internal variables required for AES decryption.
#define CMD_RS_ENCODE_INIT 0xD1 // Initializes the internal variables required for the Reed Solomon encoding.
#define CMD_RS_ENCODE 0xD0 // Calculates and appends the Reed Solomon check bytes to the transmit payload data stored in packet RAM.
#define CMD_RS_DECODE 0xD2 // Performs a Reed Solomon error correction on the received payload data stored in packet RAM.
#define CMD_SYNC 0xA2 /* This is an optional command. It is not necessary to use it during device initialization */
#define CMD_PHY_OFF 0xB0 /* Performs a transition of the device into the PHY_OFF state. */
#define CMD_PHY_ON 0xB1 /* Performs a transition of the device into the PHY_ON state. */
#define CMD_PHY_RX 0xB2 /* Performs a transition of the device into the PHY_RX state. */
#define CMD_PHY_TX 0xB5 /* Performs a transition of the device into the PHY_TX state. */
#define CMD_PHY_SLEEP 0xBA /* Performs a transition of the device into the PHY_SLEEP state. */
#define CMD_CONFIG_DEV 0xBB /* Configures the radio parameters based on the BBRAM values. */
#define CMD_GET_RSSI 0xBC /* Performs an RSSI measurement. */
#define CMD_BB_CAL 0xBE /* Performs a calibration of the IF filter. */
#define CMD_HW_RESET 0xC8 /* Performs a full hardware reset. The device enters the PHY_SLEEP state. */
#define CMD_RAM_LOAD_INIT 0xBF /* Prepares the program RAM for a firmware module download. */
#define CMD_RAM_LOAD_DONE 0xC7 /* Performs a reset of the communications processor after download of a firmware module to program RAM. */
#define CMD_IR_CAL 0xBD /* Initiates an image rejection calibration routine. */
#define CMD_AES_ENCRYPT 0xD0 /* Performs an AES encryption on the transmit payload data stored in packet RAM. */
#define CMD_AES_DECRYPT 0xD2 /* Performs an AES decryption on the received payload data stored in packet RAM. */
#define CMD_AES_DECRYPT_INIT 0xD1 /* Initializes the internal variables required for AES decryption. */
#define CMD_RS_ENCODE_INIT 0xD1 /* Initializes the internal variables required for the Reed Solomon encoding. */
#define CMD_RS_ENCODE 0xD0 /* Calculates and appends the Reed Solomon check bytes to the transmit payload data stored in packet RAM. */
#define CMD_RS_DECODE 0xD2 /* Performs a Reed Solomon error correction on the received payload data stored in packet RAM. */
/* Battery Backup Memory (BBRAM) */
#define BBRAM_REG_INTERRUPT_MASK_0 0x100
@ -295,72 +295,71 @@
#define MCR_REG_GPIO_CONFIGURE 0x3FA
#define MCR_REG_TEST_DAC_GAIN 0x3FD
struct ADF7023_BBRAM
{
unsigned char interruptMask0; // 0x100
unsigned char interruptMask1; // 0x101
unsigned char numberOfWakeups0; // 0x102
unsigned char numberOfWakeups1; // 0x103
unsigned char numberOfWakeupsIrqThreshold0; // 0x104
unsigned char numberOfWakeupsIrqThreshold1; // 0x105
unsigned char rxDwellTime; // 0x106
unsigned char parmtimeDivider; // 0x107
unsigned char swmRssiThresh; // 0x108
unsigned char channelFreq0; // 0x109
unsigned char channelFreq1; // 0x10A
unsigned char channelFreq2; // 0x10B
unsigned char radioCfg0; // 0x10C
unsigned char radioCfg1; // 0x10D
unsigned char radioCfg2; // 0x10E
unsigned char radioCfg3; // 0x10F
unsigned char radioCfg4; // 0x110
unsigned char radioCfg5; // 0x111
unsigned char radioCfg6; // 0x112
unsigned char radioCfg7; // 0x113
unsigned char radioCfg8; // 0x114
unsigned char radioCfg9; // 0x115
unsigned char radioCfg10; // 0x116
unsigned char radioCfg11; // 0x117
unsigned char imageRejectCalPhase; // 0x118
unsigned char imageRejectCalAmplitude; // 0x119
unsigned char modeControl; // 0x11A
unsigned char preambleMatch; // 0x11B
unsigned char symbolMode; // 0x11C
unsigned char preambleLen; // 0x11D
unsigned char crcPoly0; // 0x11E
unsigned char crcPoly1; // 0x11F
unsigned char syncControl; // 0x120
unsigned char syncByte0; // 0x121
unsigned char syncByte1; // 0x122
unsigned char syncByte2; // 0x123
unsigned char txBaseAdr; // 0x124
unsigned char rxBaseAdr; // 0x125
unsigned char packetLengthControl; // 0x126
unsigned char packetLengthMax; // 0x127
unsigned char staticRegFix; // 0x128
unsigned char addressMatchOffset; // 0x129
unsigned char addressLength; // 0x12A
unsigned char addressFiltering0; // 0x12B
unsigned char addressFiltering1; // 0x12C
unsigned char addressFiltering2; // 0x12D
unsigned char addressFiltering3; // 0x12E
unsigned char addressFiltering4; // 0x12F
unsigned char addressFiltering5; // 0x130
unsigned char addressFiltering6; // 0x131
unsigned char addressFiltering7; // 0x132
unsigned char addressFiltering8; // 0x133
unsigned char addressFiltering9; // 0x134
unsigned char addressFiltering10; // 0x135
unsigned char addressFiltering11; // 0x136
unsigned char addressFiltering12; // 0x137
unsigned char rssiWaitTime; // 0x138
unsigned char testmodes; // 0x139
unsigned char transitionClockDiv; // 0x13A
unsigned char reserved0; // 0x13B
unsigned char reserved1; // 0x13C
unsigned char reserved2; // 0x13D
unsigned char rxSynthLockTime; // 0x13E
unsigned char txSynthLockTime; // 0x13F
struct ADF7023_BBRAM {
unsigned char interruptMask0; /* 0x100 */
unsigned char interruptMask1; /* 0x101 */
unsigned char numberOfWakeups0; /* 0x102 */
unsigned char numberOfWakeups1; /* 0x103 */
unsigned char numberOfWakeupsIrqThreshold0; /* 0x104 */
unsigned char numberOfWakeupsIrqThreshold1; /* 0x105 */
unsigned char rxDwellTime; /* 0x106 */
unsigned char parmtimeDivider; /* 0x107 */
unsigned char swmRssiThresh; /* 0x108 */
unsigned char channelFreq0; /* 0x109 */
unsigned char channelFreq1; /* 0x10A */
unsigned char channelFreq2; /* 0x10B */
unsigned char radioCfg0; /* 0x10C */
unsigned char radioCfg1; /* 0x10D */
unsigned char radioCfg2; /* 0x10E */
unsigned char radioCfg3; /* 0x10F */
unsigned char radioCfg4; /* 0x110 */
unsigned char radioCfg5; /* 0x111 */
unsigned char radioCfg6; /* 0x112 */
unsigned char radioCfg7; /* 0x113 */
unsigned char radioCfg8; /* 0x114 */
unsigned char radioCfg9; /* 0x115 */
unsigned char radioCfg10; /* 0x116 */
unsigned char radioCfg11; /* 0x117 */
unsigned char imageRejectCalPhase; /* 0x118 */
unsigned char imageRejectCalAmplitude; /* 0x119 */
unsigned char modeControl; /* 0x11A */
unsigned char preambleMatch; /* 0x11B */
unsigned char symbolMode; /* 0x11C */
unsigned char preambleLen; /* 0x11D */
unsigned char crcPoly0; /* 0x11E */
unsigned char crcPoly1; /* 0x11F */
unsigned char syncControl; /* 0x120 */
unsigned char syncByte0; /* 0x121 */
unsigned char syncByte1; /* 0x122 */
unsigned char syncByte2; /* 0x123 */
unsigned char txBaseAdr; /* 0x124 */
unsigned char rxBaseAdr; /* 0x125 */
unsigned char packetLengthControl; /* 0x126 */
unsigned char packetLengthMax; /* 0x127 */
unsigned char staticRegFix; /* 0x128 */
unsigned char addressMatchOffset; /* 0x129 */
unsigned char addressLength; /* 0x12A */
unsigned char addressFiltering0; /* 0x12B */
unsigned char addressFiltering1; /* 0x12C */
unsigned char addressFiltering2; /* 0x12D */
unsigned char addressFiltering3; /* 0x12E */
unsigned char addressFiltering4; /* 0x12F */
unsigned char addressFiltering5; /* 0x130 */
unsigned char addressFiltering6; /* 0x131 */
unsigned char addressFiltering7; /* 0x132 */
unsigned char addressFiltering8; /* 0x133 */
unsigned char addressFiltering9; /* 0x134 */
unsigned char addressFiltering10; /* 0x135 */
unsigned char addressFiltering11; /* 0x136 */
unsigned char addressFiltering12; /* 0x137 */
unsigned char rssiWaitTime; /* 0x138 */
unsigned char testmodes; /* 0x139 */
unsigned char transitionClockDiv; /* 0x13A */
unsigned char reserved0; /* 0x13B */
unsigned char reserved1; /* 0x13C */
unsigned char reserved2; /* 0x13D */
unsigned char rxSynthLockTime; /* 0x13E */
unsigned char txSynthLockTime; /* 0x13F */
};
#define ADF7023_TX_BASE_ADR 0x10
@ -374,7 +373,7 @@ struct ADF7023_BBRAM
char ADF7023_Init(void);
/* Reads the status word of the ADF7023. */
void ADF7023_GetStatus(unsigned char* status);
void ADF7023_GetStatus(unsigned char *status);
/* Initiates a command. */
void ADF7023_SetCommand(unsigned char command);
@ -385,18 +384,18 @@ void ADF7023_SetFwState(unsigned char fwState);
/* Reads data from the RAM. */
void ADF7023_GetRAM(unsigned long address,
unsigned long length,
unsigned char* data);
unsigned char *data);
/* Writes data to RAM. */
void ADF7023_SetRAM(unsigned long address,
unsigned long length,
unsigned char* data);
unsigned char *data);
/* Receives one packet. */
void ADF7023_ReceivePacket(unsigned char* packet, unsigned char* length);
void ADF7023_ReceivePacket(unsigned char *packet, unsigned char *length);
/* Transmits one packet. */
void ADF7023_TransmitPacket(unsigned char* packet, unsigned char length);
void ADF7023_TransmitPacket(unsigned char *packet, unsigned char length);
/* Sets the channel frequency. */
void ADF7023_SetChannelFrequency(unsigned long chFreq);
@ -407,4 +406,4 @@ void ADF7023_SetDataRate(unsigned long dataRate);
/* Sets the frequency deviation. */
void ADF7023_SetFrequencyDeviation(unsigned long freqDev);
#endif // __ADF7023_H__
#endif /* __ADF7023_H__ */

276
ADF7023_Config.h
View File

@ -2,7 +2,7 @@
* @file ADF7023_Config.h
* @brief Configuration file of ADF7023 Driver.
* @author DBogdan (Dragos.Bogdan@analog.com)
********************************************************************************
********************************************************************************
* Copyright 2013(c) Analog Devices, Inc.
*
* All rights reserved.
@ -36,9 +36,9 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************
********************************************************************************
* SVN Revision: $WCREV$
*******************************************************************************/
*******************************************************************************/
#ifndef __ADF7023_CONFIG_H__
#define __ADF7023_CONFIG_H__
@ -52,140 +52,140 @@
/******************************************************************************/
struct ADF7023_BBRAM ADF7023_BBRAMDefault =
{
/* interruptMask0 - 0x100 */
BBRAM_INTERRUPT_MASK_0_INTERRUPT_TX_EOF |
BBRAM_INTERRUPT_MASK_0_INTERRUPT_CRC_CORRECT,
/* interruptMask1 - 0x101 */
0x00,
/* numberOfWakeups0 - 0x102 */
0x00,
/* numberOfWakeups1 - 0x103 */
0x00,
/* numberOfWakeupsIrqThreshold0 - 0x104 */
0xFF,
/* numberOfWakeupsIrqThreshold1 - 0x105 */
0xFF,
/* rxDwellTime - 0x106 */
0x00,
/* parmtimeDivider - 0x107 */
0x33,
/* swmRssiThresh - 0x108 */
0x31,
/* channelFreq0 - 0x109 */
0x51, // Channel Frequency: 433 MHz
/* channelFreq1 - 0x10A */
0xA7, // Channel Frequency: 433 MHz
/* channelFreq2 - 0x10B */
0x10, // Channel Frequency: 433 MHz
/* radioCfg0 - 0x10C */
BBRAM_RADIO_CFG_0_DATA_RATE_7_0(0xE8), // Data rate: 100 kbps
/* radioCfg1 - 0x10D */
BBRAM_RADIO_CFG_1_FREQ_DEVIATION_11_8(0x00) | // Frequency deviation: 25 Hz
BBRAM_RADIO_CFG_1_DATA_RATE_11_8(0x03), // Data rate: 100 kbps
/* radioCfg2 - 0x10E */
BBRAM_RADIO_CFG_2_FREQ_DEVIATION_7_0(0xFA), // Frequency deviation: 25 Hz
/* radioCfg3 - 0x10F */
0x31,
/* radioCfg4 - 0x110 */
0x16,
/* radioCfg5 - 0x111 */
0x00,
/* radioCfg6 - 0x112 */
BBRAM_RADIO_CFG_6_DISCRIM_PHASE(0x2),
/* radioCfg7 - 0x113 */
BBRAM_RADIO_CFG_7_AGC_LOCK_MODE(3),
/* radioCfg8 - 0x114 */
BBRAM_RADIO_CFG_8_PA_SINGLE_DIFF_SEL |
BBRAM_RADIO_CFG_8_PA_LEVEL(0xF) |
BBRAM_RADIO_CFG_8_PA_RAMP(1),
/* radioCfg9 - 0x115 */
BBRAM_RADIO_CFG_9_IFBW(2),
/* radioCfg10 - 0x116 */
BBRAM_RADIO_CFG_10_AFC_SCHEME(2) |
BBRAM_RADIO_CFG_10_AFC_LOCK_MODE(3),
/* radioCfg11 - 0x117 */
BBRAM_RADIO_CFG_11_AFC_KP(3) |
BBRAM_RADIO_CFG_11_AFC_KI(7),
/* imageRejectCalPhase - 0x118 */
0x00,
/* imageRejectCalAmplitude - 0x119 */
0x00,
/* modeControl - 0x11A */
BBRAM_MODE_CONTROL_BB_CAL,
/* preambleMatch - 0x11B */
0x0C,
/* symbolMode - 0x11C */
BBRAM_SYMBOL_MODE_MANCHESTER_ENC,
/* preambleLen - 0x11D */
0x20,
/* crcPoly0 - 0x11E */
0x00,
/* crcPoly1 - 0x11F */
0x00,
/* syncControl - 0x120 */
BBRAM_SYNC_CONTROL_SYNC_WORD_LENGTH(8),
/* syncByte0 - 0x121 */
0x00,
/* syncByte1 - 0x122 */
0x00,
/* syncByte2 - 0x123 */
0x12,
/* txBaseAdr - 0x124 */
ADF7023_TX_BASE_ADR,
/* rxBaseAdr - 0x125 */
ADF7023_RX_BASE_ADR,
/* packetLengthControl - 0x126 */
0x24,
/* packetLengthMax - 0x127 */
0xF0,
/* staticRegFix - 0x128 */
0x00,
/* addressMatchOffset - 0x129 */
0x01,
/* addressLength - 0x12A */
0x02,
/* addressFiltering0 - 0x12B */
0x01,
/* addressFiltering1 - 0x12C */
0xFF,
/* addressFiltering2 - 0x12D */
0xFF,
/* addressFiltering3 - 0x12E */
0xFF,
/* addressFiltering4 - 0x12F */
0x02,
/* addressFiltering5 - 0x130 */
0x0F,
/* addressFiltering6 - 0x131 */
0xFF,
/* addressFiltering7 - 0x132 */
0x0F,
/* addressFiltering8 - 0x133 */
0xFF,
/* addressFiltering9 - 0x134 */
0x00,
/* addressFiltering10 - 0x135 */
0x00,
/* addressFiltering11 - 0x136 */
0x00,
/* addressFiltering12 - 0x137 */
0x00,
/* rssiWaitTime - 0x138 */
0x00,
/* testmodes - 0x139 */
0x00,
/* transitionClockDiv - 0x13A */
0x00,
/* reserved0 - 0x13B */
0x00,
/* reserved1 - 0x13C */
0x00,
/* reserved2 - 0x13D */
0x00,
/* rxSynthLockTime - 0x13E */
0x00,
/* txSynthLockTime - 0x13F */
0x00,
/* interruptMask0 - 0x100 */
BBRAM_INTERRUPT_MASK_0_INTERRUPT_TX_EOF |
BBRAM_INTERRUPT_MASK_0_INTERRUPT_CRC_CORRECT,
/* interruptMask1 - 0x101 */
0x00,
/* numberOfWakeups0 - 0x102 */
0x00,
/* numberOfWakeups1 - 0x103 */
0x00,
/* numberOfWakeupsIrqThreshold0 - 0x104 */
0xFF,
/* numberOfWakeupsIrqThreshold1 - 0x105 */
0xFF,
/* rxDwellTime - 0x106 */
0x00,
/* parmtimeDivider - 0x107 */
0x33,
/* swmRssiThresh - 0x108 */
0x31,
/* channelFreq0 - 0x109 */
0x51, /* Channel Frequency: 433 MHz */
/* channelFreq1 - 0x10A */
0xA7, /* Channel Frequency: 433 MHz */
/* channelFreq2 - 0x10B */
0x10, /* Channel Frequency: 433 MHz */
/* radioCfg0 - 0x10C */
BBRAM_RADIO_CFG_0_DATA_RATE_7_0(0xE8), /* Data rate: 100 kbps */
/* radioCfg1 - 0x10D */
BBRAM_RADIO_CFG_1_FREQ_DEVIATION_11_8(0x00) | /* Frequency deviation: 25 Hz */
BBRAM_RADIO_CFG_1_DATA_RATE_11_8(0x03), /* Data rate: 100 kbps */
/* radioCfg2 - 0x10E */
BBRAM_RADIO_CFG_2_FREQ_DEVIATION_7_0(0xFA), /* Frequency deviation: 25 Hz */
/* radioCfg3 - 0x10F */
0x31,
/* radioCfg4 - 0x110 */
0x16,
/* radioCfg5 - 0x111 */
0x00,
/* radioCfg6 - 0x112 */
BBRAM_RADIO_CFG_6_DISCRIM_PHASE(0x2),
/* radioCfg7 - 0x113 */
BBRAM_RADIO_CFG_7_AGC_LOCK_MODE(3),
/* radioCfg8 - 0x114 */
BBRAM_RADIO_CFG_8_PA_SINGLE_DIFF_SEL |
BBRAM_RADIO_CFG_8_PA_LEVEL(0xF) |
BBRAM_RADIO_CFG_8_PA_RAMP(1),
/* radioCfg9 - 0x115 */
BBRAM_RADIO_CFG_9_IFBW(2),
/* radioCfg10 - 0x116 */
BBRAM_RADIO_CFG_10_AFC_SCHEME(2) |
BBRAM_RADIO_CFG_10_AFC_LOCK_MODE(3),
/* radioCfg11 - 0x117 */
BBRAM_RADIO_CFG_11_AFC_KP(3) |
BBRAM_RADIO_CFG_11_AFC_KI(7),
/* imageRejectCalPhase - 0x118 */
0x00,
/* imageRejectCalAmplitude - 0x119 */
0x00,
/* modeControl - 0x11A */
BBRAM_MODE_CONTROL_BB_CAL,
/* preambleMatch - 0x11B */
0x0C,
/* symbolMode - 0x11C */
BBRAM_SYMBOL_MODE_MANCHESTER_ENC,
/* preambleLen - 0x11D */
0x20,
/* crcPoly0 - 0x11E */
0x00,
/* crcPoly1 - 0x11F */
0x00,
/* syncControl - 0x120 */
BBRAM_SYNC_CONTROL_SYNC_WORD_LENGTH(8),
/* syncByte0 - 0x121 */
0x00,
/* syncByte1 - 0x122 */
0x00,
/* syncByte2 - 0x123 */
0x12,
/* txBaseAdr - 0x124 */
ADF7023_TX_BASE_ADR,
/* rxBaseAdr - 0x125 */
ADF7023_RX_BASE_ADR,
/* packetLengthControl - 0x126 */
0x24,
/* packetLengthMax - 0x127 */
0xF0,
/* staticRegFix - 0x128 */
0x00,
/* addressMatchOffset - 0x129 */
0x01,
/* addressLength - 0x12A */
0x02,
/* addressFiltering0 - 0x12B */
0x01,
/* addressFiltering1 - 0x12C */
0xFF,
/* addressFiltering2 - 0x12D */
0xFF,
/* addressFiltering3 - 0x12E */
0xFF,
/* addressFiltering4 - 0x12F */
0x02,
/* addressFiltering5 - 0x130 */
0x0F,
/* addressFiltering6 - 0x131 */
0xFF,
/* addressFiltering7 - 0x132 */
0x0F,
/* addressFiltering8 - 0x133 */
0xFF,
/* addressFiltering9 - 0x134 */
0x00,
/* addressFiltering10 - 0x135 */
0x00,
/* addressFiltering11 - 0x136 */
0x00,
/* addressFiltering12 - 0x137 */
0x00,
/* rssiWaitTime - 0x138 */
0x00,
/* testmodes - 0x139 */
0x00,
/* transitionClockDiv - 0x13A */
0x00,
/* reserved0 - 0x13B */
0x00,
/* reserved1 - 0x13C */
0x00,
/* reserved2 - 0x13D */
0x00,
/* rxSynthLockTime - 0x13E */
0x00,
/* txSynthLockTime - 0x13F */
0x00,
};
#endif // __ADF7023_CONFIG_H__
#endif /* __ADF7023_CONFIG_H__ */