Use additive offsets
OR-ing an offset to a base address instead of adding it is dangerous
because it can only work if the base address is aligned enough for the
offset.
Moreover, if the base address or the offset has a value unknown at
compile time, then the assembly instructions dedicated to 'base +
offset' addressing on most CPUs can't be emitted by the compiler because
this would require the alignment of the base address against the offset
to be known in order to optimize 'base | offset' into 'base + offset'.
In that case, the compiler has to emit more instructions in order to
compute 'base | offset' on most CPUs, e.g. on ARM, which means larger
binary size and slower execution.
Hence, replace all occurrences of 'base | offset' with 'base + offset'.
This must become a coding rule.
Here are the results for the cc2538-demo example:
- Compilation of uart_init():
* before:
REG(regs->base | UART_CC) = 0;
200b78: f446 637c orr.w r3, r6, #4032 ; 0xfc0
200b7c: f043 0308 orr.w r3, r3, #8
200b80: 2200 movs r2, #0
200b82: 601a str r2, [r3, #0]
* now:
REG(regs->base + UART_CC) = 0;
200b7a: 2300 movs r3, #0
200b7c: f8c4 3fc8 str.w r3, [r4, #4040] ; 0xfc8
- Size of the .text section:
* before: 0x4c7c
* now: 0x4c28
* saved: 84 bytes
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
This commit is contained in:
Benoît Thébaudeau
parent
c76316adf2
commit
19fd7a3551
@ -96,17 +96,17 @@ clock_init(void)
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REG(SYS_CTRL_RCGCGPT) |= SYS_CTRL_RCGCGPT_GPT0;
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/* Make sure GPT0 is off */
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REG(GPT_0_BASE | GPTIMER_CTL) = 0;
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REG(GPT_0_BASE + GPTIMER_CTL) = 0;
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/* 16-bit */
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REG(GPT_0_BASE | GPTIMER_CFG) = 0x04;
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REG(GPT_0_BASE + GPTIMER_CFG) = 0x04;
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/* One-Shot, Count Down, No Interrupts */
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REG(GPT_0_BASE | GPTIMER_TAMR) = GPTIMER_TAMR_TAMR_ONE_SHOT;
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REG(GPT_0_BASE + GPTIMER_TAMR) = GPTIMER_TAMR_TAMR_ONE_SHOT;
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/* Prescale by 16 (thus, value 15 in TAPR) */
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REG(GPT_0_BASE | GPTIMER_TAPR) = 0x0F;
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REG(GPT_0_BASE + GPTIMER_TAPR) = 0x0F;
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}
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/*---------------------------------------------------------------------------*/
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CCIF clock_time_t
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@ -144,11 +144,11 @@ clock_wait(clock_time_t i)
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void
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clock_delay_usec(uint16_t dt)
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{
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REG(GPT_0_BASE | GPTIMER_TAILR) = dt;
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REG(GPT_0_BASE | GPTIMER_CTL) |= GPTIMER_CTL_TAEN;
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REG(GPT_0_BASE + GPTIMER_TAILR) = dt;
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REG(GPT_0_BASE + GPTIMER_CTL) |= GPTIMER_CTL_TAEN;
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/* One-Shot mode: TAEN will be cleared when the timer reaches 0 */
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while(REG(GPT_0_BASE | GPTIMER_CTL) & GPTIMER_CTL_TAEN);
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while(REG(GPT_0_BASE + GPTIMER_CTL) & GPTIMER_CTL_TAEN);
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}
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/*---------------------------------------------------------------------------*/
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/**
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@ -87,7 +87,7 @@ gpio_port_a_isr()
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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notify(REG(GPIO_A_BASE | GPIO_MIS), GPIO_A_NUM);
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notify(REG(GPIO_A_BASE + GPIO_MIS), GPIO_A_NUM);
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GPIO_CLEAR_INTERRUPT(GPIO_A_BASE, 0xFF);
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GPIO_CLEAR_POWER_UP_INTERRUPT(GPIO_A_NUM, 0xFF);
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@ -103,7 +103,7 @@ gpio_port_b_isr()
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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notify(REG(GPIO_B_BASE | GPIO_MIS), GPIO_B_NUM);
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notify(REG(GPIO_B_BASE + GPIO_MIS), GPIO_B_NUM);
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GPIO_CLEAR_INTERRUPT(GPIO_B_BASE, 0xFF);
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GPIO_CLEAR_POWER_UP_INTERRUPT(GPIO_B_NUM, 0xFF);
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@ -119,7 +119,7 @@ gpio_port_c_isr()
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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notify(REG(GPIO_C_BASE | GPIO_MIS), GPIO_C_NUM);
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notify(REG(GPIO_C_BASE + GPIO_MIS), GPIO_C_NUM);
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GPIO_CLEAR_INTERRUPT(GPIO_C_BASE, 0xFF);
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GPIO_CLEAR_POWER_UP_INTERRUPT(GPIO_C_NUM, 0xFF);
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@ -135,7 +135,7 @@ gpio_port_d_isr()
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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notify(REG(GPIO_D_BASE | GPIO_MIS), GPIO_D_NUM);
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notify(REG(GPIO_D_BASE + GPIO_MIS), GPIO_D_NUM);
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GPIO_CLEAR_INTERRUPT(GPIO_D_BASE, 0xFF);
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GPIO_CLEAR_POWER_UP_INTERRUPT(GPIO_D_NUM, 0xFF);
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@ -91,28 +91,28 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_SET_INPUT(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_DIR) &= ~(PIN_MASK); } while(0)
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do { REG((PORT_BASE) + GPIO_DIR) &= ~(PIN_MASK); } while(0)
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/** \brief Set pins with PIN_MASK of port with PORT_BASE to output.
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* \param PORT_BASE GPIO Port register offset
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_SET_OUTPUT(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_DIR) |= (PIN_MASK); } while(0)
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do { REG((PORT_BASE) + GPIO_DIR) |= (PIN_MASK); } while(0)
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/** \brief Set pins with PIN_MASK of port with PORT_BASE high.
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* \param PORT_BASE GPIO Port register offset
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_SET_PIN(PORT_BASE, PIN_MASK) \
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do { REG(((PORT_BASE) | GPIO_DATA) + ((PIN_MASK) << 2)) = 0xFF; } while(0)
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do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0xFF; } while(0)
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/** \brief Set pins with PIN_MASK of port with PORT_BASE low.
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* \param PORT_BASE GPIO Port register offset
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_CLR_PIN(PORT_BASE, PIN_MASK) \
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do { REG(((PORT_BASE) | GPIO_DATA) + ((PIN_MASK) << 2)) = 0x00; } while(0)
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do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0x00; } while(0)
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/** \brief Set pins with PIN_MASK of port with PORT_BASE to value.
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* \param PORT_BASE GPIO Port register offset
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@ -133,7 +133,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* and then use 0x0A as the value ((1 << 3) | (1 << 1) for pins 3 and 1)
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*/
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#define GPIO_WRITE_PIN(PORT_BASE, PIN_MASK, value) \
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do { REG(((PORT_BASE) | GPIO_DATA) + ((PIN_MASK) << 2)) = (value); } while(0)
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do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = (value); } while(0)
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/** \brief Read pins with PIN_MASK of port with PORT_BASE.
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* \param PORT_BASE GPIO Port register offset
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@ -146,21 +146,21 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* the macro will return 0x81.
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*/
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#define GPIO_READ_PIN(PORT_BASE, PIN_MASK) \
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REG(((PORT_BASE) | GPIO_DATA) + ((PIN_MASK) << 2))
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REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2))
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/** \brief Set pins with PIN_MASK of port with PORT_BASE to detect edge.
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* \param PORT_BASE GPIO Port register offset
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_DETECT_EDGE(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_IS) &= ~(PIN_MASK); } while(0)
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do { REG((PORT_BASE) + GPIO_IS) &= ~(PIN_MASK); } while(0)
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/** \brief Set pins with PIN_MASK of port with PORT_BASE to detect level.
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* \param PORT_BASE GPIO Port register offset
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_DETECT_LEVEL(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_IS) |= (PIN_MASK); } while(0)
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do { REG((PORT_BASE) + GPIO_IS) |= (PIN_MASK); } while(0)
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/** \brief Set pins with PIN_MASK of port with PORT_BASE to trigger an
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* interrupt on both edges.
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@ -168,7 +168,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_TRIGGER_BOTH_EDGES(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_IBE) |= (PIN_MASK); } while(0)
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do { REG((PORT_BASE) + GPIO_IBE) |= (PIN_MASK); } while(0)
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/** \brief Set pins with PIN_MASK of port with PORT_BASE to trigger an
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* interrupt on single edge (controlled by GPIO_IEV).
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@ -176,7 +176,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_TRIGGER_SINGLE_EDGE(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_IBE) &= ~(PIN_MASK); } while(0)
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do { REG((PORT_BASE) + GPIO_IBE) &= ~(PIN_MASK); } while(0)
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/** \brief Set pins with PIN_MASK of port with PORT_BASE to trigger an
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* interrupt on rising edge.
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@ -184,7 +184,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_DETECT_RISING(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_IEV) |= (PIN_MASK); } while(0)
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do { REG((PORT_BASE) + GPIO_IEV) |= (PIN_MASK); } while(0)
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/** \brief Set pins with PIN_MASK of port with PORT_BASE to trigger an
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* interrupt on falling edge.
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@ -192,7 +192,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_DETECT_FALLING(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_IEV) &= ~(PIN_MASK); } while(0)
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do { REG((PORT_BASE) + GPIO_IEV) &= ~(PIN_MASK); } while(0)
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/** \brief Enable interrupt triggering for pins with PIN_MASK of port with
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* PORT_BASE.
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@ -200,7 +200,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_ENABLE_INTERRUPT(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_IE) |= (PIN_MASK); } while(0)
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do { REG((PORT_BASE) + GPIO_IE) |= (PIN_MASK); } while(0)
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/** \brief Disable interrupt triggering for pins with PIN_MASK of port with
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* PORT_BASE.
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@ -208,7 +208,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_DISABLE_INTERRUPT(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_IE) &= ~(PIN_MASK); } while(0)
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do { REG((PORT_BASE) + GPIO_IE) &= ~(PIN_MASK); } while(0)
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/** \brief Clear interrupt triggering for pins with PIN_MASK of port with
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* PORT_BASE.
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@ -216,7 +216,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_CLEAR_INTERRUPT(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_IC) = (PIN_MASK); } while(0)
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do { REG((PORT_BASE) + GPIO_IC) = (PIN_MASK); } while(0)
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/** \brief Configure the pin to be under peripheral control with PIN_MASK of
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* port with PORT_BASE.
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@ -224,7 +224,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_PERIPHERAL_CONTROL(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_AFSEL) |= (PIN_MASK); } while(0)
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do { REG((PORT_BASE) + GPIO_AFSEL) |= (PIN_MASK); } while(0)
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/** \brief Configure the pin to be software controlled with PIN_MASK of port
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* with PORT_BASE.
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@ -232,7 +232,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_SOFTWARE_CONTROL(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_AFSEL) &= ~(PIN_MASK); } while(0)
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do { REG((PORT_BASE) + GPIO_AFSEL) &= ~(PIN_MASK); } while(0)
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/** \brief Set pins with PIN_MASK of port PORT to trigger a power-up interrupt
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* on rising edge.
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@ -240,7 +240,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_POWER_UP_ON_RISING(PORT, PIN_MASK) \
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do { REG(GPIO_PORT_TO_BASE(PORT) | GPIO_P_EDGE_CTRL) &= \
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do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_P_EDGE_CTRL) &= \
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~((PIN_MASK) << ((PORT) << 3)); } while(0)
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/** \brief Set pins with PIN_MASK of port PORT to trigger a power-up interrupt
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@ -249,7 +249,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_POWER_UP_ON_FALLING(PORT, PIN_MASK) \
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do { REG(GPIO_PORT_TO_BASE(PORT) | GPIO_P_EDGE_CTRL) |= \
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do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_P_EDGE_CTRL) |= \
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(PIN_MASK) << ((PORT) << 3); } while(0)
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/** \brief Enable power-up interrupt triggering for pins with PIN_MASK of port
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@ -258,7 +258,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_ENABLE_POWER_UP_INTERRUPT(PORT, PIN_MASK) \
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do { REG(GPIO_PORT_TO_BASE(PORT) | GPIO_PI_IEN) |= \
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do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_PI_IEN) |= \
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(PIN_MASK) << ((PORT) << 3); } while(0)
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/** \brief Disable power-up interrupt triggering for pins with PIN_MASK of port
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@ -267,7 +267,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_DISABLE_POWER_UP_INTERRUPT(PORT, PIN_MASK) \
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do { REG(GPIO_PORT_TO_BASE(PORT) | GPIO_PI_IEN) &= \
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do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_PI_IEN) &= \
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~((PIN_MASK) << ((PORT) << 3)); } while(0)
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/** \brief Clear power-up interrupt triggering for pins with PIN_MASK of port
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@ -276,7 +276,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_CLEAR_POWER_UP_INTERRUPT(PORT, PIN_MASK) \
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do { REG(GPIO_PORT_TO_BASE(PORT) | GPIO_IRQ_DETECT_ACK) = \
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do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_IRQ_DETECT_ACK) = \
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(PIN_MASK) << ((PORT) << 3); } while(0)
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/**
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@ -57,7 +57,7 @@ nvic_init()
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interrupt_unpend = (uint32_t *)NVIC_UNPEND0;
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/* Provide our interrupt table to the NVIC */
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REG(SCB_VTABLE) = (NVIC_CONF_VTABLE_BASE | NVIC_CONF_VTABLE_OFFSET);
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REG(SCB_VTABLE) = (NVIC_CONF_VTABLE_BASE + NVIC_CONF_VTABLE_OFFSET);
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}
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/*---------------------------------------------------------------------------*/
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void
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@ -206,22 +206,22 @@ reset(uint32_t uart_base)
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uint32_t lchr;
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/* Make sure the UART is disabled before trying to configure it */
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REG(uart_base | UART_CTL) = UART_CTL_VALUE;
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REG(uart_base + UART_CTL) = UART_CTL_VALUE;
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/* Clear error status */
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REG(uart_base | UART_ECR) = 0xFF;
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REG(uart_base + UART_ECR) = 0xFF;
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/* Store LCHR configuration */
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lchr = REG(uart_base | UART_LCRH);
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lchr = REG(uart_base + UART_LCRH);
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/* Flush FIFOs by clearing LCHR.FEN */
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REG(uart_base | UART_LCRH) = 0;
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REG(uart_base + UART_LCRH) = 0;
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/* Restore LCHR configuration */
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REG(uart_base | UART_LCRH) = lchr;
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REG(uart_base + UART_LCRH) = lchr;
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/* UART Enable */
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REG(uart_base | UART_CTL) |= UART_CTL_UARTEN;
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REG(uart_base + UART_CTL) |= UART_CTL_UARTEN;
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}
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/*---------------------------------------------------------------------------*/
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static bool
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@ -232,7 +232,7 @@ permit_pm1(void)
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for(regs = &uart_regs[0]; regs < &uart_regs[UART_INSTANCE_COUNT]; regs++) {
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/* Note: UART_FR.TXFE reads 0 if the UART clock is gated. */
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if((REG(SYS_CTRL_RCGCUART) & regs->sys_ctrl_rcgcuart_uart) != 0 &&
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(REG(regs->base | UART_FR) & UART_FR_TXFE) == 0) {
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(REG(regs->base + UART_FR) & UART_FR_TXFE) == 0) {
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return false;
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}
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}
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@ -261,7 +261,7 @@ uart_init(uint8_t uart)
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REG(SYS_CTRL_DCGCUART) |= regs->sys_ctrl_dcgcuart_uart;
|
||||
|
||||
/* Run on SYS_DIV */
|
||||
REG(regs->base | UART_CC) = 0;
|
||||
REG(regs->base + UART_CC) = 0;
|
||||
|
||||
/*
|
||||
* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
|
||||
@ -292,21 +292,21 @@ uart_init(uint8_t uart)
|
||||
* Acknowledge RX and RX Timeout
|
||||
* Acknowledge Framing, Overrun and Break Errors
|
||||
*/
|
||||
REG(regs->base | UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
|
||||
REG(regs->base | UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
|
||||
REG(regs->base + UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
|
||||
REG(regs->base + UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
|
||||
|
||||
REG(regs->base | UART_IFLS) =
|
||||
REG(regs->base + UART_IFLS) =
|
||||
UART_IFLS_RXIFLSEL_1_8 | UART_IFLS_TXIFLSEL_1_2;
|
||||
|
||||
/* Make sure the UART is disabled before trying to configure it */
|
||||
REG(regs->base | UART_CTL) = UART_CTL_VALUE;
|
||||
REG(regs->base + UART_CTL) = UART_CTL_VALUE;
|
||||
|
||||
/* Baud Rate Generation */
|
||||
REG(regs->base | UART_IBRD) = regs->ibrd;
|
||||
REG(regs->base | UART_FBRD) = regs->fbrd;
|
||||
REG(regs->base + UART_IBRD) = regs->ibrd;
|
||||
REG(regs->base + UART_FBRD) = regs->fbrd;
|
||||
|
||||
/* UART Control: 8N1 with FIFOs */
|
||||
REG(regs->base | UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
|
||||
REG(regs->base + UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
|
||||
|
||||
/*
|
||||
* Enable hardware flow control (RTS/CTS) if requested.
|
||||
@ -316,18 +316,18 @@ uart_init(uint8_t uart)
|
||||
REG(IOC_UARTCTS_UART1) = ioc_input_sel(regs->cts.port, regs->cts.pin);
|
||||
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->cts.port), GPIO_PIN_MASK(regs->cts.pin));
|
||||
ioc_set_over(regs->cts.port, regs->cts.pin, IOC_OVERRIDE_DIS);
|
||||
REG(UART_1_BASE | UART_CTL) |= UART_CTL_CTSEN;
|
||||
REG(UART_1_BASE + UART_CTL) |= UART_CTL_CTSEN;
|
||||
}
|
||||
|
||||
if(regs->rts.port >= 0) {
|
||||
ioc_set_sel(regs->rts.port, regs->rts.pin, IOC_PXX_SEL_UART1_RTS);
|
||||
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rts.port), GPIO_PIN_MASK(regs->rts.pin));
|
||||
ioc_set_over(regs->rts.port, regs->rts.pin, IOC_OVERRIDE_OE);
|
||||
REG(UART_1_BASE | UART_CTL) |= UART_CTL_RTSEN;
|
||||
REG(UART_1_BASE + UART_CTL) |= UART_CTL_RTSEN;
|
||||
}
|
||||
|
||||
/* UART Enable */
|
||||
REG(regs->base | UART_CTL) |= UART_CTL_UARTEN;
|
||||
REG(regs->base + UART_CTL) |= UART_CTL_UARTEN;
|
||||
|
||||
/* Enable UART0 Interrupts */
|
||||
nvic_interrupt_enable(regs->nvic_int);
|
||||
@ -354,9 +354,9 @@ uart_write_byte(uint8_t uart, uint8_t b)
|
||||
uart_base = uart_regs[uart].base;
|
||||
|
||||
/* Block if the TX FIFO is full */
|
||||
while(REG(uart_base | UART_FR) & UART_FR_TXFF);
|
||||
while(REG(uart_base + UART_FR) & UART_FR_TXFF);
|
||||
|
||||
REG(uart_base | UART_DR) = b;
|
||||
REG(uart_base + UART_DR) = b;
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void
|
||||
@ -371,18 +371,18 @@ uart_isr(uint8_t uart)
|
||||
|
||||
/* Store the current MIS and clear all flags early, except the RTM flag.
|
||||
* This will clear itself when we read out the entire FIFO contents */
|
||||
mis = REG(uart_base | UART_MIS) & 0x0000FFFF;
|
||||
mis = REG(uart_base + UART_MIS) & 0x0000FFFF;
|
||||
|
||||
REG(uart_base | UART_ICR) = 0x0000FFBF;
|
||||
REG(uart_base + UART_ICR) = 0x0000FFBF;
|
||||
|
||||
if(mis & (UART_MIS_RXMIS | UART_MIS_RTMIS)) {
|
||||
while(!(REG(uart_base | UART_FR) & UART_FR_RXFE)) {
|
||||
while(!(REG(uart_base + UART_FR) & UART_FR_RXFE)) {
|
||||
if(input_handler[uart] != NULL) {
|
||||
input_handler[uart]((unsigned char)(REG(uart_base | UART_DR) & 0xFF));
|
||||
input_handler[uart]((unsigned char)(REG(uart_base + UART_DR) & 0xFF));
|
||||
} else {
|
||||
/* To prevent an Overrun Error, we need to flush the FIFO even if we
|
||||
* don't have an input_handler. Use mis as a data trash can */
|
||||
mis = REG(uart_base | UART_DR);
|
||||
mis = REG(uart_base + UART_DR);
|
||||
}
|
||||
}
|
||||
} else if(mis & (UART_MIS_OEMIS | UART_MIS_BEMIS | UART_MIS_FEMIS)) {
|
||||
|
||||
@ -167,7 +167,7 @@ clock_delay_usec(uint16_t len)
|
||||
* Wait for TBEN to clear. CC26xxware does not provide us with a convenient
|
||||
* function, hence the direct register access here
|
||||
*/
|
||||
while(HWREG(GPT0_BASE | GPT_O_CTL) & GPT_CTL_TBEN);
|
||||
while(HWREG(GPT0_BASE + GPT_O_CTL) & GPT_CTL_TBEN);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/**
|
||||
|
||||
@ -50,10 +50,10 @@ void halInternalGetMfgTokenData(void *data, uint16_t ID, uint8_t index, uint8_t
|
||||
MEMCOPY(ram, eui64, 8 /*EUI64_SIZE*/);
|
||||
} else {
|
||||
//read from the Information Blocks. The token ID is only the
|
||||
//bottom 16bits of the token's actual address. Since the info blocks
|
||||
//exist in the range DATA_BIG_INFO_BASE-DATA_BIG_INFO_END, we need
|
||||
//to OR the ID with DATA_BIG_INFO_BASE to get the real address.
|
||||
uint32_t realAddress = (DATA_BIG_INFO_BASE|ID) + (len*index);
|
||||
//DATA_BIG_INFO_BASE-relative 16-bit offset of the token. Since the
|
||||
//info blocks exist in the range DATA_BIG_INFO_BASE-DATA_BIG_INFO_END,
|
||||
//we need to add the ID to DATA_BIG_INFO_BASE to get the real address.
|
||||
uint32_t realAddress = (DATA_BIG_INFO_BASE+ID) + (len*index);
|
||||
uint8_t *flash = (uint8_t *)realAddress;
|
||||
|
||||
|
||||
@ -77,7 +77,7 @@ void halInternalGetMfgTokenData(void *data, uint16_t ID, uint8_t index, uint8_t
|
||||
void halInternalSetMfgTokenData(uint16_t token, void *data, uint8_t len)
|
||||
{
|
||||
StStatus flashStatus;
|
||||
uint32_t realAddress = (DATA_BIG_INFO_BASE|token);
|
||||
uint32_t realAddress = (DATA_BIG_INFO_BASE+token);
|
||||
uint8_t * flash = (uint8_t *)realAddress;
|
||||
uint32_t i;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user