x86: Add Intel Quark X1000 GPIO Controller (non-legacy) support
This patch adds the gpio.c and gpio.h files, which support access to GPIO Controller (non-legacy) configuration register through a function interface. It doesn't add interrupt support due to pinmux reasons. On Galileo Gen 2 we need to configure a pin as input/interrupt using pinmux and this can only be achieved through I2C. There's one pin exported by default as GPIO output and we used this one to test this driver. In the future, we plan to add an I2C driver and a pinmux configuration driver in order to solve this kind of problems.
This commit is contained in:
Ricardo de Almeida Gonzaga
Jesus Sanchez-Palencia
parent
60f6edef80
commit
2d552285cd
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@ -2,7 +2,7 @@ include $(CONTIKI)/cpu/x86/Makefile.x86_common
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CONTIKI_CPU_DIRS += drivers/legacy_pc drivers/quarkX1000 init/legacy_pc
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CONTIKI_SOURCEFILES += bootstrap_quarkX1000.S rtc.c pit.c pic.c irq.c nmi.c pci.c uart-16x50.c uart.c
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CONTIKI_SOURCEFILES += bootstrap_quarkX1000.S rtc.c pit.c pic.c irq.c nmi.c pci.c uart-16x50.c uart.c gpio.c
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CFLAGS += -m32 -march=i586 -mtune=i586
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LDFLAGS += -m32 -Xlinker -T -Xlinker $(CONTIKI)/cpu/x86/quarkX1000.ld
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@ -0,0 +1,184 @@
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/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "gpio.h"
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#include "helpers.h"
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/* GPIO Controler Registers */
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#define SWPORTA_DR 0x00
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#define SWPORTA_DDR 0x04
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#define INTEN 0x30
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#define INTMASK 0x34
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#define INTTYPE_LEVEL 0x38
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#define INT_POLARITY 0x3c
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#define INTSTATUS 0x40
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#define RAW_INTSTATUS 0x44
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#define DEBOUNCE 0x48
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#define PORTA_EOI 0x4c
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#define EXT_PORTA 0x50
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#define LS_SYNC 0x60
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#define PINS 8
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struct gpio_internal_data {
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pci_driver_t pci;
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};
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static struct gpio_internal_data data;
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static inline uint32_t
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read(uint32_t base_addr, uint32_t offset)
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{
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return *(uint32_t*)(base_addr + offset);
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}
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static inline void
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write(uint32_t base_addr, uint32_t offset, uint32_t val)
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{
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*(uint32_t*)(base_addr + offset) = val;
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}
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/* value must be 0x0 or 0x1 */
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static void
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set_bit(uint32_t base_addr, uint32_t offset, uint32_t bit, uint32_t value)
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{
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uint32_t reg;
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reg = read(base_addr, offset);
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reg &= ~BIT(bit);
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reg |= value << bit;
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write(base_addr, offset, reg);
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}
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int
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quarkX1000_gpio_config(uint8_t pin, int flags)
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{
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if (((flags & QUARKX1000_GPIO_IN) && (flags & QUARKX1000_GPIO_OUT)) ||
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((flags & QUARKX1000_GPIO_INT) && (flags & QUARKX1000_GPIO_OUT))) {
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return -1;
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}
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/* interrupts are not supported yet */
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if (flags & QUARKX1000_GPIO_INT)
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return -1;
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/* set direction */
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set_bit(data.pci.mmio, SWPORTA_DDR, pin, !!(flags & QUARKX1000_GPIO_OUT));
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/* set interrupt disabled */
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set_bit(data.pci.mmio, INTEN, pin, 0);
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return 0;
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}
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int
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quarkX1000_gpio_config_port(int flags)
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{
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uint8_t i;
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for (i = 0; i < PINS; i++) {
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if (quarkX1000_gpio_config(i, flags) < 0) {
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return -1;
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}
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}
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return 0;
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}
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int
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quarkX1000_gpio_read(uint8_t pin, uint8_t *value)
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{
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uint32_t value32 = read(data.pci.mmio, EXT_PORTA);
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*value = !!(value32 & BIT(pin));
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return 0;
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}
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int
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quarkX1000_gpio_write(uint8_t pin, uint8_t value)
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{
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set_bit(data.pci.mmio, SWPORTA_DR, pin, !!value);
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return 0;
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}
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int
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quarkX1000_gpio_read_port(uint8_t *value)
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{
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uint32_t value32 = read(data.pci.mmio, EXT_PORTA);
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*value = value32 & ~0xFFFFFF00;
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return 0;
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}
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int
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quarkX1000_gpio_write_port(uint8_t value)
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{
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write(data.pci.mmio, SWPORTA_DR, value);
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return 0;
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}
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void
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quarkX1000_gpio_clock_enable(void)
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{
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set_bit(data.pci.mmio, LS_SYNC, 0, 1);
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}
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void
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quarkX1000_gpio_clock_disable(void)
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{
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set_bit(data.pci.mmio, LS_SYNC, 0, 0);
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}
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int
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quarkX1000_gpio_init(void)
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{
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pci_config_addr_t pci_addr;
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pci_addr.raw = 0;
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pci_addr.bus = 0;
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pci_addr.dev = 21;
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pci_addr.func = 2;
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pci_addr.reg_off = PCI_CONFIG_REG_BAR1;
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pci_command_enable(pci_addr, PCI_CMD_1_MEM_SPACE_EN);
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pci_init(&data.pci, pci_addr, 0);
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quarkX1000_gpio_clock_enable();
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/* clear registers */
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write(data.pci.mmio, INTEN, 0);
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write(data.pci.mmio, INTMASK, 0);
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write(data.pci.mmio, PORTA_EOI, 0);
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return 0;
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}
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@ -0,0 +1,61 @@
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/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef CPU_X86_DRIVERS_QUARKX1000_GPIO_H_
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#define CPU_X86_DRIVERS_QUARKX1000_GPIO_H_
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#include <stdint.h>
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#include "pci.h"
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#define QUARKX1000_GPIO_IN (0 << 0)
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#define QUARKX1000_GPIO_OUT (1 << 0)
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#define QUARKX1000_GPIO_INT (1 << 1)
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#define QUARKX1000_GPIO_ACTIVE_LOW (0 << 2)
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#define QUARKX1000_GPIO_ACTIVE_HIGH (1 << 2)
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#define QUARKX1000_GPIO_LEVEL (0 << 3)
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#define QUARKX1000_GPIO_EDGE (1 << 3)
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#define QUARKX1000_GPIO_DEBOUNCE (1 << 4)
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#define QUARKX1000_GPIO_CLOCK_SYNC (1 << 5)
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int quarkX1000_gpio_init(void);
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int quarkX1000_gpio_config(uint8_t pin, int flags);
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int quarkX1000_gpio_read(uint8_t pin, uint8_t *value);
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int quarkX1000_gpio_write(uint8_t pin, uint8_t value);
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int quarkX1000_gpio_config_port(int flags);
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int quarkX1000_gpio_read_port(uint8_t *value);
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int quarkX1000_gpio_write_port(uint8_t value);
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void quarkX1000_gpio_clock_enable(void);
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void quarkX1000_gpio_clock_disable(void);
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#endif /* CPU_X86_DRIVERS_QUARKX1000_GPIO_H_ */
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