Merge pull request #1834 from mdlemay/gpio-refactor
galileo: Simplify GPIO APIs and add support for gen. 1
This commit is contained in:
Nicolas Tsiftes
GitHub
commit
61c9c21c5c
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@ -33,10 +33,11 @@
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#include "contiki.h"
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#include "sys/ctimer.h"
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#include "galileo-gpio.h"
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#include "gpio.h"
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#define PIN_OUTPUT 5
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#define PIN_INPUT 6
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#define PIN_OUTPUT 2
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#define PIN_INPUT 3
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static uint32_t value;
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static struct ctimer timer;
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@ -51,9 +52,9 @@ timeout(void *data)
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/* toggle pin state */
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value = !value;
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quarkX1000_gpio_write(PIN_OUTPUT, value);
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galileo_gpio_write(PIN_OUTPUT, value);
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quarkX1000_gpio_read(PIN_INPUT, &value_in);
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galileo_gpio_read(PIN_INPUT, &value_in);
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if (value == value_in)
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printf("GPIO pin value match!\n");
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@ -67,9 +68,6 @@ PROCESS_THREAD(gpio_input_process, ev, data)
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{
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PROCESS_BEGIN();
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quarkX1000_gpio_config(PIN_OUTPUT, QUARKX1000_GPIO_OUT);
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quarkX1000_gpio_config(PIN_INPUT, QUARKX1000_GPIO_IN);
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quarkX1000_gpio_clock_enable();
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ctimer_set(&timer, CLOCK_SECOND / 2, timeout, NULL);
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@ -33,10 +33,11 @@
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#include "contiki.h"
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#include "sys/ctimer.h"
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#include "galileo-gpio.h"
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#include "gpio.h"
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#define PIN_OUTPUT 5
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#define PIN_INTR 6
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#define PIN_OUTPUT 2
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#define PIN_INTR 3
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static struct ctimer timer;
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@ -47,8 +48,8 @@ static void
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timeout(void *data)
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{
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/* emulate an interrupt */
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quarkX1000_gpio_write(PIN_OUTPUT, 0);
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quarkX1000_gpio_write(PIN_OUTPUT, 1);
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galileo_gpio_write(PIN_OUTPUT, 0);
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galileo_gpio_write(PIN_OUTPUT, 1);
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ctimer_reset(&timer);
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}
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@ -63,8 +64,7 @@ PROCESS_THREAD(gpio_interrupt_process, ev, data)
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{
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PROCESS_BEGIN();
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quarkX1000_gpio_config(PIN_OUTPUT, QUARKX1000_GPIO_OUT);
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quarkX1000_gpio_config(PIN_INTR, QUARKX1000_GPIO_INT | QUARKX1000_GPIO_ACTIVE_HIGH | QUARKX1000_GPIO_EDGE);
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galileo_gpio_config(PIN_INTR, QUARKX1000_GPIO_INT | QUARKX1000_GPIO_ACTIVE_HIGH | QUARKX1000_GPIO_EDGE);
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quarkX1000_gpio_set_callback(callback);
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@ -33,9 +33,10 @@
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#include "contiki.h"
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#include "sys/ctimer.h"
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#include "galileo-gpio.h"
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#include "gpio.h"
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#define PIN 5 /* IO2 */
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#define PIN 2
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static uint32_t value;
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static struct ctimer timer;
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@ -48,7 +49,7 @@ timeout(void *data)
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{
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/* toggle pin state */
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value = !value;
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quarkX1000_gpio_write(PIN, value);
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galileo_gpio_write(PIN, value);
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ctimer_reset(&timer);
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}
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@ -57,8 +58,6 @@ PROCESS_THREAD(gpio_output_process, ev, data)
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{
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PROCESS_BEGIN();
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quarkX1000_gpio_config(PIN, QUARKX1000_GPIO_OUT);
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quarkX1000_gpio_clock_enable();
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ctimer_set(&timer, CLOCK_SECOND / 2, timeout, NULL);
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@ -5,7 +5,17 @@ LIBGCC_PATH = /usr/lib/gcc/$(shell gcc -dumpmachine)/$(shell gcc -dumpversion)
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CONTIKI_TARGET_DIRS = . core/sys/ drivers/ net/
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CONTIKI_TARGET_MAIN = ${addprefix $(OBJECTDIR)/,contiki-main.o}
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CONTIKI_SOURCEFILES += contiki-main.c clock.c rtimer-arch.c gpio-pcal9535a.c pwm-pca9685.c galileo-pinmux.c eth-proc.c eth-conf.c
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CONTIKI_SOURCEFILES += contiki-main.c clock.c rtimer-arch.c eth-proc.c eth-conf.c galileo-gpio.c
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GALILEO_GEN ?= 2
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CFLAGS += -DGALILEO_GEN=$(GALILEO_GEN)
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CONTIKI_SOURCEFILES += galileo-gen$(GALILEO_GEN)-pinmux.c
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ifeq ($(GALILEO_GEN),2)
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CONTIKI_SOURCEFILES += gpio-pcal9535a.c pwm-pca9685.c
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else
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CONTIKI_SOURCEFILES += cy8c9540a.c
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endif
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ifeq ($(CONTIKI_WITH_IPV6),1)
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CONTIKI_SOURCEFILES += nbr-table.c packetbuf.c linkaddr.c link-stats.c
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@ -141,6 +141,9 @@ specify X86_CONF_RESTRICT_DMA=1 as a command-line argument to the make
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command that is used to build the image. This will configure and lock
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the IMRs.
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Galileo Gen. 2 is targeted by default. Specify GALILEO_GEN=1 on the build
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command line to target first generation boards.
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Running
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-------
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@ -193,7 +196,8 @@ $ cp examples/hello-world/hello-world.galileo.efi /mnt/sdcard/efi/boot/bootia32.
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### Connect to the console output
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Connect the serial cable to your computer as shown in [2].
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Connect the serial cable to your computer as shown in [8] for first generation
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boards and [2] for second generation boards.
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Choose a terminal emulator such as PuTTY. Make sure you use the SCO keyboard
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mode (on PuTTY that option is at Terminal -> Keyboard, on the left menu).
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@ -277,3 +281,5 @@ References
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[6] https://docs.docker.com/docker-for-windows/#/shared-drives
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[7] https://docs.docker.com/engine/understanding-docker/
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[8] https://software.intel.com/en-us/articles/intel-galileo-gen-1-board-assembly-using-eclipse-and-intel-xdk-iot-edition
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@ -99,11 +99,15 @@ main(void)
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quarkX1000_i2c_init();
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quarkX1000_i2c_configure(QUARKX1000_I2C_SPEED_STANDARD,
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QUARKX1000_I2C_ADDR_MODE_7BIT);
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/* The GPIO subsystem must be initialized prior to configuring pinmux, because
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* the pinmux configuration automatically performs GPIO configuration for the
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* relevant pins.
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*/
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quarkX1000_gpio_init();
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/* use default pinmux configuration */
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if(galileo_pinmux_initialize() < 0) {
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fprintf(stderr, "Failed to initialize pinmux\n");
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}
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quarkX1000_gpio_init();
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shared_isr_init();
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/* The ability to remap interrupts is not needed after this point and should
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@ -0,0 +1,131 @@
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/*
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* Copyright (C) 2016, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cy8c9540a.h"
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#include <assert.h>
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#include "i2c.h"
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#include <stdio.h>
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/* Change this to 0x21 if J2 is set to 1-2
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* (covering the pin marked with the white triangle). */
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#define I2C_ADDR 0x20
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#define REG_PORT_SEL 0x18
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#define REG_PORT_DIR 0x1C
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#define PORT_CNT 6
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/* Cache the current state of each port to obviate the need for reading before
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* writing to output ports when simply updating a single pin.
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*/
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static uint8_t out_cache[PORT_CNT];
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/*---------------------------------------------------------------------------*/
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static void
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write_reg(uint8_t reg, uint8_t data)
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{
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uint8_t pkt[] = { reg, data };
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assert(quarkX1000_i2c_polling_write(pkt, sizeof(pkt), I2C_ADDR) == 0);
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}
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/*---------------------------------------------------------------------------*/
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static uint8_t
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read_reg(uint8_t reg)
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{
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uint8_t data;
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assert(quarkX1000_i2c_polling_write(®, 1, I2C_ADDR) == 0);
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assert(quarkX1000_i2c_polling_read(&data, 1, I2C_ADDR) == 0);
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return data;
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}
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/*---------------------------------------------------------------------------*/
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void
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cy8c9540a_init(void)
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{
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uint8_t status;
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/* has to init after I2C master */
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assert(quarkX1000_i2c_is_available());
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status = read_reg(0x2E);
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if((status >> 4) != 4) {
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fprintf(stderr, "Failed to communicate with CY8C9540A. Perhaps jumper J2 "
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"is not set to 2-3? Halting.\n");
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halt();
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}
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Set the direction (in or out) for the indicated GPIO pin.
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*/
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void
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cy8c9540a_set_port_dir(cy8c9540a_bit_addr_t addr, cy8c9540a_port_dir_t dir)
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{
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uint8_t mask;
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assert(addr.port < PORT_CNT);
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write_reg(REG_PORT_SEL, addr.port);
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mask = read_reg(REG_PORT_DIR);
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mask &= ~(1 << addr.pin);
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mask |= ((uint8_t)dir) << addr.pin;
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write_reg(REG_PORT_DIR, mask);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Set the drive mode for the indicated GPIO pin.
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*/
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void
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cy8c9540a_set_drive_mode(cy8c9540a_bit_addr_t addr,
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cy8c9540a_drive_mode_t drv_mode)
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{
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assert(addr.port < PORT_CNT);
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write_reg(REG_PORT_SEL, addr.port);
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write_reg((uint8_t)drv_mode, 1 << addr.pin);
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}
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/*---------------------------------------------------------------------------*/
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bool
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cy8c9540a_read(cy8c9540a_bit_addr_t addr)
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{
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assert(addr.port < PORT_CNT);
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return ((read_reg(addr.port) >> addr.pin) & 1) == 1;
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}
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/*---------------------------------------------------------------------------*/
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void
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cy8c9540a_write(cy8c9540a_bit_addr_t addr, bool val)
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{
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assert(addr.port < PORT_CNT);
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out_cache[addr.port] &= ~(1 << addr.pin);
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out_cache[addr.port] |= ((uint8_t)val) << addr.pin;
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write_reg(8 + addr.port, out_cache[addr.port]);
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}
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/*---------------------------------------------------------------------------*/
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@ -0,0 +1,72 @@
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/*
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* Copyright (C) 2016, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
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* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
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* OF THE POSSIBILITY OF SUCH DAMAGE.
|
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*/
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#ifndef PLATFORM_GALILEO_DRIVERS_CY8C9540A_H_
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#define PLATFORM_GALILEO_DRIVERS_CY8C9540A_H_
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#include <stdbool.h>
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#include <stdint.h>
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/* Driver for Cypress Semiconductors CY8C9540A device used for GPIO, PWM, and
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* pinmuxing on the first generation Intel Galileo.
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*/
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/* The numeric value of each drive mode corresponds to the device register
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* address for selecting that mode. Only a subset of the available modes are
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* listed here.
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*/
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typedef enum cy8c9540a_drive_mode {
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CY8C9540A_DRIVE_PULL_UP = 0x1D,
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CY8C9540A_DRIVE_PULL_DOWN = 0x1E,
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CY8C9540A_DRIVE_STRONG = 0x21,
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CY8C9540A_DRIVE_HI_Z = 0x23
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} cy8c9540a_drive_mode_t;
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typedef enum cy8c9540a_port_dir {
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CY8C9540A_PORT_DIR_OUT = 0,
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CY8C9540A_PORT_DIR_IN = 1
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} cy8c9540a_port_dir_t;
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typedef struct cy8c9540a_bit_addr {
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uint8_t port;
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int pin;
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} cy8c9540a_bit_addr_t;
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#define CY8C9540A_BIT_ADDR_INVALID_PORT 0xFF
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void cy8c9540a_init(void);
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void cy8c9540a_set_port_dir(cy8c9540a_bit_addr_t addr,
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cy8c9540a_port_dir_t dir);
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void cy8c9540a_set_drive_mode(cy8c9540a_bit_addr_t addr,
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cy8c9540a_drive_mode_t drv_mode);
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bool cy8c9540a_read(cy8c9540a_bit_addr_t addr);
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void cy8c9540a_write(cy8c9540a_bit_addr_t addr, bool val);
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#endif /* PLATFORM_GALILEO_DRIVERS_CY8C9540A_H_ */
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@ -0,0 +1,282 @@
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/*
|
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* Copyright (C) 2016, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
||||
* OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
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#include "galileo-pinmux.h"
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|
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#include <assert.h>
|
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#include "cy8c9540a.h"
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#include "gpio.h"
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#include <stdio.h>
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|
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static cy8c9540a_bit_addr_t mux_bit_addrs[] = {
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{ 3, 4 }, /* IO0 */
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{ 3, 5 }, /* IO1 */
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{ 1, 7 }, /* IO2 */
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{ 1, 6 }, /* IO3 */
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 }, /* IO4 */
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 }, /* IO5 */
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 }, /* IO6 */
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 }, /* IO7 */
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 }, /* IO8 */
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 }, /* IO9 */
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{ 3, 6 }, /* IO10 */
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{ 3, 7 }, /* IO11 */
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{ 5, 2 }, /* IO12 */
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{ 5, 3 }, /* IO13 */
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{ 3, 1 }, /* A0 */
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{ 3, 0 }, /* A1 */
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{ 0, 7 }, /* A2 */
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{ 0, 6 }, /* A3 */
|
||||
{ 0, 5 }, /* A4 (also controlled by I2C mux) */
|
||||
{ 0, 4 }, /* A5 (also controlled by I2C mux) */
|
||||
};
|
||||
|
||||
static cy8c9540a_bit_addr_t i2c_mux_bit_addr = { 1, 5 };
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
flatten_pin_num(galileo_pin_group_t grp, unsigned *pin)
|
||||
{
|
||||
if(grp == GALILEO_PIN_GRP_ANALOG) {
|
||||
*pin += GALILEO_NUM_DIGITAL_PINS;
|
||||
}
|
||||
|
||||
assert(*pin < GALILEO_NUM_PINS);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/* See galileo-gpio.c for the declaration of this function. */
|
||||
int
|
||||
galileo_brd_to_cpu_gpio_pin(unsigned pin, bool *sus)
|
||||
{
|
||||
assert(pin < GALILEO_NUM_PINS);
|
||||
*sus = false;
|
||||
switch(pin) {
|
||||
case 2:
|
||||
return 6;
|
||||
case 3:
|
||||
return 7;
|
||||
case 10:
|
||||
return 2;
|
||||
default:
|
||||
return -1; /* GPIO pin may be connected to the CY8C9540A chip, but not the
|
||||
CPU. */
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
static cy8c9540a_bit_addr_t cy8c9540a_gpio_mapping[] = {
|
||||
{ 4, 6 },
|
||||
{ 4, 7 },
|
||||
{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 },
|
||||
{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 },
|
||||
{ 1, 4 },
|
||||
{ 0, 1 },
|
||||
{ 1, 0 },
|
||||
{ 1, 3 },
|
||||
{ 1, 2 },
|
||||
{ 0, 3 },
|
||||
{ 0, 0 }, /* This driver configures IO10 to connect to CPU GPIO when setting
|
||||
IO10 to a digital mode, but hardware exists to alternately
|
||||
connect it to this pin of the CY8C9540A chip. */
|
||||
{ 1, 1 },
|
||||
{ 3, 2 },
|
||||
{ 3, 3 },
|
||||
{ 4, 0 },
|
||||
{ 4, 1 },
|
||||
{ 4, 2 },
|
||||
{ 4, 3 },
|
||||
{ 4, 4 },
|
||||
{ 4, 5 }
|
||||
};
|
||||
/* Map a board-level GPIO pin number to the address of the CY8C9540A pin that
|
||||
* implements it.
|
||||
*/
|
||||
cy8c9540a_bit_addr_t
|
||||
galileo_brd_to_cy8c9540a_gpio_pin(unsigned pin)
|
||||
{
|
||||
assert(pin < GALILEO_NUM_PINS);
|
||||
return cy8c9540a_gpio_mapping[pin];
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/* The I2C mux control must be set high to be able to access A4 and A5.
|
||||
*/
|
||||
static void
|
||||
set_i2c_mux(bool val)
|
||||
{
|
||||
cy8c9540a_write(i2c_mux_bit_addr, val);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
select_gpio_pwm(unsigned flat_pin, bool pwm)
|
||||
{
|
||||
bool mux_val;
|
||||
cy8c9540a_bit_addr_t mux_bit_addr;
|
||||
mux_bit_addr = mux_bit_addrs[flat_pin];
|
||||
if(mux_bit_addr.port != CY8C9540A_BIT_ADDR_INVALID_PORT) {
|
||||
mux_val = pwm || !(flat_pin == 2 || flat_pin == 3 || flat_pin == 10);
|
||||
cy8c9540a_write(mux_bit_addr, mux_val);
|
||||
}
|
||||
if((GALILEO_NUM_DIGITAL_PINS + 4) <= flat_pin) {
|
||||
/* This single control switches away from both I2C pins. */
|
||||
set_i2c_mux(true);
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
select_gpio(galileo_pin_group_t grp, unsigned pin, bool out)
|
||||
{
|
||||
bool sus;
|
||||
int cpu_pin;
|
||||
cy8c9540a_bit_addr_t gpio_bit_addr;
|
||||
|
||||
flatten_pin_num(grp, &pin);
|
||||
select_gpio_pwm(pin, false);
|
||||
|
||||
cpu_pin = galileo_brd_to_cpu_gpio_pin(pin, &sus);
|
||||
if(cpu_pin == -1) {
|
||||
gpio_bit_addr = galileo_brd_to_cy8c9540a_gpio_pin(pin);
|
||||
cy8c9540a_set_port_dir(gpio_bit_addr,
|
||||
out?
|
||||
CY8C9540A_PORT_DIR_OUT :
|
||||
CY8C9540A_PORT_DIR_IN);
|
||||
cy8c9540a_set_drive_mode(gpio_bit_addr,
|
||||
out?
|
||||
CY8C9540A_DRIVE_STRONG :
|
||||
CY8C9540A_DRIVE_HI_Z);
|
||||
} else {
|
||||
quarkX1000_gpio_config(cpu_pin,
|
||||
out? QUARKX1000_GPIO_OUT : QUARKX1000_GPIO_IN);
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void
|
||||
galileo_pinmux_select_din(galileo_pin_group_t grp, unsigned pin)
|
||||
{
|
||||
select_gpio(grp, pin, false);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void galileo_pinmux_select_dout(galileo_pin_group_t grp, unsigned pin)
|
||||
{
|
||||
select_gpio(grp, pin, true);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void galileo_pinmux_select_pwm(unsigned pin)
|
||||
{
|
||||
switch(pin) {
|
||||
case 3:
|
||||
case 5:
|
||||
case 6:
|
||||
case 9:
|
||||
case 10:
|
||||
case 11:
|
||||
break;
|
||||
default:
|
||||
fprintf(stderr, "%s: invalid pin: %d.\n", __FUNCTION__, pin);
|
||||
halt();
|
||||
}
|
||||
|
||||
select_gpio_pwm(pin, true);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void galileo_pinmux_select_serial(unsigned pin)
|
||||
{
|
||||
assert(pin == 0 || pin == 1);
|
||||
|
||||
cy8c9540a_write(mux_bit_addrs[pin], false);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void galileo_pinmux_select_i2c(void)
|
||||
{
|
||||
set_i2c_mux(false);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void galileo_pinmux_select_spi(void)
|
||||
{
|
||||
unsigned pin;
|
||||
for(pin = 11; pin <= 13; pin++) {
|
||||
cy8c9540a_write(mux_bit_addrs[pin], false);
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void galileo_pinmux_select_analog(unsigned pin)
|
||||
{
|
||||
assert(pin < GALILEO_NUM_ANALOG_PINS);
|
||||
pin += GALILEO_NUM_DIGITAL_PINS;
|
||||
|
||||
cy8c9540a_write(mux_bit_addrs[pin], false);
|
||||
|
||||
if(4 <= pin) {
|
||||
/* This single control switches away from both I2C pins. */
|
||||
set_i2c_mux(true);
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
int
|
||||
galileo_pinmux_initialize(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
cy8c9540a_init();
|
||||
|
||||
/* Configure all mux control pins as outputs. */
|
||||
for(i = 0; i < GALILEO_NUM_PINS; i++) {
|
||||
if(mux_bit_addrs[i].port == CY8C9540A_BIT_ADDR_INVALID_PORT) {
|
||||
continue;
|
||||
}
|
||||
|
||||
cy8c9540a_set_port_dir(mux_bit_addrs[i], CY8C9540A_PORT_DIR_OUT);
|
||||
cy8c9540a_set_drive_mode(mux_bit_addrs[i], CY8C9540A_DRIVE_STRONG);
|
||||
}
|
||||
cy8c9540a_set_port_dir(i2c_mux_bit_addr, CY8C9540A_PORT_DIR_OUT);
|
||||
cy8c9540a_set_drive_mode(i2c_mux_bit_addr, CY8C9540A_DRIVE_STRONG);
|
||||
|
||||
/* Activate default pinmux configuration. */
|
||||
galileo_pinmux_select_serial(0);
|
||||
galileo_pinmux_select_serial(1);
|
||||
galileo_pinmux_select_dout(GALILEO_PIN_GRP_DIGITAL, 2);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 3);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 4);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 5);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 6);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 7);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 8);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 9);
|
||||
galileo_pinmux_select_dout(GALILEO_PIN_GRP_DIGITAL, 10);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 11);
|
||||
galileo_pinmux_select_dout(GALILEO_PIN_GRP_DIGITAL, 12);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 13);
|
||||
galileo_pinmux_select_analog(0);
|
||||
galileo_pinmux_select_analog(1);
|
||||
galileo_pinmux_select_analog(2);
|
||||
galileo_pinmux_select_analog(3);
|
||||
galileo_pinmux_select_i2c();
|
||||
|
||||
return 0;
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
|
@ -29,10 +29,19 @@
|
|||
*/
|
||||
|
||||
#include "galileo-pinmux.h"
|
||||
#include <assert.h>
|
||||
#include "gpio.h"
|
||||
#include "gpio-pcal9535a.h"
|
||||
#include "i2c.h"
|
||||
#include "pwm-pca9685.h"
|
||||
#include <stdio.h>
|
||||
|
||||
typedef enum {
|
||||
GALILEO_PINMUX_FUNC_A,
|
||||
GALILEO_PINMUX_FUNC_B,
|
||||
GALILEO_PINMUX_FUNC_C,
|
||||
GALILEO_PINMUX_FUNC_D
|
||||
} GALILEO_PINMUX_FUNC;
|
||||
|
||||
#define GPIO_PCAL9535A_0_I2C_ADDR 0x25
|
||||
#define GPIO_PCAL9535A_1_I2C_ADDR 0x26
|
||||
|
|
@ -41,7 +50,6 @@
|
|||
|
||||
#define PINMUX_NUM_FUNCS 4
|
||||
#define PINMUX_NUM_PATHS 4
|
||||
#define PINMUX_NUM_PINS 20
|
||||
|
||||
typedef enum {
|
||||
NONE,
|
||||
|
|
@ -62,29 +70,6 @@ struct pin_config {
|
|||
GALILEO_PINMUX_FUNC func;
|
||||
};
|
||||
|
||||
static struct pin_config default_pinmux_config[PINMUX_NUM_PINS] = {
|
||||
{ 0, GALILEO_PINMUX_FUNC_C }, /* UART0_RXD */
|
||||
{ 1, GALILEO_PINMUX_FUNC_C }, /* UART0_TXD */
|
||||
{ 2, GALILEO_PINMUX_FUNC_A }, /* GPIO5(out) */
|
||||
{ 3, GALILEO_PINMUX_FUNC_B }, /* GPIO6(in) */
|
||||
{ 4, GALILEO_PINMUX_FUNC_B }, /* GPIO_SUS4 (in) */
|
||||
{ 5, GALILEO_PINMUX_FUNC_B }, /* GPIO8 (in) */
|
||||
{ 6, GALILEO_PINMUX_FUNC_B }, /* GPIO9 (in) */
|
||||
{ 7, GALILEO_PINMUX_FUNC_B }, /* EXP1.P0_6 (in) */
|
||||
{ 8, GALILEO_PINMUX_FUNC_B }, /* EXP1.P1_0 (in) */
|
||||
{ 9, GALILEO_PINMUX_FUNC_B }, /* GPIO_SUS2 (in) */
|
||||
{ 10, GALILEO_PINMUX_FUNC_A }, /* GPIO2 (out) */
|
||||
{ 11, GALILEO_PINMUX_FUNC_B }, /* GPIO_SUS3 (in) */
|
||||
{ 12, GALILEO_PINMUX_FUNC_B }, /* GPIO7 (in) */
|
||||
{ 13, GALILEO_PINMUX_FUNC_B }, /* GPIO_SUS5(in) */
|
||||
{ 14, GALILEO_PINMUX_FUNC_B }, /* EXP2.P0_0 (in)/ADC.IN0 */
|
||||
{ 15, GALILEO_PINMUX_FUNC_B }, /* EXP2.P0_2 (in)/ADC.IN1 */
|
||||
{ 16, GALILEO_PINMUX_FUNC_B }, /* EXP2.P0_4 (in)/ADC.IN2 */
|
||||
{ 17, GALILEO_PINMUX_FUNC_B }, /* EXP2.P0_6 (in)/ADC.IN3 */
|
||||
{ 18, GALILEO_PINMUX_FUNC_C }, /* I2C_SDA */
|
||||
{ 19, GALILEO_PINMUX_FUNC_C }, /* I2C_SCL */
|
||||
};
|
||||
|
||||
struct mux_pin {
|
||||
MUX_CHIP chip;
|
||||
uint8_t pin;
|
||||
|
|
@ -107,7 +92,7 @@ struct pinmux_internal_data {
|
|||
|
||||
static struct pinmux_internal_data data;
|
||||
|
||||
static struct mux_path galileo_pinmux_paths[PINMUX_NUM_PINS * PINMUX_NUM_FUNCS] = {
|
||||
static struct mux_path galileo_pinmux_paths[GALILEO_NUM_PINS * PINMUX_NUM_FUNCS] = {
|
||||
{0, GALILEO_PINMUX_FUNC_A, {
|
||||
{ EXP1, 0, PIN_HIGH, (QUARKX1000_GPIO_OUT) }, /* GPIO3 out */
|
||||
{ EXP1, 1, PIN_LOW, (QUARKX1000_GPIO_OUT) },
|
||||
|
|
@ -529,13 +514,13 @@ static struct mux_path galileo_pinmux_paths[PINMUX_NUM_PINS * PINMUX_NUM_FUNCS]
|
|||
{ NONE, 0, DISABLED, (QUARKX1000_GPIO_IN ) }}},
|
||||
};
|
||||
|
||||
int
|
||||
static int
|
||||
galileo_pinmux_set_pin(uint8_t pin, GALILEO_PINMUX_FUNC func)
|
||||
{
|
||||
struct mux_path *mux_path;
|
||||
uint8_t index, i;
|
||||
|
||||
if(pin > PINMUX_NUM_PINS) {
|
||||
if(pin >= GALILEO_NUM_PINS) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
|
@ -545,48 +530,151 @@ galileo_pinmux_set_pin(uint8_t pin, GALILEO_PINMUX_FUNC func)
|
|||
mux_path = &galileo_pinmux_paths[index];
|
||||
|
||||
for(i = 0; i < PINMUX_NUM_PATHS; i++) {
|
||||
struct gpio_pcal9535a_data *exp = NULL;
|
||||
switch(mux_path->path[i].chip) {
|
||||
case EXP0:
|
||||
if(gpio_pcal9535a_write(&data.exp0, mux_path->path[i].pin, mux_path->path[i].level) < 0) {
|
||||
return -1;
|
||||
}
|
||||
if(gpio_pcal9535a_config(&data.exp0, mux_path->path[i].pin, mux_path->path[i].cfg) < 0) {
|
||||
return -1;
|
||||
}
|
||||
exp = &data.exp0;
|
||||
break;
|
||||
case EXP1:
|
||||
if(gpio_pcal9535a_write(&data.exp1, mux_path->path[i].pin, mux_path->path[i].level) < 0) {
|
||||
return -1;
|
||||
}
|
||||
if(gpio_pcal9535a_config(&data.exp1, mux_path->path[i].pin, mux_path->path[i].cfg) < 0) {
|
||||
return -1;
|
||||
}
|
||||
exp = &data.exp1;
|
||||
break;
|
||||
case EXP2:
|
||||
if(gpio_pcal9535a_write(&data.exp2, mux_path->path[i].pin, mux_path->path[i].level) < 0) {
|
||||
return -1;
|
||||
}
|
||||
if(gpio_pcal9535a_config(&data.exp2, mux_path->path[i].pin, mux_path->path[i].cfg) < 0) {
|
||||
return -1;
|
||||
}
|
||||
exp = &data.exp2;
|
||||
break;
|
||||
case PWM0:
|
||||
if(pwm_pca9685_set_duty_cycle(&data.pwm0, mux_path->path[i].pin, mux_path->path[i].level ? 100 : 0) < 0) {
|
||||
return -1;
|
||||
}
|
||||
break;
|
||||
continue;
|
||||
case NONE:
|
||||
break;
|
||||
continue;
|
||||
}
|
||||
|
||||
assert(exp != NULL);
|
||||
|
||||
if(gpio_pcal9535a_write(exp, mux_path->path[i].pin, mux_path->path[i].level) < 0) {
|
||||
return -1;
|
||||
}
|
||||
if(gpio_pcal9535a_config(exp, mux_path->path[i].pin, mux_path->path[i].cfg) < 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
static void
|
||||
flatten_pin_num(galileo_pin_group_t grp, unsigned *pin)
|
||||
{
|
||||
if(grp == GALILEO_PIN_GRP_ANALOG) {
|
||||
*pin += GALILEO_NUM_DIGITAL_PINS;
|
||||
}
|
||||
|
||||
assert(*pin < GALILEO_NUM_PINS);
|
||||
}
|
||||
/* See galileo-gpio.c for the declaration of this function. */
|
||||
int
|
||||
galileo_brd_to_cpu_gpio_pin(unsigned pin, bool *sus)
|
||||
{
|
||||
static const int SUS = 0x100;
|
||||
unsigned pins[GALILEO_NUM_PINS] = {
|
||||
3, 4, 5, 6,
|
||||
SUS | 4, 8, 9, SUS | 0,
|
||||
SUS | 1, SUS | 2, 2, SUS | 3,
|
||||
7, SUS | 5
|
||||
};
|
||||
int cpu_pin;
|
||||
|
||||
/* GPIOs in the analog pin space are implemented by EXP2, not the CPU. */
|
||||
assert(pin < GALILEO_NUM_DIGITAL_PINS);
|
||||
cpu_pin = pins[pin];
|
||||
|
||||
*sus = (cpu_pin & SUS) == SUS;
|
||||
|
||||
return cpu_pin & ~SUS;
|
||||
}
|
||||
void
|
||||
galileo_pinmux_select_din(galileo_pin_group_t grp, unsigned pin)
|
||||
{
|
||||
bool sus;
|
||||
int cpu_pin;
|
||||
|
||||
flatten_pin_num(grp, &pin);
|
||||
|
||||
assert(galileo_pinmux_set_pin(pin, GALILEO_PINMUX_FUNC_B) == 0);
|
||||
|
||||
cpu_pin = galileo_brd_to_cpu_gpio_pin(pin, &sus);
|
||||
/* GPIO_SUS pins are currently unsupported. */
|
||||
assert(!sus);
|
||||
quarkX1000_gpio_config(cpu_pin, QUARKX1000_GPIO_IN);
|
||||
}
|
||||
void
|
||||
galileo_pinmux_select_dout(galileo_pin_group_t grp, unsigned pin)
|
||||
{
|
||||
bool sus;
|
||||
int cpu_pin;
|
||||
|
||||
flatten_pin_num(grp, &pin);
|
||||
|
||||
assert(galileo_pinmux_set_pin(pin, GALILEO_PINMUX_FUNC_A) == 0);
|
||||
|
||||
cpu_pin = galileo_brd_to_cpu_gpio_pin(pin, &sus);
|
||||
/* GPIO_SUS pins are currently unsupported. */
|
||||
assert(!sus);
|
||||
quarkX1000_gpio_config(cpu_pin, QUARKX1000_GPIO_OUT);
|
||||
}
|
||||
void
|
||||
galileo_pinmux_select_pwm(unsigned pin)
|
||||
{
|
||||
GALILEO_PINMUX_FUNC func = GALILEO_PINMUX_FUNC_C;
|
||||
switch(pin) {
|
||||
case 3:
|
||||
func = GALILEO_PINMUX_FUNC_D;
|
||||
break;
|
||||
case 5:
|
||||
case 6:
|
||||
case 9:
|
||||
case 10:
|
||||
case 11:
|
||||
break;
|
||||
default:
|
||||
fprintf(stderr, "%s: invalid pin: %d.\n", __FUNCTION__, pin);
|
||||
halt();
|
||||
}
|
||||
|
||||
assert(galileo_pinmux_set_pin(pin, func) == 0);
|
||||
}
|
||||
void
|
||||
galileo_pinmux_select_serial(unsigned pin)
|
||||
{
|
||||
assert(pin < 4);
|
||||
|
||||
assert(galileo_pinmux_set_pin(pin, GALILEO_PINMUX_FUNC_C) == 0);
|
||||
}
|
||||
void
|
||||
galileo_pinmux_select_i2c(void)
|
||||
{
|
||||
assert(galileo_pinmux_set_pin(18, GALILEO_PINMUX_FUNC_C) == 0);
|
||||
assert(galileo_pinmux_set_pin(19, GALILEO_PINMUX_FUNC_C) == 0);
|
||||
}
|
||||
void
|
||||
galileo_pinmux_select_spi(void)
|
||||
{
|
||||
assert(galileo_pinmux_set_pin(11, GALILEO_PINMUX_FUNC_D) == 0);
|
||||
assert(galileo_pinmux_set_pin(12, GALILEO_PINMUX_FUNC_C) == 0);
|
||||
assert(galileo_pinmux_set_pin(13, GALILEO_PINMUX_FUNC_C) == 0);
|
||||
}
|
||||
void
|
||||
galileo_pinmux_select_analog(unsigned pin)
|
||||
{
|
||||
assert(pin < GALILEO_NUM_ANALOG_PINS);
|
||||
|
||||
pin += GALILEO_NUM_DIGITAL_PINS;
|
||||
|
||||
assert(galileo_pinmux_set_pin(pin, GALILEO_PINMUX_FUNC_B) == 0);
|
||||
}
|
||||
int
|
||||
galileo_pinmux_initialize(void)
|
||||
{
|
||||
uint8_t i;
|
||||
|
||||
/* has to init after I2C master */
|
||||
if(!quarkX1000_i2c_is_available()) {
|
||||
return -1;
|
||||
|
|
@ -608,11 +696,29 @@ galileo_pinmux_initialize(void)
|
|||
return -1;
|
||||
}
|
||||
|
||||
for(i = 0; i < PINMUX_NUM_PINS; i++) {
|
||||
if(galileo_pinmux_set_pin(default_pinmux_config[i].pin_num, default_pinmux_config[i].func) < 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
/* Activate default pinmux configuration. */
|
||||
/* Some of the following lines are commented out due to the GPIO_SUS pins
|
||||
* being currently unsupported.
|
||||
*/
|
||||
galileo_pinmux_select_serial(0);
|
||||
galileo_pinmux_select_serial(1);
|
||||
galileo_pinmux_select_dout(GALILEO_PIN_GRP_DIGITAL, 2);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 3);
|
||||
/*galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 4);*/
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 5);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 6);
|
||||
/*galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 7);*/
|
||||
/*galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 8);*/
|
||||
/*galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 9);*/
|
||||
galileo_pinmux_select_dout(GALILEO_PIN_GRP_DIGITAL, 10);
|
||||
/*galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 11);*/
|
||||
galileo_pinmux_select_dout(GALILEO_PIN_GRP_DIGITAL, 12);
|
||||
/*galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 13);*/
|
||||
galileo_pinmux_select_analog(0);
|
||||
galileo_pinmux_select_analog(1);
|
||||
galileo_pinmux_select_analog(2);
|
||||
galileo_pinmux_select_analog(3);
|
||||
galileo_pinmux_select_i2c();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* Copyright (C) 2016, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
||||
* OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "galileo-gpio.h"
|
||||
#include <assert.h>
|
||||
#include "gpio.h"
|
||||
#if GALILEO_GEN == 1
|
||||
#include "cy8c9540a.h"
|
||||
#endif
|
||||
|
||||
/* Must be implemented in board-specific pinmux file to map a board-level GPIO
|
||||
* pin number to the corresponding CPU GPIO pin number.
|
||||
*
|
||||
* For gen. 1 boards, the value -1 may be returned to indicate that the
|
||||
* specified GPIO pin is not connected to any CPU pin. For gen. 2 boards, the
|
||||
* return value should always be a positive number. An assertion within the
|
||||
* function should check the validity of the pin number.
|
||||
*/
|
||||
int galileo_brd_to_cpu_gpio_pin(unsigned pin, bool *sus);
|
||||
#if GALILEO_GEN == 1
|
||||
cy8c9540a_bit_addr_t galileo_brd_to_cy8c9540a_gpio_pin(unsigned pin);
|
||||
#endif
|
||||
|
||||
static int
|
||||
brd_to_cpu_pin(unsigned pin)
|
||||
{
|
||||
int cpu_pin;
|
||||
bool sus;
|
||||
|
||||
cpu_pin = galileo_brd_to_cpu_gpio_pin(pin, &sus);
|
||||
assert(!sus);
|
||||
|
||||
return cpu_pin;
|
||||
}
|
||||
|
||||
void galileo_gpio_config(uint8_t pin, int flags)
|
||||
{
|
||||
assert(quarkX1000_gpio_config(brd_to_cpu_pin(pin), flags) == 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Read from GPIO.
|
||||
* \param pin Board-level IO pin number.
|
||||
*/
|
||||
void galileo_gpio_read(uint8_t pin, uint8_t *value)
|
||||
{
|
||||
#if GALILEO_GEN == 1
|
||||
cy8c9540a_bit_addr_t bit_addr;
|
||||
#endif
|
||||
int cpu_pin = brd_to_cpu_pin(pin);
|
||||
#if GALILEO_GEN == 1
|
||||
if(cpu_pin == -1) {
|
||||
bit_addr = galileo_brd_to_cy8c9540a_gpio_pin(pin);
|
||||
*value = cy8c9540a_read(bit_addr);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
assert(quarkX1000_gpio_read(cpu_pin, value) == 0);
|
||||
}
|
||||
|
||||
void galileo_gpio_write(uint8_t pin, uint8_t value)
|
||||
{
|
||||
#if GALILEO_GEN == 1
|
||||
cy8c9540a_bit_addr_t bit_addr;
|
||||
#endif
|
||||
int cpu_pin = brd_to_cpu_pin(pin);
|
||||
#if GALILEO_GEN == 1
|
||||
if(cpu_pin == -1) {
|
||||
bit_addr = galileo_brd_to_cy8c9540a_gpio_pin(pin);
|
||||
cy8c9540a_write(bit_addr, value);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
assert(quarkX1000_gpio_write(cpu_pin, value) == 0);
|
||||
}
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright (C) 2016, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
||||
* OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_GALILEO_DRIVERS_GALILEO_GPIO_H_
|
||||
#define PLATFORM_GALILEO_DRIVERS_GALILEO_GPIO_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
void galileo_gpio_config(uint8_t pin, int flags);
|
||||
void galileo_gpio_read(uint8_t pin, uint8_t *value);
|
||||
void galileo_gpio_write(uint8_t pin, uint8_t value);
|
||||
|
||||
#endif /* PLATFORM_GALILEO_DRIVERS_GALILEO_GPIO_H_ */
|
||||
|
|
@ -33,14 +33,51 @@
|
|||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef enum {
|
||||
GALILEO_PINMUX_FUNC_A,
|
||||
GALILEO_PINMUX_FUNC_B,
|
||||
GALILEO_PINMUX_FUNC_C,
|
||||
GALILEO_PINMUX_FUNC_D
|
||||
} GALILEO_PINMUX_FUNC;
|
||||
typedef enum galileo_pin_group {
|
||||
GALILEO_PIN_GRP_ANALOG,
|
||||
GALILEO_PIN_GRP_DIGITAL
|
||||
} galileo_pin_group_t;
|
||||
|
||||
#define GALILEO_NUM_ANALOG_PINS 6
|
||||
#define GALILEO_NUM_DIGITAL_PINS 14
|
||||
#define GALILEO_NUM_PINS (GALILEO_NUM_ANALOG_PINS + GALILEO_NUM_DIGITAL_PINS)
|
||||
|
||||
int galileo_pinmux_initialize(void);
|
||||
int galileo_pinmux_set_pin(uint8_t pin, GALILEO_PINMUX_FUNC func);
|
||||
|
||||
/**
|
||||
* \brief Set the indicated pin to be a digital input.
|
||||
* \param grp Indicates whether the pin is in the analog or digital group.
|
||||
* \param pin Index of pin within group.
|
||||
*/
|
||||
void galileo_pinmux_select_din(galileo_pin_group_t grp, unsigned pin);
|
||||
/**
|
||||
* \brief Set the indicated pin to be a digital output.
|
||||
*/
|
||||
void galileo_pinmux_select_dout(galileo_pin_group_t grp, unsigned pin);
|
||||
/**
|
||||
* \brief Set the indicated pin to be a PWM pin. Only a subset of the pins
|
||||
* support PWM output. This implicitly operates on the digital pin
|
||||
* group.
|
||||
*/
|
||||
void galileo_pinmux_select_pwm(unsigned pin);
|
||||
/**
|
||||
* \brief Connect the indicated pin to a serial port. This implicitly operates
|
||||
* on the digital pin group. Galileo Gen. 2 supports UART0 on pins 0 and
|
||||
* 1 and UART1 on pins 2 and 3.
|
||||
*/
|
||||
void galileo_pinmux_select_serial(unsigned pin);
|
||||
/**
|
||||
* \brief Connect analog pins 4 (SDA) and 5 (SCL) to I2C.
|
||||
*/
|
||||
void galileo_pinmux_select_i2c(void);
|
||||
/**
|
||||
* \brief Connect digital pins 11 (MOSI), 12 (MISO), and 13 (CLK) to SPI.
|
||||
*/
|
||||
void galileo_pinmux_select_spi(void);
|
||||
/**
|
||||
* \brief Set the indicated pin to be an ADC input. This implicitly operates
|
||||
* on the analog pin group.
|
||||
*/
|
||||
void galileo_pinmux_select_analog(unsigned pin);
|
||||
|
||||
#endif /* CPU_X86_DRIVERS_GALILEO_PINMUX_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue