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Remove all instances of ti_lib_rom_ macros

This commit is contained in:
George Oikonomou 2018-10-02 23:07:24 +01:00
parent ec5c391d06
commit 8e990819a8
9 changed files with 30 additions and 58 deletions
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10
arch/cpu/cc26xx-cc13xx/dev/gpio-hal-arch.c
View File

@ -53,11 +53,7 @@ gpio_hal_arch_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg)
gpio_hal_pin_cfg_t tmp;
/* Clear settings that we are about to change, keep everything else */
#ifdef ThisLibraryIsFor_CC26x0R2_HaltIfViolated
config = ti_lib_ioc_port_configure_get(pin);
#else
config = ti_lib_rom_ioc_port_configure_get(pin);
#endif
config &= ~CONFIG_MASK;
tmp = cfg & GPIO_HAL_PIN_CFG_EDGE_BOTH;
@ -87,7 +83,7 @@ gpio_hal_arch_pin_cfg_set(gpio_hal_pin_t pin, gpio_hal_pin_cfg_t cfg)
config |= IOC_INT_ENABLE;
}
ti_lib_rom_ioc_port_configure_set(pin, IOC_PORT_GPIO, config);
ti_lib_ioc_port_configure_set(pin, IOC_PORT_GPIO, config);
}
/*---------------------------------------------------------------------------*/
gpio_hal_pin_cfg_t
@ -98,11 +94,7 @@ gpio_hal_arch_pin_cfg_get(gpio_hal_pin_t pin)
uint32_t config;
cfg = 0;
#ifdef ThisLibraryIsFor_CC26x0R2_HaltIfViolated
config = ti_lib_ioc_port_configure_get(pin);
#else
config = ti_lib_rom_ioc_port_configure_get(pin);
#endif
/* Pull */
tmp = config & IOC_IOPULL_M;

11
arch/cpu/cc26xx-cc13xx/dev/gpio-hal-arch.h
View File

@ -57,15 +57,10 @@
#define gpio_hal_arch_interrupt_enable(p) interrupt_enable(p)
#ifdef ThisLibraryIsFor_CC26x0R2_HaltIfViolated
#define gpio_hal_arch_interrupt_disable(p) ti_lib_ioc_int_disable(p)
#define gpio_hal_arch_pin_set_input(p) ti_lib_ioc_pin_type_gpio_input(p)
#define gpio_hal_arch_pin_set_output(p) ti_lib_ioc_pin_type_gpio_output(p)
#else
#define gpio_hal_arch_interrupt_disable(p) ti_lib_rom_ioc_int_disable(p)
#define gpio_hal_arch_pin_set_input(p) ti_lib_rom_ioc_pin_type_gpio_input(p)
#define gpio_hal_arch_pin_set_output(p) ti_lib_rom_ioc_pin_type_gpio_output(p)
#endif
#define gpio_hal_arch_set_pin(p) ti_lib_gpio_set_dio(p)
#define gpio_hal_arch_clear_pin(p) ti_lib_gpio_clear_dio(p)
#define gpio_hal_arch_toggle_pin(p) ti_lib_gpio_toggle_dio(p)
@ -80,11 +75,7 @@ static inline void
interrupt_enable(gpio_hal_pin_t pin)
{
ti_lib_gpio_clear_event_dio(pin);
#ifndef ThisLibraryIsFor_CC26x0R2_HaltIfViolated
ti_lib_rom_ioc_int_enable(pin);
#else
ti_lib_ioc_int_enable(pin);
#endif
}
/*---------------------------------------------------------------------------*/
#endif /* GPIO_HAL_ARCH_H_ */

2
arch/cpu/cc26xx-cc13xx/dev/soc-rtc.c
View File

@ -99,7 +99,7 @@ soc_rtc_init(void)
ti_lib_aon_rtc_channel_enable(AON_RTC_CH1);
ti_lib_aon_rtc_enable();
ti_lib_rom_int_enable(INT_AON_RTC_COMB);
ti_lib_int_enable(INT_AON_RTC_COMB);
/* Re-enable interrupts */
if(!interrupts_disabled) {

18
arch/cpu/cc26xx-cc13xx/dev/soc-trng.c
View File

@ -71,7 +71,7 @@ static void
disable_number_ready_interrupt(void)
{
ti_lib_trng_int_disable(TRNG_NUMBER_READY);
ti_lib_rom_int_disable(INT_TRNG_IRQ);
ti_lib_int_disable(INT_TRNG_IRQ);
}
/*---------------------------------------------------------------------------*/
static void
@ -79,14 +79,14 @@ enable_number_ready_interrupt(void)
{
ti_lib_trng_int_clear(TRNG_NUMBER_READY);
ti_lib_trng_int_enable(TRNG_NUMBER_READY);
ti_lib_rom_int_enable(INT_TRNG_IRQ);
ti_lib_int_enable(INT_TRNG_IRQ);
}
/*---------------------------------------------------------------------------*/
static bool
accessible(void)
{
/* First, check the PD */
if(ti_lib_rom_prcm_power_domain_status(PRCM_DOMAIN_PERIPH)
if(ti_lib_prcm_power_domain_status(PRCM_DOMAIN_PERIPH)
!= PRCM_DOMAIN_POWER_ON) {
return false;
}
@ -104,12 +104,12 @@ static void
power_up(void)
{
/* First, make sure the PERIPH PD is on */
ti_lib_rom_prcm_power_domain_on(PRCM_DOMAIN_PERIPH);
while((ti_lib_rom_prcm_power_domain_status(PRCM_DOMAIN_PERIPH)
ti_lib_prcm_power_domain_on(PRCM_DOMAIN_PERIPH);
while((ti_lib_prcm_power_domain_status(PRCM_DOMAIN_PERIPH)
!= PRCM_DOMAIN_POWER_ON));
/* Enable clock in active mode */
ti_lib_rom_prcm_peripheral_run_enable(PRCM_PERIPH_TRNG);
ti_lib_prcm_peripheral_run_enable(PRCM_PERIPH_TRNG);
ti_lib_prcm_load_set();
while(!ti_lib_prcm_load_get());
}
@ -136,7 +136,7 @@ static uint64_t
read_number(void)
{
uint64_t ran = (uint64_t)HWREG(TRNG_BASE + TRNG_O_OUT1) << 32;
ran += ti_lib_rom_trng_number_get(TRNG_LOW_WORD);
ran += ti_lib_trng_number_get(TRNG_LOW_WORD);
return ran;
}
@ -237,7 +237,7 @@ soc_trng_rand_asynchronous(uint32_t samples, soc_trng_callback_t cb)
ti_lib_trng_int_clear(TRNG_NUMBER_READY);
/* Enable clock in sleep mode and register with LPM */
ti_lib_rom_prcm_peripheral_sleep_enable(PRCM_PERIPH_TRNG);
ti_lib_prcm_peripheral_sleep_enable(PRCM_PERIPH_TRNG);
ti_lib_prcm_load_set();
while(!ti_lib_prcm_load_get());
@ -271,7 +271,7 @@ PROCESS_THREAD(soc_trng_process, ev, data)
}
/* Disable clock in sleep mode */
ti_lib_rom_prcm_peripheral_sleep_disable(PRCM_PERIPH_TRNG);
ti_lib_prcm_peripheral_sleep_disable(PRCM_PERIPH_TRNG);
ti_lib_prcm_load_set();
while(!ti_lib_prcm_load_get());

31
arch/cpu/cc26xx-cc13xx/dev/spi-arch.c
View File

@ -123,7 +123,7 @@ spi_arch_lock_and_open(const spi_device_t *dev)
!= PRCM_DOMAIN_POWER_ON)) ;
/* Enable clock in active mode */
ti_lib_rom_prcm_peripheral_run_enable(spi_controller[dev->spi_controller].prcm_periph);
ti_lib_prcm_peripheral_run_enable(spi_controller[dev->spi_controller].prcm_periph);
ti_lib_prcm_load_set();
while(!ti_lib_prcm_load_get()) ;
@ -131,17 +131,14 @@ spi_arch_lock_and_open(const spi_device_t *dev)
ti_lib_ssi_int_disable(spi_controller[dev->spi_controller].ssi_base, SSI_RXOR | SSI_RXFF | SSI_RXTO | SSI_TXFF);
ti_lib_ssi_int_clear(spi_controller[dev->spi_controller].ssi_base, SSI_RXOR | SSI_RXTO);
#ifdef ThisLibraryIsFor_CC26x0R2_HaltIfViolated
ti_lib_ssi_config_set_exp_clk(spi_controller[dev->spi_controller].ssi_base, ti_lib_sys_ctrl_clock_get(),
get_mode(dev), SSI_MODE_MASTER, dev->spi_bit_rate, 8);
ti_lib_ioc_pin_type_ssi_master(spi_controller[dev->spi_controller].ssi_base, dev->pin_spi_miso,
dev->pin_spi_mosi, IOID_UNUSED, dev->pin_spi_sck);
#else
ti_lib_rom_ssi_config_set_exp_clk(spi_controller[dev->spi_controller].ssi_base, ti_lib_sys_ctrl_clock_get(),
get_mode(dev), SSI_MODE_MASTER, dev->spi_bit_rate, 8);
ti_lib_rom_ioc_pin_type_ssi_master(spi_controller[dev->spi_controller].ssi_base, dev->pin_spi_miso,
dev->pin_spi_mosi, IOID_UNUSED, dev->pin_spi_sck);
#endif
ti_lib_ssi_config_set_exp_clk(spi_controller[dev->spi_controller].ssi_base,
ti_lib_sys_ctrl_clock_get(),
get_mode(dev), SSI_MODE_MASTER,
dev->spi_bit_rate, 8);
ti_lib_ioc_pin_type_ssi_master(spi_controller[dev->spi_controller].ssi_base,
dev->pin_spi_miso,
dev->pin_spi_mosi, IOID_UNUSED,
dev->pin_spi_sck);
ti_lib_ssi_enable(spi_controller[dev->spi_controller].ssi_base);
@ -159,7 +156,7 @@ spi_arch_close_and_unlock(const spi_device_t *dev)
}
/* Power down SSI */
ti_lib_rom_prcm_peripheral_run_disable(spi_controller[dev->spi_controller].prcm_periph);
ti_lib_prcm_peripheral_run_disable(spi_controller[dev->spi_controller].prcm_periph);
ti_lib_prcm_load_set();
while(!ti_lib_prcm_load_get()) ;
@ -213,20 +210,12 @@ spi_arch_transfer(const spi_device_t *dev,
for(i = 0; i < totlen; i++) {
c = i < wlen ? write_buf[i] : 0;
ti_lib_ssi_data_put(spi_controller[dev->spi_controller].ssi_base, (uint8_t)c);
#ifdef ThisLibraryIsFor_CC26x0R2_HaltIfViolated
ti_lib_ssi_data_get(spi_controller[dev->spi_controller].ssi_base, &c);
#else
ti_lib_rom_ssi_data_get(spi_controller[dev->spi_controller].ssi_base, &c);
#endif
if(i < rlen) {
inbuf[i] = (uint8_t)c;
}
}
#ifdef ThisLibraryIsFor_CC26x0R2_HaltIfViolated
while(ti_lib_ssi_data_get_non_blocking(spi_controller[dev->spi_controller].ssi_base, &c)) ;
#else
while(ti_lib_rom_ssi_data_get_non_blocking(spi_controller[dev->spi_controller].ssi_base, &c)) ;
#endif
return SPI_DEV_STATUS_OK;
}
/*---------------------------------------------------------------------------*/

4
arch/platform/srf06-cc26xx/launchpad/cc1350/rf-switch.c
View File

@ -63,9 +63,9 @@ LPM_MODULE(rf_switch_module, NULL, shutdown_handler, NULL, LPM_DOMAIN_NONE);
void
rf_switch_init()
{
ti_lib_rom_ioc_pin_type_gpio_output(POWER_PIN);
ti_lib_ioc_pin_type_gpio_output(POWER_PIN);
ti_lib_gpio_clear_dio(POWER_PIN);
ti_lib_rom_ioc_pin_type_gpio_output(SELECT_PIN);
ti_lib_ioc_pin_type_gpio_output(SELECT_PIN);
ti_lib_gpio_clear_dio(SELECT_PIN);
lpm_register_module(&rf_switch_module);

2
arch/platform/srf06-cc26xx/platform.c
View File

@ -162,7 +162,7 @@ platform_init_stage_one()
ti_lib_pwr_ctrl_io_freeze_disable();
#endif
ti_lib_rom_int_enable(INT_AON_GPIO_EDGE);
ti_lib_int_enable(INT_AON_GPIO_EDGE);
ti_lib_int_master_enable();
soc_rtc_init();

4
arch/platform/srf06-cc26xx/sensortag/mpu-9250-sensor.c
View File

@ -601,11 +601,11 @@ configure(int type, int enable)
{
switch(type) {
case SENSORS_HW_INIT:
ti_lib_rom_ioc_pin_type_gpio_input(BOARD_IOID_MPU_INT);
ti_lib_ioc_pin_type_gpio_input(BOARD_IOID_MPU_INT);
ti_lib_ioc_io_port_pull_set(BOARD_IOID_MPU_INT, IOC_IOPULL_DOWN);
ti_lib_ioc_io_hyst_set(BOARD_IOID_MPU_INT, IOC_HYST_ENABLE);
ti_lib_rom_ioc_pin_type_gpio_output(BOARD_IOID_MPU_POWER);
ti_lib_ioc_pin_type_gpio_output(BOARD_IOID_MPU_POWER);
ti_lib_ioc_io_drv_strength_set(BOARD_IOID_MPU_POWER, IOC_CURRENT_4MA,
IOC_STRENGTH_MAX);
ti_lib_gpio_clear_dio(BOARD_IOID_MPU_POWER);

6
arch/platform/srf06-cc26xx/srf06/als-sensor.c
View File

@ -59,10 +59,10 @@ config(int type, int enable)
ti_lib_ioc_pin_type_gpio_output(BOARD_IOID_ALS_PWR);
break;
case SENSORS_ACTIVE:
ti_lib_rom_ioc_pin_type_gpio_output(BOARD_IOID_ALS_PWR);
ti_lib_rom_ioc_port_configure_set(BOARD_IOID_ALS_OUT, IOC_PORT_GPIO,
ti_lib_ioc_pin_type_gpio_output(BOARD_IOID_ALS_PWR);
ti_lib_ioc_port_configure_set(BOARD_IOID_ALS_OUT, IOC_PORT_GPIO,
IOC_STD_OUTPUT);
ti_lib_rom_ioc_pin_type_gpio_input(BOARD_IOID_ALS_OUT);
ti_lib_ioc_pin_type_gpio_input(BOARD_IOID_ALS_OUT);
if(enable) {
ti_lib_gpio_set_dio(BOARD_IOID_ALS_PWR);