cc2538: gpio: Add pin read / write and interrupt clear macros
Introduce new useful GPIO macros to: - read the levels of some port pins, - write the levels of some port pins (pass bit-field value to be set), - clear the interrupt flags for some port pins. These macros are cleaner and less error prone than raw register access code copied all over the place. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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@ -114,6 +114,20 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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#define GPIO_CLR_PIN(PORT_BASE, PIN_MASK) \
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do { REG(((PORT_BASE) | GPIO_DATA) + ((PIN_MASK) << 2)) = 0x00; } while(0)
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/** \brief Set pins with PIN_MASK of port with PORT_BASE to value.
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* \param PORT_BASE GPIO Port register offset
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_WRITE_PIN(PORT_BASE, PIN_MASK, value) \
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do { REG(((PORT_BASE) | GPIO_DATA) + ((PIN_MASK) << 2)) = (value); } while(0)
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/** \brief Read pins with PIN_MASK of port with PORT_BASE.
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* \param PORT_BASE GPIO Port register offset
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_READ_PIN(PORT_BASE, PIN_MASK) \
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REG(((PORT_BASE) | GPIO_DATA) + ((PIN_MASK) << 2))
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/** \brief Set pins with PIN_MASK of port with PORT_BASE to detect edge.
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* \param PORT_BASE GPIO Port register offset
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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@ -176,6 +190,14 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
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#define GPIO_DISABLE_INTERRUPT(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_IE) &= ~(PIN_MASK); } while(0)
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/** \brief Clear interrupt triggering for pins with PIN_MASK of port with
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* PORT_BASE.
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* \param PORT_BASE GPIO Port register offset
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* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
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*/
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#define GPIO_CLEAR_INTERRUPT(PORT_BASE, PIN_MASK) \
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do { REG((PORT_BASE) | GPIO_IC) = (PIN_MASK); } while(0)
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/** \brief Configure the pin to be under peripheral control with PIN_MASK of
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* port with PORT_BASE.
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* \param PORT_BASE GPIO Port register offset
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