TSCH: move 10ms and 15ms timeslot timings to separate files
This commit is contained in:
parent
b5e12154c4
commit
cc0c70c1b3
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Copyright (c) 2018, RISE SICS.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the Institute nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the Contiki operating system.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* \file
|
||||
* IEEE 802.15.4 TSCH timeslot timings for 15ms slots
|
||||
* \author
|
||||
* Simon Duquennoy <simon.duquennoy@ri.se>
|
||||
*
|
||||
*/
|
||||
|
||||
#include "contiki.h"
|
||||
#include "net/mac/tsch/tsch.h"
|
||||
|
||||
/**
|
||||
* \brief 15ms TSCH timeslot timings, required for cc2420 platforms as
|
||||
* they are unable to keep up with the defulat 10ms timeslots.
|
||||
*/
|
||||
uint16_t tsch_timeslot_timing_us_15000[tsch_ts_elements_count] = {
|
||||
1800, /* CCAOffset */
|
||||
128, /* CCA */
|
||||
4000, /* TxOffset */
|
||||
(4000 - (TSCH_CONF_RX_WAIT / 2)), /* RxOffset */
|
||||
3600, /* RxAckDelay */
|
||||
4000, /* TxAckDelay */
|
||||
TSCH_CONF_RX_WAIT, /* RxWait */
|
||||
800, /* AckWait */
|
||||
2072, /* RxTx */
|
||||
2400, /* MaxAck */
|
||||
4256, /* MaxTx */
|
||||
15000, /* TimeslotLength */
|
||||
};
|
|
@ -17,7 +17,9 @@
|
|||
#define NETSTACK_CONF_RADIO cc2420_driver
|
||||
#endif /* NETSTACK_CONF_RADIO */
|
||||
|
||||
/* TSCH 15ms timeslot timing template, required for cc2420 */
|
||||
extern uint16_t tsch_timeslot_timing_us_15000[];
|
||||
|
||||
/* The TSCH default slot length of 10ms is a bit too short for this platform,
|
||||
* use 15ms instead. */
|
||||
#ifndef TSCH_CONF_DEFAULT_TIMESLOT_TIMING
|
||||
|
|
|
@ -64,22 +64,6 @@ extern int msp430_dco_required;
|
|||
#include "experiment-setup.h"
|
||||
#endif
|
||||
|
||||
/* TSCH timeslot timing for platforms requiring 15ms slots */
|
||||
uint16_t tsch_timeslot_timing_us_15000[tsch_ts_elements_count] = {
|
||||
1800, /* CCAOffset */
|
||||
128, /* CCA */
|
||||
4000, /* TxOffset */
|
||||
(4000 - (TSCH_CONF_RX_WAIT / 2)), /* RxOffset */
|
||||
3600, /* RxAckDelay */
|
||||
4000, /* TxAckDelay */
|
||||
TSCH_CONF_RX_WAIT, /* RxWait */
|
||||
800, /* AckWait */
|
||||
2072, /* RxTx */
|
||||
2400, /* MaxAck */
|
||||
4256, /* MaxTx */
|
||||
15000, /* TimeslotLength */
|
||||
};
|
||||
|
||||
void init_platform(void);
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/* Log configuration */
|
||||
|
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright (c) 2018, RISE SICS.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the Institute nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the Contiki operating system.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* \file
|
||||
* IEEE 802.15.4 TSCH timeslot timings
|
||||
* \author
|
||||
* Simon Duquennoy <simon.duquennoy@ri.se>
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* \addtogroup tsch
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "contiki.h"
|
||||
#include "net/mac/tsch/tsch.h"
|
||||
|
||||
/**
|
||||
* \brief The default timeslot timing in the standard is a guard time of
|
||||
* 2200 us, a Tx offset of 2120 us and a Rx offset of 1120 us.
|
||||
* As a result, the listening device has a guard time not centered
|
||||
* on the expected Tx time. This is to be fixed in the next iteration
|
||||
* of the standard. This can be enabled with:
|
||||
* TxOffset: 2120
|
||||
* RxOffset: 1120
|
||||
* RxWait: 2200
|
||||
*
|
||||
* Instead, we align the Rx guard time on expected Tx time. The Rx
|
||||
* guard time is user-configurable with TSCH_CONF_RX_WAIT.
|
||||
* (TxOffset - (RxWait / 2)) instead
|
||||
*/
|
||||
|
||||
uint16_t tsch_timeslot_timing_us_10000[tsch_ts_elements_count] = {
|
||||
1800, /* CCAOffset */
|
||||
128, /* CCA */
|
||||
2120, /* TxOffset */
|
||||
(2120 - (TSCH_CONF_RX_WAIT / 2)), /* RxOffset */
|
||||
800, /* RxAckDelay */
|
||||
1000, /* TxAckDelay */
|
||||
TSCH_CONF_RX_WAIT, /* RxWait */
|
||||
400, /* AckWait */
|
||||
192, /* RxTx */
|
||||
2400, /* MaxAck */
|
||||
4256, /* MaxTx */
|
||||
10000, /* TimeslotLength */
|
||||
};
|
||||
|
||||
/** @} */
|
|
@ -101,34 +101,6 @@ NBR_TABLE(struct eb_stat, eb_stats);
|
|||
uint8_t tsch_hopping_sequence[TSCH_HOPPING_SEQUENCE_MAX_LEN];
|
||||
struct tsch_asn_divisor_t tsch_hopping_sequence_length;
|
||||
|
||||
/* The default timeslot timing in the standard is a guard time of
|
||||
* 2200 us, a Tx offset of 2120 us and a Rx offset of 1120 us.
|
||||
* As a result, the listening device has a guard time not centered
|
||||
* on the expected Tx time. This is to be fixed in the next iteration
|
||||
* of the standard. This can be enabled with:
|
||||
* TxOffset: 2120
|
||||
* RxOffset: 1120
|
||||
* RxWait: 2200
|
||||
*
|
||||
* Instead, we align the Rx guard time on expected Tx time. The Rx
|
||||
* guard time is user-configurable with TSCH_CONF_RX_WAIT.
|
||||
* (TxOffset - (RxWait / 2)) instead */
|
||||
|
||||
uint16_t tsch_timeslot_timing_us_10000[tsch_ts_elements_count] = {
|
||||
1800, /* CCAOffset */
|
||||
128, /* CCA */
|
||||
2120, /* TxOffset */
|
||||
(2120 - (TSCH_CONF_RX_WAIT / 2)), /* RxOffset */
|
||||
800, /* RxAckDelay */
|
||||
1000, /* TxAckDelay */
|
||||
TSCH_CONF_RX_WAIT, /* RxWait */
|
||||
400, /* AckWait */
|
||||
192, /* RxTx */
|
||||
2400, /* MaxAck */
|
||||
4256, /* MaxTx */
|
||||
10000, /* TimeslotLength */
|
||||
};
|
||||
|
||||
/* Default TSCH timeslot timing (in micro-second) */
|
||||
static const uint16_t *tsch_default_timing_us;
|
||||
/* TSCH timeslot timing (in micro-second) */
|
||||
|
|
|
@ -180,7 +180,7 @@ extern unsigned long rx_count;
|
|||
extern unsigned long sync_count;
|
||||
extern int32_t min_drift_seen;
|
||||
extern int32_t max_drift_seen;
|
||||
|
||||
/* The TSCH standard 10ms timeslot timing */
|
||||
extern uint16_t tsch_timeslot_timing_us_10000[tsch_ts_elements_count];
|
||||
|
||||
/* TSCH processes */
|
||||
|
|
Loading…
Reference in New Issue