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/******************************************************************************
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*
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* $RCSfile: interrupt-utils.c,v $
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* $Revision: 1.2 $
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*
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* This module provides the interface routines for setting up and
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* controlling the various interrupt modes present on the ARM processor.
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* Copyright 2004, R O SoftWare
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* No guarantees, warrantees, or promises, implied or otherwise.
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* May be used for hobby or commercial purposes provided copyright
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* notice remains intact.
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*
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*****************************************************************************/
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#include "interrupt-utils.h"
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#define IRQ_MASK 0x00000080
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#define FIQ_MASK 0x00000040
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#define INT_MASK (IRQ_MASK | FIQ_MASK)
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static inline unsigned __get_cpsr(void)
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{
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unsigned long retval;
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asm volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ );
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return retval;
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}
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static inline void __set_cpsr(unsigned val)
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{
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asm volatile (" msr cpsr_c, %0" : /* no outputs */ : "r" (val) );
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}
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unsigned disableIRQ(void)
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{
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unsigned _cpsr;
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_cpsr = __get_cpsr();
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__set_cpsr(_cpsr | IRQ_MASK);
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return _cpsr;
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}
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unsigned restoreIRQ(unsigned oldCPSR)
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{
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unsigned _cpsr;
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_cpsr = __get_cpsr();
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__set_cpsr((_cpsr & ~IRQ_MASK) | (oldCPSR & IRQ_MASK));
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return _cpsr;
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}
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unsigned enableIRQ(void)
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{
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unsigned _cpsr;
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_cpsr = __get_cpsr();
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__set_cpsr(_cpsr & ~IRQ_MASK);
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return _cpsr;
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}
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unsigned disableFIQ(void)
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{
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unsigned _cpsr;
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_cpsr = __get_cpsr();
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__set_cpsr(_cpsr | FIQ_MASK);
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return _cpsr;
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}
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unsigned restoreFIQ(unsigned oldCPSR)
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{
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unsigned _cpsr;
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_cpsr = __get_cpsr();
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__set_cpsr((_cpsr & ~FIQ_MASK) | (oldCPSR & FIQ_MASK));
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return _cpsr;
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}
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unsigned enableFIQ(void)
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{
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unsigned _cpsr;
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_cpsr = __get_cpsr();
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__set_cpsr(_cpsr & ~FIQ_MASK);
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return _cpsr;
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}
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/*
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* Defines and Macros for Interrupt-Service-Routines
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* collected and partly created by
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* Martin Thomas <mthomas@rhrk.uni-kl.de>
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*
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* Copyright 2005 M. Thomas
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* No guarantees, warrantees, or promises, implied or otherwise.
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* May be used for hobby or commercial purposes provided copyright
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* notice remains intact.
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*/
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#ifndef interrupt_utils_
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#define interrupt_utils_
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/*
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The following defines are usefull for
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interrupt service routine declarations.
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*/
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/*
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RAMFUNC
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Attribute which defines a function to be located
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in memory section .fastrun and called via "long calls".
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See linker-skript and startup-code to see how the
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.fastrun-section is handled.
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The definition is not only useful for ISRs but since
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ISRs should be executed fast the macro is defined in
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this header.
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*/
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#define RAMFUNC __attribute__ ((long_call, section (".fastrun")))
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/*
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INTFUNC
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standard attribute for arm-elf-gcc which marks
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a function as ISR (for the VIC). Since gcc seems
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to produce wrong code if this attribute is used in
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thumb/thumb-interwork the attribute should only be
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used for "pure ARM-mode" binaries.
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*/
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#define INTFUNC __attribute__ ((interrupt("IRQ")))
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/*
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NACKEDFUNC
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gcc will not add any code to a function declared
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"nacked". The user has to take care to save registers
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and add the needed code for ISR functions. Some
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macros for this tasks are provided below.
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*/
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#define NACKEDFUNC __attribute__((naked))
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/******************************************************************************
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*
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* MACRO Name: ISR_STORE()
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*
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* Description:
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* This MACRO is used upon entry to an ISR with interrupt nesting.
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* Should be used together with ISR_ENABLE_NEST(). The MACRO
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* performs the following steps:
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*
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* 1 - Save the non-banked registers r0-r12 and lr onto the IRQ stack.
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*
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*****************************************************************************/
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#define ISR_STORE() asm volatile( \
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"STMDB SP!,{R0-R12,LR}\n" )
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/******************************************************************************
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*
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* MACRO Name: ISR_RESTORE()
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*
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* Description:
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* This MACRO is used upon exit from an ISR with interrupt nesting.
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* Should be used together with ISR_DISABLE_NEST(). The MACRO
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* performs the following steps:
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*
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* 1 - Load the non-banked registers r0-r12 and lr from the IRQ stack.
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* 2 - Adjusts resume adress
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*
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*****************************************************************************/
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#define ISR_RESTORE() asm volatile( \
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"LDMIA SP!,{R0-R12,LR}\n" \
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"SUBS R15,R14,#0x0004\n" )
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/******************************************************************************
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*
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* MACRO Name: ISR_ENABLE_NEST()
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*
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* Description:
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* This MACRO is used upon entry from an ISR with interrupt nesting.
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* Should be used after ISR_STORE.
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*
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*****************************************************************************/
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#define ISR_ENABLE_NEST() asm volatile( \
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"MRS LR, SPSR \n" \
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"STMFD SP!, {LR} \n" \
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"MSR CPSR_c, #0x1f \n" \
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"STMFD SP!, {LR} " )
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/******************************************************************************
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*
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* MACRO Name: ISR_DISABLE_NEST()
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*
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* Description:
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* This MACRO is used upon entry from an ISR with interrupt nesting.
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* Should be used before ISR_RESTORE.
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*
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*****************************************************************************/
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#define ISR_DISABLE_NEST() asm volatile( \
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"LDMFD SP!, {LR} \n" \
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"MSR CPSR_c, #0x92 \n" \
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"LDMFD SP!, {LR} \n" \
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"MSR SPSR_cxsf, LR \n" )
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/*
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* The following marcos are from the file "armVIC.h" by:
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*
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* Copyright 2004, R O SoftWare
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* No guarantees, warrantees, or promises, implied or otherwise.
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* May be used for hobby or commercial purposes provided copyright
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* notice remains intact.
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*
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*/
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/******************************************************************************
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*
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* MACRO Name: ISR_ENTRY()
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*
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* Description:
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* This MACRO is used upon entry to an ISR. The current version of
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* the gcc compiler for ARM does not produce correct code for
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* interrupt routines to operate properly with THUMB code. The MACRO
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* performs the following steps:
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*
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* 1 - Adjust address at which execution should resume after servicing
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* ISR to compensate for IRQ entry
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* 2 - Save the non-banked registers r0-r12 and lr onto the IRQ stack.
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* 3 - Get the status of the interrupted program is in SPSR.
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* 4 - Push it onto the IRQ stack as well.
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*
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*****************************************************************************/
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#define ISR_ENTRY() asm volatile(" sub lr, lr,#4\n" \
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" stmfd sp!,{r0-r12,lr}\n" \
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" mrs r1, spsr\n" \
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" stmfd sp!,{r1}")
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/******************************************************************************
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*
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* MACRO Name: ISR_EXIT()
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*
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* Description:
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* This MACRO is used to exit an ISR. The current version of the gcc
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* compiler for ARM does not produce correct code for interrupt
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* routines to operate properly with THUMB code. The MACRO performs
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* the following steps:
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*
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* 1 - Recover SPSR value from stack
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* 2 - and restore its value
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* 3 - Pop the return address & the saved general registers from
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* the IRQ stack & return
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*
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*****************************************************************************/
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#define ISR_EXIT() asm volatile(" ldmfd sp!,{r1}\n" \
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" msr spsr_c,r1\n" \
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" ldmfd sp!,{r0-r12,pc}^")
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/******************************************************************************
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*
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* Function Name: disableIRQ()
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*
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* Description:
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* This function sets the IRQ disable bit in the status register
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* previous value of CPSR
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*
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*****************************************************************************/
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unsigned disableIRQ(void);
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/******************************************************************************
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*
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* Function Name: enableIRQ()
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*
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* Description:
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* This function clears the IRQ disable bit in the status register
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* previous value of CPSR
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*
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*****************************************************************************/
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unsigned enableIRQ(void);
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/******************************************************************************
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*
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* Function Name: restoreIRQ()
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*
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* Description:
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* This function restores the IRQ disable bit in the status register
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* to the value contained within passed oldCPSR
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* previous value of CPSR
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*
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*****************************************************************************/
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unsigned restoreIRQ(unsigned oldCPSR);
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/******************************************************************************
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*
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* Function Name: disableFIQ()
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*
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* Description:
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* This function sets the FIQ disable bit in the status register
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* previous value of CPSR
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*
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*****************************************************************************/
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unsigned disableFIQ(void);
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/******************************************************************************
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*
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* Function Name: enableFIQ()
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*
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* Description:
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* This function clears the FIQ disable bit in the status register
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* previous value of CPSR
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*
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*****************************************************************************/
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unsigned enableFIQ(void);
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/******************************************************************************
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*
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* Function Name: restoreFIQ()
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*
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* Description:
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* This function restores the FIQ disable bit in the status register
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* to the value contained within passed oldCPSR
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*
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* Calling Sequence:
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* void
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*
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* Returns:
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* previous value of CPSR
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*
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*****************************************************************************/
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unsigned restoreFIQ(unsigned oldCPSR);
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#endif
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@ -0,0 +1,100 @@
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#include <sys-interrupt.h>
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#include <interrupt-utils.h>
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#include <AT91SAM7S64.h>
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#define ATTR
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#ifndef NULL
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#define NULL 0
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#endif
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static SystemInterruptHandler *handlers = NULL;
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static void
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system_int_safe (void) __attribute__((noinline));
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static void
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system_int_safe (void)
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{
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SystemInterruptHandler *h;
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h = handlers;
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while (h) {
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if (h->handler()) break;
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h = h->next;
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}
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}
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static void NACKEDFUNC ATTR
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system_int (void) /* System Interrupt Handler */
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{
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ISR_ENTRY();
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system_int_safe();
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*AT91C_AIC_EOICR = 0; /* End of Interrupt */
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ISR_EXIT();
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}
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static unsigned int enabled = 0; /* Number of times the system
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interrupt has been enabled */
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#define DIS_INT *AT91C_AIC_IDCR = (1 << AT91C_ID_SYS)
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#define EN_INT if (enabled > 0) *AT91C_AIC_IECR = (1 << AT91C_ID_SYS)
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void
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sys_interrupt_enable()
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{
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if (enabled++ == 0) {
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/* Level trigged at priority 5 */
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AT91C_AIC_SMR[AT91C_ID_SYS] = AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | 5;
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/* Interrupt vector */
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AT91C_AIC_SVR[AT91C_ID_SYS] = (unsigned long) system_int;
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/* Enable */
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EN_INT;
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}
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}
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void
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sys_interrupt_disable()
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{
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if (--enabled == 0) {
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DIS_INT;
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}
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}
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void
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sys_interrupt_append_handler(SystemInterruptHandler *handler)
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{
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SystemInterruptHandler **h = &handlers;
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while(*h) {
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h = &(*h)->next;
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}
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DIS_INT;
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*h = handler;
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handler->next = NULL;
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EN_INT;
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}
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void
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sys_interrupt_prepend_handler(SystemInterruptHandler *handler)
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{
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DIS_INT;
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handler->next = handlers;
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handlers = handler;
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EN_INT;
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}
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void
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sys_interrupt_remove_handler(SystemInterruptHandler *handler)
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{
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SystemInterruptHandler **h = &handlers;
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while(*h) {
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if (*h == handler) {
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DIS_INT;
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*h = handler->next;
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EN_INT;
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break;
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}
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h = &(*h)->next;
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}
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}
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@ -0,0 +1,31 @@
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#ifndef __SYS_INTERRUPT_H__QIHZ66NP8K__
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#define __SYS_INTERRUPT_H__QIHZ66NP8K__
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/* Returns true if it handled an activbe interrupt */
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typedef int (*SystemInterruptFunc)();
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typedef struct _SystemInterruptHandler SystemInterruptHandler;
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struct _SystemInterruptHandler
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{
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SystemInterruptHandler *next;
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SystemInterruptFunc handler;
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};
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void
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sys_interrupt_enable();
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void
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sys_interrupt_disable();
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void
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sys_interrupt_append_handler(SystemInterruptHandler *handler);
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void
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sys_interrupt_prepend_handler(SystemInterruptHandler *handler);
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void
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sys_interrupt_remove_handler(SystemInterruptHandler *handler);
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#endif /* __SYS_INTERRUPT_H__QIHZ66NP8K__ */
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@ -0,0 +1,92 @@
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/* Timer registers are all 16-bit wide with 16-bit access only */
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#define TMR_OFFSET (0x20)
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#define TMR_BASE (0x80007000)
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#define TMR0_BASE (TMR_BASE)
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#define TMR1_BASE (TMR_BASE + TMR_OFFSET*1)
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#define TMR2_BASE (TMR_BASE + TMR_OFFSET*2)
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#define TMR3_BASE (TMR_BASE + TMR_OFFSET*3)
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#define TMR_REGOFF_COMP1 (0x0)
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#define TMR_REGOFF_COMP2 (0x2)
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#define TMR_REGOFF_CAPT (0x4)
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#define TMR_REGOFF_LOAD (0x6)
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#define TMR_REGOFF_HOLD (0x8)
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#define TMR_REGOFF_CNTR (0xa)
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#define TMR_REGOFF_CTRL (0xc)
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#define TMR_REGOFF_SCTRL (0xe)
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#define TMR_REGOFF_CMPLD1 (0x10)
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#define TMR_REGOFF_CMPLD2 (0x12)
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#define TMR_REGOFF_CSCTRL (0x14)
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#define TMR_REGOFF_ENBL (0x1e)
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/* Timer 0 registers */
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#define TMR0_COMP1 (TMR0_BASE + TMR_REGOFF_COMP1)
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#define TMR0_COMP_UP TMR0_COMP1
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#define TMR0_COMP2 (TMR0_BASE + TMR_REGOFF_COMP2)
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#define TMR0_COMP_DOWN TMR0_COMP2
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#define TMR0_CAPT (TMR0_BASE + TMR_REGOFF_CAPT)
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#define TMR0_LOAD (TMR0_BASE + TMR_REGOFF_LOAD)
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#define TMR0_HOLD (TMR0_BASE + TMR_REGOFF_HOLD)
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#define TMR0_CNTR (TMR0_BASE + TMR_REGOFF_CTRL)
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#define TMR0_CTRL (TMR0_BASE + TMR_REGOFF_CTRL)
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#define TMR0_SCTRL (TMR0_BASE + TMR_REGOFF_SCTRL)
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#define TMR0_CMPLD1 (TMR0_BASE + TMR_REGOFF_CMPLD1)
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#define TMR0_CMPLD2 (TMR0_BASE + TMR_REGOFF_CMPLD2)
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#define TMR0_CSCTRL (TMR0_BASE + TMR_REGOFF_CSCTRL)
|
||||
|
||||
/* one enable register to rule them all */
|
||||
#define TMR_ENBL TMR0_BASE + TMR_REGOFF_ENBL
|
||||
|
||||
#define MBAR_GPIO 0x80000000
|
||||
#define GPIO_PAD_DIR0 0x80000000
|
||||
#define GPIO_DATA0 0x80000008
|
||||
#define UART1_DATA 0x80005008
|
||||
#define DELAY 400000
|
||||
|
||||
#define reg32(x) (*(volatile uint32_t *)(x))
|
||||
#define reg16(x) (*(volatile uint16_t *)(x))
|
||||
|
||||
#include "embedded_types.h"
|
||||
|
||||
__attribute__ ((section ("startup")))
|
||||
void main(void) {
|
||||
|
||||
/* pin direction */
|
||||
reg32(GPIO_PAD_DIR0) = 0x00000400;
|
||||
|
||||
/* timer setup */
|
||||
/* CTRL */
|
||||
#define COUNT_MODE 1 /* use rising edge of primary source */
|
||||
#define PRIME_SRC 0xf /* Perip. clock with 128 prescale (for 24Mhz = 187500Hz)*/
|
||||
#define SEC_SRC 0 /* don't need this */
|
||||
#define ONCE 0 /* keep counting */
|
||||
#define LEN 1 /* count until compare then reload with value in LOAD */
|
||||
#define DIR 0 /* count up */
|
||||
#define CO_INIT 0 /* other counters cannot force a re-initialization of this counter */
|
||||
#define OUT_MODE 0 /* OFLAG is asserted while counter is active */
|
||||
|
||||
reg16(TMR_ENBL) = 0; /* tmrs reset to enabled */
|
||||
reg16(TMR0_SCTRL) = 0;
|
||||
reg16(TMR0_LOAD) = 0; /* reload to zero */
|
||||
reg16(TMR0_COMP_UP) = 18750; /* trigger a reload at the end */
|
||||
reg16(TMR0_CMPLD1) = 18750; /* compare 1 triggered reload level, 10HZ maybe? */
|
||||
reg16(TMR0_CNTR) = 0; /* reset count register */
|
||||
reg16(TMR0_CTRL) = (COUNT_MODE<<13) | (PRIME_SRC<<9) | (SEC_SRC<<7) | (ONCE<<6) | (LEN<<5) | (DIR<<4) | (CO_INIT<<3) | (OUT_MODE);
|
||||
reg16(TMR_ENBL) = 0xf; /* enable all the timers --- why not? */
|
||||
|
||||
while(1) {
|
||||
|
||||
/* blink on */
|
||||
reg32(GPIO_DATA0) = 0x00000400;
|
||||
|
||||
while((reg16(TMR0_SCTRL)>>15) == 0) { continue; }
|
||||
reg16(TMR0_SCTRL) = 0; /*clear bit 15, and all the others --- should be ok, but clearly not "the right thing to do" */
|
||||
|
||||
/* blink off */
|
||||
reg32(GPIO_DATA0) = 0x00000000;
|
||||
|
||||
while((reg16(TMR0_SCTRL)>>15) == 0) { continue; }
|
||||
reg16(TMR0_SCTRL) = 0; /*clear bit 15, and all the others --- should be ok, but clearly not "the right thing to do" */
|
||||
|
||||
};
|
||||
}
|
Loading…
Reference in New Issue