102 lines
3.7 KiB
C
102 lines
3.7 KiB
C
/*
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* Copyright (c) 2014, CETIC.
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* Copyright (c) 2016, Zolertia <http://www.zolertia.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*---------------------------------------------------------------------------*/
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/**
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* \addtogroup zolertia-orion-ethernet-router
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* @{
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*
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* \defgroup zolertia-eth-arch-spi Zolertia ENC28J60 SPI arch
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*
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* ENC28J60 eth-gw SPI arch specifics
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* @{
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*
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* \file
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* eth-gw SPI arch specifics
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*/
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/*---------------------------------------------------------------------------*/
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#include "dev/spi-arch-legacy.h"
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#include "spi.h"
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#include "dev/gpio.h"
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/*---------------------------------------------------------------------------*/
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#define RESET_PORT GPIO_PORT_TO_BASE(ETH_RESET_PORT)
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#define RESET_BIT GPIO_PIN_MASK(ETH_RESET_PIN)
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/*---------------------------------------------------------------------------*/
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void
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enc28j60_arch_spi_init(void)
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{
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spix_init(ETH_SPI_INSTANCE);
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spix_cs_init(ETH_SPI_CSN_PORT, ETH_SPI_CSN_PIN);
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spix_set_mode(ETH_SPI_INSTANCE, SSI_CR0_FRF_MOTOROLA, 0, 0, 8);
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GPIO_SOFTWARE_CONTROL(RESET_PORT, RESET_BIT);
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GPIO_SET_OUTPUT(RESET_PORT, RESET_BIT);
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GPIO_SET_INPUT(RESET_PORT, RESET_BIT);
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}
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/*---------------------------------------------------------------------------*/
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void
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enc28j60_arch_spi_select(void)
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{
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SPIX_CS_CLR(ETH_SPI_CSN_PORT, ETH_SPI_CSN_PIN);
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}
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/*---------------------------------------------------------------------------*/
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void
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enc28j60_arch_spi_deselect(void)
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{
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SPIX_CS_SET(ETH_SPI_CSN_PORT, ETH_SPI_CSN_PIN);
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}
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/*---------------------------------------------------------------------------*/
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void
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enc28j60_arch_spi_write(uint8_t output)
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{
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SPIX_WAITFORTxREADY(ETH_SPI_INSTANCE);
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SPIX_BUF(ETH_SPI_INSTANCE) = output;
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SPIX_WAITFOREOTx(ETH_SPI_INSTANCE);
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SPIX_WAITFOREORx(ETH_SPI_INSTANCE);
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uint32_t dummy = SPIX_BUF(ETH_SPI_INSTANCE);
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(void) dummy;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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enc28j60_arch_spi_read(void)
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{
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SPIX_WAITFORTxREADY(ETH_SPI_INSTANCE);
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SPIX_BUF(ETH_SPI_INSTANCE) = 0;
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SPIX_WAITFOREOTx(ETH_SPI_INSTANCE);
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SPIX_WAITFOREORx(ETH_SPI_INSTANCE);
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return SPIX_BUF(ETH_SPI_INSTANCE);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* @}
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* @}
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*/
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