62 lines
2.3 KiB
C
62 lines
2.3 KiB
C
/*
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* Copyright (c) 2018, RISE SICS.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki operating system.
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*
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*/
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/**
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* \file
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* IEEE 802.15.4 TSCH timeslot timings for 15ms slots
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* \author
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* Simon Duquennoy <simon.duquennoy@ri.se>
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*
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*/
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#include "contiki.h"
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#include "net/mac/tsch/tsch.h"
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/**
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* \brief 15ms TSCH timeslot timings, required for cc2420 platforms as
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* they are unable to keep up with the defulat 10ms timeslots.
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*/
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const tsch_timeslot_timing_usec tsch_timeslot_timing_us_15000= {
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1800, /* CCAOffset */
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128, /* CCA */
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4000, /* TxOffset */
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(4000 - (TSCH_CONF_RX_WAIT / 2)), /* RxOffset */
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3600, /* RxAckDelay */
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4000, /* TxAckDelay */
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TSCH_CONF_RX_WAIT, /* RxWait */
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800, /* AckWait */
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2072, /* RxTx */
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2400, /* MaxAck */
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4256, /* MaxTx */
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15000, /* TimeslotLength */
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};
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