255 lines
8.2 KiB
C
255 lines
8.2 KiB
C
/*
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* Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
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* to the MC1322x project (http://mc1322x.devl.org)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of libmc1322x: see http://mc1322x.devl.org
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* for details.
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*
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*
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*/
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#include <mc1322x.h>
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#include <stdlib.h>
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#include "pwm.h"
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static struct {
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uint32_t period;
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uint32_t guard;
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uint32_t pad_forced;
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} pwm_info[4];
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static inline void pad_set_output(int timer_num) { // set to output (when in GPIO mode)
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switch (timer_num) {
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case 0: GPIO->DATA_SEL.TMR0_PIN = 1; GPIO->PAD_DIR.TMR0_PIN = 1; break;
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case 1: GPIO->DATA_SEL.TMR1_PIN = 1; GPIO->PAD_DIR.TMR1_PIN = 1; break;
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case 2: GPIO->DATA_SEL.TMR2_PIN = 1; GPIO->PAD_DIR.TMR2_PIN = 1; break;
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case 3: GPIO->DATA_SEL.TMR3_PIN = 1; GPIO->PAD_DIR.TMR3_PIN = 1; break;
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default: break;
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}
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}
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static inline void pad_set_zero(int timer_num) { // set to zero in GPIO mode
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switch (timer_num) {
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case 0: GPIO->DATA_RESET.TMR0_PIN = 1; GPIO->FUNC_SEL.TMR0_PIN = 0; break;
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case 1: GPIO->DATA_RESET.TMR1_PIN = 1; GPIO->FUNC_SEL.TMR1_PIN = 0; break;
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case 2: GPIO->DATA_RESET.TMR2_PIN = 1; GPIO->FUNC_SEL.TMR2_PIN = 0; break;
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case 3: GPIO->DATA_RESET.TMR3_PIN = 1; GPIO->FUNC_SEL.TMR3_PIN = 0; break;
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default: break;
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}
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}
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static inline void pad_set_one(int timer_num) { // set to one in GPIO mode
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switch (timer_num) {
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case 0: GPIO->DATA_SET.TMR0_PIN = 1; GPIO->FUNC_SEL.TMR0_PIN = 0; break;
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case 1: GPIO->DATA_SET.TMR1_PIN = 1; GPIO->FUNC_SEL.TMR1_PIN = 0; break;
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case 2: GPIO->DATA_SET.TMR2_PIN = 1; GPIO->FUNC_SEL.TMR2_PIN = 0; break;
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case 3: GPIO->DATA_SET.TMR3_PIN = 1; GPIO->FUNC_SEL.TMR3_PIN = 0; break;
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default: break;
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}
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}
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static inline void pad_set_normal(int timer_num) { // set to TMR OFLAG output
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switch (timer_num) {
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case 0: GPIO->FUNC_SEL.TMR0_PIN = 1; break;
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case 1: GPIO->FUNC_SEL.TMR1_PIN = 1; break;
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case 2: GPIO->FUNC_SEL.TMR2_PIN = 1; break;
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case 3: GPIO->FUNC_SEL.TMR3_PIN = 1; break;
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default: break;
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}
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}
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/* Initialize PWM output.
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timer_num = 0, 1, 2, 3
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rate = desired rate in Hz,
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duty = desired duty cycle. 0=always off, 65536=always on.
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enable_timer = whether to actually run the timer, versus just configuring it
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Returns actual PWM rate. */
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uint32_t pwm_init_ex(int timer_num, uint32_t rate, uint32_t duty, int enable_timer)
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{
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uint32_t actual_rate;
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volatile struct TMR_struct *timer = TMR_ADDR(timer_num);
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int log_divisor = 0;
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uint32_t period, guard;
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/* Turn timer off */
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TMR0->ENBL &= ~(1 << timer_num);
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/* Calculate optimal rate */
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for (log_divisor = 0; log_divisor < 8; log_divisor++)
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{
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int denom = (rate * (1 << log_divisor));
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period = (REF_OSC + denom/2) / denom;
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if (period <= 65535)
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break;
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}
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if (log_divisor >= 8)
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{
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period = 65535;
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log_divisor = 7;
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}
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/* Guard value (for safely changing duty cycle) should be
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about 32 CPU clocks. Calculate how many timer counts that
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is, based on prescaler */
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guard = 32 >> log_divisor;
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if (guard < 2) guard = 2;
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/* Period should be about 50% longer than guard */
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if (period < ((guard * 3) / 2))
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period = guard + 4;
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/* Store period, guard, actual rate */
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pwm_info[timer_num].period = period;
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pwm_info[timer_num].guard = guard;
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actual_rate = REF_OSC / (period * (1 << log_divisor));
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/* Set up timer */
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pwm_duty_ex(timer_num, duty); // sets CMPLD1, LOAD
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timer->SCTRLbits = (struct TMR_SCTRL) {
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.OEN = 1, // drive OFLAG
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};
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timer->CSCTRLbits = (struct TMR_CSCTRL) {
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.CL1 = 0x01, // Reload COMP1 when COMP1 matches
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};
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timer->COMP1 = timer->CMPLD1;
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timer->CNTR = timer->LOAD;
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timer->CTRLbits = (struct TMR_CTRL) {
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.COUNT_MODE = 1, // Count rising edge of primary source
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.PRIMARY_CNT_SOURCE = 8 + log_divisor, // Peripheral clock divided by (divisor)
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.LENGTH = 1, // At compare, reset to LOAD
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.OUTPUT_MODE = 6, // Set on COMP1, clear on rollover
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};
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pad_set_output(timer_num);
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pad_set_normal(timer_num);
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if (enable_timer) {
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TMR0->ENBL |= (1 << timer_num);
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}
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// printf("pwm timer %d, addr %p, requested rate %d, actual rate: %d, period %d, guard %d, divisor %d\r\n",
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// timer_num, timer, rate, actual_rate, period, guard, 1 << log_divisor);
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return actual_rate;
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}
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/* Change duty cycle. Safe to call at any time.
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timer_num = 0, 1, 2, 3
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duty = desired duty cycle. 0=always off, 65536=always on.
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*/
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void pwm_duty_ex(int timer_num, uint32_t duty)
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{
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uint16_t comp1, load;
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volatile struct TMR_struct *timer = TMR_ADDR(timer_num);
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uint32_t period = pwm_info[timer_num].period;
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duty = (duty * period + 32767) / 65536;
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/* We don't use the "variable PWM" mode described in the datasheet because
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there's no way to reliably change the duty cycle without potentially
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changing the period for one cycle, which will cause phase drifts.
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Instead, we use the "Set on compare, clear on rollover" output mode:
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waveform: |_________| |----------|
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counter: 0 COMP1 LOAD 65535
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The low portion of the wave is COMP1 cycles long. The
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compare changes the counter to LOAD, and so the high
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portion is (65536 - LOAD) cycles long.
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Now, we just have to make sure we're not about to hit COMP1
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before we change LOAD and COMPLD1. If (COMP1 - CNTR) is less
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than GUARD cycles, we wait for it to reload before changing.
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*/
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if (duty == 0) {
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pad_set_zero(timer_num);
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pwm_info[timer_num].pad_forced = 1;
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return;
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}
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if (duty >= period) {
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pad_set_one(timer_num);
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pwm_info[timer_num].pad_forced = 1;
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return;
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}
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if (pwm_info[timer_num].pad_forced) {
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pad_set_normal(timer_num);
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pwm_info[timer_num].pad_forced = 0;
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}
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comp1 = (period - duty) - 1;
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load = (65536 - duty);
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/* Disable interrupts */
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uint32_t old_INTCNTL = ITC->INTCNTL;
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ITC->INTCNTL = 0;
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if (TMR0->ENBL & (1 << timer_num))
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{
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/* Timer is enabled, so use the careful approach.
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Implemented in ASM so we can be sure of the cycle
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count */
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uint32_t tmp1, tmp2;
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asm volatile (//".arm \n\t"
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"1: \n\t"
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"ldrh %[tmp1], %[comp] \n\t" // load COMP1
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"ldrh %[tmp2], %[count] \n\t" // load CNTR
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"sub %[tmp1], %[tmp1], %[tmp2] \n\t" // subtract
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"lsl %[tmp1], %[tmp1], #16 \n\t" // clear high bits
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"lsr %[tmp1], %[tmp1], #16 \n\t"
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"cmp %[tmp1], %[guard] \n\t" // compare to GUARD
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"bls 1b \n\t" // if less, goto 1
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"strh %[ld1], %[cmpld] \n\t" // store CMPLD1
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"strh %[ld2], %[load] \n\t" // store LOAD
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: /* out */
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[tmp1] "=&l" (tmp1),
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[tmp2] "=&l" (tmp2),
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[cmpld] "=m" (timer->CMPLD1),
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[load] "=m" (timer->LOAD)
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: /* in */
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[comp] "m" (timer->COMP1),
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[count] "m" (timer->CNTR),
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[ld1] "l" (comp1),
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[ld2] "l" (load),
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[guard] "l" (pwm_info[timer_num].guard)
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: "memory"
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);
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} else {
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/* Just set it directly, timer isn't running */
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timer->CMPLD1 = comp1;
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timer->LOAD = load;
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}
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/* Re-enable interrupts */
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ITC->INTCNTL = old_INTCNTL;
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}
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