330 lines
9.4 KiB
C
330 lines
9.4 KiB
C
/*
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* Copyright (c) 2015, Nordic Semiconductor
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/**
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* \addtogroup nrf52dk
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* @{
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*
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* \defgroup nrf52dk-config nRF52 SDK configuration
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* @{
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*/
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#ifndef NRF_DRV_CONFIG_H
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#define NRF_DRV_CONFIG_H
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/* CLOCK */
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#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
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#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LF_SRC_Xtal
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#define CLOCK_CONFIG_LF_RC_CAL_INTERVAL RC_2000MS_CALIBRATION_INTERVAL
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#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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/* GPIOTE */
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#define GPIOTE_ENABLED 1
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#if (GPIOTE_ENABLED == 1)
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#define GPIOTE_CONFIG_USE_SWI_EGU false
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#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
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#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4
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#endif
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/* TIMER */
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#define TIMER0_ENABLED 0
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#if (TIMER0_ENABLED == 1)
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#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
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#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER0_INSTANCE_INDEX 0
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#endif
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#define TIMER1_ENABLED 1
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#if (TIMER1_ENABLED == 1)
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#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_62500Hz
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#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
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#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
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#endif
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#define TIMER2_ENABLED 0
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#if (TIMER2_ENABLED == 1)
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#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
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#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
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#endif
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#define TIMER3_ENABLED 0
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#if (TIMER3_ENABLED == 1)
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#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
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#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER2_INSTANCE_INDEX)
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#endif
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#define TIMER4_ENABLED 0
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#if (TIMER4_ENABLED == 1)
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#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
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#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
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#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
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#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER3_INSTANCE_INDEX)
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#endif
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#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
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/* RTC */
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#define RTC0_ENABLED 0
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#if (RTC0_ENABLED == 1)
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#define RTC0_CONFIG_FREQUENCY 32678
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#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define RTC0_CONFIG_RELIABLE false
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#define RTC0_INSTANCE_INDEX 0
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#endif
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#define RTC1_ENABLED 1
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#if (RTC1_ENABLED == 1)
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#define RTC1_CONFIG_FREQUENCY 128
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#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define RTC1_CONFIG_RELIABLE false
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#define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
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#endif
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#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED)
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#define NRF_MAXIMUM_LATENCY_US 2000
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/* RNG */
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#define RNG_ENABLED 1
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#if (RNG_ENABLED == 1)
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#define RNG_CONFIG_ERROR_CORRECTION true
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#define RNG_CONFIG_POOL_SIZE 8
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#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#endif
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/* SPI */
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#define SPI0_ENABLED 0
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#if (SPI0_ENABLED == 1)
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#define SPI0_USE_EASY_DMA 0
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#define SPI0_CONFIG_SCK_PIN 2
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#define SPI0_CONFIG_MOSI_PIN 3
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#define SPI0_CONFIG_MISO_PIN 4
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#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define SPI0_INSTANCE_INDEX 0
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#endif
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#define SPI1_ENABLED 0
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#if (SPI1_ENABLED == 1)
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#define SPI1_USE_EASY_DMA 0
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#define SPI1_CONFIG_SCK_PIN 2
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#define SPI1_CONFIG_MOSI_PIN 3
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#define SPI1_CONFIG_MISO_PIN 4
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#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
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#endif
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#define SPI2_ENABLED 0
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#if (SPI2_ENABLED == 1)
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#define SPI2_USE_EASY_DMA 0
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#define SPI2_CONFIG_SCK_PIN 2
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#define SPI2_CONFIG_MOSI_PIN 3
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#define SPI2_CONFIG_MISO_PIN 4
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#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
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#endif
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#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
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/* UART */
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#define UART0_ENABLED 1
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#if (UART0_ENABLED == 1)
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#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED
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#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
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#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_38400
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#define UART0_CONFIG_PSEL_TXD 6
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#define UART0_CONFIG_PSEL_RXD 8
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#define UART0_CONFIG_PSEL_CTS 7
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#define UART0_CONFIG_PSEL_RTS 5
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#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#ifdef NRF52
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#define UART0_CONFIG_USE_EASY_DMA false
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//Compile time flag
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#define UART_EASY_DMA_SUPPORT 1
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#define UART_LEGACY_SUPPORT 1
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#endif //NRF52
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#endif
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#define TWI0_ENABLED 0
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#if (TWI0_ENABLED == 1)
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#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
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#define TWI0_CONFIG_SCL 0
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#define TWI0_CONFIG_SDA 1
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#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
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#define TWI0_INSTANCE_INDEX 0
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#endif
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#define TWI1_ENABLED 0
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#if (TWI1_ENABLED == 1)
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#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
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#define TWI1_CONFIG_SCL 0
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#define TWI1_CONFIG_SDA 1
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#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
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#define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
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#endif
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#define TWI_COUNT (TWI0_ENABLED+TWI1_ENABLED)
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/* TWIS */
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#define TWIS0_ENABLED 0
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#if (TWIS0_ENABLED == 1)
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#define TWIS0_CONFIG_ADDR0 0
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#define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
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#define TWIS0_CONFIG_SCL 0
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#define TWIS0_CONFIG_SDA 1
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#define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
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#define TWIS0_INSTANCE_INDEX 0
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#endif
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#define TWIS1_ENABLED 0
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#if (TWIS1_ENABLED == 1)
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#define TWIS1_CONFIG_ADDR0 0
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#define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
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#define TWIS1_CONFIG_SCL 0
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#define TWIS1_CONFIG_SDA 1
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#define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
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#define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
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#endif
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#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
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/* For more documentation see nrf_drv_twis.h file */
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#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
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/* For more documentation see nrf_drv_twis.h file */
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#define TWIS_NO_SYNC_MODE 0
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/**
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* \brief Definition for patching PAN problems
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*
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* Set this definition to nonzero value to patch anomalies
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* from MPW3 - first lunch microcontroller.
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*
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* Concerns:
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* - PAN-29: TWIS: incorrect bits in ERRORSRC
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* - PAN-30: TWIS: STOP task does not work as expected
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*/
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#define NRF_TWIS_PATCH_FOR_MPW3 1
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/* QDEC */
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#define QDEC_ENABLED 0
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#if (QDEC_ENABLED == 1)
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#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
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#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
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#define QDEC_CONFIG_PIO_A 1
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#define QDEC_CONFIG_PIO_B 2
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#define QDEC_CONFIG_PIO_LED 3
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#define QDEC_CONFIG_LEDPRE 511
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#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
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#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define QDEC_CONFIG_DBFEN false
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#define QDEC_CONFIG_SAMPLE_INTEN false
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#endif
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/* SAADC */
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#define SAADC_ENABLED 0
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#if (SAADC_ENABLED == 1)
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#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
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#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
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#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#endif
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/* LPCOMP */
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#define LPCOMP_ENABLED 0
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#if (LPCOMP_ENABLED == 1)
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#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
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#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
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#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
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#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
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#endif
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/* WDT */
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#define WDT_ENABLED 1
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#if (WDT_ENABLED == 1)
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#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
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#define WDT_CONFIG_RELOAD_VALUE 2000
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#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
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#endif
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#include "nrf_drv_config_validation.h"
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#endif // NRF_DRV_CONFIG_H
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/**
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* @}
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* @}
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*/
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