331 lines
11 KiB
C
331 lines
11 KiB
C
/*
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* Original file:
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Port to Contiki:
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* Copyright (c) 2013, ADVANSEE - http://www.advansee.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538-aes
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* @{
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*
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* \file
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* Implementation of the cc2538 AES driver
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*/
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#include "contiki.h"
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#include "dev/rom-util.h"
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#include "dev/nvic.h"
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#include "dev/aes.h"
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#include "reg.h"
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#include <stdbool.h>
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#include <stdint.h>
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/*---------------------------------------------------------------------------*/
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uint8_t
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aes_load_keys(const void *keys, uint8_t key_size, uint8_t count,
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uint8_t start_area)
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{
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uint32_t aes_key_store_size;
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uint32_t areas;
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uint64_t aligned_keys[AES_KEY_AREAS * 128 / 8 / sizeof(uint64_t)];
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int i;
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if(REG(AES_CTRL_ALG_SEL) != 0x00000000) {
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return CRYPTO_RESOURCE_IN_USE;
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}
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/* 192-bit keys must be padded to 256 bits */
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if(key_size == AES_KEY_STORE_SIZE_KEY_SIZE_192) {
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for(i = 0; i < count; i++) {
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rom_util_memcpy(&aligned_keys[i << 2], &((const uint64_t *)keys)[i * 3],
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192 / 8);
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aligned_keys[(i << 2) + 3] = 0;
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}
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}
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/* Change count to the number of 128-bit key areas */
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if(key_size != AES_KEY_STORE_SIZE_KEY_SIZE_128) {
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count <<= 1;
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}
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/* The keys base address needs to be 4-byte aligned */
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if(key_size != AES_KEY_STORE_SIZE_KEY_SIZE_192) {
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rom_util_memcpy(aligned_keys, keys, count << 4);
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}
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/* Workaround for AES registers not retained after PM2 */
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REG(AES_CTRL_INT_CFG) = AES_CTRL_INT_CFG_LEVEL;
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REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_DMA_IN_DONE |
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AES_CTRL_INT_EN_RESULT_AV;
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/* Configure master control module */
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REG(AES_CTRL_ALG_SEL) = AES_CTRL_ALG_SEL_KEYSTORE;
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/* Clear any outstanding events */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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/* Configure key store module (areas, size)
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* Note that writing AES_KEY_STORE_SIZE deletes all stored keys */
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aes_key_store_size = REG(AES_KEY_STORE_SIZE);
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if((aes_key_store_size & AES_KEY_STORE_SIZE_KEY_SIZE_M) != key_size) {
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REG(AES_KEY_STORE_SIZE) = (aes_key_store_size &
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~AES_KEY_STORE_SIZE_KEY_SIZE_M) | key_size;
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}
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/* Free possibly already occupied key areas */
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areas = ((0x00000001 << count) - 1) << start_area;
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REG(AES_KEY_STORE_WRITTEN_AREA) = areas;
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/* Enable key areas to write */
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REG(AES_KEY_STORE_WRITE_AREA) = areas;
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/* Configure DMAC
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* Enable DMA channel 0 */
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REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the keys in ext. memory */
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REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)aligned_keys;
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/* Total keys length in bytes (e.g. 16 for 1 x 128-bit key) */
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REG(AES_DMAC_CH0_DMALENGTH) = (REG(AES_DMAC_CH0_DMALENGTH) &
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~AES_DMAC_CH_DMALENGTH_DMALEN_M) |
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(count << (4 + AES_DMAC_CH_DMALENGTH_DMALEN_S));
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/* Wait for operation to complete */
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while(!(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_RESULT_AV));
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/* Check for absence of errors in DMA and key store */
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if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR;
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/* Disable master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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return CRYPTO_DMA_BUS_ERROR;
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}
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if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_KEY_ST_WR_ERR) {
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_KEY_ST_WR_ERR;
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/* Disable master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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return AES_KEYSTORE_WRITE_ERROR;
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}
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/* Acknowledge the interrupt */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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/* Disable master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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/* Check status, if error return error code */
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if((REG(AES_KEY_STORE_WRITTEN_AREA) & areas) != areas) {
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return AES_KEYSTORE_WRITE_ERROR;
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}
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return CRYPTO_SUCCESS;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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aes_auth_crypt_start(uint32_t ctrl, uint8_t key_area, const void *iv,
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const void *adata, uint16_t adata_len,
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const void *data_in, void *data_out, uint16_t data_len,
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struct process *process)
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{
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if(REG(AES_CTRL_ALG_SEL) != 0x00000000) {
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return CRYPTO_RESOURCE_IN_USE;
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}
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/* Workaround for AES registers not retained after PM2 */
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REG(AES_CTRL_INT_CFG) = AES_CTRL_INT_CFG_LEVEL;
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REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_DMA_IN_DONE |
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AES_CTRL_INT_EN_RESULT_AV;
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REG(AES_CTRL_ALG_SEL) = AES_CTRL_ALG_SEL_AES;
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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REG(AES_KEY_STORE_READ_AREA) = key_area;
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/* Wait until key is loaded to the AES module */
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while(REG(AES_KEY_STORE_READ_AREA) & AES_KEY_STORE_READ_AREA_BUSY);
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/* Check for Key Store read error */
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if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_KEY_ST_RD_ERR) {
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/* Clear the Keystore Read error bit */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_KEY_ST_RD_ERR;
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/* Disable the master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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return AES_KEYSTORE_READ_ERROR;
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}
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if(iv != NULL) {
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/* Write initialization vector */
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REG(AES_AES_IV_0) = ((const uint32_t *)iv)[0];
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REG(AES_AES_IV_1) = ((const uint32_t *)iv)[1];
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REG(AES_AES_IV_2) = ((const uint32_t *)iv)[2];
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REG(AES_AES_IV_3) = ((const uint32_t *)iv)[3];
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}
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/* Program AES authentication/crypto operation */
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REG(AES_AES_CTRL) = ctrl;
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/* Write the length of the payload block (lo) */
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REG(AES_AES_C_LENGTH_0) = data_len;
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/* Write the length of the payload block (hi) */
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REG(AES_AES_C_LENGTH_1) = 0;
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/* For combined modes only (CCM or GCM) */
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if(ctrl & (AES_AES_CTRL_CCM | AES_AES_CTRL_GCM)) {
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/* Write the length of the AAD data block (may be non-block size-aligned) */
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REG(AES_AES_AUTH_LENGTH) = adata_len;
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if(adata_len != 0) {
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/* Configure DMAC to fetch the AAD data
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* Enable DMA channel 0 */
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REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the AAD data buffer */
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REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)adata;
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/* AAD data length in bytes */
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REG(AES_DMAC_CH0_DMALENGTH) = adata_len;
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/* Wait for completion of the AAD data transfer, DMA_IN_DONE */
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while(!(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_IN_DONE));
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/* Check for the absence of error */
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if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
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/* Clear the DMA error */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR;
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/* Disable the master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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return CRYPTO_DMA_BUS_ERROR;
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}
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/* Clear interrupt status */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE;
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}
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}
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/* Enable result available bit in interrupt enable */
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REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_RESULT_AV;
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if(process != NULL) {
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crypto_register_process_notification(process);
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NVIC_ClearPendingIRQ(AES_IRQn);
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NVIC_EnableIRQ(AES_IRQn);
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}
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if(data_len != 0) {
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/* Configure DMAC
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* Enable DMA channel 0 */
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REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the input payload data buffer */
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REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)data_in;
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/* Input payload data length in bytes */
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REG(AES_DMAC_CH0_DMALENGTH) = data_len;
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if(data_out != NULL) {
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/* Enable DMA channel 1 */
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REG(AES_DMAC_CH1_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the output payload data buffer */
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REG(AES_DMAC_CH1_EXTADDR) = (uint32_t)data_out;
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/* Output payload data length in bytes */
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REG(AES_DMAC_CH1_DMALENGTH) = data_len;
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}
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}
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return CRYPTO_SUCCESS;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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aes_auth_crypt_check_status(void)
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{
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return !!(REG(AES_CTRL_INT_STAT) &
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(AES_CTRL_INT_STAT_DMA_BUS_ERR | AES_CTRL_INT_STAT_KEY_ST_WR_ERR |
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AES_CTRL_INT_STAT_KEY_ST_RD_ERR | AES_CTRL_INT_STAT_RESULT_AV));
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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aes_auth_crypt_get_result(void *iv, void *tag)
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{
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uint32_t aes_ctrl_int_stat;
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aes_ctrl_int_stat = REG(AES_CTRL_INT_STAT);
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/* Clear the error bits */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR |
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AES_CTRL_INT_CLR_KEY_ST_WR_ERR |
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AES_CTRL_INT_CLR_KEY_ST_RD_ERR;
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NVIC_DisableIRQ(AES_IRQn);
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crypto_register_process_notification(NULL);
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/* Disable the master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
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return CRYPTO_DMA_BUS_ERROR;
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}
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if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_KEY_ST_WR_ERR) {
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return AES_KEYSTORE_WRITE_ERROR;
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}
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if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_KEY_ST_RD_ERR) {
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return AES_KEYSTORE_READ_ERROR;
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}
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if(iv != NULL || tag != NULL) {
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/* Read result
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* Wait for the context ready bit */
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while(!(REG(AES_AES_CTRL) & AES_AES_CTRL_SAVED_CONTEXT_READY));
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if(iv != NULL) {
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/* Read the initialization vector registers */
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((uint32_t *)iv)[0] = REG(AES_AES_IV_0);
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((uint32_t *)iv)[1] = REG(AES_AES_IV_1);
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((uint32_t *)iv)[2] = REG(AES_AES_IV_2);
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((uint32_t *)iv)[3] = REG(AES_AES_IV_3);
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}
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if(tag != NULL) {
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/* Read the tag registers */
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((uint32_t *)tag)[0] = REG(AES_AES_TAG_OUT_0);
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((uint32_t *)tag)[1] = REG(AES_AES_TAG_OUT_1);
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((uint32_t *)tag)[2] = REG(AES_AES_TAG_OUT_2);
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((uint32_t *)tag)[3] = REG(AES_AES_TAG_OUT_3);
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}
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}
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/* Clear the interrupt status */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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return CRYPTO_SUCCESS;
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}
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/** @} */
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