222 lines
7.6 KiB
C
222 lines
7.6 KiB
C
/*
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* Copyright (c) 2017, University of Bristol - http://www.bristol.ac.uk/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "contiki.h"
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#include "ti-lib.h"
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#include "dev/spi.h"
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#include "sys/mutex.h"
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#include <stdint.h>
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#include <stdbool.h>
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typedef struct spi_locks_s {
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mutex_t lock;
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const spi_device_t *owner;
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} spi_locks_t;
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/* One lock per SPI controller */
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spi_locks_t board_spi_locks_spi[SPI_CONTROLLER_COUNT] = { { MUTEX_STATUS_UNLOCKED, NULL } };
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/*---------------------------------------------------------------------------*/
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/* Arch-specific properties of each SPI controller */
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typedef struct board_spi_controller_s {
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uint32_t ssi_base;
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uint32_t power_domain;
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uint32_t prcm_periph;
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uint32_t ssi_clkgr_clk_en;
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} board_spi_controller_t;
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static const board_spi_controller_t spi_controller[SPI_CONTROLLER_COUNT] = {
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{
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.ssi_base = SSI0_BASE,
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.power_domain = PRCM_DOMAIN_SERIAL,
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.prcm_periph = PRCM_PERIPH_SSI0,
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.ssi_clkgr_clk_en = PRCM_SSICLKGR_CLK_EN_SSI0
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},
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{
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.ssi_base = SSI1_BASE,
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.power_domain = PRCM_DOMAIN_PERIPH,
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.prcm_periph = PRCM_PERIPH_SSI1,
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.ssi_clkgr_clk_en = PRCM_SSICLKGR_CLK_EN_SSI1
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}
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};
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/*---------------------------------------------------------------------------*/
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bool
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spi_arch_has_lock(const spi_device_t *dev)
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{
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if(board_spi_locks_spi[dev->spi_controller].owner == dev) {
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return true;
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}
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return false;
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}
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/*---------------------------------------------------------------------------*/
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bool
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spi_arch_is_bus_locked(const spi_device_t *dev)
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{
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if(board_spi_locks_spi[dev->spi_controller].lock == MUTEX_STATUS_LOCKED) {
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return true;
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}
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return false;
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}
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/*---------------------------------------------------------------------------*/
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static uint32_t
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get_mode(const spi_device_t *dev)
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{
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/* Select the correct SPI mode */
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if(dev->spi_pha == 0 && dev->spi_pol == 0) {
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return SSI_FRF_MOTO_MODE_0;
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} else if(dev->spi_pha != 0 && dev->spi_pol == 0) {
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return SSI_FRF_MOTO_MODE_1;
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} else if(dev->spi_pha == 0 && dev->spi_pol != 0) {
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return SSI_FRF_MOTO_MODE_2;
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} else {
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return SSI_FRF_MOTO_MODE_3;
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}
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}
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/*---------------------------------------------------------------------------*/
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spi_status_t
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spi_arch_lock_and_open(const spi_device_t *dev)
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{
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uint32_t c;
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/* Lock the SPI bus */
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if(mutex_try_lock(&board_spi_locks_spi[dev->spi_controller].lock) == false) {
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return SPI_DEV_STATUS_BUS_LOCKED;
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}
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board_spi_locks_spi[dev->spi_controller].owner = dev;
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/* CS pin configuration */
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ti_lib_ioc_pin_type_gpio_output(dev->pin_spi_cs);
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/* First, make sure the SERIAL PD is on */
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ti_lib_prcm_power_domain_on(spi_controller[dev->spi_controller].power_domain);
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while((ti_lib_prcm_power_domain_status(spi_controller[dev->spi_controller].power_domain)
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!= PRCM_DOMAIN_POWER_ON)) ;
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/* Enable clock in active mode */
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ti_lib_prcm_peripheral_run_enable(spi_controller[dev->spi_controller].prcm_periph);
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ti_lib_prcm_load_set();
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while(!ti_lib_prcm_load_get()) ;
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/* SPI configuration */
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ti_lib_ssi_int_disable(spi_controller[dev->spi_controller].ssi_base, SSI_RXOR | SSI_RXFF | SSI_RXTO | SSI_TXFF);
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ti_lib_ssi_int_clear(spi_controller[dev->spi_controller].ssi_base, SSI_RXOR | SSI_RXTO);
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ti_lib_ssi_config_set_exp_clk(spi_controller[dev->spi_controller].ssi_base,
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ti_lib_sys_ctrl_clock_get(),
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get_mode(dev), SSI_MODE_MASTER,
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dev->spi_bit_rate, 8);
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ti_lib_ioc_pin_type_ssi_master(spi_controller[dev->spi_controller].ssi_base,
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dev->pin_spi_miso,
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dev->pin_spi_mosi, IOID_UNUSED,
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dev->pin_spi_sck);
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ti_lib_ssi_enable(spi_controller[dev->spi_controller].ssi_base);
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/* Get rid of residual data from SSI port */
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while(ti_lib_ssi_data_get_non_blocking(spi_controller[dev->spi_controller].ssi_base, &c)) ;
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return SPI_DEV_STATUS_OK;
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}
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/*---------------------------------------------------------------------------*/
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spi_status_t
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spi_arch_close_and_unlock(const spi_device_t *dev)
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{
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if(!spi_arch_has_lock(dev)) {
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return SPI_DEV_STATUS_BUS_NOT_OWNED;
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}
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/* Power down SSI */
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ti_lib_prcm_peripheral_run_disable(spi_controller[dev->spi_controller].prcm_periph);
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ti_lib_prcm_load_set();
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while(!ti_lib_prcm_load_get()) ;
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/* Restore pins to a low-consumption state */
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ti_lib_ioc_pin_type_gpio_input(dev->pin_spi_miso);
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ti_lib_ioc_io_port_pull_set(dev->pin_spi_miso, IOC_IOPULL_DOWN);
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ti_lib_ioc_pin_type_gpio_input(dev->pin_spi_mosi);
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ti_lib_ioc_io_port_pull_set(dev->pin_spi_mosi, IOC_IOPULL_DOWN);
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ti_lib_ioc_pin_type_gpio_input(dev->pin_spi_sck);
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ti_lib_ioc_io_port_pull_set(dev->pin_spi_sck, IOC_IOPULL_DOWN);
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/* Unlock the SPI bus */
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board_spi_locks_spi[dev->spi_controller].owner = NULL;
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mutex_unlock(&board_spi_locks_spi[dev->spi_controller].lock);
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return SPI_DEV_STATUS_OK;
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}
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/*---------------------------------------------------------------------------*/
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spi_status_t
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spi_arch_transfer(const spi_device_t *dev,
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const uint8_t *write_buf, int wlen,
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uint8_t *inbuf, int rlen, int ignore_len)
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{
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int i;
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int totlen;
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uint32_t c;
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if(!spi_arch_has_lock(dev)) {
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return SPI_DEV_STATUS_BUS_NOT_OWNED;
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}
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if(ti_lib_prcm_power_domain_status(spi_controller[dev->spi_controller].power_domain)
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!= PRCM_DOMAIN_POWER_ON) {
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return SPI_DEV_STATUS_CLOSED;
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}
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/* Then check the 'run mode' clock gate */
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if(!(HWREG(PRCM_BASE + PRCM_O_SSICLKGR) & spi_controller[dev->spi_controller].ssi_clkgr_clk_en)) {
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return SPI_DEV_STATUS_CLOSED;
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}
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totlen = MAX(rlen + ignore_len, wlen);
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if(totlen == 0) {
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/* Nothing to do */
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return SPI_DEV_STATUS_OK;
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}
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for(i = 0; i < totlen; i++) {
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c = i < wlen ? write_buf[i] : 0;
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ti_lib_ssi_data_put(spi_controller[dev->spi_controller].ssi_base, (uint8_t)c);
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ti_lib_ssi_data_get(spi_controller[dev->spi_controller].ssi_base, &c);
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if(i < rlen) {
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inbuf[i] = (uint8_t)c;
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}
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}
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while(ti_lib_ssi_data_get_non_blocking(spi_controller[dev->spi_controller].ssi_base, &c)) ;
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return SPI_DEV_STATUS_OK;
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}
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/*---------------------------------------------------------------------------*/
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