172 lines
4.9 KiB
C
172 lines
4.9 KiB
C
/*
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* Copyright (c) 2006, Swedish Institute of Computer Science
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)$Id: slip_uart1.c,v 1.3 2006/12/01 15:07:49 bg- Exp $
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*/
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/*
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* Machine dependent MSP430 SLIP routines for UART1.
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*/
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#include <io.h>
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#include <signal.h>
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#include "contiki.h"
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#include "dev/slip.h"
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void
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slip_arch_writeb(unsigned char c)
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{
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/* Loop until the transmission buffer is available. */
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while ((IFG2 & UTXIFG1) == 0);
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/* Transmit the data. */
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TXBUF1 = c;
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}
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/*
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* The serial line is used to transfer IP packets using slip. To make
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* it possible to send debug output over the same line we send debug
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* output as slip frames (i.e delimeted by SLIP_END).
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*
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*/
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int
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putchar(int c)
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{
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#define SLIP_END 0300
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static char debug_frame = 0;
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if (!debug_frame) { /* Start of debug output */
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slip_arch_writeb(SLIP_END);
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slip_arch_writeb('\r'); /* Type debug line == '\r' */
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debug_frame = 1;
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}
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slip_arch_writeb((char)c);
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/*
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* Line buffered output, a newline marks the end of debug output and
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* implicitly flushes debug output.
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*/
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if (c == '\n') {
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slip_arch_writeb(SLIP_END);
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debug_frame = 0;
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}
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return c;
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}
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#define RS232_19200 1
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#define RS232_38400 2
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#define RS232_57600 3
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#define RS232_115200 3
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#if 0
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void
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rs232_set_speed(unsigned char speed)
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{
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if(speed == RS232_19200) {
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/* Set RS232 to 19200 */
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UBR01 = 0x80; /* 2,457MHz/19200 = 128 -> 0x80 */
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UBR11 = 0x00; /* */
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UMCTL1 = 0x00; /* no modulation */
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} else if(speed == RS232_38400) {
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/* Set RS232 to 38400 */
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UBR01 = 0x40; /* 2,457MHz/38400 = 64 -> 0x40 */
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UBR11 = 0x00; /* */
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UMCTL1 = 0x00; /* no modulation */
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} else if(speed == RS232_57600) {
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UBR01 = 0x2a; /* 2,457MHz/57600 = 42.7 -> 0x2A */
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UBR11 = 0x00; /* */
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UMCTL1 = 0x5b; /* */
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} else if(speed == RS232_115200) {
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UBR01 = 0x15; /* 2,457MHz/115200 = 21.4 -> 0x15 */
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UBR11 = 0x00; /* */
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UMCTL1 = 0x4a; /* */
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} else {
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rs232_set_speed(RS232_57600);
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}
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}
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#endif
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/**
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* Initalize the RS232 port and the SLIP driver.
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*
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*/
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void
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slip_arch_init(void)
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{
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/* RS232 */
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P3DIR &= ~0x80; /* Select P37 for input (UART1RX) */
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P3DIR |= 0x40; /* Select P36 for output (UART1TX) */
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P3SEL |= 0xC0; /* Select P36,P37 for UART1{TX,RX} */
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UCTL1 = SWRST | CHAR; /* 8-bit character, UART mode */
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/* U1RCTL &= ~URXEIE; /\* even erroneous characters trigger interrupts *\/ */
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UTCTL1 = SSEL1; /* UCLK = MCLK */
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#ifdef TMOTE_SKY
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/* rs232_set_speed(RS232_115200); */
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UBR01 = 0x15;
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UBR11 = 0x00;
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UMCTL1 = 0x4a;
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#else
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/* rs232_set_speed(RS232_57600); */
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UBR01 = 0x2a;
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UBR11 = 0x00;
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UMCTL1 = 0x5b;
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#endif
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ME2 &= ~USPIE1; /* USART1 SPI module disable */
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ME2 |= (UTXE1 | URXE1); /* Enable USART1 TXD/RXD */
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UCTL1 &= ~SWRST;
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/* XXX Clear pending interrupts before enable!!! */
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IE2 |= URXIE1; /* Enable USART1 RX interrupt */
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}
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interrupt(UART1RX_VECTOR)
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__uart1_intr()
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{
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/* Check status register for receive errors. */
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if (URCTL1 & RXERR) {
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volatile unsigned dummy;
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dummy = RXBUF1; /* Clear error flags by forcing a dummy read. */
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} else {
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if(slip_input_byte(RXBUF1))
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LPM4_EXIT;
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}
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}
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