2dccb55e15
This patch adds the pci.c and pci.h files, which support access to PCI configuration registers through a function interface. It defines the PCI configuration register access I/O port addresses and the pci_config_addr union and structure to assist in specifying addresses of PCI configuration registers. It also defines the PCI configuration register identifier for PCI BAR0. This patch also adds wrappers for 32-bit 'in' and 'out' port I/O instructions. They were placed in helpers.S, since they may be useful to other modules besides just the PCI support module.
62 lines
2.5 KiB
C
62 lines
2.5 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef CPU_X86_DRIVERS_LEGACY_PC_PCI_H_
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#define CPU_X86_DRIVERS_LEGACY_PC_PCI_H_
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#include <stdint.h>
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/** PCI configuration register identifier for Base Address Register 0 (BAR0) */
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#define PCI_CONFIG_REG_BAR0 0x10
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/**
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* PCI configuration address
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*
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* Refer to Intel Quark SoC X1000 Datasheet, Section 5.5 for more details on
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* PCI configuration register access.
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*/
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typedef union pci_config_addr {
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struct {
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/** Register/offset number. Least-significant two bits should be zero. */
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uint32_t reg_off : 8;
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uint32_t func : 3; /**< Function number */
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uint32_t dev : 5; /**< Device number */
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uint32_t bus : 8; /**< Bus number */
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uint32_t : 7;
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/** Must be set to perform PCI configuration access. */
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uint32_t en_mapping : 1;
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};
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uint32_t raw;
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} pci_config_addr_t;
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uint32_t pci_config_read(pci_config_addr_t addr);
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#endif /* CPU_X86_DRIVERS_LEGACY_PC_PCI_H_ */
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