fb8bbf37cf
This is a major change to how the main tick interrupt is handled on the mc1322x platforms. Instead of using two timer resources, TMR0 and RTC, this patch unifies all the timers to use the RTC. This is enabled by implementing etimers as scheduled rtimers. The main advantage (aside from freeing TMR0 for general use) is have the Contiki timebase come from the same source that will be used for sleeping and wakeup.
151 lines
4.2 KiB
C
151 lines
4.2 KiB
C
/*
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* Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
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* to the MC1322x project (http://mc1322x.devl.org) and Contiki.
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki OS.
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*
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*
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*/
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/**
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* \file
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* mc1322x-specific rtimer code
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* \author
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* Mariano Alvira <mar@devl.org>
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*/
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#include <signal.h>
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/* contiki */
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#include "sys/energest.h"
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#include "sys/rtimer.h"
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/* mc1322x */
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#include "utils.h"
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#define DEBUG 0
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#if DEBUG
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#include <stdio.h>
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#define PRINTF(...) printf(__VA_ARGS__)
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#else
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#define PRINTF(...)
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#endif
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static uint32_t last_rtc;
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void
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rtc_isr(void)
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{
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/* see note in table 5-13 of the reference manual: it takes at least two RTC clocks for the EVT bit to clear */
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if ((CRM->RTC_COUNT - last_rtc) <= 2) {
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CRM->STATUS = ~0; /* Clear all events */
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// CRM->STATUSbits.RTC_WU_EVT = 1;
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return;
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}
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last_rtc = CRM->RTC_COUNT;
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/* Clear all events (for paranoia) */
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/* clear RTC event flag (for paranoia)*/
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// CRM->STATUSbits.RTC_WU_EVT = 1;
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CRM->STATUS = ~0;
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rtimer_run_next();
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}
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void
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rtimer_arch_init(void)
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{
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last_rtc = CRM->RTC_COUNT;
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/* enable timeout interrupts */
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/* RTC WU is the periodic RTC timer */
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/* TIMER WU is the wakeup timers (clocked from the RTC source) */
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/* it does not appear you can have both enabled at the same time */
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CRM->WU_CNTLbits.RTC_WU_EN = 1;
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CRM->WU_CNTLbits.RTC_WU_IEN = 1;
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enable_irq(CRM);
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}
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void
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rtimer_arch_schedule(rtimer_clock_t t)
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{
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volatile uint32_t now;
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now = rtimer_arch_now();
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PRINTF("rtimer_arch_schedule time %u; now is %u\n", t, now);
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/* Immediate interrupt if specified time is before current time. This may also
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happen on counter overflow. */
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if(now > t) {
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CRM->RTC_TIMEOUT = 1;
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} else {
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CRM->RTC_TIMEOUT = t - now;
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}
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}
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void
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rtimer_arch_sleep(rtimer_clock_t howlong)
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{
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CRM->WU_CNTLbits.TIMER_WU_EN = 1;
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CRM->WU_CNTLbits.RTC_WU_EN = 0;
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CRM->WU_TIMEOUT = howlong;
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/* the maca must be off before going to sleep */
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/* otherwise the mcu will reboot on wakeup */
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maca_off();
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CRM->SLEEP_CNTLbits.DOZE = 0;
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CRM->SLEEP_CNTLbits.RAM_RET = 3;
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CRM->SLEEP_CNTLbits.MCU_RET = 1;
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CRM->SLEEP_CNTLbits.DIG_PAD_EN = 1;
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CRM->SLEEP_CNTLbits.HIB = 1;
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/* wait for the sleep cycle to complete */
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while((*CRM_STATUS & 0x1) == 0) { continue; }
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/* write 1 to sleep_sync --- this clears the bit (it's a r1wc bit) and powers down */
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*CRM_STATUS = 1;
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/* asleep */
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/* wait for the awake cycle to complete */
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while((*CRM_STATUS & 0x1) == 0) { continue; }
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/* write 1 to sleep_sync --- this clears the bit (it's a r1wc bit) and finishes wakeup */
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*CRM_STATUS = 1;
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CRM->WU_CNTLbits.TIMER_WU_EN = 0;
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CRM->WU_CNTLbits.RTC_WU_EN = 1;
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/* reschedule clock ticks */
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clock_init();
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clock_adjust_ticks((CRM->WU_COUNT*CLOCK_CONF_SECOND)/rtc_freq);
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}
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