271 lines
7.5 KiB
C
271 lines
7.5 KiB
C
/*
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* Copyright (c) 2005, Swedish Institute of Computer Science
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki operating system.
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*
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* @(#)$Id: msp430.c,v 1.10 2009/02/04 18:28:44 joxe Exp $
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*/
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#include <io.h>
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#include <signal.h>
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#include <sys/unistd.h>
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#include "msp430.h"
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#include "dev/watchdog.h"
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#include "net/uip.h"
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/*---------------------------------------------------------------------------*/
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void
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msp430_init_dco(void)
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{
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/* This code taken from the FU Berlin sources and reformatted. */
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#define DELTA ((MSP430_CPU_SPEED) / (32768 / 8))
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unsigned int compare, oldcapture = 0;
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unsigned int i;
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BCSCTL1 = 0xa4; /* ACLK is devided by 4. RSEL=6 no division for MCLK
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and SSMCLK. XT2 is off. */
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BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
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crystal DCO frquenzy = 2,4576 MHz */
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BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
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for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
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asm("nop");
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}
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CCTL2 = CCIS0 + CM0 + CAP; // Define CCR2, CAP, ACLK
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TACTL = TASSEL1 + TACLR + MC1; // SMCLK, continous mode
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while(1) {
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while((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured! */
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CCTL2 &= ~CCIFG; /* Capture occured, clear flag */
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compare = CCR2; /* Get current captured SMCLK */
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compare = compare - oldcapture; /* SMCLK difference */
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oldcapture = CCR2; /* Save current captured SMCLK */
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if(DELTA == compare) {
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break; /* if equal, leave "while(1)" */
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} else if(DELTA < compare) { /* DCO is too fast, slow it down */
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DCOCTL--;
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if(DCOCTL == 0xFF) { /* Did DCO role under? */
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BCSCTL1--;
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}
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} else { /* -> Select next lower RSEL */
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DCOCTL++;
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if(DCOCTL == 0x00) { /* Did DCO role over? */
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BCSCTL1++;
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}
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/* -> Select next higher RSEL */
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}
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}
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CCTL2 = 0; /* Stop CCR2 function */
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TACTL = 0; /* Stop Timer_A */
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BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */
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}
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/*---------------------------------------------------------------------------*/
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static void
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init_ports(void)
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{
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/* Turn everything off, device drivers enable what is needed. */
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/* All configured for digital I/O */
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#ifdef P1SEL
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P1SEL = 0;
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#endif
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#ifdef P2SEL
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P2SEL = 0;
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#endif
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#ifdef P3SEL
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P3SEL = 0;
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#endif
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#ifdef P4SEL
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P4SEL = 0;
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#endif
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#ifdef P5SEL
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P5SEL = 0;
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#endif
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#ifdef P6SEL
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P6SEL = 0;
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#endif
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/* All available inputs */
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#ifdef P1DIR
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P1DIR = 0;
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P1OUT = 0;
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#endif
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#ifdef P2DIR
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P2DIR = 0;
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P2OUT = 0;
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#endif
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#ifdef P3DIR
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P3DIR = 0;
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P3OUT = 0;
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#endif
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#ifdef P4DIR
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P4DIR = 0;
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P4OUT = 0;
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#endif
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#ifdef P5DIR
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P5DIR = 0;
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P5OUT = 0;
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#endif
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#ifdef P6DIR
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P6DIR = 0;
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P6OUT = 0;
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#endif
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P1IE = 0;
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P2IE = 0;
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}
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/*---------------------------------------------------------------------------*/
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/* msp430-ld may align _end incorrectly. Workaround in cpu_init. */
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extern int _end; /* Not in sys/unistd.h */
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static char *cur_break = (char *)&_end;
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void
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msp430_cpu_init(void)
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{
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dint();
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watchdog_init();
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init_ports();
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msp430_init_dco();
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eint();
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if((uintptr_t)cur_break & 1) { /* Workaround for msp430-ld bug! */
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cur_break++;
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}
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}
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/*---------------------------------------------------------------------------*/
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#define asmv(arg) __asm__ __volatile__(arg)
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#define STACK_EXTRA 32
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/*
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* Allocate memory from the heap. Check that we don't collide with the
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* stack right now (some other routine might later). A watchdog might
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* be used to check if cur_break and the stack pointer meet during
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* runtime.
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*/
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void *
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sbrk(int incr)
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{
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char *stack_pointer;
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asmv("mov r1, %0" : "=r" (stack_pointer));
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stack_pointer -= STACK_EXTRA;
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if(incr > (stack_pointer - cur_break))
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return (void *)-1; /* ENOMEM */
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void *old_break = cur_break;
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cur_break += incr;
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/*
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* If the stack was never here then [old_break .. cur_break] should
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* be filled with zeros.
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*/
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return old_break;
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}
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/*---------------------------------------------------------------------------*/
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/*
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* Mask all interrupts that can be masked.
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*/
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int
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splhigh_(void)
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{
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/* Clear the GIE (General Interrupt Enable) flag. */
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int sr;
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asmv("mov r2, %0" : "=r" (sr));
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asmv("bic %0, r2" : : "i" (GIE));
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return sr & GIE; /* Ignore other sr bits. */
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}
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/*---------------------------------------------------------------------------*/
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/*
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* Restore previous interrupt mask.
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*/
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void
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splx_(int sr)
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{
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/* If GIE was set, restore it. */
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asmv("bis %0, r2" : : "r" (sr));
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}
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/*---------------------------------------------------------------------------*/
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/* this code will always start the TimerB if not already started */
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void
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msp430_sync_dco(void) {
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uint16_t last;
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uint16_t diff;
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/* uint32_t speed; */
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/* DELTA_2 assumes an ACLK of 32768 Hz */
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#define DELTA_2 ((MSP430_CPU_SPEED) / 32768)
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/* Select SMCLK clock, and capture on ACLK for TBCCR6 */
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TBCTL = TBSSEL1 | TBCLR;
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TBCCTL6 = CCIS0 + CM0 + CAP;
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/* start the timer */
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TBCTL |= MC1;
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// wait for next Capture
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TBCCTL6 &= ~CCIFG;
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while(!(TBCCTL6 & CCIFG));
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last = TBCCR6;
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TBCCTL6 &= ~CCIFG;
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// wait for next Capture - and calculate difference
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while(!(TBCCTL6 & CCIFG));
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diff = TBCCR6 - last;
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/* Stop timer - conserves energy according to user guide */
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TBCTL = 0;
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/* speed = diff; */
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/* speed = speed * 32768; */
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/* printf("Last TAR diff:%d target: %ld ", diff, DELTA_2); */
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/* printf("CPU Speed: %lu DCOCTL: %d\n", speed, DCOCTL); */
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/* resynchronize the DCO speed if not at target */
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if(DELTA_2 < diff) { /* DCO is too fast, slow it down */
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DCOCTL--;
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if(DCOCTL == 0xFF) { /* Did DCO role under? */
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BCSCTL1--;
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}
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} else if (DELTA_2 > diff) {
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DCOCTL++;
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if(DCOCTL == 0x00) { /* Did DCO role over? */
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BCSCTL1++;
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}
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}
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}
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/*---------------------------------------------------------------------------*/
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