282 lines
9.2 KiB
C
282 lines
9.2 KiB
C
/*
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* Copyright (c) 2010, Swedish Institute of Computer Science.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/**
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* \file
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* Platform configuration for the Z1 platform
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* \author
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* Joakim Eriksson <joakime@sics.se>
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*/
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#ifndef PLATFORM_CONF_H_
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#define PLATFORM_CONF_H_
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/*
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* Definitions below are dictated by the hardware and not really
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* changeable!
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*/
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#define ZOLERTIA_Z1 1 /* Enric */
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/* Delay between GO signal and SFD: radio fixed delay + 4Bytes preample + 1B SFD -- 1Byte time is 32us
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* ~327us + 129preample = 456 us */
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#define RADIO_DELAY_BEFORE_TX ((unsigned)US_TO_RTIMERTICKS(456))
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/* Delay between GO signal and start listening
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* ~50us delay + 129preample + ?? = 183 us */
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#define RADIO_DELAY_BEFORE_RX ((unsigned)US_TO_RTIMERTICKS(183))
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/* Delay between the SFD finishes arriving and it is detected in software */
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#define RADIO_DELAY_BEFORE_DETECT 0
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#define PLATFORM_HAS_LEDS 1
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#define PLATFORM_HAS_BUTTON 1
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#define PLATFORM_HAS_RADIO 1
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#define PLATFORM_HAS_BATTERY 1
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/* CPU target speed in Hz */
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#define F_CPU 8000000uL /* 8MHz by default */
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/* Our clock resolution, this is the same as Unix HZ. */
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#define CLOCK_CONF_SECOND 128UL
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#define BAUD2UBR(baud) ((F_CPU / baud))
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#define CCIF
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#define CLIF
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#define HAVE_STDINT_H
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#include "msp430def.h"
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/* XXX Temporary place for defines that are lacking in mspgcc4's gpio.h */
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#ifdef __IAR_SYSTEMS_ICC__
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#ifndef P1SEL2_
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#define P1SEL2_ (0x0041u) /* Port 1 Selection 2*/
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DEFC(P1SEL2, P1SEL2_)
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#endif
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#ifndef P5SEL2_
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#define P5SEL2_ (0x0045u) /* Port 5 Selection 2*/
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DEFC(P5SEL2, P5SEL2_)
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#endif
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#else /* __IAR_SYSTEMS_ICC__ */
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#ifdef __GNUC__
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#ifndef P1SEL2_
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#define P1SEL2_ 0x0041 /* Port 1 Selection 2*/
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sfrb(P1SEL2, P1SEL2_);
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#endif
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#ifndef P5SEL2_
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#define P5SEL2_ 0x0045 /* Port 5 Selection 2*/
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sfrb(P5SEL2, P5SEL2_);
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#endif
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#endif /* __GNUC__ */
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#endif /* __IAR_SYSTEMS_ICC__ */
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/* Types for clocks and uip_stats */
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typedef unsigned short uip_stats_t;
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typedef unsigned long clock_time_t;
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typedef unsigned long off_t;
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/* the low-level radio driver */
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#define NETSTACK_CONF_RADIO cc2420_driver
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/*
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* Definitions below are dictated by the hardware and not really
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* changeable!
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*/
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/* LED ports */
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#ifdef Z1_IS_Z1SP
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#define LEDS_PxDIR P4DIR
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#define LEDS_PxOUT P4OUT
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#define LEDS_CONF_RED 0x04
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#define LEDS_CONF_GREEN 0x01
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#define LEDS_CONF_YELLOW 0x80
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#else
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#define LEDS_PxDIR P5DIR
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#define LEDS_PxOUT P5OUT
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#define LEDS_CONF_RED 0x10
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#define LEDS_CONF_GREEN 0x40
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#define LEDS_CONF_YELLOW 0x20
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#endif /* Z1_IS_Z1SP */
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/* DCO speed resynchronization for more robust UART, etc. */
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#define DCOSYNCH_CONF_ENABLED 0
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#define DCOSYNCH_CONF_PERIOD 30
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#define ROM_ERASE_UNIT_SIZE 512
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#define XMEM_ERASE_UNIT_SIZE (64 * 1024L)
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#define CFS_CONF_OFFSET_TYPE long
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/* Use the first 64k of external flash for node configuration */
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#define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
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/* Use the second 64k of external flash for codeprop. */
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#define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
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#define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
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#define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
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#define CFS_RAM_CONF_SIZE 4096
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/*
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* SPI bus configuration for the Z1 mote.
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*/
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/* SPI input/output registers. */
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#define SPI_TXBUF UCB0TXBUF
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#define SPI_RXBUF UCB0RXBUF
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/* USART0 Tx ready? */
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#define SPI_WAITFOREOTx() while((UCB0STAT & UCBUSY) != 0)
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/* USART0 Rx ready? */
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#define SPI_WAITFOREORx() while((IFG2 & UCB0RXIFG) == 0)
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/* USART0 Tx buffer ready? */
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#define SPI_WAITFORTxREADY() while((IFG2 & UCB0TXIFG) == 0)
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#define MOSI 1 /* P3.1 - Output: SPI Master out - slave in (MOSI) */
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#define MISO 2 /* P3.2 - Input: SPI Master in - slave out (MISO) */
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#define SCK 3 /* P3.3 - Output: SPI Serial Clock (SCLK) */
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/*
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* SPI bus - M25P80 external flash configuration.
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*/
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/* FLASH_PWR P4.3 Output ALWAYS POWERED ON Z1 */
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#define FLASH_CS 4 /* P4.4 Output */
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#define FLASH_HOLD 7 /* P5.7 Output */
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/* Enable/disable flash access to the SPI bus (active low). */
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#define SPI_FLASH_ENABLE() (P4OUT &= ~BV(FLASH_CS))
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#define SPI_FLASH_DISABLE() (P4OUT |= BV(FLASH_CS))
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#define SPI_FLASH_HOLD() (P5OUT &= ~BV(FLASH_HOLD))
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#define SPI_FLASH_UNHOLD() (P5OUT |= BV(FLASH_HOLD))
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/*
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* SPI bus - CC2420 pin configuration.
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*/
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#define CC2420_CONF_SYMBOL_LOOP_COUNT 1302 /* 326us msp430X @ 8MHz */
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/* P1.2 - Input: FIFOP from CC2420 */
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#define CC2420_FIFOP_PORT(type) P1##type
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#define CC2420_FIFOP_PIN 2
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/* P1.3 - Input: FIFO from CC2420 */
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#define CC2420_FIFO_PORT(type) P1##type
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#define CC2420_FIFO_PIN 3
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/* P1.4 - Input: CCA from CC2420 */
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#define CC2420_CCA_PORT(type) P1##type
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#define CC2420_CCA_PIN 4
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/* P4.1 - Input: SFD from CC2420 */
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#define CC2420_SFD_PORT(type) P4##type
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#define CC2420_SFD_PIN 1
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/* P3.0 - Output: SPI Chip Select (CS_N) */
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#define CC2420_CSN_PORT(type) P3##type
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#define CC2420_CSN_PIN 0
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/* P4.5 - Output: VREG_EN to CC2420 */
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#define CC2420_VREG_PORT(type) P4##type
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#define CC2420_VREG_PIN 5
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/* P4.6 - Output: RESET_N to CC2420 */
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#define CC2420_RESET_PORT(type) P4##type
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#define CC2420_RESET_PIN 6
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#define CC2420_IRQ_VECTOR PORT1_VECTOR
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/* Pin status. */
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#define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
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#define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
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#define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
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#define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
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/* The CC2420 reset pin. */
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#define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
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#define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
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/* CC2420 voltage regulator enable pin. */
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#define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
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#define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
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/* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
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#define CC2420_FIFOP_INT_INIT() do { \
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CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
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CC2420_CLEAR_FIFOP_INT(); \
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} while(0)
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/* FIFOP on external interrupt 0. */
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#define CC2420_ENABLE_FIFOP_INT() do { CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN); } while(0)
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#define CC2420_DISABLE_FIFOP_INT() do { CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN); } while(0)
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#define CC2420_CLEAR_FIFOP_INT() do { CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN); } while(0)
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/*
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* Enables/disables CC2420 access to the SPI bus (not the bus).
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* (Chip Select)
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*/
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/* ENABLE CSn (active low) */
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#define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
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/* DISABLE CSn (active low) */
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#define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
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#define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
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/*
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* I2C configuration
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*/
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#define I2C_PxDIR P5DIR
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#define I2C_PxIN P5IN
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#define I2C_PxOUT P5OUT
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#define I2C_PxSEL P5SEL
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#define I2C_PxSEL2 P5SEL2
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#define I2C_PxREN P5REN
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#define I2C_SDA (1 << 1) /* SDA == P5.1 */
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#define I2C_SCL (1 << 2) /* SCL == P5.2 */
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#define I2C_PRESC_1KHZ_LSB 0x00
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#define I2C_PRESC_1KHZ_MSB 0x20
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#define I2C_PRESC_100KHZ_LSB 0x50
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#define I2C_PRESC_100KHZ_MSB 0x00
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#define I2C_PRESC_400KHZ_LSB 0x14
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#define I2C_PRESC_400KHZ_MSB 0x00
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/* Set rate as high as possible by default */
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#ifndef I2C_PRESC_Z1_LSB
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#define I2C_PRESC_Z1_LSB I2C_PRESC_400KHZ_LSB
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#endif
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#ifndef I2C_PRESC_Z1_MSB
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#define I2C_PRESC_Z1_MSB I2C_PRESC_400KHZ_MSB
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#endif
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/* I2C configuration with RX interrupts */
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#ifdef I2C_CONF_RX_WITH_INTERRUPT
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#define I2C_RX_WITH_INTERRUPT I2C_CONF_RX_WITH_INTERRUPT
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#else /* I2C_CONF_RX_WITH_INTERRUPT */
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#define I2C_RX_WITH_INTERRUPT 1
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#endif /* I2C_CONF_RX_WITH_INTERRUPT */
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#endif /* PLATFORM_CONF_H_ */
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