c815fa4511
This patch permits interrupts to be generated by both the I2C and GPIO controllers for simultaneously-executing applications. The controllers share a single interrupt pin, INTC. Prior to this patch, quarkX1000_gpio_init() routed INTA to PIRQC and IRQ 10 (due to an incorrect assumption that INTA is connected to the GPIO controller), and quarkX1000_i2c_init() routed INTC to PIRQC and IRQ 9. The I2C controller initialization is a prerequisite for GPIO initialization, so the final configuration was that INTA and INTC were both routed to PIRQC and IRQ 10. Thus, only the GPIO ISR was being invoked, even if the I2C controller was actually responsible for the interrupt. This patch refactors the I2C and GPIO ISR setup and handler code so that the shared portions are combined in cpu/x86/drivers/legacy_pc/shared-isr.[ch]. The I2C and GPIO drivers communicate their interrupt information to the shared component by placing structures in a specific section of the binary.
81 lines
3.1 KiB
Plaintext
81 lines
3.1 KiB
Plaintext
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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OUTPUT_FORMAT("elf32-i386")
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ENTRY(start)
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SECTIONS {
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/*
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OS-Dev Wiki says it is common for kernels to start at 1M. Addresses before that
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are used by BIOS/EFI, the bootloader and memory-mapped I/O.
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The UEFI GenFw program inserts a 0x240-byte offset between the image base and
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the .text section. We add that same offset here to align the symbols in the
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UEFI DLL with those in the final UEFI binary to make debugging easier. We also
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apply 32-byte alignments to sections rather than more conventional 4K-byte
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alignments to avoid symbols being shifted from the intermediate DLL to the
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final UEFI image as would occur if the GenFw program shifted the .text section
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from a higher, 4K-aligned offset to the 0x240-byte offset from the image base.
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Such shifting may make debugging more difficult by preventing the DLL from
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being a directly-useful source of symbol information. The debugging symbols
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are not included in the final UEFI image. The GenFw program uses a minimum
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section alignment of 32 bytes, so smaller alignment granularities may also
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result in symbol perturbation.
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*/
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. = 1M + 0x240;
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.text ALIGN (32) :
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{
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KEEP(*(.multiboot))
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*(.text*)
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}
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.rodata ALIGN (32) :
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{
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*(.rodata*)
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_sdata_shared_isr = .;
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KEEP(*(.shared_isr_data*))
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_edata_shared_isr = .;
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}
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.data ALIGN (32) :
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{
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*(.data*)
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}
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.bss ALIGN (32) :
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{
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*(COMMON)
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*(.bss*)
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}
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}
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