40f49948e6
This commit adds cpu, platform and example files, providing support for running Contiki on TI's cc2538 DK
120 lines
5.3 KiB
C
120 lines
5.3 KiB
C
/*
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* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538
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* @{
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*
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* \defgroup cc2538-smwdthrosc cc2538 Sleep Timer and Watchdog
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*
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* Register declarations for the cc2538 Sleep Timer and Watchdog
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* @{
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*
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* \file
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* Header file with register declarations and bit masks for the cc2538
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* Sleep Timer and Watchdog
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*/
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#ifndef SMWDTHROSC_H_
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#define SMWDTHROSC_H_
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/*---------------------------------------------------------------------------*/
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/** \name ST and WDT Register offset declarations
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* @{
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*/
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#define SMWDTHROSC_WDCTL 0x400D5000 /**< Watchdog Control */
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#define SMWDTHROSC_ST0 0x400D5040 /**< ST count/compare value 0 */
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#define SMWDTHROSC_ST1 0x400D5044 /**< ST count/compare value 1 */
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#define SMWDTHROSC_ST2 0x400D5048 /**< ST count/compare value 2 */
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#define SMWDTHROSC_ST3 0x400D504C /**< ST count/compare value 3 */
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#define SMWDTHROSC_STLOAD 0x400D5050 /**< Compare value load status */
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#define SMWDTHROSC_STCC 0x400D5054 /**< ST capture control */
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#define SMWDTHROSC_STCS 0x400D5058 /**< ST capture status */
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#define SMWDTHROSC_STCV0 0x400D505C /**< ST capture value 0 */
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#define SMWDTHROSC_STCV1 0x400D5060 /**< ST capture value 1 */
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#define SMWDTHROSC_STCV2 0x400D5064 /**< ST capture value 2 */
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#define SMWDTHROSC_STCV3 0x400D5068 /**< ST capture value 3 */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SMWDTHROSC_WDCTL register bit masks
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* @{
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*/
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#define SMWDTHROSC_WDCTL_CLR 0x000000F0 /**< Clear timer mask */
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#define SMWDTHROSC_WDCTL_CLR_3 0x00000080 /**< Clear timer mask[3] */
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#define SMWDTHROSC_WDCTL_CLR_2 0x00000040 /**< Clear timer mask[2] */
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#define SMWDTHROSC_WDCTL_CLR_1 0x00000020 /**< Clear timer mask[1] */
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#define SMWDTHROSC_WDCTL_CLR_0 0x00000010 /**< Clear timer mask[0] */
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#define SMWDTHROSC_WDCTL_EN 0x00000008 /**< Enable mask */
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#define SMWDTHROSC_WDCTL_MODE 0x00000004 /**< Mode select mask */
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#define SMWDTHROSC_WDCTL_INT 0x00000003 /**< Interval Select mask */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SMWDTHROSC_ST[0:3] register bit masks
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* @{
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*/
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#define SMWDTHROSC_ST0_ST0 0x000000FF /**< ST count/compare bits [7:0] */
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#define SMWDTHROSC_ST1_ST1 0x000000FF /**< ST count/compare bits [15:8] */
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#define SMWDTHROSC_ST2_ST2 0x000000FF /**< ST count/compare bits [23:16] */
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#define SMWDTHROSC_ST3_ST3 0x000000FF /**< ST count/compare bits [31:24] */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SMWDTHROSC_STLOAD register bit masks
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* @{
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*/
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#define SMWDTHROSC_STLOAD_STLOAD 0x00000001 /**< STx upload status signal */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SMWDTHROSC_STCC register bit masks
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* @{
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*/
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#define SMWDTHROSC_STCC_PORT 0x00000038 /**< Port select */
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#define SMWDTHROSC_STCC_PIN 0x00000007 /**< Pin select */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SMWDTHROSC_STCS register bit masks
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* @{
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*/
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#define SMWDTHROSC_STCS_VALID 0x00000001 /**< Capture valid flag */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SMWDTHROSC_STCV[0:3] register bit masks
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* @{
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*/
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#define SMWDTHROSC_STCV0_STCV0 0x000000FF /**< ST capture bits [7:0] */
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#define SMWDTHROSC_STCV1_STCV1 0x000000FF /**< ST capture bits [15:8] */
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#define SMWDTHROSC_STCV2_STCV2 0x000000FF /**< ST capture bits [23:16] */
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#define SMWDTHROSC_STCV3_STCV3 0x000000FF /**< ST capture bits [32:24] */
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/** @} */
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#endif /* SMWDTHROSC_H_ */
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/**
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* @}
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* @}
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*/
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