84 lines
3.6 KiB
C
84 lines
3.6 KiB
C
/*
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* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538
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* @{
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*
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* \defgroup cc2538-scb cc2538 System Control Block (SCB)
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*
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* Offsets and bit definitions for SCB registers
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* @{
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*
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* \file
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* Header file for the System Control Block (SCB)
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*/
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#ifndef SCB_H_
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#define SCB_H_
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#define SCB_CPUID 0xE000ED00 /**< CPU ID Base */
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#define SCB_INTCTRL 0xE000ED04 /**< Interrupt Control and State */
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#define SCB_VTABLE 0xE000ED08 /**< Vector Table Offset */
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#define SCB_APINT 0xE000ED0C /**< Application Interrupt and Reset Control */
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#define SCB_SYSCTRL 0xE000ED10 /**< System Control */
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#define SCB_CFGCTRL 0xE000ED14 /**< Configuration and Control */
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#define SCB_SYSPRI1 0xE000ED18 /**< System Handler Priority 1 */
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#define SCB_SYSPRI2 0xE000ED1C /**< System Handler Priority 2 */
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#define SCB_SYSPRI3 0xE000ED20 /**< System Handler Priority 3 */
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#define SCB_SYSHNDCTRL 0xE000ED24 /**< System Handler Control and State */
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#define SCB_FAULTSTAT 0xE000ED28 /**< Configurable Fault Status */
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#define SCB_HFAULTSTAT 0xE000ED2C /**< Hard Fault Status */
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#define SCB_DEBUG_STAT 0xE000ED30 /**< Debug Status Register */
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#define SCB_MMADDR 0xE000ED34 /**< Memory Management Fault Address */
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#define SCB_FAULT_ADDR 0xE000ED38 /**< Bus Fault Address */
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/*---------------------------------------------------------------------------*/
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/** \name VTABLE register bits
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* @{
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*/
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#define SCB_VTABLE_BASE 0x20000000 /**< Vector Table Base */
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#define SCB_VTABLE_OFFSET_M 0x1FFFFE00 /**< Vector Table Offset */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name SCB_SYSCTRL register bits
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* @{
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*/
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#define SCB_SYSCTRL_SEVONPEND 0x00000010 /**< Wake up on pending */
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#define SCB_SYSCTRL_SLEEPDEEP 0x00000004 /**< Deep sleep enable */
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#define SCB_SYSCTRL_SLEEPEXIT 0x00000002 /**< Sleep on ISR exit */
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/** @} */
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/*---------------------------------------------------------------------------*/
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#endif /* SCB_H_ */
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/**
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* @}
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* @}
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*/
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